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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-u300.c
blobcc306448259eca81cf350c8c8602c076b5eba284
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the U300 pin controller
4 *
5 * Based on the original U300 padmux functions
6 * Copyright (C) 2009-2011 ST-Ericsson AB
7 * Author: Martin Persson <martin.persson@stericsson.com>
8 * Author: Linus Walleij <linus.walleij@linaro.org>
9 *
10 * The DB3350 design and control registers are oriented around pads rather than
11 * pins, so we enumerate the pads we can mux rather than actual pins. The pads
12 * are connected to different pins in different packaging types, so it would
13 * be confusing.
14 */
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/platform_device.h>
19 #include <linux/io.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-coh901.h"
27
28 /*
29 * Register definitions for the U300 Padmux control registers in the
30 * system controller
31 */
32
33 /* PAD MUX Control register 1 (LOW) 16bit (R/W) */
34 #define U300_SYSCON_PMC1LR 0x007C
35 #define U300_SYSCON_PMC1LR_MASK 0xFFFF
36 #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
37 #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
38 #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
39 /* For BS335 */
40 #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
41 #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
42 /* For BS365 */
43 #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
44 #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
45 /* Common defs */
46 #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
47 #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
48 #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
49 #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
50 #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
51 #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
52 #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
53 #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
54 #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
55 #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
56 #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
57 #define U300_SYSCON_PMC1LR_ETM_APP 0x0100
58 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
59 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
60 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
61 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
62 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
63 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
64 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
65 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
66 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
67 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
68 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
69 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
70 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
71 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
72 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
73 #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
74 #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
75 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
76 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
77 #define U300_SYSCON_PMC1LR_EMIF_1 0x0003
78 /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
79 #define U300_SYSCON_PMC1HR 0x007E
80 #define U300_SYSCON_PMC1HR_MASK 0xFFFF
81 #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
82 #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
83 #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
84 #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
85 #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
86 #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
87 #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
88 #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
89 #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
90 #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
91 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
92 #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
93 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
94 #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
95 #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
96 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
97 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
98 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
99 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
100 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
101 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
102 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
103 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
104 #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
105 #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
106 #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
107 #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
108 #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
109 #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
110 #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
111 #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
112 #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
113 #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
114 #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
115 #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
116 #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
117 #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
118 /* Padmux 2 control */
119 #define U300_SYSCON_PMC2R 0x100
120 #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
121 #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
122 #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
123 #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
124 #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
125 #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
126 #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
127 #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
128 #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
129 #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
130 #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
131 #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
132 #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
133 #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
134 #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
135 #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
136 #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
137 #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
138 #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
139 #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
140 #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
141 #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
142 #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
143 #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
144 #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
145 /* TODO: More SYSCON registers missing */
146 #define U300_SYSCON_PMC3R 0x10C
147 #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
148 #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
149 #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
150 #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
151 /* TODO: Missing other configs */
152 #define U300_SYSCON_PMC4R 0x168
153 #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
154 #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
155 #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
156 #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
157 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
158 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
159 #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
160 #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
161 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
162 #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
163 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
164 #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
165 #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
166 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
167 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
168 #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
169
170 #define DRIVER_NAME "pinctrl-u300"
171
172 /*
173 * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
174 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
175 * Data taken from the PadRing chart, arranged like this:
176 *
177 * 0 ..... 104
178 * 466 105
179 * . .
180 * . .
181 * 358 224
182 * 357 .... 225
183 */
184 #define U300_NUM_PADS 467
185
186 /* Pad names for the pinmux subsystem */
187 static const struct pinctrl_pin_desc u300_pads[] = {
188 /* Pads along the top edge of the chip */
189 PINCTRL_PIN(0, "P PAD VDD 28"),
190 PINCTRL_PIN(1, "P PAD GND 28"),
191 PINCTRL_PIN(2, "PO SIM RST N"),
192 PINCTRL_PIN(3, "VSSIO 25"),
193 PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
194 PINCTRL_PIN(5, "PWR VSSCOMMON"),
195 PINCTRL_PIN(6, "PI ADC I1 POS"),
196 PINCTRL_PIN(7, "PI ADC I1 NEG"),
197 PINCTRL_PIN(8, "PWR VSSAD0"),
198 PINCTRL_PIN(9, "PWR VCCAD0"),
199 PINCTRL_PIN(10, "PI ADC Q1 NEG"),
200 PINCTRL_PIN(11, "PI ADC Q1 POS"),
201 PINCTRL_PIN(12, "PWR VDDAD"),
202 PINCTRL_PIN(13, "PWR GNDAD"),
203 PINCTRL_PIN(14, "PI ADC I2 POS"),
204 PINCTRL_PIN(15, "PI ADC I2 NEG"),
205 PINCTRL_PIN(16, "PWR VSSAD1"),
206 PINCTRL_PIN(17, "PWR VCCAD1"),
207 PINCTRL_PIN(18, "PI ADC Q2 NEG"),
208 PINCTRL_PIN(19, "PI ADC Q2 POS"),
209 PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
210 PINCTRL_PIN(21, "PWR VCCGPAD"),
211 PINCTRL_PIN(22, "PI TX POW"),
212 PINCTRL_PIN(23, "PWR VSSGPAD"),
213 PINCTRL_PIN(24, "PO DAC I POS"),
214 PINCTRL_PIN(25, "PO DAC I NEG"),
215 PINCTRL_PIN(26, "PO DAC Q POS"),
216 PINCTRL_PIN(27, "PO DAC Q NEG"),
217 PINCTRL_PIN(28, "PWR VSSDA"),
218 PINCTRL_PIN(29, "PWR VCCDA"),
219 PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
220 PINCTRL_PIN(31, "P PAD VDDIO 11"),
221 PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
222 PINCTRL_PIN(33, "PI PLL 26 VCONT"),
223 PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
224 PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
225 PINCTRL_PIN(36, "VDDA PLL ESD"),
226 PINCTRL_PIN(37, "VSSA PLL ESD"),
227 PINCTRL_PIN(38, "VSS PLL"),
228 PINCTRL_PIN(39, "VDDC PLL"),
229 PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
230 PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
231 PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
232 PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
233 PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
234 PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
235 PINCTRL_PIN(46, "P PAD VSSIO 11"),
236 PINCTRL_PIN(47, "P PAD VSSIO 12"),
237 PINCTRL_PIN(48, "PI POW RST N"),
238 PINCTRL_PIN(49, "VDDC IO"),
239 PINCTRL_PIN(50, "P PAD VDDIO 16"),
240 PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
241 PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
242 PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
243 PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
244 PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
245 PINCTRL_PIN(56, "PO GSM PA ENABLE"),
246 PINCTRL_PIN(57, "PO RF DATA STRB"),
247 PINCTRL_PIN(58, "PO RF DATA2"),
248 PINCTRL_PIN(59, "PIO RF DATA1"),
249 PINCTRL_PIN(60, "PIO RF DATA0"),
250 PINCTRL_PIN(61, "P PAD VDD 11"),
251 PINCTRL_PIN(62, "P PAD GND 11"),
252 PINCTRL_PIN(63, "P PAD VSSIO 16"),
253 PINCTRL_PIN(64, "P PAD VDDIO 18"),
254 PINCTRL_PIN(65, "PO RF CTRL STRB2"),
255 PINCTRL_PIN(66, "PO RF CTRL STRB1"),
256 PINCTRL_PIN(67, "PO RF CTRL STRB0"),
257 PINCTRL_PIN(68, "PIO RF CTRL DATA"),
258 PINCTRL_PIN(69, "PO RF CTRL CLK"),
259 PINCTRL_PIN(70, "PO TX ADC STRB"),
260 PINCTRL_PIN(71, "PO ANT SW 2"),
261 PINCTRL_PIN(72, "PO ANT SW 3"),
262 PINCTRL_PIN(73, "PO ANT SW 0"),
263 PINCTRL_PIN(74, "PO ANT SW 1"),
264 PINCTRL_PIN(75, "PO M CLKRQ"),
265 PINCTRL_PIN(76, "PI M CLK"),
266 PINCTRL_PIN(77, "PI RTC CLK"),
267 PINCTRL_PIN(78, "P PAD VDD 8"),
268 PINCTRL_PIN(79, "P PAD GND 8"),
269 PINCTRL_PIN(80, "P PAD VSSIO 13"),
270 PINCTRL_PIN(81, "P PAD VDDIO 13"),
271 PINCTRL_PIN(82, "PO SYS 1 CLK"),
272 PINCTRL_PIN(83, "PO SYS 2 CLK"),
273 PINCTRL_PIN(84, "PO SYS 0 CLK"),
274 PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
275 PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
276 PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
277 PINCTRL_PIN(88, "PO RESOUT2 RST N"),
278 PINCTRL_PIN(89, "PO RESOUT1 RST N"),
279 PINCTRL_PIN(90, "PO RESOUT0 RST N"),
280 PINCTRL_PIN(91, "PI SERVICE N"),
281 PINCTRL_PIN(92, "P PAD VDD 29"),
282 PINCTRL_PIN(93, "P PAD GND 29"),
283 PINCTRL_PIN(94, "P PAD VSSIO 8"),
284 PINCTRL_PIN(95, "P PAD VDDIO 8"),
285 PINCTRL_PIN(96, "PI EXT IRQ1 N"),
286 PINCTRL_PIN(97, "PI EXT IRQ0 N"),
287 PINCTRL_PIN(98, "PIO DC ON"),
288 PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
289 PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
290 PINCTRL_PIN(101, "P PAD VDD 12"),
291 PINCTRL_PIN(102, "P PAD GND 12"),
292 PINCTRL_PIN(103, "P PAD VSSIO 14"),
293 PINCTRL_PIN(104, "P PAD VDDIO 14"),
294 /* Pads along the right edge of the chip */
295 PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
296 PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
297 PINCTRL_PIN(107, "PO KEY OUT0"),
298 PINCTRL_PIN(108, "PO KEY OUT1"),
299 PINCTRL_PIN(109, "PO KEY OUT2"),
300 PINCTRL_PIN(110, "PO KEY OUT3"),
301 PINCTRL_PIN(111, "PO KEY OUT4"),
302 PINCTRL_PIN(112, "PI KEY IN0"),
303 PINCTRL_PIN(113, "PI KEY IN1"),
304 PINCTRL_PIN(114, "PI KEY IN2"),
305 PINCTRL_PIN(115, "P PAD VDDIO 15"),
306 PINCTRL_PIN(116, "P PAD VSSIO 15"),
307 PINCTRL_PIN(117, "P PAD GND 13"),
308 PINCTRL_PIN(118, "P PAD VDD 13"),
309 PINCTRL_PIN(119, "PI KEY IN3"),
310 PINCTRL_PIN(120, "PI KEY IN4"),
311 PINCTRL_PIN(121, "PI KEY IN5"),
312 PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
313 PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
314 PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
315 PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
316 PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
317 PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
318 PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
319 PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
320 PINCTRL_PIN(130, "P PAD VDD 17"),
321 PINCTRL_PIN(131, "P PAD GND 17"),
322 PINCTRL_PIN(132, "P PAD VSSIO 19"),
323 PINCTRL_PIN(133, "P PAD VDDIO 19"),
324 PINCTRL_PIN(134, "UART0 RTS"),
325 PINCTRL_PIN(135, "UART0 CTS"),
326 PINCTRL_PIN(136, "UART0 TX"),
327 PINCTRL_PIN(137, "UART0 RX"),
328 PINCTRL_PIN(138, "PIO ACC SPI DO"),
329 PINCTRL_PIN(139, "PIO ACC SPI DI"),
330 PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
331 PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
332 PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
333 PINCTRL_PIN(143, "PIO ACC SPI CLK"),
334 PINCTRL_PIN(144, "PO PDI EXT RST N"),
335 PINCTRL_PIN(145, "P PAD VDDIO 22"),
336 PINCTRL_PIN(146, "P PAD VSSIO 22"),
337 PINCTRL_PIN(147, "P PAD GND 18"),
338 PINCTRL_PIN(148, "P PAD VDD 18"),
339 PINCTRL_PIN(149, "PIO PDI C0"),
340 PINCTRL_PIN(150, "PIO PDI C1"),
341 PINCTRL_PIN(151, "PIO PDI C2"),
342 PINCTRL_PIN(152, "PIO PDI C3"),
343 PINCTRL_PIN(153, "PIO PDI C4"),
344 PINCTRL_PIN(154, "PIO PDI C5"),
345 PINCTRL_PIN(155, "PIO PDI D0"),
346 PINCTRL_PIN(156, "PIO PDI D1"),
347 PINCTRL_PIN(157, "PIO PDI D2"),
348 PINCTRL_PIN(158, "PIO PDI D3"),
349 PINCTRL_PIN(159, "P PAD VDDIO 21"),
350 PINCTRL_PIN(160, "P PAD VSSIO 21"),
351 PINCTRL_PIN(161, "PIO PDI D4"),
352 PINCTRL_PIN(162, "PIO PDI D5"),
353 PINCTRL_PIN(163, "PIO PDI D6"),
354 PINCTRL_PIN(164, "PIO PDI D7"),
355 PINCTRL_PIN(165, "PIO MS INS"),
356 PINCTRL_PIN(166, "MMC DATA DIR LS"),
357 PINCTRL_PIN(167, "MMC DATA 3"),
358 PINCTRL_PIN(168, "MMC DATA 2"),
359 PINCTRL_PIN(169, "MMC DATA 1"),
360 PINCTRL_PIN(170, "MMC DATA 0"),
361 PINCTRL_PIN(171, "MMC CMD DIR LS"),
362 PINCTRL_PIN(172, "P PAD VDD 27"),
363 PINCTRL_PIN(173, "P PAD GND 27"),
364 PINCTRL_PIN(174, "P PAD VSSIO 20"),
365 PINCTRL_PIN(175, "P PAD VDDIO 20"),
366 PINCTRL_PIN(176, "MMC CMD"),
367 PINCTRL_PIN(177, "MMC CLK"),
368 PINCTRL_PIN(178, "PIO APP GPIO 14"),
369 PINCTRL_PIN(179, "PIO APP GPIO 13"),
370 PINCTRL_PIN(180, "PIO APP GPIO 11"),
371 PINCTRL_PIN(181, "PIO APP GPIO 25"),
372 PINCTRL_PIN(182, "PIO APP GPIO 24"),
373 PINCTRL_PIN(183, "PIO APP GPIO 23"),
374 PINCTRL_PIN(184, "PIO APP GPIO 22"),
375 PINCTRL_PIN(185, "PIO APP GPIO 21"),
376 PINCTRL_PIN(186, "PIO APP GPIO 20"),
377 PINCTRL_PIN(187, "P PAD VDD 19"),
378 PINCTRL_PIN(188, "P PAD GND 19"),
379 PINCTRL_PIN(189, "P PAD VSSIO 23"),
380 PINCTRL_PIN(190, "P PAD VDDIO 23"),
381 PINCTRL_PIN(191, "PIO APP GPIO 19"),
382 PINCTRL_PIN(192, "PIO APP GPIO 18"),
383 PINCTRL_PIN(193, "PIO APP GPIO 17"),
384 PINCTRL_PIN(194, "PIO APP GPIO 16"),
385 PINCTRL_PIN(195, "PI CI D1"),
386 PINCTRL_PIN(196, "PI CI D0"),
387 PINCTRL_PIN(197, "PI CI HSYNC"),
388 PINCTRL_PIN(198, "PI CI VSYNC"),
389 PINCTRL_PIN(199, "PI CI EXT CLK"),
390 PINCTRL_PIN(200, "PO CI EXT RST N"),
391 PINCTRL_PIN(201, "P PAD VSSIO 43"),
392 PINCTRL_PIN(202, "P PAD VDDIO 43"),
393 PINCTRL_PIN(203, "PI CI D6"),
394 PINCTRL_PIN(204, "PI CI D7"),
395 PINCTRL_PIN(205, "PI CI D2"),
396 PINCTRL_PIN(206, "PI CI D3"),
397 PINCTRL_PIN(207, "PI CI D4"),
398 PINCTRL_PIN(208, "PI CI D5"),
399 PINCTRL_PIN(209, "PI CI D8"),
400 PINCTRL_PIN(210, "PI CI D9"),
401 PINCTRL_PIN(211, "P PAD VDD 20"),
402 PINCTRL_PIN(212, "P PAD GND 20"),
403 PINCTRL_PIN(213, "P PAD VSSIO 24"),
404 PINCTRL_PIN(214, "P PAD VDDIO 24"),
405 PINCTRL_PIN(215, "P PAD VDDIO 26"),
406 PINCTRL_PIN(216, "PO EMIF 1 A26"),
407 PINCTRL_PIN(217, "PO EMIF 1 A25"),
408 PINCTRL_PIN(218, "P PAD VSSIO 26"),
409 PINCTRL_PIN(219, "PO EMIF 1 A24"),
410 PINCTRL_PIN(220, "PO EMIF 1 A23"),
411 /* Pads along the bottom edge of the chip */
412 PINCTRL_PIN(221, "PO EMIF 1 A22"),
413 PINCTRL_PIN(222, "PO EMIF 1 A21"),
414 PINCTRL_PIN(223, "P PAD VDD 21"),
415 PINCTRL_PIN(224, "P PAD GND 21"),
416 PINCTRL_PIN(225, "P PAD VSSIO 27"),
417 PINCTRL_PIN(226, "P PAD VDDIO 27"),
418 PINCTRL_PIN(227, "PO EMIF 1 A20"),
419 PINCTRL_PIN(228, "PO EMIF 1 A19"),
420 PINCTRL_PIN(229, "PO EMIF 1 A18"),
421 PINCTRL_PIN(230, "PO EMIF 1 A17"),
422 PINCTRL_PIN(231, "P PAD VDDIO 28"),
423 PINCTRL_PIN(232, "P PAD VSSIO 28"),
424 PINCTRL_PIN(233, "PO EMIF 1 A16"),
425 PINCTRL_PIN(234, "PIO EMIF 1 D15"),
426 PINCTRL_PIN(235, "PO EMIF 1 A15"),
427 PINCTRL_PIN(236, "PIO EMIF 1 D14"),
428 PINCTRL_PIN(237, "P PAD VDD 22"),
429 PINCTRL_PIN(238, "P PAD GND 22"),
430 PINCTRL_PIN(239, "P PAD VSSIO 29"),
431 PINCTRL_PIN(240, "P PAD VDDIO 29"),
432 PINCTRL_PIN(241, "PO EMIF 1 A14"),
433 PINCTRL_PIN(242, "PIO EMIF 1 D13"),
434 PINCTRL_PIN(243, "PO EMIF 1 A13"),
435 PINCTRL_PIN(244, "PIO EMIF 1 D12"),
436 PINCTRL_PIN(245, "P PAD VSSIO 30"),
437 PINCTRL_PIN(246, "P PAD VDDIO 30"),
438 PINCTRL_PIN(247, "PO EMIF 1 A12"),
439 PINCTRL_PIN(248, "PIO EMIF 1 D11"),
440 PINCTRL_PIN(249, "PO EMIF 1 A11"),
441 PINCTRL_PIN(250, "PIO EMIF 1 D10"),
442 PINCTRL_PIN(251, "P PAD VSSIO 31"),
443 PINCTRL_PIN(252, "P PAD VDDIO 31"),
444 PINCTRL_PIN(253, "PO EMIF 1 A10"),
445 PINCTRL_PIN(254, "PIO EMIF 1 D09"),
446 PINCTRL_PIN(255, "PO EMIF 1 A09"),
447 PINCTRL_PIN(256, "P PAD VDDIO 32"),
448 PINCTRL_PIN(257, "P PAD VSSIO 32"),
449 PINCTRL_PIN(258, "P PAD GND 24"),
450 PINCTRL_PIN(259, "P PAD VDD 24"),
451 PINCTRL_PIN(260, "PIO EMIF 1 D08"),
452 PINCTRL_PIN(261, "PO EMIF 1 A08"),
453 PINCTRL_PIN(262, "PIO EMIF 1 D07"),
454 PINCTRL_PIN(263, "PO EMIF 1 A07"),
455 PINCTRL_PIN(264, "P PAD VDDIO 33"),
456 PINCTRL_PIN(265, "P PAD VSSIO 33"),
457 PINCTRL_PIN(266, "PIO EMIF 1 D06"),
458 PINCTRL_PIN(267, "PO EMIF 1 A06"),
459 PINCTRL_PIN(268, "PIO EMIF 1 D05"),
460 PINCTRL_PIN(269, "PO EMIF 1 A05"),
461 PINCTRL_PIN(270, "P PAD VDDIO 34"),
462 PINCTRL_PIN(271, "P PAD VSSIO 34"),
463 PINCTRL_PIN(272, "PIO EMIF 1 D04"),
464 PINCTRL_PIN(273, "PO EMIF 1 A04"),
465 PINCTRL_PIN(274, "PIO EMIF 1 D03"),
466 PINCTRL_PIN(275, "PO EMIF 1 A03"),
467 PINCTRL_PIN(276, "P PAD VDDIO 35"),
468 PINCTRL_PIN(277, "P PAD VSSIO 35"),
469 PINCTRL_PIN(278, "P PAD GND 23"),
470 PINCTRL_PIN(279, "P PAD VDD 23"),
471 PINCTRL_PIN(280, "PIO EMIF 1 D02"),
472 PINCTRL_PIN(281, "PO EMIF 1 A02"),
473 PINCTRL_PIN(282, "PIO EMIF 1 D01"),
474 PINCTRL_PIN(283, "PO EMIF 1 A01"),
475 PINCTRL_PIN(284, "P PAD VDDIO 36"),
476 PINCTRL_PIN(285, "P PAD VSSIO 36"),
477 PINCTRL_PIN(286, "PIO EMIF 1 D00"),
478 PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
479 PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
480 PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
481 PINCTRL_PIN(290, "P PAD VDDIO 37"),
482 PINCTRL_PIN(291, "P PAD VSSIO 37"),
483 PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
484 PINCTRL_PIN(293, "PO EMIF 1 OE N"),
485 PINCTRL_PIN(294, "PO EMIF 1 WE N"),
486 PINCTRL_PIN(295, "P PAD VDDIO 38"),
487 PINCTRL_PIN(296, "P PAD VSSIO 38"),
488 PINCTRL_PIN(297, "PO EMIF 1 CLK"),
489 PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
490 PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
491 PINCTRL_PIN(300, "P PAD VDDIO 42"),
492 PINCTRL_PIN(301, "P PAD VSSIO 42"),
493 PINCTRL_PIN(302, "P PAD GND 31"),
494 PINCTRL_PIN(303, "P PAD VDD 31"),
495 PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
496 PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
497 PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
498 PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
499 PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
500 PINCTRL_PIN(309, "P PAD VDD 25"),
501 PINCTRL_PIN(310, "P PAD GND 25"),
502 PINCTRL_PIN(311, "P PAD VSSIO 39"),
503 PINCTRL_PIN(312, "P PAD VDDIO 39"),
504 PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
505 PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
506 PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
507 PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
508 PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
509 PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
510 PINCTRL_PIN(319, "P PAD VDD 30"),
511 PINCTRL_PIN(320, "P PAD GND 30"),
512 PINCTRL_PIN(321, "P PAD VSSIO 44"),
513 PINCTRL_PIN(322, "P PAD VDDIO 44"),
514 PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
515 PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
516 PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
517 PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
518 PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
519 PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
520 PINCTRL_PIN(329, "P PAD VDD 26"),
521 PINCTRL_PIN(330, "P PAD GND 26"),
522 PINCTRL_PIN(331, "P PAD VSSIO 40"),
523 PINCTRL_PIN(332, "P PAD VDDIO 40"),
524 PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
525 PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
526 PINCTRL_PIN(335, "PO ETM TRACE CLK"),
527 PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
528 PINCTRL_PIN(337, "PIO ACC GPIO 33"),
529 PINCTRL_PIN(338, "PIO ACC GPIO 32"),
530 PINCTRL_PIN(339, "PIO ACC GPIO 30"),
531 PINCTRL_PIN(340, "PIO ACC GPIO 29"),
532 PINCTRL_PIN(341, "P PAD VDDIO 17"),
533 PINCTRL_PIN(342, "P PAD VSSIO 17"),
534 PINCTRL_PIN(343, "P PAD GND 15"),
535 PINCTRL_PIN(344, "P PAD VDD 15"),
536 PINCTRL_PIN(345, "PIO ACC GPIO 28"),
537 PINCTRL_PIN(346, "PIO ACC GPIO 27"),
538 PINCTRL_PIN(347, "PIO ACC GPIO 16"),
539 PINCTRL_PIN(348, "PI TAP TMS"),
540 PINCTRL_PIN(349, "PI TAP TDI"),
541 PINCTRL_PIN(350, "PO TAP TDO"),
542 PINCTRL_PIN(351, "PI TAP RST N"),
543 /* Pads along the left edge of the chip */
544 PINCTRL_PIN(352, "PI EMU MODE 0"),
545 PINCTRL_PIN(353, "PO TAP RET CLK"),
546 PINCTRL_PIN(354, "PI TAP CLK"),
547 PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
548 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
549 PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
550 PINCTRL_PIN(358, "P PAD VDDIO 1"),
551 PINCTRL_PIN(359, "P PAD VSSIO 1"),
552 PINCTRL_PIN(360, "P PAD GND 1"),
553 PINCTRL_PIN(361, "P PAD VDD 1"),
554 PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
555 PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
556 PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
557 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
558 PINCTRL_PIN(366, "PIO EMIF 0 D15"),
559 PINCTRL_PIN(367, "PO EMIF 0 A15"),
560 PINCTRL_PIN(368, "PIO EMIF 0 D14"),
561 PINCTRL_PIN(369, "PO EMIF 0 A14"),
562 PINCTRL_PIN(370, "PIO EMIF 0 D13"),
563 PINCTRL_PIN(371, "PO EMIF 0 A13"),
564 PINCTRL_PIN(372, "P PAD VDDIO 2"),
565 PINCTRL_PIN(373, "P PAD VSSIO 2"),
566 PINCTRL_PIN(374, "P PAD GND 2"),
567 PINCTRL_PIN(375, "P PAD VDD 2"),
568 PINCTRL_PIN(376, "PIO EMIF 0 D12"),
569 PINCTRL_PIN(377, "PO EMIF 0 A12"),
570 PINCTRL_PIN(378, "PIO EMIF 0 D11"),
571 PINCTRL_PIN(379, "PO EMIF 0 A11"),
572 PINCTRL_PIN(380, "PIO EMIF 0 D10"),
573 PINCTRL_PIN(381, "PO EMIF 0 A10"),
574 PINCTRL_PIN(382, "PIO EMIF 0 D09"),
575 PINCTRL_PIN(383, "PO EMIF 0 A09"),
576 PINCTRL_PIN(384, "PIO EMIF 0 D08"),
577 PINCTRL_PIN(385, "PO EMIF 0 A08"),
578 PINCTRL_PIN(386, "PIO EMIF 0 D07"),
579 PINCTRL_PIN(387, "PO EMIF 0 A07"),
580 PINCTRL_PIN(388, "P PAD VDDIO 3"),
581 PINCTRL_PIN(389, "P PAD VSSIO 3"),
582 PINCTRL_PIN(390, "P PAD GND 3"),
583 PINCTRL_PIN(391, "P PAD VDD 3"),
584 PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
585 PINCTRL_PIN(393, "PIO EMIF 0 D06"),
586 PINCTRL_PIN(394, "PO EMIF 0 A06"),
587 PINCTRL_PIN(395, "PIO EMIF 0 D05"),
588 PINCTRL_PIN(396, "PO EMIF 0 A05"),
589 PINCTRL_PIN(397, "PIO EMIF 0 D04"),
590 PINCTRL_PIN(398, "PO EMIF 0 A04"),
591 PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
592 PINCTRL_PIN(400, "PWR VDDCO AF"),
593 PINCTRL_PIN(401, "PWR EFUSE HV1"),
594 PINCTRL_PIN(402, "P PAD VSSIO 4"),
595 PINCTRL_PIN(403, "P PAD VDDIO 4"),
596 PINCTRL_PIN(404, "P PAD GND 4"),
597 PINCTRL_PIN(405, "P PAD VDD 4"),
598 PINCTRL_PIN(406, "PIO EMIF 0 D03"),
599 PINCTRL_PIN(407, "PO EMIF 0 A03"),
600 PINCTRL_PIN(408, "PWR EFUSE HV2"),
601 PINCTRL_PIN(409, "PWR EFUSE HV3"),
602 PINCTRL_PIN(410, "PIO EMIF 0 D02"),
603 PINCTRL_PIN(411, "PO EMIF 0 A02"),
604 PINCTRL_PIN(412, "PIO EMIF 0 D01"),
605 PINCTRL_PIN(413, "P PAD VDDIO 5"),
606 PINCTRL_PIN(414, "P PAD VSSIO 5"),
607 PINCTRL_PIN(415, "P PAD GND 5"),
608 PINCTRL_PIN(416, "P PAD VDD 5"),
609 PINCTRL_PIN(417, "PO EMIF 0 A01"),
610 PINCTRL_PIN(418, "PIO EMIF 0 D00"),
611 PINCTRL_PIN(419, "IF 0 SD CLK"),
612 PINCTRL_PIN(420, "APP SPI CLK"),
613 PINCTRL_PIN(421, "APP SPI DO"),
614 PINCTRL_PIN(422, "APP SPI DI"),
615 PINCTRL_PIN(423, "APP SPI CS0"),
616 PINCTRL_PIN(424, "APP SPI CS1"),
617 PINCTRL_PIN(425, "APP SPI CS2"),
618 PINCTRL_PIN(426, "PIO APP GPIO 10"),
619 PINCTRL_PIN(427, "P PAD VDDIO 41"),
620 PINCTRL_PIN(428, "P PAD VSSIO 41"),
621 PINCTRL_PIN(429, "P PAD GND 6"),
622 PINCTRL_PIN(430, "P PAD VDD 6"),
623 PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
624 PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
625 PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
626 PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
627 PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
628 PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
629 PINCTRL_PIN(437, "PIO USB PU"),
630 PINCTRL_PIN(438, "PIO USB SP"),
631 PINCTRL_PIN(439, "PIO USB DAT VP"),
632 PINCTRL_PIN(440, "PIO USB SE0 VM"),
633 PINCTRL_PIN(441, "PIO USB OE"),
634 PINCTRL_PIN(442, "PIO USB SUSP"),
635 PINCTRL_PIN(443, "P PAD VSSIO 6"),
636 PINCTRL_PIN(444, "P PAD VDDIO 6"),
637 PINCTRL_PIN(445, "PIO USB PUEN"),
638 PINCTRL_PIN(446, "PIO ACC UART0 RX"),
639 PINCTRL_PIN(447, "PIO ACC UART0 TX"),
640 PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
641 PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
642 PINCTRL_PIN(450, "PIO ACC UART3 RX"),
643 PINCTRL_PIN(451, "PIO ACC UART3 TX"),
644 PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
645 PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
646 PINCTRL_PIN(454, "PIO ACC IRDA TX"),
647 PINCTRL_PIN(455, "P PAD VDDIO 7"),
648 PINCTRL_PIN(456, "P PAD VSSIO 7"),
649 PINCTRL_PIN(457, "P PAD GND 7"),
650 PINCTRL_PIN(458, "P PAD VDD 7"),
651 PINCTRL_PIN(459, "PIO ACC IRDA RX"),
652 PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
653 PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
654 PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
655 PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
656 PINCTRL_PIN(464, "PO SIM CLK"),
657 PINCTRL_PIN(465, "PIO ACC IRDA SD"),
658 PINCTRL_PIN(466, "PIO SIM DATA"),
659 };
660
661 /**
662 * @dev: a pointer back to containing device
663 * @virtbase: the offset to the controller in virtual memory
664 */
665 struct u300_pmx {
666 struct device *dev;
667 struct pinctrl_dev *pctl;
668 void __iomem *virtbase;
669 };
670
671 /**
672 * u300_pmx_registers - the array of registers read/written for each pinmux
673 * shunt setting
674 */
675 static const u32 u300_pmx_registers[] = {
676 U300_SYSCON_PMC1LR,
677 U300_SYSCON_PMC1HR,
678 U300_SYSCON_PMC2R,
679 U300_SYSCON_PMC3R,
680 U300_SYSCON_PMC4R,
681 };
682
683 /**
684 * struct u300_pin_group - describes a U300 pin group
685 * @name: the name of this specific pin group
686 * @pins: an array of discrete physical pins used in this group, taken
687 * from the driver-local pin enumeration space
688 * @num_pins: the number of pins in this group array, i.e. the number of
689 * elements in .pins so we can iterate over that array
690 */
691 struct u300_pin_group {
692 const char *name;
693 const unsigned int *pins;
694 const unsigned num_pins;
695 };
696
697 /**
698 * struct pmx_onmask - mask bits to enable/disable padmux
699 * @mask: mask bits to disable
700 * @val: mask bits to enable
701 *
702 * onmask lazy dog:
703 * onmask = {
704 * {"PMC1LR" mask, "PMC1LR" value},
705 * {"PMC1HR" mask, "PMC1HR" value},
706 * {"PMC2R" mask, "PMC2R" value},
707 * {"PMC3R" mask, "PMC3R" value},
708 * {"PMC4R" mask, "PMC4R" value}
709 * }
710 */
711 struct u300_pmx_mask {
712 u16 mask;
713 u16 bits;
714 };
715
716 /* The chip power pins are VDD, GND, VDDIO and VSSIO */
717 static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
718 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
719 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
720 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
721 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
722 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
723 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
724 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
725 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
726 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
727 static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
728 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
729 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
730 417, 418 };
731 static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
732 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
733 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
734 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
735 304, 305, 306, 307, 308, 313, 314, 315 };
736 static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
737 static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
738 static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
739
740 static const struct u300_pmx_mask emif0_mask[] = {
741 {0, 0},
742 {0, 0},
743 {0, 0},
744 {0, 0},
745 {0, 0},
746 };
747
748 static const struct u300_pmx_mask emif1_mask[] = {
749 /*
750 * This connects the SDRAM to CS2 and a NAND flash to
751 * CS0 on the EMIF.
752 */
753 {
754 U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
755 U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
756 U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
757 U300_SYSCON_PMC1LR_EMIF_1_MASK,
758 U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
759 U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
760 U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
761 U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
762 },
763 {0, 0},
764 {0, 0},
765 {0, 0},
766 {0, 0},
767 };
768
769 static const struct u300_pmx_mask uart0_mask[] = {
770 {0, 0},
771 {
772 U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
773 U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
774 U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
775 U300_SYSCON_PMC1HR_APP_UART0_2_UART0
776 },
777 {0, 0},
778 {0, 0},
779 {0, 0},
780 };
781
782 static const struct u300_pmx_mask mmc0_mask[] = {
783 { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
784 {0, 0},
785 {0, 0},
786 {0, 0},
787 { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
788 U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
789 };
790
791 static const struct u300_pmx_mask spi0_mask[] = {
792 {0, 0},
793 {
794 U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
795 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
796 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
797 U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
798 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
799 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
800 },
801 {0, 0},
802 {0, 0},
803 {0, 0}
804 };
805
806 static const struct u300_pin_group u300_pin_groups[] = {
807 {
808 .name = "powergrp",
809 .pins = power_pins,
810 .num_pins = ARRAY_SIZE(power_pins),
811 },
812 {
813 .name = "emif0grp",
814 .pins = emif0_pins,
815 .num_pins = ARRAY_SIZE(emif0_pins),
816 },
817 {
818 .name = "emif1grp",
819 .pins = emif1_pins,
820 .num_pins = ARRAY_SIZE(emif1_pins),
821 },
822 {
823 .name = "uart0grp",
824 .pins = uart0_pins,
825 .num_pins = ARRAY_SIZE(uart0_pins),
826 },
827 {
828 .name = "mmc0grp",
829 .pins = mmc0_pins,
830 .num_pins = ARRAY_SIZE(mmc0_pins),
831 },
832 {
833 .name = "spi0grp",
834 .pins = spi0_pins,
835 .num_pins = ARRAY_SIZE(spi0_pins),
836 },
837 };
838
839 static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840 {
841 return ARRAY_SIZE(u300_pin_groups);
842 }
843
844 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
845 unsigned selector)
846 {
847 return u300_pin_groups[selector].name;
848 }
849
850 static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
851 const unsigned **pins,
852 unsigned *num_pins)
853 {
854 *pins = u300_pin_groups[selector].pins;
855 *num_pins = u300_pin_groups[selector].num_pins;
856 return 0;
857 }
858
859 static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
860 unsigned offset)
861 {
862 seq_printf(s, " " DRIVER_NAME);
863 }
864
865 static const struct pinctrl_ops u300_pctrl_ops = {
866 .get_groups_count = u300_get_groups_count,
867 .get_group_name = u300_get_group_name,
868 .get_group_pins = u300_get_group_pins,
869 .pin_dbg_show = u300_pin_dbg_show,
870 };
871
872 /*
873 * Here we define the available functions and their corresponding pin groups
874 */
875
876 /**
877 * struct u300_pmx_func - describes U300 pinmux functions
878 * @name: the name of this specific function
879 * @groups: corresponding pin groups
880 * @onmask: bits to set to enable this when doing pin muxing
881 */
882 struct u300_pmx_func {
883 const char *name;
884 const char * const *groups;
885 const unsigned num_groups;
886 const struct u300_pmx_mask *mask;
887 };
888
889 static const char * const powergrps[] = { "powergrp" };
890 static const char * const emif0grps[] = { "emif0grp" };
891 static const char * const emif1grps[] = { "emif1grp" };
892 static const char * const uart0grps[] = { "uart0grp" };
893 static const char * const mmc0grps[] = { "mmc0grp" };
894 static const char * const spi0grps[] = { "spi0grp" };
895
896 static const struct u300_pmx_func u300_pmx_functions[] = {
897 {
898 .name = "power",
899 .groups = powergrps,
900 .num_groups = ARRAY_SIZE(powergrps),
901 /* Mask is N/A */
902 },
903 {
904 .name = "emif0",
905 .groups = emif0grps,
906 .num_groups = ARRAY_SIZE(emif0grps),
907 .mask = emif0_mask,
908 },
909 {
910 .name = "emif1",
911 .groups = emif1grps,
912 .num_groups = ARRAY_SIZE(emif1grps),
913 .mask = emif1_mask,
914 },
915 {
916 .name = "uart0",
917 .groups = uart0grps,
918 .num_groups = ARRAY_SIZE(uart0grps),
919 .mask = uart0_mask,
920 },
921 {
922 .name = "mmc0",
923 .groups = mmc0grps,
924 .num_groups = ARRAY_SIZE(mmc0grps),
925 .mask = mmc0_mask,
926 },
927 {
928 .name = "spi0",
929 .groups = spi0grps,
930 .num_groups = ARRAY_SIZE(spi0grps),
931 .mask = spi0_mask,
932 },
933 };
934
935 static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
936 bool enable)
937 {
938 u16 regval, val, mask;
939 int i;
940 const struct u300_pmx_mask *upmx_mask;
941
942 upmx_mask = u300_pmx_functions[selector].mask;
943 for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
944 if (enable)
945 val = upmx_mask->bits;
946 else
947 val = 0;
948
949 mask = upmx_mask->mask;
950 if (mask != 0) {
951 regval = readw(upmx->virtbase + u300_pmx_registers[i]);
952 regval &= ~mask;
953 regval |= val;
954 writew(regval, upmx->virtbase + u300_pmx_registers[i]);
955 }
956 upmx_mask++;
957 }
958 }
959
960 static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
961 unsigned group)
962 {
963 struct u300_pmx *upmx;
964
965 /* There is nothing to do with the power pins */
966 if (selector == 0)
967 return 0;
968
969 upmx = pinctrl_dev_get_drvdata(pctldev);
970 u300_pmx_endisable(upmx, selector, true);
971
972 return 0;
973 }
974
975 static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
976 {
977 return ARRAY_SIZE(u300_pmx_functions);
978 }
979
980 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
981 unsigned selector)
982 {
983 return u300_pmx_functions[selector].name;
984 }
985
986 static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
987 const char * const **groups,
988 unsigned * const num_groups)
989 {
990 *groups = u300_pmx_functions[selector].groups;
991 *num_groups = u300_pmx_functions[selector].num_groups;
992 return 0;
993 }
994
995 static const struct pinmux_ops u300_pmx_ops = {
996 .get_functions_count = u300_pmx_get_funcs_count,
997 .get_function_name = u300_pmx_get_func_name,
998 .get_function_groups = u300_pmx_get_groups,
999 .set_mux = u300_pmx_set_mux,
1000 };
1001
1002 static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1003 unsigned long *config)
1004 {
1005 struct pinctrl_gpio_range *range =
1006 pinctrl_find_gpio_range_from_pin(pctldev, pin);
1007
1008 /* We get config for those pins we CAN get it for and that's it */
1009 if (!range)
1010 return -ENOTSUPP;
1011
1012 return u300_gpio_config_get(range->gc,
1013 (pin - range->pin_base + range->base),
1014 config);
1015 }
1016
1017 static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1018 unsigned long *configs, unsigned num_configs)
1019 {
1020 struct pinctrl_gpio_range *range =
1021 pinctrl_find_gpio_range_from_pin(pctldev, pin);
1022 int ret, i;
1023
1024 if (!range)
1025 return -EINVAL;
1026
1027 for (i = 0; i < num_configs; i++) {
1028 /* Note: none of these configurations take any argument */
1029 ret = u300_gpio_config_set(range->gc,
1030 (pin - range->pin_base + range->base),
1031 pinconf_to_config_param(configs[i]));
1032 if (ret)
1033 return ret;
1034 } /* for each config */
1035
1036 return 0;
1037 }
1038
1039 static const struct pinconf_ops u300_pconf_ops = {
1040 .is_generic = true,
1041 .pin_config_get = u300_pin_config_get,
1042 .pin_config_set = u300_pin_config_set,
1043 };
1044
1045 static struct pinctrl_desc u300_pmx_desc = {
1046 .name = DRIVER_NAME,
1047 .pins = u300_pads,
1048 .npins = ARRAY_SIZE(u300_pads),
1049 .pctlops = &u300_pctrl_ops,
1050 .pmxops = &u300_pmx_ops,
1051 .confops = &u300_pconf_ops,
1052 .owner = THIS_MODULE,
1053 };
1054
1055 static int u300_pmx_probe(struct platform_device *pdev)
1056 {
1057 struct u300_pmx *upmx;
1058
1059 /* Create state holders etc for this driver */
1060 upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1061 if (!upmx)
1062 return -ENOMEM;
1063
1064 upmx->dev = &pdev->dev;
1065
1066 upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
1067 if (IS_ERR(upmx->virtbase))
1068 return PTR_ERR(upmx->virtbase);
1069
1070 upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
1071 if (IS_ERR(upmx->pctl)) {
1072 dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1073 return PTR_ERR(upmx->pctl);
1074 }
1075
1076 platform_set_drvdata(pdev, upmx);
1077
1078 dev_info(&pdev->dev, "initialized U300 pin control driver\n");
1079
1080 return 0;
1081 }
1082
1083 static const struct of_device_id u300_pinctrl_match[] = {
1084 { .compatible = "stericsson,pinctrl-u300" },
1085 {},
1086 };
1087
1088
1089 static struct platform_driver u300_pmx_driver = {
1090 .driver = {
1091 .name = DRIVER_NAME,
1092 .of_match_table = u300_pinctrl_match,
1093 },
1094 .probe = u300_pmx_probe,
1095 };
1096
1097 static int __init u300_pmx_init(void)
1098 {
1099 return platform_driver_register(&u300_pmx_driver);
1100 }
1101 arch_initcall(u300_pmx_init);
1102
1103 static void __exit u300_pmx_exit(void)
1104 {
1105 platform_driver_unregister(&u300_pmx_driver);
1106 }
1107 module_exit(u300_pmx_exit);
1108
1109 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1110 MODULE_DESCRIPTION("U300 pin control driver");
1111 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support