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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-sm8250.c
blobaf144e724bd9c61e2ce9045b1e04e4b3d55935ed
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10
11 #include "pinctrl-msm.h"
12
13 static const char * const sm8250_tiles[] = {
14 "west",
15 "south",
16 "north",
17 };
18
19 enum {
20 WEST,
21 SOUTH,
22 NORTH,
23 };
24
25 #define FUNCTION(fname) \
26 [msm_mux_##fname] = { \
27 .name = #fname, \
28 .groups = fname##_groups, \
29 .ngroups = ARRAY_SIZE(fname##_groups), \
30 }
31
32 #define REG_SIZE 0x1000
33 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
34 { \
35 .name = "gpio" #id, \
36 .pins = gpio##id##_pins, \
37 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
38 .funcs = (int[]){ \
39 msm_mux_gpio, /* gpio mode */ \
40 msm_mux_##f1, \
41 msm_mux_##f2, \
42 msm_mux_##f3, \
43 msm_mux_##f4, \
44 msm_mux_##f5, \
45 msm_mux_##f6, \
46 msm_mux_##f7, \
47 msm_mux_##f8, \
48 msm_mux_##f9 \
49 }, \
50 .nfuncs = 10, \
51 .ctl_reg = REG_SIZE * id, \
52 .io_reg = REG_SIZE * id + 0x4, \
53 .intr_cfg_reg = REG_SIZE * id + 0x8, \
54 .intr_status_reg = REG_SIZE * id + 0xc, \
55 .intr_target_reg = REG_SIZE * id + 0x8, \
56 .tile = _tile, \
57 .mux_bit = 2, \
58 .pull_bit = 0, \
59 .drv_bit = 6, \
60 .oe_bit = 9, \
61 .in_bit = 0, \
62 .out_bit = 1, \
63 .intr_enable_bit = 0, \
64 .intr_status_bit = 0, \
65 .intr_target_bit = 5, \
66 .intr_target_kpss_val = 3, \
67 .intr_raw_status_bit = 4, \
68 .intr_polarity_bit = 1, \
69 .intr_detection_bit = 2, \
70 .intr_detection_width = 2, \
71 }
72
73 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
74 { \
75 .name = #pg_name, \
76 .pins = pg_name##_pins, \
77 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
78 .ctl_reg = ctl, \
79 .io_reg = 0, \
80 .intr_cfg_reg = 0, \
81 .intr_status_reg = 0, \
82 .intr_target_reg = 0, \
83 .tile = NORTH, \
84 .mux_bit = -1, \
85 .pull_bit = pull, \
86 .drv_bit = drv, \
87 .oe_bit = -1, \
88 .in_bit = -1, \
89 .out_bit = -1, \
90 .intr_enable_bit = -1, \
91 .intr_status_bit = -1, \
92 .intr_target_bit = -1, \
93 .intr_raw_status_bit = -1, \
94 .intr_polarity_bit = -1, \
95 .intr_detection_bit = -1, \
96 .intr_detection_width = -1, \
97 }
98
99 #define UFS_RESET(pg_name, offset) \
100 { \
101 .name = #pg_name, \
102 .pins = pg_name##_pins, \
103 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
104 .ctl_reg = offset, \
105 .io_reg = offset + 0x4, \
106 .intr_cfg_reg = 0, \
107 .intr_status_reg = 0, \
108 .intr_target_reg = 0, \
109 .tile = SOUTH, \
110 .mux_bit = -1, \
111 .pull_bit = 3, \
112 .drv_bit = 0, \
113 .oe_bit = -1, \
114 .in_bit = -1, \
115 .out_bit = 0, \
116 .intr_enable_bit = -1, \
117 .intr_status_bit = -1, \
118 .intr_target_bit = -1, \
119 .intr_raw_status_bit = -1, \
120 .intr_polarity_bit = -1, \
121 .intr_detection_bit = -1, \
122 .intr_detection_width = -1, \
123 }
124
125 static const struct pinctrl_pin_desc sm8250_pins[] = {
126 PINCTRL_PIN(0, "GPIO_0"),
127 PINCTRL_PIN(1, "GPIO_1"),
128 PINCTRL_PIN(2, "GPIO_2"),
129 PINCTRL_PIN(3, "GPIO_3"),
130 PINCTRL_PIN(4, "GPIO_4"),
131 PINCTRL_PIN(5, "GPIO_5"),
132 PINCTRL_PIN(6, "GPIO_6"),
133 PINCTRL_PIN(7, "GPIO_7"),
134 PINCTRL_PIN(8, "GPIO_8"),
135 PINCTRL_PIN(9, "GPIO_9"),
136 PINCTRL_PIN(10, "GPIO_10"),
137 PINCTRL_PIN(11, "GPIO_11"),
138 PINCTRL_PIN(12, "GPIO_12"),
139 PINCTRL_PIN(13, "GPIO_13"),
140 PINCTRL_PIN(14, "GPIO_14"),
141 PINCTRL_PIN(15, "GPIO_15"),
142 PINCTRL_PIN(16, "GPIO_16"),
143 PINCTRL_PIN(17, "GPIO_17"),
144 PINCTRL_PIN(18, "GPIO_18"),
145 PINCTRL_PIN(19, "GPIO_19"),
146 PINCTRL_PIN(20, "GPIO_20"),
147 PINCTRL_PIN(21, "GPIO_21"),
148 PINCTRL_PIN(22, "GPIO_22"),
149 PINCTRL_PIN(23, "GPIO_23"),
150 PINCTRL_PIN(24, "GPIO_24"),
151 PINCTRL_PIN(25, "GPIO_25"),
152 PINCTRL_PIN(26, "GPIO_26"),
153 PINCTRL_PIN(27, "GPIO_27"),
154 PINCTRL_PIN(28, "GPIO_28"),
155 PINCTRL_PIN(29, "GPIO_29"),
156 PINCTRL_PIN(30, "GPIO_30"),
157 PINCTRL_PIN(31, "GPIO_31"),
158 PINCTRL_PIN(32, "GPIO_32"),
159 PINCTRL_PIN(33, "GPIO_33"),
160 PINCTRL_PIN(34, "GPIO_34"),
161 PINCTRL_PIN(35, "GPIO_35"),
162 PINCTRL_PIN(36, "GPIO_36"),
163 PINCTRL_PIN(37, "GPIO_37"),
164 PINCTRL_PIN(38, "GPIO_38"),
165 PINCTRL_PIN(39, "GPIO_39"),
166 PINCTRL_PIN(40, "GPIO_40"),
167 PINCTRL_PIN(41, "GPIO_41"),
168 PINCTRL_PIN(42, "GPIO_42"),
169 PINCTRL_PIN(43, "GPIO_43"),
170 PINCTRL_PIN(44, "GPIO_44"),
171 PINCTRL_PIN(45, "GPIO_45"),
172 PINCTRL_PIN(46, "GPIO_46"),
173 PINCTRL_PIN(47, "GPIO_47"),
174 PINCTRL_PIN(48, "GPIO_48"),
175 PINCTRL_PIN(49, "GPIO_49"),
176 PINCTRL_PIN(50, "GPIO_50"),
177 PINCTRL_PIN(51, "GPIO_51"),
178 PINCTRL_PIN(52, "GPIO_52"),
179 PINCTRL_PIN(53, "GPIO_53"),
180 PINCTRL_PIN(54, "GPIO_54"),
181 PINCTRL_PIN(55, "GPIO_55"),
182 PINCTRL_PIN(56, "GPIO_56"),
183 PINCTRL_PIN(57, "GPIO_57"),
184 PINCTRL_PIN(58, "GPIO_58"),
185 PINCTRL_PIN(59, "GPIO_59"),
186 PINCTRL_PIN(60, "GPIO_60"),
187 PINCTRL_PIN(61, "GPIO_61"),
188 PINCTRL_PIN(62, "GPIO_62"),
189 PINCTRL_PIN(63, "GPIO_63"),
190 PINCTRL_PIN(64, "GPIO_64"),
191 PINCTRL_PIN(65, "GPIO_65"),
192 PINCTRL_PIN(66, "GPIO_66"),
193 PINCTRL_PIN(67, "GPIO_67"),
194 PINCTRL_PIN(68, "GPIO_68"),
195 PINCTRL_PIN(69, "GPIO_69"),
196 PINCTRL_PIN(70, "GPIO_70"),
197 PINCTRL_PIN(71, "GPIO_71"),
198 PINCTRL_PIN(72, "GPIO_72"),
199 PINCTRL_PIN(73, "GPIO_73"),
200 PINCTRL_PIN(74, "GPIO_74"),
201 PINCTRL_PIN(75, "GPIO_75"),
202 PINCTRL_PIN(76, "GPIO_76"),
203 PINCTRL_PIN(77, "GPIO_77"),
204 PINCTRL_PIN(78, "GPIO_78"),
205 PINCTRL_PIN(79, "GPIO_79"),
206 PINCTRL_PIN(80, "GPIO_80"),
207 PINCTRL_PIN(81, "GPIO_81"),
208 PINCTRL_PIN(82, "GPIO_82"),
209 PINCTRL_PIN(83, "GPIO_83"),
210 PINCTRL_PIN(84, "GPIO_84"),
211 PINCTRL_PIN(85, "GPIO_85"),
212 PINCTRL_PIN(86, "GPIO_86"),
213 PINCTRL_PIN(87, "GPIO_87"),
214 PINCTRL_PIN(88, "GPIO_88"),
215 PINCTRL_PIN(89, "GPIO_89"),
216 PINCTRL_PIN(90, "GPIO_90"),
217 PINCTRL_PIN(91, "GPIO_91"),
218 PINCTRL_PIN(92, "GPIO_92"),
219 PINCTRL_PIN(93, "GPIO_93"),
220 PINCTRL_PIN(94, "GPIO_94"),
221 PINCTRL_PIN(95, "GPIO_95"),
222 PINCTRL_PIN(96, "GPIO_96"),
223 PINCTRL_PIN(97, "GPIO_97"),
224 PINCTRL_PIN(98, "GPIO_98"),
225 PINCTRL_PIN(99, "GPIO_99"),
226 PINCTRL_PIN(100, "GPIO_100"),
227 PINCTRL_PIN(101, "GPIO_101"),
228 PINCTRL_PIN(102, "GPIO_102"),
229 PINCTRL_PIN(103, "GPIO_103"),
230 PINCTRL_PIN(104, "GPIO_104"),
231 PINCTRL_PIN(105, "GPIO_105"),
232 PINCTRL_PIN(106, "GPIO_106"),
233 PINCTRL_PIN(107, "GPIO_107"),
234 PINCTRL_PIN(108, "GPIO_108"),
235 PINCTRL_PIN(109, "GPIO_109"),
236 PINCTRL_PIN(110, "GPIO_110"),
237 PINCTRL_PIN(111, "GPIO_111"),
238 PINCTRL_PIN(112, "GPIO_112"),
239 PINCTRL_PIN(113, "GPIO_113"),
240 PINCTRL_PIN(114, "GPIO_114"),
241 PINCTRL_PIN(115, "GPIO_115"),
242 PINCTRL_PIN(116, "GPIO_116"),
243 PINCTRL_PIN(117, "GPIO_117"),
244 PINCTRL_PIN(118, "GPIO_118"),
245 PINCTRL_PIN(119, "GPIO_119"),
246 PINCTRL_PIN(120, "GPIO_120"),
247 PINCTRL_PIN(121, "GPIO_121"),
248 PINCTRL_PIN(122, "GPIO_122"),
249 PINCTRL_PIN(123, "GPIO_123"),
250 PINCTRL_PIN(124, "GPIO_124"),
251 PINCTRL_PIN(125, "GPIO_125"),
252 PINCTRL_PIN(126, "GPIO_126"),
253 PINCTRL_PIN(127, "GPIO_127"),
254 PINCTRL_PIN(128, "GPIO_128"),
255 PINCTRL_PIN(129, "GPIO_129"),
256 PINCTRL_PIN(130, "GPIO_130"),
257 PINCTRL_PIN(131, "GPIO_131"),
258 PINCTRL_PIN(132, "GPIO_132"),
259 PINCTRL_PIN(133, "GPIO_133"),
260 PINCTRL_PIN(134, "GPIO_134"),
261 PINCTRL_PIN(135, "GPIO_135"),
262 PINCTRL_PIN(136, "GPIO_136"),
263 PINCTRL_PIN(137, "GPIO_137"),
264 PINCTRL_PIN(138, "GPIO_138"),
265 PINCTRL_PIN(139, "GPIO_139"),
266 PINCTRL_PIN(140, "GPIO_140"),
267 PINCTRL_PIN(141, "GPIO_141"),
268 PINCTRL_PIN(142, "GPIO_142"),
269 PINCTRL_PIN(143, "GPIO_143"),
270 PINCTRL_PIN(144, "GPIO_144"),
271 PINCTRL_PIN(145, "GPIO_145"),
272 PINCTRL_PIN(146, "GPIO_146"),
273 PINCTRL_PIN(147, "GPIO_147"),
274 PINCTRL_PIN(148, "GPIO_148"),
275 PINCTRL_PIN(149, "GPIO_149"),
276 PINCTRL_PIN(150, "GPIO_150"),
277 PINCTRL_PIN(151, "GPIO_151"),
278 PINCTRL_PIN(152, "GPIO_152"),
279 PINCTRL_PIN(153, "GPIO_153"),
280 PINCTRL_PIN(154, "GPIO_154"),
281 PINCTRL_PIN(155, "GPIO_155"),
282 PINCTRL_PIN(156, "GPIO_156"),
283 PINCTRL_PIN(157, "GPIO_157"),
284 PINCTRL_PIN(158, "GPIO_158"),
285 PINCTRL_PIN(159, "GPIO_159"),
286 PINCTRL_PIN(160, "GPIO_160"),
287 PINCTRL_PIN(161, "GPIO_161"),
288 PINCTRL_PIN(162, "GPIO_162"),
289 PINCTRL_PIN(163, "GPIO_163"),
290 PINCTRL_PIN(164, "GPIO_164"),
291 PINCTRL_PIN(165, "GPIO_165"),
292 PINCTRL_PIN(166, "GPIO_166"),
293 PINCTRL_PIN(167, "GPIO_167"),
294 PINCTRL_PIN(168, "GPIO_168"),
295 PINCTRL_PIN(169, "GPIO_169"),
296 PINCTRL_PIN(170, "GPIO_170"),
297 PINCTRL_PIN(171, "GPIO_171"),
298 PINCTRL_PIN(172, "GPIO_172"),
299 PINCTRL_PIN(173, "GPIO_173"),
300 PINCTRL_PIN(174, "GPIO_174"),
301 PINCTRL_PIN(175, "GPIO_175"),
302 PINCTRL_PIN(176, "GPIO_176"),
303 PINCTRL_PIN(177, "GPIO_177"),
304 PINCTRL_PIN(178, "GPIO_178"),
305 PINCTRL_PIN(179, "GPIO_179"),
306 PINCTRL_PIN(180, "SDC2_CLK"),
307 PINCTRL_PIN(181, "SDC2_CMD"),
308 PINCTRL_PIN(182, "SDC2_DATA"),
309 PINCTRL_PIN(183, "UFS_RESET"),
310 };
311
312 #define DECLARE_MSM_GPIO_PINS(pin) \
313 static const unsigned int gpio##pin##_pins[] = { pin }
314 DECLARE_MSM_GPIO_PINS(0);
315 DECLARE_MSM_GPIO_PINS(1);
316 DECLARE_MSM_GPIO_PINS(2);
317 DECLARE_MSM_GPIO_PINS(3);
318 DECLARE_MSM_GPIO_PINS(4);
319 DECLARE_MSM_GPIO_PINS(5);
320 DECLARE_MSM_GPIO_PINS(6);
321 DECLARE_MSM_GPIO_PINS(7);
322 DECLARE_MSM_GPIO_PINS(8);
323 DECLARE_MSM_GPIO_PINS(9);
324 DECLARE_MSM_GPIO_PINS(10);
325 DECLARE_MSM_GPIO_PINS(11);
326 DECLARE_MSM_GPIO_PINS(12);
327 DECLARE_MSM_GPIO_PINS(13);
328 DECLARE_MSM_GPIO_PINS(14);
329 DECLARE_MSM_GPIO_PINS(15);
330 DECLARE_MSM_GPIO_PINS(16);
331 DECLARE_MSM_GPIO_PINS(17);
332 DECLARE_MSM_GPIO_PINS(18);
333 DECLARE_MSM_GPIO_PINS(19);
334 DECLARE_MSM_GPIO_PINS(20);
335 DECLARE_MSM_GPIO_PINS(21);
336 DECLARE_MSM_GPIO_PINS(22);
337 DECLARE_MSM_GPIO_PINS(23);
338 DECLARE_MSM_GPIO_PINS(24);
339 DECLARE_MSM_GPIO_PINS(25);
340 DECLARE_MSM_GPIO_PINS(26);
341 DECLARE_MSM_GPIO_PINS(27);
342 DECLARE_MSM_GPIO_PINS(28);
343 DECLARE_MSM_GPIO_PINS(29);
344 DECLARE_MSM_GPIO_PINS(30);
345 DECLARE_MSM_GPIO_PINS(31);
346 DECLARE_MSM_GPIO_PINS(32);
347 DECLARE_MSM_GPIO_PINS(33);
348 DECLARE_MSM_GPIO_PINS(34);
349 DECLARE_MSM_GPIO_PINS(35);
350 DECLARE_MSM_GPIO_PINS(36);
351 DECLARE_MSM_GPIO_PINS(37);
352 DECLARE_MSM_GPIO_PINS(38);
353 DECLARE_MSM_GPIO_PINS(39);
354 DECLARE_MSM_GPIO_PINS(40);
355 DECLARE_MSM_GPIO_PINS(41);
356 DECLARE_MSM_GPIO_PINS(42);
357 DECLARE_MSM_GPIO_PINS(43);
358 DECLARE_MSM_GPIO_PINS(44);
359 DECLARE_MSM_GPIO_PINS(45);
360 DECLARE_MSM_GPIO_PINS(46);
361 DECLARE_MSM_GPIO_PINS(47);
362 DECLARE_MSM_GPIO_PINS(48);
363 DECLARE_MSM_GPIO_PINS(49);
364 DECLARE_MSM_GPIO_PINS(50);
365 DECLARE_MSM_GPIO_PINS(51);
366 DECLARE_MSM_GPIO_PINS(52);
367 DECLARE_MSM_GPIO_PINS(53);
368 DECLARE_MSM_GPIO_PINS(54);
369 DECLARE_MSM_GPIO_PINS(55);
370 DECLARE_MSM_GPIO_PINS(56);
371 DECLARE_MSM_GPIO_PINS(57);
372 DECLARE_MSM_GPIO_PINS(58);
373 DECLARE_MSM_GPIO_PINS(59);
374 DECLARE_MSM_GPIO_PINS(60);
375 DECLARE_MSM_GPIO_PINS(61);
376 DECLARE_MSM_GPIO_PINS(62);
377 DECLARE_MSM_GPIO_PINS(63);
378 DECLARE_MSM_GPIO_PINS(64);
379 DECLARE_MSM_GPIO_PINS(65);
380 DECLARE_MSM_GPIO_PINS(66);
381 DECLARE_MSM_GPIO_PINS(67);
382 DECLARE_MSM_GPIO_PINS(68);
383 DECLARE_MSM_GPIO_PINS(69);
384 DECLARE_MSM_GPIO_PINS(70);
385 DECLARE_MSM_GPIO_PINS(71);
386 DECLARE_MSM_GPIO_PINS(72);
387 DECLARE_MSM_GPIO_PINS(73);
388 DECLARE_MSM_GPIO_PINS(74);
389 DECLARE_MSM_GPIO_PINS(75);
390 DECLARE_MSM_GPIO_PINS(76);
391 DECLARE_MSM_GPIO_PINS(77);
392 DECLARE_MSM_GPIO_PINS(78);
393 DECLARE_MSM_GPIO_PINS(79);
394 DECLARE_MSM_GPIO_PINS(80);
395 DECLARE_MSM_GPIO_PINS(81);
396 DECLARE_MSM_GPIO_PINS(82);
397 DECLARE_MSM_GPIO_PINS(83);
398 DECLARE_MSM_GPIO_PINS(84);
399 DECLARE_MSM_GPIO_PINS(85);
400 DECLARE_MSM_GPIO_PINS(86);
401 DECLARE_MSM_GPIO_PINS(87);
402 DECLARE_MSM_GPIO_PINS(88);
403 DECLARE_MSM_GPIO_PINS(89);
404 DECLARE_MSM_GPIO_PINS(90);
405 DECLARE_MSM_GPIO_PINS(91);
406 DECLARE_MSM_GPIO_PINS(92);
407 DECLARE_MSM_GPIO_PINS(93);
408 DECLARE_MSM_GPIO_PINS(94);
409 DECLARE_MSM_GPIO_PINS(95);
410 DECLARE_MSM_GPIO_PINS(96);
411 DECLARE_MSM_GPIO_PINS(97);
412 DECLARE_MSM_GPIO_PINS(98);
413 DECLARE_MSM_GPIO_PINS(99);
414 DECLARE_MSM_GPIO_PINS(100);
415 DECLARE_MSM_GPIO_PINS(101);
416 DECLARE_MSM_GPIO_PINS(102);
417 DECLARE_MSM_GPIO_PINS(103);
418 DECLARE_MSM_GPIO_PINS(104);
419 DECLARE_MSM_GPIO_PINS(105);
420 DECLARE_MSM_GPIO_PINS(106);
421 DECLARE_MSM_GPIO_PINS(107);
422 DECLARE_MSM_GPIO_PINS(108);
423 DECLARE_MSM_GPIO_PINS(109);
424 DECLARE_MSM_GPIO_PINS(110);
425 DECLARE_MSM_GPIO_PINS(111);
426 DECLARE_MSM_GPIO_PINS(112);
427 DECLARE_MSM_GPIO_PINS(113);
428 DECLARE_MSM_GPIO_PINS(114);
429 DECLARE_MSM_GPIO_PINS(115);
430 DECLARE_MSM_GPIO_PINS(116);
431 DECLARE_MSM_GPIO_PINS(117);
432 DECLARE_MSM_GPIO_PINS(118);
433 DECLARE_MSM_GPIO_PINS(119);
434 DECLARE_MSM_GPIO_PINS(120);
435 DECLARE_MSM_GPIO_PINS(121);
436 DECLARE_MSM_GPIO_PINS(122);
437 DECLARE_MSM_GPIO_PINS(123);
438 DECLARE_MSM_GPIO_PINS(124);
439 DECLARE_MSM_GPIO_PINS(125);
440 DECLARE_MSM_GPIO_PINS(126);
441 DECLARE_MSM_GPIO_PINS(127);
442 DECLARE_MSM_GPIO_PINS(128);
443 DECLARE_MSM_GPIO_PINS(129);
444 DECLARE_MSM_GPIO_PINS(130);
445 DECLARE_MSM_GPIO_PINS(131);
446 DECLARE_MSM_GPIO_PINS(132);
447 DECLARE_MSM_GPIO_PINS(133);
448 DECLARE_MSM_GPIO_PINS(134);
449 DECLARE_MSM_GPIO_PINS(135);
450 DECLARE_MSM_GPIO_PINS(136);
451 DECLARE_MSM_GPIO_PINS(137);
452 DECLARE_MSM_GPIO_PINS(138);
453 DECLARE_MSM_GPIO_PINS(139);
454 DECLARE_MSM_GPIO_PINS(140);
455 DECLARE_MSM_GPIO_PINS(141);
456 DECLARE_MSM_GPIO_PINS(142);
457 DECLARE_MSM_GPIO_PINS(143);
458 DECLARE_MSM_GPIO_PINS(144);
459 DECLARE_MSM_GPIO_PINS(145);
460 DECLARE_MSM_GPIO_PINS(146);
461 DECLARE_MSM_GPIO_PINS(147);
462 DECLARE_MSM_GPIO_PINS(148);
463 DECLARE_MSM_GPIO_PINS(149);
464 DECLARE_MSM_GPIO_PINS(150);
465 DECLARE_MSM_GPIO_PINS(151);
466 DECLARE_MSM_GPIO_PINS(152);
467 DECLARE_MSM_GPIO_PINS(153);
468 DECLARE_MSM_GPIO_PINS(154);
469 DECLARE_MSM_GPIO_PINS(155);
470 DECLARE_MSM_GPIO_PINS(156);
471 DECLARE_MSM_GPIO_PINS(157);
472 DECLARE_MSM_GPIO_PINS(158);
473 DECLARE_MSM_GPIO_PINS(159);
474 DECLARE_MSM_GPIO_PINS(160);
475 DECLARE_MSM_GPIO_PINS(161);
476 DECLARE_MSM_GPIO_PINS(162);
477 DECLARE_MSM_GPIO_PINS(163);
478 DECLARE_MSM_GPIO_PINS(164);
479 DECLARE_MSM_GPIO_PINS(165);
480 DECLARE_MSM_GPIO_PINS(166);
481 DECLARE_MSM_GPIO_PINS(167);
482 DECLARE_MSM_GPIO_PINS(168);
483 DECLARE_MSM_GPIO_PINS(169);
484 DECLARE_MSM_GPIO_PINS(170);
485 DECLARE_MSM_GPIO_PINS(171);
486 DECLARE_MSM_GPIO_PINS(172);
487 DECLARE_MSM_GPIO_PINS(173);
488 DECLARE_MSM_GPIO_PINS(174);
489 DECLARE_MSM_GPIO_PINS(175);
490 DECLARE_MSM_GPIO_PINS(176);
491 DECLARE_MSM_GPIO_PINS(177);
492 DECLARE_MSM_GPIO_PINS(178);
493 DECLARE_MSM_GPIO_PINS(179);
494
495 static const unsigned int ufs_reset_pins[] = { 180 };
496 static const unsigned int sdc2_clk_pins[] = { 181 };
497 static const unsigned int sdc2_cmd_pins[] = { 182 };
498 static const unsigned int sdc2_data_pins[] = { 183 };
499
500 enum sm8250_functions {
501 msm_mux_aoss_cti,
502 msm_mux_atest,
503 msm_mux_audio_ref,
504 msm_mux_cam_mclk,
505 msm_mux_cci_async,
506 msm_mux_cci_i2c,
507 msm_mux_cci_timer0,
508 msm_mux_cci_timer1,
509 msm_mux_cci_timer2,
510 msm_mux_cci_timer3,
511 msm_mux_cci_timer4,
512 msm_mux_cri_trng,
513 msm_mux_cri_trng0,
514 msm_mux_cri_trng1,
515 msm_mux_dbg_out,
516 msm_mux_ddr_bist,
517 msm_mux_ddr_pxi0,
518 msm_mux_ddr_pxi1,
519 msm_mux_ddr_pxi2,
520 msm_mux_ddr_pxi3,
521 msm_mux_dp_hot,
522 msm_mux_dp_lcd,
523 msm_mux_gcc_gp1,
524 msm_mux_gcc_gp2,
525 msm_mux_gcc_gp3,
526 msm_mux_gpio,
527 msm_mux_ibi_i3c,
528 msm_mux_jitter_bist,
529 msm_mux_lpass_slimbus,
530 msm_mux_mdp_vsync,
531 msm_mux_mdp_vsync0,
532 msm_mux_mdp_vsync1,
533 msm_mux_mdp_vsync2,
534 msm_mux_mdp_vsync3,
535 msm_mux_mi2s0_data0,
536 msm_mux_mi2s0_data1,
537 msm_mux_mi2s0_sck,
538 msm_mux_mi2s0_ws,
539 msm_mux_mi2s1_data0,
540 msm_mux_mi2s1_data1,
541 msm_mux_mi2s1_sck,
542 msm_mux_mi2s1_ws,
543 msm_mux_mi2s2_data0,
544 msm_mux_mi2s2_data1,
545 msm_mux_mi2s2_sck,
546 msm_mux_mi2s2_ws,
547 msm_mux_pci_e0,
548 msm_mux_pci_e1,
549 msm_mux_pci_e2,
550 msm_mux_phase_flag,
551 msm_mux_pll_bist,
552 msm_mux_pll_bypassnl,
553 msm_mux_pll_clk,
554 msm_mux_pll_reset,
555 msm_mux_pri_mi2s,
556 msm_mux_prng_rosc,
557 msm_mux_qdss_cti,
558 msm_mux_qdss_gpio,
559 msm_mux_qspi0,
560 msm_mux_qspi1,
561 msm_mux_qspi2,
562 msm_mux_qspi3,
563 msm_mux_qspi_clk,
564 msm_mux_qspi_cs,
565 msm_mux_qup0,
566 msm_mux_qup1,
567 msm_mux_qup10,
568 msm_mux_qup11,
569 msm_mux_qup12,
570 msm_mux_qup13,
571 msm_mux_qup14,
572 msm_mux_qup15,
573 msm_mux_qup16,
574 msm_mux_qup17,
575 msm_mux_qup18,
576 msm_mux_qup19,
577 msm_mux_qup2,
578 msm_mux_qup3,
579 msm_mux_qup4,
580 msm_mux_qup5,
581 msm_mux_qup6,
582 msm_mux_qup7,
583 msm_mux_qup8,
584 msm_mux_qup9,
585 msm_mux_qup_l4,
586 msm_mux_qup_l5,
587 msm_mux_qup_l6,
588 msm_mux_sd_write,
589 msm_mux_sdc40,
590 msm_mux_sdc41,
591 msm_mux_sdc42,
592 msm_mux_sdc43,
593 msm_mux_sdc4_clk,
594 msm_mux_sdc4_cmd,
595 msm_mux_sec_mi2s,
596 msm_mux_sp_cmu,
597 msm_mux_tgu_ch0,
598 msm_mux_tgu_ch1,
599 msm_mux_tgu_ch2,
600 msm_mux_tgu_ch3,
601 msm_mux_tsense_pwm1,
602 msm_mux_tsense_pwm2,
603 msm_mux_tsif0_clk,
604 msm_mux_tsif0_data,
605 msm_mux_tsif0_en,
606 msm_mux_tsif0_error,
607 msm_mux_tsif0_sync,
608 msm_mux_tsif1_clk,
609 msm_mux_tsif1_data,
610 msm_mux_tsif1_en,
611 msm_mux_tsif1_error,
612 msm_mux_tsif1_sync,
613 msm_mux_usb2phy_ac,
614 msm_mux_usb_phy,
615 msm_mux_vsense_trigger,
616 msm_mux__,
617 };
618
619 static const char * const tsif1_data_groups[] = {
620 "gpio75",
621 };
622 static const char * const sdc41_groups[] = {
623 "gpio75",
624 };
625 static const char * const tsif1_sync_groups[] = {
626 "gpio76",
627 };
628 static const char * const sdc40_groups[] = {
629 "gpio76",
630 };
631 static const char * const aoss_cti_groups[] = {
632 "gpio77",
633 };
634 static const char * const phase_flag_groups[] = {
635 "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
636 "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77",
637 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
638 "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118",
639 "gpio119", "gpio120", "gpio122", "gpio124", "gpio125",
640 };
641 static const char * const sd_write_groups[] = {
642 "gpio78",
643 };
644 static const char * const pci_e0_groups[] = {
645 "gpio79", "gpio80",
646 };
647 static const char * const pci_e1_groups[] = {
648 "gpio82", "gpio83",
649 };
650 static const char * const pci_e2_groups[] = {
651 "gpio85", "gpio86",
652 };
653 static const char * const tgu_ch0_groups[] = {
654 "gpio85",
655 };
656 static const char * const atest_groups[] = {
657 "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34",
658 "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88",
659 "gpio89",
660 };
661 static const char * const tgu_ch3_groups[] = {
662 "gpio86",
663 };
664 static const char * const tsif1_error_groups[] = {
665 "gpio90",
666 };
667 static const char * const tgu_ch1_groups[] = {
668 "gpio90",
669 };
670 static const char * const tsif0_error_groups[] = {
671 "gpio91",
672 };
673 static const char * const tgu_ch2_groups[] = {
674 "gpio91",
675 };
676 static const char * const cam_mclk_groups[] = {
677 "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
678 };
679 static const char * const ddr_bist_groups[] = {
680 "gpio94", "gpio95", "gpio143", "gpio144",
681 };
682 static const char * const pll_bypassnl_groups[] = {
683 "gpio96",
684 };
685 static const char * const pll_reset_groups[] = {
686 "gpio97",
687 };
688 static const char * const cci_i2c_groups[] = {
689 "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
690 "gpio107", "gpio108",
691 };
692 static const char * const qdss_gpio_groups[] = {
693 "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
694 "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
695 "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160",
696 "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
697 "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172",
698 "gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
699 };
700 static const char * const gcc_gp1_groups[] = {
701 "gpio106", "gpio136",
702 };
703 static const char * const gcc_gp2_groups[] = {
704 "gpio107", "gpio137",
705 };
706 static const char * const gcc_gp3_groups[] = {
707 "gpio108", "gpio138",
708 };
709 static const char * const cci_timer0_groups[] = {
710 "gpio109",
711 };
712 static const char * const cci_timer1_groups[] = {
713 "gpio110",
714 };
715 static const char * const cci_timer2_groups[] = {
716 "gpio111",
717 };
718 static const char * const cci_timer3_groups[] = {
719 "gpio112",
720 };
721 static const char * const cci_async_groups[] = {
722 "gpio112", "gpio113", "gpio114",
723 };
724 static const char * const cci_timer4_groups[] = {
725 "gpio113",
726 };
727 static const char * const qup2_groups[] = {
728 "gpio115", "gpio116", "gpio117", "gpio118",
729 };
730 static const char * const qup3_groups[] = {
731 "gpio119", "gpio120", "gpio121", "gpio122",
732 };
733 static const char * const tsense_pwm1_groups[] = {
734 "gpio123",
735 };
736 static const char * const tsense_pwm2_groups[] = {
737 "gpio123",
738 };
739 static const char * const qup9_groups[] = {
740 "gpio125", "gpio126", "gpio127", "gpio128",
741 };
742 static const char * const qup10_groups[] = {
743 "gpio129", "gpio130", "gpio131", "gpio132",
744 };
745 static const char * const mi2s2_sck_groups[] = {
746 "gpio133",
747 };
748 static const char * const mi2s2_data0_groups[] = {
749 "gpio134",
750 };
751 static const char * const mi2s2_ws_groups[] = {
752 "gpio135",
753 };
754 static const char * const pri_mi2s_groups[] = {
755 "gpio136",
756 };
757 static const char * const sec_mi2s_groups[] = {
758 "gpio137",
759 };
760 static const char * const audio_ref_groups[] = {
761 "gpio137",
762 };
763 static const char * const mi2s2_data1_groups[] = {
764 "gpio137",
765 };
766 static const char * const mi2s0_sck_groups[] = {
767 "gpio138",
768 };
769 static const char * const mi2s0_data0_groups[] = {
770 "gpio139",
771 };
772 static const char * const mi2s0_data1_groups[] = {
773 "gpio140",
774 };
775 static const char * const mi2s0_ws_groups[] = {
776 "gpio141",
777 };
778 static const char * const lpass_slimbus_groups[] = {
779 "gpio142", "gpio143", "gpio144", "gpio145",
780 };
781 static const char * const mi2s1_sck_groups[] = {
782 "gpio142",
783 };
784 static const char * const mi2s1_data0_groups[] = {
785 "gpio143",
786 };
787 static const char * const mi2s1_data1_groups[] = {
788 "gpio144",
789 };
790 static const char * const mi2s1_ws_groups[] = {
791 "gpio145",
792 };
793 static const char * const cri_trng0_groups[] = {
794 "gpio159",
795 };
796 static const char * const cri_trng1_groups[] = {
797 "gpio160",
798 };
799 static const char * const cri_trng_groups[] = {
800 "gpio161",
801 };
802 static const char * const sp_cmu_groups[] = {
803 "gpio162",
804 };
805 static const char * const prng_rosc_groups[] = {
806 "gpio163",
807 };
808 static const char * const qup19_groups[] = {
809 "gpio0", "gpio1", "gpio2", "gpio3",
810 };
811 static const char * const gpio_groups[] = {
812 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
813 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
814 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
815 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
816 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
817 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
818 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
819 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
820 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
821 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
822 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
823 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
824 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
825 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
826 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
827 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
828 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
829 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
830 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
831 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
832 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
833 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
834 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
835 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
836 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
837 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
838 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
839 "gpio177", "gpio178", "gpio179",
840 };
841 static const char * const qdss_cti_groups[] = {
842 "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92",
843 "gpio93",
844 };
845 static const char * const qup1_groups[] = {
846 "gpio4", "gpio5", "gpio6", "gpio7",
847 };
848 static const char * const ibi_i3c_groups[] = {
849 "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40",
850 "gpio41",
851 };
852 static const char * const qup_l4_groups[] = {
853 "gpio6", "gpio14", "gpio46", "gpio123",
854 };
855 static const char * const qup_l5_groups[] = {
856 "gpio7", "gpio15", "gpio47", "gpio124",
857 };
858 static const char * const qup4_groups[] = {
859 "gpio8", "gpio9", "gpio10", "gpio11",
860 };
861 static const char * const qup5_groups[] = {
862 "gpio12", "gpio13", "gpio14", "gpio15",
863 };
864 static const char * const qup6_groups[] = {
865 "gpio16", "gpio17", "gpio18", "gpio19",
866 };
867 static const char * const qup7_groups[] = {
868 "gpio20", "gpio21", "gpio22", "gpio23",
869 };
870 static const char * const qup8_groups[] = {
871 "gpio24", "gpio25", "gpio26", "gpio27",
872 };
873 static const char * const qup0_groups[] = {
874 "gpio28", "gpio29", "gpio30", "gpio31",
875 };
876 static const char * const qup12_groups[] = {
877 "gpio32", "gpio33", "gpio34", "gpio35",
878 };
879 static const char * const qup13_groups[] = {
880 "gpio36", "gpio37", "gpio38", "gpio39",
881 };
882 static const char * const qup14_groups[] = {
883 "gpio40", "gpio41", "gpio42", "gpio43",
884 };
885 static const char * const ddr_pxi3_groups[] = {
886 "gpio40", "gpio43",
887 };
888 static const char * const ddr_pxi1_groups[] = {
889 "gpio41", "gpio42",
890 };
891 static const char * const vsense_trigger_groups[] = {
892 "gpio42",
893 };
894 static const char * const qup15_groups[] = {
895 "gpio44", "gpio45", "gpio46", "gpio47",
896 };
897 static const char * const dbg_out_groups[] = {
898 "gpio44",
899 };
900 static const char * const qup16_groups[] = {
901 "gpio48", "gpio49", "gpio50", "gpio51",
902 };
903 static const char * const qup17_groups[] = {
904 "gpio52", "gpio53", "gpio54", "gpio55",
905 };
906 static const char * const ddr_pxi0_groups[] = {
907 "gpio52", "gpio53",
908 };
909 static const char * const jitter_bist_groups[] = {
910 "gpio54",
911 };
912 static const char * const pll_bist_groups[] = {
913 "gpio55",
914 };
915 static const char * const ddr_pxi2_groups[] = {
916 "gpio55", "gpio56",
917 };
918 static const char * const qup18_groups[] = {
919 "gpio56", "gpio57", "gpio58", "gpio59",
920 };
921 static const char * const qup11_groups[] = {
922 "gpio60", "gpio61", "gpio62", "gpio63",
923 };
924 static const char * const usb2phy_ac_groups[] = {
925 "gpio64", "gpio90",
926 };
927 static const char * const qup_l6_groups[] = {
928 "gpio64", "gpio77", "gpio92", "gpio93",
929 };
930 static const char * const usb_phy_groups[] = {
931 "gpio65",
932 };
933 static const char * const pll_clk_groups[] = {
934 "gpio65",
935 };
936 static const char * const mdp_vsync_groups[] = {
937 "gpio66", "gpio67", "gpio68", "gpio122", "gpio124",
938 };
939 static const char * const dp_lcd_groups[] = {
940 "gpio67",
941 };
942 static const char * const dp_hot_groups[] = {
943 "gpio68",
944 };
945 static const char * const qspi_cs_groups[] = {
946 "gpio69", "gpio75",
947 };
948 static const char * const tsif0_clk_groups[] = {
949 "gpio69",
950 };
951 static const char * const qspi0_groups[] = {
952 "gpio70",
953 };
954 static const char * const tsif0_en_groups[] = {
955 "gpio70",
956 };
957 static const char * const mdp_vsync0_groups[] = {
958 "gpio70",
959 };
960 static const char * const mdp_vsync1_groups[] = {
961 "gpio70",
962 };
963 static const char * const mdp_vsync2_groups[] = {
964 "gpio70",
965 };
966 static const char * const mdp_vsync3_groups[] = {
967 "gpio70",
968 };
969 static const char * const qspi1_groups[] = {
970 "gpio71",
971 };
972 static const char * const tsif0_data_groups[] = {
973 "gpio71",
974 };
975 static const char * const sdc4_cmd_groups[] = {
976 "gpio71",
977 };
978 static const char * const qspi2_groups[] = {
979 "gpio72",
980 };
981 static const char * const tsif0_sync_groups[] = {
982 "gpio72",
983 };
984 static const char * const sdc43_groups[] = {
985 "gpio72",
986 };
987 static const char * const qspi_clk_groups[] = {
988 "gpio73",
989 };
990 static const char * const tsif1_clk_groups[] = {
991 "gpio73",
992 };
993 static const char * const sdc4_clk_groups[] = {
994 "gpio73",
995 };
996 static const char * const qspi3_groups[] = {
997 "gpio74",
998 };
999 static const char * const tsif1_en_groups[] = {
1000 "gpio74",
1001 };
1002 static const char * const sdc42_groups[] = {
1003 "gpio74",
1004 };
1005
1006 static const struct msm_function sm8250_functions[] = {
1007 FUNCTION(aoss_cti),
1008 FUNCTION(atest),
1009 FUNCTION(audio_ref),
1010 FUNCTION(cam_mclk),
1011 FUNCTION(cci_async),
1012 FUNCTION(cci_i2c),
1013 FUNCTION(cci_timer0),
1014 FUNCTION(cci_timer1),
1015 FUNCTION(cci_timer2),
1016 FUNCTION(cci_timer3),
1017 FUNCTION(cci_timer4),
1018 FUNCTION(cri_trng),
1019 FUNCTION(cri_trng0),
1020 FUNCTION(cri_trng1),
1021 FUNCTION(dbg_out),
1022 FUNCTION(ddr_bist),
1023 FUNCTION(ddr_pxi0),
1024 FUNCTION(ddr_pxi1),
1025 FUNCTION(ddr_pxi2),
1026 FUNCTION(ddr_pxi3),
1027 FUNCTION(dp_hot),
1028 FUNCTION(dp_lcd),
1029 FUNCTION(gcc_gp1),
1030 FUNCTION(gcc_gp2),
1031 FUNCTION(gcc_gp3),
1032 FUNCTION(gpio),
1033 FUNCTION(ibi_i3c),
1034 FUNCTION(jitter_bist),
1035 FUNCTION(lpass_slimbus),
1036 FUNCTION(mdp_vsync),
1037 FUNCTION(mdp_vsync0),
1038 FUNCTION(mdp_vsync1),
1039 FUNCTION(mdp_vsync2),
1040 FUNCTION(mdp_vsync3),
1041 FUNCTION(mi2s0_data0),
1042 FUNCTION(mi2s0_data1),
1043 FUNCTION(mi2s0_sck),
1044 FUNCTION(mi2s0_ws),
1045 FUNCTION(mi2s1_data0),
1046 FUNCTION(mi2s1_data1),
1047 FUNCTION(mi2s1_sck),
1048 FUNCTION(mi2s1_ws),
1049 FUNCTION(mi2s2_data0),
1050 FUNCTION(mi2s2_data1),
1051 FUNCTION(mi2s2_sck),
1052 FUNCTION(mi2s2_ws),
1053 FUNCTION(pci_e0),
1054 FUNCTION(pci_e1),
1055 FUNCTION(pci_e2),
1056 FUNCTION(phase_flag),
1057 FUNCTION(pll_bist),
1058 FUNCTION(pll_bypassnl),
1059 FUNCTION(pll_clk),
1060 FUNCTION(pll_reset),
1061 FUNCTION(pri_mi2s),
1062 FUNCTION(prng_rosc),
1063 FUNCTION(qdss_cti),
1064 FUNCTION(qdss_gpio),
1065 FUNCTION(qspi0),
1066 FUNCTION(qspi1),
1067 FUNCTION(qspi2),
1068 FUNCTION(qspi3),
1069 FUNCTION(qspi_clk),
1070 FUNCTION(qspi_cs),
1071 FUNCTION(qup0),
1072 FUNCTION(qup1),
1073 FUNCTION(qup10),
1074 FUNCTION(qup11),
1075 FUNCTION(qup12),
1076 FUNCTION(qup13),
1077 FUNCTION(qup14),
1078 FUNCTION(qup15),
1079 FUNCTION(qup16),
1080 FUNCTION(qup17),
1081 FUNCTION(qup18),
1082 FUNCTION(qup19),
1083 FUNCTION(qup2),
1084 FUNCTION(qup3),
1085 FUNCTION(qup4),
1086 FUNCTION(qup5),
1087 FUNCTION(qup6),
1088 FUNCTION(qup7),
1089 FUNCTION(qup8),
1090 FUNCTION(qup9),
1091 FUNCTION(qup_l4),
1092 FUNCTION(qup_l5),
1093 FUNCTION(qup_l6),
1094 FUNCTION(sd_write),
1095 FUNCTION(sdc40),
1096 FUNCTION(sdc41),
1097 FUNCTION(sdc42),
1098 FUNCTION(sdc43),
1099 FUNCTION(sdc4_clk),
1100 FUNCTION(sdc4_cmd),
1101 FUNCTION(sec_mi2s),
1102 FUNCTION(sp_cmu),
1103 FUNCTION(tgu_ch0),
1104 FUNCTION(tgu_ch1),
1105 FUNCTION(tgu_ch2),
1106 FUNCTION(tgu_ch3),
1107 FUNCTION(tsense_pwm1),
1108 FUNCTION(tsense_pwm2),
1109 FUNCTION(tsif0_clk),
1110 FUNCTION(tsif0_data),
1111 FUNCTION(tsif0_en),
1112 FUNCTION(tsif0_error),
1113 FUNCTION(tsif0_sync),
1114 FUNCTION(tsif1_clk),
1115 FUNCTION(tsif1_data),
1116 FUNCTION(tsif1_en),
1117 FUNCTION(tsif1_error),
1118 FUNCTION(tsif1_sync),
1119 FUNCTION(usb2phy_ac),
1120 FUNCTION(usb_phy),
1121 FUNCTION(vsense_trigger),
1122 };
1123
1124 /* Every pin is maintained as a single group, and missing or non-existing pin
1125 * would be maintained as dummy group to synchronize pin group index with
1126 * pin descriptor registered with pinctrl core.
1127 * Clients would not be able to request these dummy pin groups.
1128 */
1129 static const struct msm_pingroup sm8250_groups[] = {
1130 [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _),
1131 [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _),
1132 [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _),
1133 [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _),
1134 [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1135 [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1136 [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _),
1137 [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _),
1138 [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _),
1139 [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _),
1140 [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _),
1141 [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _),
1142 [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _),
1143 [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _),
1144 [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _),
1145 [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _),
1146 [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _),
1147 [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _),
1148 [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _),
1149 [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _),
1150 [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _),
1151 [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _),
1152 [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _),
1153 [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _),
1154 [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1155 [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1156 [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1157 [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1158 [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1159 [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1160 [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _),
1161 [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _),
1162 [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _),
1163 [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1164 [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1165 [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1166 [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1167 [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1168 [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _),
1169 [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _),
1170 [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _),
1171 [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _),
1172 [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _),
1173 [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _),
1174 [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _),
1175 [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _),
1176 [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _),
1177 [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _),
1178 [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1179 [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1180 [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1181 [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1182 [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1183 [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1184 [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _),
1185 [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _),
1186 [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _),
1187 [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _),
1188 [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _),
1189 [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _),
1190 [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _),
1191 [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _),
1192 [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _),
1193 [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _),
1194 [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _),
1195 [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _),
1196 [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
1197 [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
1198 [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _),
1199 [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _),
1200 [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _),
1201 [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _),
1202 [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _),
1203 [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _),
1204 [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _),
1205 [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _),
1206 [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _),
1207 [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _),
1208 [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _),
1209 [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1210 [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1211 [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1212 [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1213 [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1214 [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1215 [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _),
1216 [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _),
1217 [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _),
1218 [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _),
1219 [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _),
1220 [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _),
1221 [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _),
1222 [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1223 [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1224 [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1225 [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1226 [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _),
1227 [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _),
1228 [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1229 [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1230 [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1231 [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1232 [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1233 [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1234 [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1235 [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1236 [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _),
1237 [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1238 [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1239 [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _),
1240 [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _),
1241 [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _),
1242 [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _),
1243 [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _),
1244 [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _),
1245 [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1246 [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1247 [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1248 [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1249 [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1250 [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1251 [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _),
1252 [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _),
1253 [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1254 [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _),
1255 [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _),
1256 [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _),
1257 [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _),
1258 [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _),
1259 [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _),
1260 [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _),
1261 [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _),
1262 [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _),
1263 [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _),
1264 [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _),
1265 [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _),
1266 [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1267 [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _),
1268 [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _),
1269 [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _),
1270 [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _),
1271 [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _),
1272 [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _),
1273 [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _),
1274 [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _),
1275 [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _),
1276 [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1277 [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1278 [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1279 [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1280 [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _),
1281 [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _),
1282 [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _),
1283 [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _),
1284 [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _),
1285 [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _),
1286 [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _),
1287 [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _),
1288 [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _),
1289 [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _),
1290 [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
1291 [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
1292 [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _),
1293 [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
1294 [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1295 [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1296 [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1297 [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1298 [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1299 [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1300 [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1301 [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1302 [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1303 [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1304 [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1305 [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1306 [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1307 [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1308 [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
1309 [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
1310 [180] = UFS_RESET(ufs_reset, 0xb8000),
1311 [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
1312 [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
1313 [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
1314 };
1315
1316 static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = {
1317 { 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 },
1318 { 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 },
1319 { 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 37 },
1320 { 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 },
1321 { 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 },
1322 { 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 },
1323 { 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 },
1324 { 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 },
1325 { 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 },
1326 { 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 },
1327 { 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 },
1328 { 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 },
1329 { 142, 60 }, { 143, 61 }
1330 };
1331
1332 static const struct msm_pinctrl_soc_data sm8250_pinctrl = {
1333 .pins = sm8250_pins,
1334 .npins = ARRAY_SIZE(sm8250_pins),
1335 .functions = sm8250_functions,
1336 .nfunctions = ARRAY_SIZE(sm8250_functions),
1337 .groups = sm8250_groups,
1338 .ngroups = ARRAY_SIZE(sm8250_groups),
1339 .ngpios = 181,
1340 .tiles = sm8250_tiles,
1341 .ntiles = ARRAY_SIZE(sm8250_tiles),
1342 .wakeirq_map = sm8250_pdc_map,
1343 .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map),
1344 };
1345
1346 static int sm8250_pinctrl_probe(struct platform_device *pdev)
1347 {
1348 return msm_pinctrl_probe(pdev, &sm8250_pinctrl);
1349 }
1350
1351 static const struct of_device_id sm8250_pinctrl_of_match[] = {
1352 { .compatible = "qcom,sm8250-pinctrl", },
1353 { },
1354 };
1355
1356 static struct platform_driver sm8250_pinctrl_driver = {
1357 .driver = {
1358 .name = "sm8250-pinctrl",
1359 .of_match_table = sm8250_pinctrl_of_match,
1360 },
1361 .probe = sm8250_pinctrl_probe,
1362 .remove = msm_pinctrl_remove,
1363 };
1364
1365 static int __init sm8250_pinctrl_init(void)
1366 {
1367 return platform_driver_register(&sm8250_pinctrl_driver);
1368 }
1369 arch_initcall(sm8250_pinctrl_init);
1370
1371 static void __exit sm8250_pinctrl_exit(void)
1372 {
1373 platform_driver_unregister(&sm8250_pinctrl_driver);
1374 }
1375 module_exit(sm8250_pinctrl_exit);
1376
1377 MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");
1378 MODULE_LICENSE("GPL v2");
1379 MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);
Linux with added FPC-III support