drivers/pinctrl/renesas/gpio.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Pin Function Controller GPIO driver.
   4  *
   5  * Copyright (C) 2008 Magnus Damm
   6  * Copyright (C) 2009 - 2012 Paul Mundt
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/gpio/driver.h>
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/pinctrl/consumer.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16
  17 #include "core.h"
  18
  19 struct sh_pfc_gpio_data_reg {
  20         const struct pinmux_data_reg *info;
  21         u32 shadow;
  22 };
  23
  24 struct sh_pfc_gpio_pin {
  25         u8 dbit;
  26         u8 dreg;
  27 };
  28
  29 struct sh_pfc_chip {
  30         struct sh_pfc                   *pfc;
  31         struct gpio_chip                gpio_chip;
  32
  33         struct sh_pfc_window            *mem;
  34         struct sh_pfc_gpio_data_reg     *regs;
  35         struct sh_pfc_gpio_pin          *pins;
  36 };
  37
  38 static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
  39 {
  40         struct sh_pfc_chip *chip = gpiochip_get_data(gc);
  41         return chip->pfc;
  42 }
  43
  44 static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
  45                               struct sh_pfc_gpio_data_reg **reg,
  46                               unsigned int *bit)
  47 {
  48         int idx = sh_pfc_get_pin_index(chip->pfc, offset);
  49         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  50
  51         *reg = &chip->regs[gpio_pin->dreg];
  52         *bit = gpio_pin->dbit;
  53 }
  54
  55 static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
  56                               const struct pinmux_data_reg *dreg)
  57 {
  58         phys_addr_t address = dreg->reg;
  59         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  60
  61         return sh_pfc_read_raw_reg(mem, dreg->reg_width);
  62 }
  63
  64 static void gpio_write_data_reg(struct sh_pfc_chip *chip,
  65                                 const struct pinmux_data_reg *dreg, u32 value)
  66 {
  67         phys_addr_t address = dreg->reg;
  68         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  69
  70         sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
  71 }
  72
  73 static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
  74 {
  75         struct sh_pfc *pfc = chip->pfc;
  76         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  77         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  78         const struct pinmux_data_reg *dreg;
  79         unsigned int bit;
  80         unsigned int i;
  81
  82         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
  83                 for (bit = 0; bit < dreg->reg_width; bit++) {
  84                         if (dreg->enum_ids[bit] == pin->enum_id) {
  85                                 gpio_pin->dreg = i;
  86                                 gpio_pin->dbit = bit;
  87                                 return;
  88                         }
  89                 }
  90         }
  91
  92         BUG();
  93 }
  94
  95 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
  96 {
  97         struct sh_pfc *pfc = chip->pfc;
  98         const struct pinmux_data_reg *dreg;
  99         unsigned int i;
 100
 101         /* Count the number of data registers, allocate memory and initialize
 102          * them.
 103          */
 104         for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
 105                 ;
 106
 107         chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
 108                                   GFP_KERNEL);
 109         if (chip->regs == NULL)
 110                 return -ENOMEM;
 111
 112         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
 113                 chip->regs[i].info = dreg;
 114                 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
 115         }
 116
 117         for (i = 0; i < pfc->info->nr_pins; i++) {
 118                 if (pfc->info->pins[i].enum_id == 0)
 119                         continue;
 120
 121                 gpio_setup_data_reg(chip, i);
 122         }
 123
 124         return 0;
 125 }
 126
 127 /* -----------------------------------------------------------------------------
 128  * Pin GPIOs
 129  */
 130
 131 static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
 132 {
 133         struct sh_pfc *pfc = gpio_to_pfc(gc);
 134         int idx = sh_pfc_get_pin_index(pfc, offset);
 135
 136         if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
 137                 return -EINVAL;
 138
 139         return pinctrl_gpio_request(offset);
 140 }
 141
 142 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
 143 {
 144         return pinctrl_gpio_free(offset);
 145 }
 146
 147 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
 148                                int value)
 149 {
 150         struct sh_pfc_gpio_data_reg *reg;
 151         unsigned int bit;
 152         unsigned int pos;
 153
 154         gpio_get_data_reg(chip, offset, &reg, &bit);
 155
 156         pos = reg->info->reg_width - (bit + 1);
 157
 158         if (value)
 159                 reg->shadow |= BIT(pos);
 160         else
 161                 reg->shadow &= ~BIT(pos);
 162
 163         gpio_write_data_reg(chip, reg->info, reg->shadow);
 164 }
 165
 166 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
 167 {
 168         return pinctrl_gpio_direction_input(offset);
 169 }
 170
 171 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
 172                                     int value)
 173 {
 174         gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
 175
 176         return pinctrl_gpio_direction_output(offset);
 177 }
 178
 179 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
 180 {
 181         struct sh_pfc_chip *chip = gpiochip_get_data(gc);
 182         struct sh_pfc_gpio_data_reg *reg;
 183         unsigned int bit;
 184         unsigned int pos;
 185
 186         gpio_get_data_reg(chip, offset, &reg, &bit);
 187
 188         pos = reg->info->reg_width - (bit + 1);
 189
 190         return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
 191 }
 192
 193 static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
 194 {
 195         gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
 196 }
 197
 198 static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
 199 {
 200         struct sh_pfc *pfc = gpio_to_pfc(gc);
 201         unsigned int i, k;
 202
 203         for (i = 0; i < pfc->info->gpio_irq_size; i++) {
 204                 const short *gpios = pfc->info->gpio_irq[i].gpios;
 205
 206                 for (k = 0; gpios[k] >= 0; k++) {
 207                         if (gpios[k] == offset)
 208                                 return pfc->irqs[i];
 209                 }
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int gpio_pin_setup(struct sh_pfc_chip *chip)
 216 {
 217         struct sh_pfc *pfc = chip->pfc;
 218         struct gpio_chip *gc = &chip->gpio_chip;
 219         int ret;
 220
 221         chip->pins = devm_kcalloc(pfc->dev,
 222                                   pfc->info->nr_pins, sizeof(*chip->pins),
 223                                   GFP_KERNEL);
 224         if (chip->pins == NULL)
 225                 return -ENOMEM;
 226
 227         ret = gpio_setup_data_regs(chip);
 228         if (ret < 0)
 229                 return ret;
 230
 231         gc->request = gpio_pin_request;
 232         gc->free = gpio_pin_free;
 233         gc->direction_input = gpio_pin_direction_input;
 234         gc->get = gpio_pin_get;
 235         gc->direction_output = gpio_pin_direction_output;
 236         gc->set = gpio_pin_set;
 237         gc->to_irq = gpio_pin_to_irq;
 238
 239         gc->label = pfc->info->name;
 240         gc->parent = pfc->dev;
 241         gc->owner = THIS_MODULE;
 242         gc->base = 0;
 243         gc->ngpio = pfc->nr_gpio_pins;
 244
 245         return 0;
 246 }
 247
 248 /* -----------------------------------------------------------------------------
 249  * Function GPIOs
 250  */
 251
 252 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
 253 static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
 254 {
 255         struct sh_pfc *pfc = gpio_to_pfc(gc);
 256         unsigned int mark = pfc->info->func_gpios[offset].enum_id;
 257         unsigned long flags;
 258         int ret;
 259
 260         dev_notice_once(pfc->dev,
 261                         "Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
 262
 263         if (mark == 0)
 264                 return -EINVAL;
 265
 266         spin_lock_irqsave(&pfc->lock, flags);
 267         ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
 268         spin_unlock_irqrestore(&pfc->lock, flags);
 269
 270         return ret;
 271 }
 272
 273 static int gpio_function_setup(struct sh_pfc_chip *chip)
 274 {
 275         struct sh_pfc *pfc = chip->pfc;
 276         struct gpio_chip *gc = &chip->gpio_chip;
 277
 278         gc->request = gpio_function_request;
 279
 280         gc->label = pfc->info->name;
 281         gc->owner = THIS_MODULE;
 282         gc->base = pfc->nr_gpio_pins;
 283         gc->ngpio = pfc->info->nr_func_gpios;
 284
 285         return 0;
 286 }
 287 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
 288
 289 /* -----------------------------------------------------------------------------
 290  * Register/unregister
 291  */
 292
 293 static struct sh_pfc_chip *
 294 sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
 295                     struct sh_pfc_window *mem)
 296 {
 297         struct sh_pfc_chip *chip;
 298         int ret;
 299
 300         chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
 301         if (unlikely(!chip))
 302                 return ERR_PTR(-ENOMEM);
 303
 304         chip->mem = mem;
 305         chip->pfc = pfc;
 306
 307         ret = setup(chip);
 308         if (ret < 0)
 309                 return ERR_PTR(ret);
 310
 311         ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
 312         if (unlikely(ret < 0))
 313                 return ERR_PTR(ret);
 314
 315         dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
 316                  chip->gpio_chip.label, chip->gpio_chip.base,
 317                  chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
 318
 319         return chip;
 320 }
 321
 322 int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 323 {
 324         struct sh_pfc_chip *chip;
 325         phys_addr_t address;
 326         unsigned int i;
 327
 328         if (pfc->info->data_regs == NULL)
 329                 return 0;
 330
 331         /* Find the memory window that contains the GPIO registers. Boards that
 332          * register a separate GPIO device will not supply a memory resource
 333          * that covers the data registers. In that case don't try to handle
 334          * GPIOs.
 335          */
 336         address = pfc->info->data_regs[0].reg;
 337         for (i = 0; i < pfc->num_windows; ++i) {
 338                 struct sh_pfc_window *window = &pfc->windows[i];
 339
 340                 if (address >= window->phys &&
 341                     address < window->phys + window->size)
 342                         break;
 343         }
 344
 345         if (i == pfc->num_windows)
 346                 return 0;
 347
 348         /* If we have IRQ resources make sure their number is correct. */
 349         if (pfc->num_irqs != pfc->info->gpio_irq_size) {
 350                 dev_err(pfc->dev, "invalid number of IRQ resources\n");
 351                 return -EINVAL;
 352         }
 353
 354         /* Register the real GPIOs chip. */
 355         chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
 356         if (IS_ERR(chip))
 357                 return PTR_ERR(chip);
 358
 359         pfc->gpio = chip;
 360
 361         if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
 362                 return 0;
 363
 364 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
 365         /*
 366          * Register the GPIO to pin mappings. As pins with GPIO ports
 367          * must come first in the ranges, skip the pins without GPIO
 368          * ports by stopping at the first range that contains such a
 369          * pin.
 370          */
 371         for (i = 0; i < pfc->nr_ranges; ++i) {
 372                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 373                 int ret;
 374
 375                 if (range->start >= pfc->nr_gpio_pins)
 376                         break;
 377
 378                 ret = gpiochip_add_pin_range(&chip->gpio_chip,
 379                         dev_name(pfc->dev), range->start, range->start,
 380                         range->end - range->start + 1);
 381                 if (ret < 0)
 382                         return ret;
 383         }
 384
 385         /* Register the function GPIOs chip. */
 386         if (pfc->info->nr_func_gpios) {
 387                 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
 388                 if (IS_ERR(chip))
 389                         return PTR_ERR(chip);
 390         }
 391 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
 392
 393         return 0;
 394 }