| blob | 38d963561b5f3c0e58a35ae44a173aadaaf679d6 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
4 *
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 #define CPU_ALL_NOGP(fn) \
80 /*
81 * F_() : just information
82 * FM() : macro for FN_xxx / xxx_MARK
83 */
85 /* GPSR0 */
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
103 /* GPSR1 */
104 #define GPSR1_28 FM(CLKOUT)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
134 /* GPSR2 */
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
151 /* GPSR3 */
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
169 /* GPSR4 */
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
189 /* GPSR5 */
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193 #define GPSR5_22 FM(MSIOF0_RXD)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195 #define GPSR5_20 FM(MSIOF0_TXD)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198 #define GPSR5_17 FM(MSIOF0_SCK)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
217 /* GPSR6 */
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236 #define GPSR6_13 FM(SSI_SDATA5)
237 #define GPSR6_12 FM(SSI_WS5)
238 #define GPSR6_11 FM(SSI_SCK5)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
251 /* GPSR7 */
252 #define GPSR7_3 FM(GP7_03)
253 #define GPSR7_2 FM(GP7_02)
254 #define GPSR7_1 FM(AVS2)
255 #define GPSR7_0 FM(AVS1)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413 #define PINMUX_GPSR \
414 \
415 GPSR6_31 \
416 GPSR6_30 \
417 GPSR6_29 \
418 GPSR1_28 GPSR6_28 \
419 GPSR1_27 GPSR6_27 \
420 GPSR1_26 GPSR6_26 \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448 #define PINMUX_IPSR \
449 \
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
458 \
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
467 \
468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
476 \
477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
485 \
486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554 #define PINMUX_MOD_SELS \
555 \
556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
557 MOD_SEL2_30 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559 MOD_SEL0_28_27 MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562 MOD_SEL0_23 MOD_SEL1_23_22_21 \
563 MOD_SEL0_22 MOD_SEL2_22 \
564 MOD_SEL0_21 MOD_SEL2_21 \
565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
568 MOD_SEL2_17 \
569 MOD_SEL0_16 MOD_SEL1_16 \
570 MOD_SEL1_15_14 \
571 MOD_SEL0_14_13 \
572 MOD_SEL1_13 \
573 MOD_SEL0_12 MOD_SEL1_12 \
574 MOD_SEL0_11 MOD_SEL1_11 \
575 MOD_SEL0_10 MOD_SEL1_10 \
576 MOD_SEL0_9_8 MOD_SEL1_9 \
577 MOD_SEL0_7_6 \
578 MOD_SEL1_6 \
579 MOD_SEL0_5 MOD_SEL1_5 \
580 MOD_SEL0_4_3 MOD_SEL1_4 \
581 MOD_SEL1_3 \
582 MOD_SEL1_2 \
583 MOD_SEL1_1 \
584 MOD_SEL1_0 MOD_SEL2_0
586 /*
587 * These pins are not able to be muxed but have other properties
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
589 */
590 #define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
599 FM(PRESETOUT) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603 #define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
609 PINMUX_DATA_BEGIN,
611 PINMUX_DATA_END,
613 #define F_(x, y)
614 #define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
617 PINMUX_GPSR
618 PINMUX_IPSR
619 PINMUX_MOD_SELS
620 PINMUX_FUNCTION_END,
621 #undef F_
622 #undef FM
624 #define F_(x, y)
625 #define FM(x) x##_MARK,
626 PINMUX_MARK_BEGIN,
627 PINMUX_GPSR
628 PINMUX_IPSR
629 PINMUX_MOD_SELS
630 PINMUX_STATIC
631 PINMUX_PHYS
632 PINMUX_MARK_END,
633 #undef F_
634 #undef FM
635 };
652 /* IPSR0 */
694 /* IPSR1 */
746 /* IPSR2 */
807 /* IPSR3 */
861 /* IPSR4 */
907 /* IPSR5 */
957 /* IPSR6 */
1009 /* IPSR7 */
1051 /* IPSR8 */
1100 /* IPSR9 */
1125 /* IPSR10 */
1153 /* IPSR11 */
1197 /* IPSR12 */
1258 /* IPSR13 */
1318 /* IPSR14 */
1359 /* IPSR15 */
1406 /* IPSR16 */
1458 /* IPSR17 */
1524 /* IPSR18 */
1545 /*
1546 * Static pins can not be muxed between different functions but
1547 * still need mark entries in the pinmux list. Add each static
1548 * pin to the list without an associated function. The sh-pfc
1549 * core will do the right thing and skip trying to mux the pin
1550 * while still applying configuration to it.
1551 */
1552 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1553 PINMUX_STATIC
1554 #undef FM
1555 };
1557 /*
1558 * Pins not associated with a GPIO port.
1559 */
1563 };
1568 };
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1572 /* CLK A */
1574 };
1576 AUDIO_CLKA_A_MARK,
1577 };
1579 /* CLK A */
1581 };
1583 AUDIO_CLKA_B_MARK,
1584 };
1586 /* CLK A */
1588 };
1590 AUDIO_CLKA_C_MARK,
1591 };
1593 /* CLK B */
1595 };
1597 AUDIO_CLKB_A_MARK,
1598 };
1600 /* CLK B */
1602 };
1604 AUDIO_CLKB_B_MARK,
1605 };
1607 /* CLK C */
1609 };
1611 AUDIO_CLKC_A_MARK,
1612 };
1614 /* CLK C */
1616 };
1618 AUDIO_CLKC_B_MARK,
1619 };
1621 /* CLKOUT */
1623 };
1625 AUDIO_CLKOUT_A_MARK,
1626 };
1628 /* CLKOUT */
1630 };
1632 AUDIO_CLKOUT_B_MARK,
1633 };
1635 /* CLKOUT */
1637 };
1639 AUDIO_CLKOUT_C_MARK,
1640 };
1642 /* CLKOUT */
1644 };
1646 AUDIO_CLKOUT_D_MARK,
1647 };
1649 /* CLKOUT1 */
1651 };
1653 AUDIO_CLKOUT1_A_MARK,
1654 };
1656 /* CLKOUT1 */
1658 };
1660 AUDIO_CLKOUT1_B_MARK,
1661 };
1663 /* CLKOUT2 */
1665 };
1667 AUDIO_CLKOUT2_A_MARK,
1668 };
1670 /* CLKOUT2 */
1672 };
1674 AUDIO_CLKOUT2_B_MARK,
1675 };
1678 /* CLKOUT3 */
1680 };
1682 AUDIO_CLKOUT3_A_MARK,
1683 };
1685 /* CLKOUT3 */
1687 };
1689 AUDIO_CLKOUT3_B_MARK,
1690 };
1692 /* - EtherAVB --------------------------------------------------------------- */
1694 /* AVB_LINK */
1696 };
1698 AVB_LINK_MARK,
1699 };
1701 /* AVB_MAGIC_ */
1703 };
1705 AVB_MAGIC_MARK,
1706 };
1708 /* AVB_PHY_INT */
1710 };
1712 AVB_PHY_INT_MARK,
1713 };
1715 /* AVB_MDC, AVB_MDIO */
1717 };
1720 };
1722 /*
1723 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 * AVB_RD1, AVB_RD2, AVB_RD3,
1727 * AVB_TXCREFCLK
1728 */
1733 PIN_AVB_TXCREFCLK,
1735 };
1741 AVB_TXCREFCLK_MARK,
1742 };
1744 /* AVB_AVTP_PPS */
1746 };
1748 AVB_AVTP_PPS_MARK,
1749 };
1751 /* AVB_AVTP_MATCH_A */
1753 };
1755 AVB_AVTP_MATCH_A_MARK,
1756 };
1758 /* AVB_AVTP_CAPTURE_A */
1760 };
1762 AVB_AVTP_CAPTURE_A_MARK,
1763 };
1765 /* AVB_AVTP_MATCH_B */
1767 };
1769 AVB_AVTP_MATCH_B_MARK,
1770 };
1772 /* AVB_AVTP_CAPTURE_B */
1774 };
1776 AVB_AVTP_CAPTURE_B_MARK,
1777 };
1779 /* - CAN ------------------------------------------------------------------ */
1781 /* TX, RX */
1783 };
1786 };
1788 /* TX, RX */
1790 };
1793 };
1795 /* TX, RX */
1797 };
1800 };
1802 /* - CAN Clock -------------------------------------------------------------- */
1804 /* CLK */
1806 };
1808 CAN_CLK_MARK,
1809 };
1811 /* - CAN FD --------------------------------------------------------------- */
1813 /* TX, RX */
1815 };
1818 };
1820 /* TX, RX */
1822 };
1825 };
1827 /* TX, RX */
1829 };
1832 };
1834 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1835 /* - DRIF0 --------------------------------------------------------------- */
1837 /* CLK, SYNC */
1839 };
1842 };
1844 /* D0 */
1846 };
1848 RIF0_D0_A_MARK,
1849 };
1851 /* D1 */
1853 };
1855 RIF0_D1_A_MARK,
1856 };
1858 /* CLK, SYNC */
1860 };
1863 };
1865 /* D0 */
1867 };
1869 RIF0_D0_B_MARK,
1870 };
1872 /* D1 */
1874 };
1876 RIF0_D1_B_MARK,
1877 };
1879 /* CLK, SYNC */
1881 };
1884 };
1886 /* D0 */
1888 };
1890 RIF0_D0_C_MARK,
1891 };
1893 /* D1 */
1895 };
1897 RIF0_D1_C_MARK,
1898 };
1899 /* - DRIF1 --------------------------------------------------------------- */
1901 /* CLK, SYNC */
1903 };
1906 };
1908 /* D0 */
1910 };
1912 RIF1_D0_A_MARK,
1913 };
1915 /* D1 */
1917 };
1919 RIF1_D1_A_MARK,
1920 };
1922 /* CLK, SYNC */
1924 };
1927 };
1929 /* D0 */
1931 };
1933 RIF1_D0_B_MARK,
1934 };
1936 /* D1 */
1938 };
1940 RIF1_D1_B_MARK,
1941 };
1943 /* CLK, SYNC */
1945 };
1948 };
1950 /* D0 */
1952 };
1954 RIF1_D0_C_MARK,
1955 };
1957 /* D1 */
1959 };
1961 RIF1_D1_C_MARK,
1962 };
1963 /* - DRIF2 --------------------------------------------------------------- */
1965 /* CLK, SYNC */
1967 };
1970 };
1972 /* D0 */
1974 };
1976 RIF2_D0_A_MARK,
1977 };
1979 /* D1 */
1981 };
1983 RIF2_D1_A_MARK,
1984 };
1986 /* CLK, SYNC */
1988 };
1991 };
1993 /* D0 */
1995 };
1997 RIF2_D0_B_MARK,
1998 };
2000 /* D1 */
2002 };
2004 RIF2_D1_B_MARK,
2005 };
2006 /* - DRIF3 --------------------------------------------------------------- */
2008 /* CLK, SYNC */
2010 };
2013 };
2015 /* D0 */
2017 };
2019 RIF3_D0_A_MARK,
2020 };
2022 /* D1 */
2024 };
2026 RIF3_D1_A_MARK,
2027 };
2029 /* CLK, SYNC */
2031 };
2034 };
2036 /* D0 */
2038 };
2040 RIF3_D0_B_MARK,
2041 };
2043 /* D1 */
2045 };
2047 RIF3_D1_B_MARK,
2048 };
2051 /* - DU --------------------------------------------------------------------- */
2053 /* R[7:2], G[7:2], B[7:2] */
2060 };
2068 };
2070 /* R[7:0], G[7:0], B[7:0] */
2080 };
2088 };
2090 /* CLKOUT */
2092 };
2094 DU_DOTCLKOUT0_MARK
2095 };
2097 /* CLKOUT */
2099 };
2101 DU_DOTCLKOUT1_MARK
2102 };
2104 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2106 };
2108 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2109 };
2111 /* EXDISP/EXODDF/EXCDE */
2113 };
2115 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2116 };
2118 /* CDE */
2120 };
2122 DU_CDE_MARK,
2123 };
2125 /* DISP */
2127 };
2129 DU_DISP_MARK,
2130 };
2132 /* - HSCIF0 ----------------------------------------------------------------- */
2134 /* RX, TX */
2136 };
2139 };
2141 /* SCK */
2143 };
2145 HSCK0_MARK,
2146 };
2148 /* RTS, CTS */
2150 };
2153 };
2154 /* - HSCIF1 ----------------------------------------------------------------- */
2156 /* RX, TX */
2158 };
2161 };
2163 /* SCK */
2165 };
2167 HSCK1_A_MARK,
2168 };
2170 /* RTS, CTS */
2172 };
2175 };
2178 /* RX, TX */
2180 };
2183 };
2185 /* SCK */
2187 };
2189 HSCK1_B_MARK,
2190 };
2192 /* RTS, CTS */
2194 };
2197 };
2198 /* - HSCIF2 ----------------------------------------------------------------- */
2200 /* RX, TX */
2202 };
2205 };
2207 /* SCK */
2209 };
2211 HSCK2_A_MARK,
2212 };
2214 /* RTS, CTS */
2216 };
2219 };
2222 /* RX, TX */
2224 };
2227 };
2229 /* SCK */
2231 };
2233 HSCK2_B_MARK,
2234 };
2236 /* RTS, CTS */
2238 };
2241 };
2244 /* RX, TX */
2246 };
2249 };
2251 /* SCK */
2253 };
2255 HSCK2_C_MARK,
2256 };
2258 /* RTS, CTS */
2260 };
2263 };
2264 /* - HSCIF3 ----------------------------------------------------------------- */
2266 /* RX, TX */
2268 };
2271 };
2273 /* SCK */
2275 };
2277 HSCK3_MARK,
2278 };
2280 /* RTS, CTS */
2282 };
2285 };
2288 /* RX, TX */
2290 };
2293 };
2295 /* RX, TX */
2297 };
2300 };
2302 /* RX, TX */
2304 };
2307 };
2308 /* - HSCIF4 ----------------------------------------------------------------- */
2310 /* RX, TX */
2312 };
2315 };
2317 /* SCK */
2319 };
2321 HSCK4_MARK,
2322 };
2324 /* RTS, CTS */
2326 };
2329 };
2332 /* RX, TX */
2334 };
2337 };
2339 /* - I2C -------------------------------------------------------------------- */
2341 /* SCL, SDA */
2343 };
2347 };
2350 /* SDA, SCL */
2352 };
2355 };
2357 /* SDA, SCL */
2359 };
2362 };
2364 /* SDA, SCL */
2366 };
2369 };
2371 /* SDA, SCL */
2373 };
2376 };
2379 /* SCL, SDA */
2381 };
2385 };
2388 /* SCL, SDA */
2390 };
2394 };
2397 /* SDA, SCL */
2399 };
2402 };
2404 /* SDA, SCL */
2406 };
2409 };
2411 /* SDA, SCL */
2413 };
2416 };
2418 /* - INTC-EX ---------------------------------------------------------------- */
2420 /* IRQ0 */
2422 };
2424 IRQ0_MARK,
2425 };
2427 /* IRQ1 */
2429 };
2431 IRQ1_MARK,
2432 };
2434 /* IRQ2 */
2436 };
2438 IRQ2_MARK,
2439 };
2441 /* IRQ3 */
2443 };
2445 IRQ3_MARK,
2446 };
2448 /* IRQ4 */
2450 };
2452 IRQ4_MARK,
2453 };
2455 /* IRQ5 */
2457 };
2459 IRQ5_MARK,
2460 };
2462 /* - MSIOF0 ----------------------------------------------------------------- */
2464 /* SCK */
2466 };
2468 MSIOF0_SCK_MARK,
2469 };
2471 /* SYNC */
2473 };
2475 MSIOF0_SYNC_MARK,
2476 };
2478 /* SS1 */
2480 };
2482 MSIOF0_SS1_MARK,
2483 };
2485 /* SS2 */
2487 };
2489 MSIOF0_SS2_MARK,
2490 };
2492 /* TXD */
2494 };
2496 MSIOF0_TXD_MARK,
2497 };
2499 /* RXD */
2501 };
2503 MSIOF0_RXD_MARK,
2504 };
2505 /* - MSIOF1 ----------------------------------------------------------------- */
2507 /* SCK */
2509 };
2511 MSIOF1_SCK_A_MARK,
2512 };
2514 /* SYNC */
2516 };
2518 MSIOF1_SYNC_A_MARK,
2519 };
2521 /* SS1 */
2523 };
2525 MSIOF1_SS1_A_MARK,
2526 };
2528 /* SS2 */
2530 };
2532 MSIOF1_SS2_A_MARK,
2533 };
2535 /* TXD */
2537 };
2539 MSIOF1_TXD_A_MARK,
2540 };
2542 /* RXD */
2544 };
2546 MSIOF1_RXD_A_MARK,
2547 };
2549 /* SCK */
2551 };
2553 MSIOF1_SCK_B_MARK,
2554 };
2556 /* SYNC */
2558 };
2560 MSIOF1_SYNC_B_MARK,
2561 };
2563 /* SS1 */
2565 };
2567 MSIOF1_SS1_B_MARK,
2568 };
2570 /* SS2 */
2572 };
2574 MSIOF1_SS2_B_MARK,
2575 };
2577 /* TXD */
2579 };
2581 MSIOF1_TXD_B_MARK,
2582 };
2584 /* RXD */
2586 };
2588 MSIOF1_RXD_B_MARK,
2589 };
2591 /* SCK */
2593 };
2595 MSIOF1_SCK_C_MARK,
2596 };
2598 /* SYNC */
2600 };
2602 MSIOF1_SYNC_C_MARK,
2603 };
2605 /* SS1 */
2607 };
2609 MSIOF1_SS1_C_MARK,
2610 };
2612 /* SS2 */
2614 };
2616 MSIOF1_SS2_C_MARK,
2617 };
2619 /* TXD */
2621 };
2623 MSIOF1_TXD_C_MARK,
2624 };
2626 /* RXD */
2628 };
2630 MSIOF1_RXD_C_MARK,
2631 };
2633 /* SCK */
2635 };
2637 MSIOF1_SCK_D_MARK,
2638 };
2640 /* SYNC */
2642 };
2644 MSIOF1_SYNC_D_MARK,
2645 };
2647 /* SS1 */
2649 };
2651 MSIOF1_SS1_D_MARK,
2652 };
2654 /* SS2 */
2656 };
2658 MSIOF1_SS2_D_MARK,
2659 };
2661 /* TXD */
2663 };
2665 MSIOF1_TXD_D_MARK,
2666 };
2668 /* RXD */
2670 };
2672 MSIOF1_RXD_D_MARK,
2673 };
2675 /* SCK */
2677 };
2679 MSIOF1_SCK_E_MARK,
2680 };
2682 /* SYNC */
2684 };
2686 MSIOF1_SYNC_E_MARK,
2687 };
2689 /* SS1 */
2691 };
2693 MSIOF1_SS1_E_MARK,
2694 };
2696 /* SS2 */
2698 };
2700 MSIOF1_SS2_E_MARK,
2701 };
2703 /* TXD */
2705 };
2707 MSIOF1_TXD_E_MARK,
2708 };
2710 /* RXD */
2712 };
2714 MSIOF1_RXD_E_MARK,
2715 };
2717 /* SCK */
2719 };
2721 MSIOF1_SCK_F_MARK,
2722 };
2724 /* SYNC */
2726 };
2728 MSIOF1_SYNC_F_MARK,
2729 };
2731 /* SS1 */
2733 };
2735 MSIOF1_SS1_F_MARK,
2736 };
2738 /* SS2 */
2740 };
2742 MSIOF1_SS2_F_MARK,
2743 };
2745 /* TXD */
2747 };
2749 MSIOF1_TXD_F_MARK,
2750 };
2752 /* RXD */
2754 };
2756 MSIOF1_RXD_F_MARK,
2757 };
2759 /* SCK */
2761 };
2763 MSIOF1_SCK_G_MARK,
2764 };
2766 /* SYNC */
2768 };
2770 MSIOF1_SYNC_G_MARK,
2771 };
2773 /* SS1 */
2775 };
2777 MSIOF1_SS1_G_MARK,
2778 };
2780 /* SS2 */
2782 };
2784 MSIOF1_SS2_G_MARK,
2785 };
2787 /* TXD */
2789 };
2791 MSIOF1_TXD_G_MARK,
2792 };
2794 /* RXD */
2796 };
2798 MSIOF1_RXD_G_MARK,
2799 };
2800 /* - MSIOF2 ----------------------------------------------------------------- */
2802 /* SCK */
2804 };
2806 MSIOF2_SCK_A_MARK,
2807 };
2809 /* SYNC */
2811 };
2813 MSIOF2_SYNC_A_MARK,
2814 };
2816 /* SS1 */
2818 };
2820 MSIOF2_SS1_A_MARK,
2821 };
2823 /* SS2 */
2825 };
2827 MSIOF2_SS2_A_MARK,
2828 };
2830 /* TXD */
2832 };
2834 MSIOF2_TXD_A_MARK,
2835 };
2837 /* RXD */
2839 };
2841 MSIOF2_RXD_A_MARK,
2842 };
2844 /* SCK */
2846 };
2848 MSIOF2_SCK_B_MARK,
2849 };
2851 /* SYNC */
2853 };
2855 MSIOF2_SYNC_B_MARK,
2856 };
2858 /* SS1 */
2860 };
2862 MSIOF2_SS1_B_MARK,
2863 };
2865 /* SS2 */
2867 };
2869 MSIOF2_SS2_B_MARK,
2870 };
2872 /* TXD */
2874 };
2876 MSIOF2_TXD_B_MARK,
2877 };
2879 /* RXD */
2881 };
2883 MSIOF2_RXD_B_MARK,
2884 };
2886 /* SCK */
2888 };
2890 MSIOF2_SCK_C_MARK,
2891 };
2893 /* SYNC */
2895 };
2897 MSIOF2_SYNC_C_MARK,
2898 };
2900 /* SS1 */
2902 };
2904 MSIOF2_SS1_C_MARK,
2905 };
2907 /* SS2 */
2909 };
2911 MSIOF2_SS2_C_MARK,
2912 };
2914 /* TXD */
2916 };
2918 MSIOF2_TXD_C_MARK,
2919 };
2921 /* RXD */
2923 };
2925 MSIOF2_RXD_C_MARK,
2926 };
2928 /* SCK */
2930 };
2932 MSIOF2_SCK_D_MARK,
2933 };
2935 /* SYNC */
2937 };
2939 MSIOF2_SYNC_D_MARK,
2940 };
2942 /* SS1 */
2944 };
2946 MSIOF2_SS1_D_MARK,
2947 };
2949 /* SS2 */
2951 };
2953 MSIOF2_SS2_D_MARK,
2954 };
2956 /* TXD */
2958 };
2960 MSIOF2_TXD_D_MARK,
2961 };
2963 /* RXD */
2965 };
2967 MSIOF2_RXD_D_MARK,
2968 };
2969 /* - MSIOF3 ----------------------------------------------------------------- */
2971 /* SCK */
2973 };
2975 MSIOF3_SCK_A_MARK,
2976 };
2978 /* SYNC */
2980 };
2982 MSIOF3_SYNC_A_MARK,
2983 };
2985 /* SS1 */
2987 };
2989 MSIOF3_SS1_A_MARK,
2990 };
2992 /* SS2 */
2994 };
2996 MSIOF3_SS2_A_MARK,
2997 };
2999 /* TXD */
3001 };
3003 MSIOF3_TXD_A_MARK,
3004 };
3006 /* RXD */
3008 };
3010 MSIOF3_RXD_A_MARK,
3011 };
3013 /* SCK */
3015 };
3017 MSIOF3_SCK_B_MARK,
3018 };
3020 /* SYNC */
3022 };
3024 MSIOF3_SYNC_B_MARK,
3025 };
3027 /* SS1 */
3029 };
3031 MSIOF3_SS1_B_MARK,
3032 };
3034 /* SS2 */
3036 };
3038 MSIOF3_SS2_B_MARK,
3039 };
3041 /* TXD */
3043 };
3045 MSIOF3_TXD_B_MARK,
3046 };
3048 /* RXD */
3050 };
3052 MSIOF3_RXD_B_MARK,
3053 };
3055 /* SCK */
3057 };
3059 MSIOF3_SCK_C_MARK,
3060 };
3062 /* SYNC */
3064 };
3066 MSIOF3_SYNC_C_MARK,
3067 };
3069 /* TXD */
3071 };
3073 MSIOF3_TXD_C_MARK,
3074 };
3076 /* RXD */
3078 };
3080 MSIOF3_RXD_C_MARK,
3081 };
3083 /* SCK */
3085 };
3087 MSIOF3_SCK_D_MARK,
3088 };
3090 /* SYNC */
3092 };
3094 MSIOF3_SYNC_D_MARK,
3095 };
3097 /* SS1 */
3099 };
3101 MSIOF3_SS1_D_MARK,
3102 };
3104 /* TXD */
3106 };
3108 MSIOF3_TXD_D_MARK,
3109 };
3111 /* RXD */
3113 };
3115 MSIOF3_RXD_D_MARK,
3116 };
3119 /* SCK */
3121 };
3123 MSIOF3_SCK_E_MARK,
3124 };
3126 /* SYNC */
3128 };
3130 MSIOF3_SYNC_E_MARK,
3131 };
3133 /* SS1 */
3135 };
3137 MSIOF3_SS1_E_MARK,
3138 };
3140 /* SS2 */
3142 };
3144 MSIOF3_SS2_E_MARK,
3145 };
3147 /* TXD */
3149 };
3151 MSIOF3_TXD_E_MARK,
3152 };
3154 /* RXD */
3156 };
3158 MSIOF3_RXD_E_MARK,
3159 };
3161 /* - PWM0 --------------------------------------------------------------------*/
3163 /* PWM */
3165 };
3167 PWM0_MARK,
3168 };
3169 /* - PWM1 --------------------------------------------------------------------*/
3171 /* PWM */
3173 };
3175 PWM1_A_MARK,
3176 };
3178 /* PWM */
3180 };
3182 PWM1_B_MARK,
3183 };
3184 /* - PWM2 --------------------------------------------------------------------*/
3186 /* PWM */
3188 };
3190 PWM2_A_MARK,
3191 };
3193 /* PWM */
3195 };
3197 PWM2_B_MARK,
3198 };
3199 /* - PWM3 --------------------------------------------------------------------*/
3201 /* PWM */
3203 };
3205 PWM3_A_MARK,
3206 };
3208 /* PWM */
3210 };
3212 PWM3_B_MARK,
3213 };
3214 /* - PWM4 --------------------------------------------------------------------*/
3216 /* PWM */
3218 };
3220 PWM4_A_MARK,
3221 };
3223 /* PWM */
3225 };
3227 PWM4_B_MARK,
3228 };
3229 /* - PWM5 --------------------------------------------------------------------*/
3231 /* PWM */
3233 };
3235 PWM5_A_MARK,
3236 };
3238 /* PWM */
3240 };
3242 PWM5_B_MARK,
3243 };
3244 /* - PWM6 --------------------------------------------------------------------*/
3246 /* PWM */
3248 };
3250 PWM6_A_MARK,
3251 };
3253 /* PWM */
3255 };
3257 PWM6_B_MARK,
3258 };
3260 /* - QSPI0 ------------------------------------------------------------------ */
3262 /* QSPI0_SPCLK, QSPI0_SSL */
3264 };
3267 };
3269 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3271 };
3274 };
3276 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3278 /* QSPI0_IO2, QSPI0_IO3 */
3280 };
3284 };
3285 /* - QSPI1 ------------------------------------------------------------------ */
3287 /* QSPI1_SPCLK, QSPI1_SSL */
3289 };
3292 };
3294 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3296 };
3299 };
3301 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3303 /* QSPI1_IO2, QSPI1_IO3 */
3305 };
3309 };
3311 /* - SCIF0 ------------------------------------------------------------------ */
3313 /* RX, TX */
3315 };
3318 };
3320 /* SCK */
3322 };
3324 SCK0_MARK,
3325 };
3327 /* RTS, CTS */
3329 };
3332 };
3333 /* - SCIF1 ------------------------------------------------------------------ */
3335 /* RX, TX */
3337 };
3340 };
3342 /* SCK */
3344 };
3346 SCK1_MARK,
3347 };
3349 /* RTS, CTS */
3351 };
3354 };
3357 /* RX, TX */
3359 };
3362 };
3363 /* - SCIF2 ------------------------------------------------------------------ */
3365 /* RX, TX */
3367 };
3370 };
3372 /* SCK */
3374 };
3376 SCK2_MARK,
3377 };
3379 /* RX, TX */
3381 };
3384 };
3385 /* - SCIF3 ------------------------------------------------------------------ */
3387 /* RX, TX */
3389 };
3392 };
3394 /* SCK */
3396 };
3398 SCK3_MARK,
3399 };
3401 /* RTS, CTS */
3403 };
3406 };
3408 /* RX, TX */
3410 };
3413 };
3414 /* - SCIF4 ------------------------------------------------------------------ */
3416 /* RX, TX */
3418 };
3421 };
3423 /* SCK */
3425 };
3427 SCK4_A_MARK,
3428 };
3430 /* RTS, CTS */
3432 };
3435 };
3437 /* RX, TX */
3439 };
3442 };
3444 /* SCK */
3446 };
3448 SCK4_B_MARK,
3449 };
3451 /* RTS, CTS */
3453 };
3456 };
3458 /* RX, TX */
3460 };
3463 };
3465 /* SCK */
3467 };
3469 SCK4_C_MARK,
3470 };
3472 /* RTS, CTS */
3474 };
3477 };
3478 /* - SCIF5 ------------------------------------------------------------------ */
3480 /* RX, TX */
3482 };
3485 };
3487 /* SCK */
3489 };
3491 SCK5_A_MARK,
3492 };
3495 /* RX, TX */
3497 };
3500 };
3502 /* SCK */
3504 };
3506 SCK5_B_MARK,
3507 };
3509 /* - SCIF Clock ------------------------------------------------------------- */
3511 /* SCIF_CLK */
3513 };
3515 SCIF_CLK_A_MARK,
3516 };
3518 /* SCIF_CLK */
3520 };
3522 SCIF_CLK_B_MARK,
3523 };
3525 /* - SDHI0 ------------------------------------------------------------------ */
3527 /* D0 */
3529 };
3531 SD0_DAT0_MARK,
3532 };
3534 /* D[0:3] */
3537 };
3541 };
3543 /* CLK, CMD */
3545 };
3548 };
3550 /* CD */
3552 };
3554 SD0_CD_MARK,
3555 };
3557 /* WP */
3559 };
3561 SD0_WP_MARK,
3562 };
3563 /* - SDHI1 ------------------------------------------------------------------ */
3565 /* D0 */
3567 };
3569 SD1_DAT0_MARK,
3570 };
3572 /* D[0:3] */
3575 };
3579 };
3581 /* CLK, CMD */
3583 };
3586 };
3588 /* CD */
3590 };
3592 SD1_CD_MARK,
3593 };
3595 /* WP */
3597 };
3599 SD1_WP_MARK,
3600 };
3601 /* - SDHI2 ------------------------------------------------------------------ */
3603 /* D0 */
3605 };
3607 SD2_DAT0_MARK,
3608 };
3610 /* D[0:3] */
3613 };
3617 };
3619 /* D[0:7] */
3624 };
3630 };
3632 /* CLK, CMD */
3634 };
3637 };
3639 /* CD */
3641 };
3643 SD2_CD_A_MARK,
3644 };
3646 /* CD */
3648 };
3650 SD2_CD_B_MARK,
3651 };
3653 /* WP */
3655 };
3657 SD2_WP_A_MARK,
3658 };
3660 /* WP */
3662 };
3664 SD2_WP_B_MARK,
3665 };
3667 /* DS */
3669 };
3671 SD2_DS_MARK,
3672 };
3673 /* - SDHI3 ------------------------------------------------------------------ */
3675 /* D0 */
3677 };
3679 SD3_DAT0_MARK,
3680 };
3682 /* D[0:3] */
3685 };
3689 };
3691 /* D[0:7] */
3696 };
3702 };
3704 /* CLK, CMD */
3706 };
3709 };
3711 /* CD */
3713 };
3715 SD3_CD_MARK,
3716 };
3718 /* WP */
3720 };
3722 SD3_WP_MARK,
3723 };
3725 /* DS */
3727 };
3729 SD3_DS_MARK,
3730 };
3732 /* - SSI -------------------------------------------------------------------- */
3734 /* SDATA */
3736 };
3738 SSI_SDATA0_MARK,
3739 };
3741 /* SCK, WS */
3743 };
3746 };
3748 /* SDATA */
3750 };
3752 SSI_SDATA1_A_MARK,
3753 };
3755 /* SDATA */
3757 };
3759 SSI_SDATA1_B_MARK,
3760 };
3762 /* SCK, WS */
3764 };
3767 };
3769 /* SCK, WS */
3771 };
3774 };
3776 /* SDATA */
3778 };
3780 SSI_SDATA2_A_MARK,
3781 };
3783 /* SDATA */
3785 };
3787 SSI_SDATA2_B_MARK,
3788 };
3790 /* SCK, WS */
3792 };
3795 };
3797 /* SCK, WS */
3799 };
3802 };
3804 /* SDATA */
3806 };
3808 SSI_SDATA3_MARK,
3809 };
3811 /* SCK, WS */
3813 };
3816 };
3818 /* SDATA */
3820 };
3822 SSI_SDATA4_MARK,
3823 };
3825 /* SCK, WS */
3827 };
3830 };
3832 /* SDATA */
3834 };
3836 SSI_SDATA5_MARK,
3837 };
3839 /* SCK, WS */
3841 };
3844 };
3846 /* SDATA */
3848 };
3850 SSI_SDATA6_MARK,
3851 };
3853 /* SCK, WS */
3855 };
3858 };
3860 /* SDATA */
3862 };
3864 SSI_SDATA7_MARK,
3865 };
3867 /* SCK, WS */
3869 };
3872 };
3874 /* SDATA */
3876 };
3878 SSI_SDATA8_MARK,
3879 };
3881 /* SDATA */
3883 };
3885 SSI_SDATA9_A_MARK,
3886 };
3888 /* SDATA */
3890 };
3892 SSI_SDATA9_B_MARK,
3893 };
3895 /* SCK, WS */
3897 };
3900 };
3902 /* SCK, WS */
3904 };
3907 };
3909 /* - TMU -------------------------------------------------------------------- */
3911 /* TCLK */
3913 };
3915 TCLK1_A_MARK,
3916 };
3918 /* TCLK */
3920 };
3922 TCLK1_B_MARK,
3923 };
3925 /* TCLK */
3927 };
3929 TCLK2_A_MARK,
3930 };
3932 /* TCLK */
3934 };
3936 TCLK2_B_MARK,
3937 };
3939 /* - TPU ------------------------------------------------------------------- */
3941 /* TPU0TO0 */
3943 };
3945 TPU0TO0_MARK,
3946 };
3948 /* TPU0TO1 */
3950 };
3952 TPU0TO1_MARK,
3953 };
3955 /* TPU0TO2 */
3957 };
3959 TPU0TO2_MARK,
3960 };
3962 /* TPU0TO3 */
3964 };
3966 TPU0TO3_MARK,
3967 };
3969 /* - USB0 ------------------------------------------------------------------- */
3971 /* PWEN, OVC */
3973 };
3976 };
3977 /* - USB1 ------------------------------------------------------------------- */
3979 /* PWEN, OVC */
3981 };
3984 };
3986 /* - USB30 ------------------------------------------------------------------ */
3988 /* PWEN, OVC */
3990 };
3993 };
3995 /* - VIN4 ------------------------------------------------------------------- */
4006 };
4017 };
4028 };
4039 };
4054 },
4055 };
4070 },
4071 };
4086 },
4087 };
4102 },
4103 };
4105 /* HSYNC#, VSYNC# */
4107 };
4110 };
4112 /* FIELD */
4114 };
4116 VI4_FIELD_MARK,
4117 };
4119 /* CLKENB */
4121 };
4123 VI4_CLKENB_MARK,
4124 };
4126 /* CLK */
4128 };
4130 VI4_CLK_MARK,
4131 };
4133 /* - VIN5 ------------------------------------------------------------------- */
4144 },
4145 };
4156 },
4157 };
4159 /* HSYNC#, VSYNC# */
4161 };
4164 };
4167 };
4169 /* FIELD */
4170 VI5_FIELD_MARK,
4171 };
4174 };
4176 /* CLKENB */
4177 VI5_CLKENB_MARK,
4178 };
4181 };
4183 /* CLK */
4184 VI5_CLK_MARK,
4185 };
4189 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4191 #endif
4516 },
4517 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4549 }
4551 };
4571 };
4585 };
4590 };
4594 };
4598 };
4603 };
4607 };
4609 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4620 };
4632 };
4641 };
4650 };
4662 };
4668 };
4677 };
4689 };
4698 };
4705 };
4709 };
4714 };
4719 };
4723 };
4727 };
4733 };
4742 };
4751 };
4796 };
4823 };
4853 };
4857 };
4862 };
4867 };
4872 };
4877 };
4882 };
4887 };
4893 };
4899 };
4905 };
4912 };
4918 };
4925 };
4937 };
4944 };
4949 };
4957 };
4965 };
4977 };
4987 };
5015 };
5022 };
5029 };
5033 };
5037 };
5041 };
5062 };
5073 };
5077 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5079 #endif
5134 },
5135 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5141 }
5143 };
5146 #define F_(x, y) FN_##y
5147 #define FM(x) FN_##x
5181 },
5215 },
5249 },
5283 },
5317 },
5351 },
5385 },
5419 },
5420 #undef F_
5421 #undef FM
5423 #define F_(x, y) x,
5424 #define FM(x) FN_##x,
5426 IP0_31_28
5427 IP0_27_24
5428 IP0_23_20
5429 IP0_19_16
5430 IP0_15_12
5431 IP0_11_8
5432 IP0_7_4
5433 IP0_3_0 ))
5434 },
5436 IP1_31_28
5437 IP1_27_24
5438 IP1_23_20
5439 IP1_19_16
5440 IP1_15_12
5441 IP1_11_8
5442 IP1_7_4
5443 IP1_3_0 ))
5444 },
5446 IP2_31_28
5447 IP2_27_24
5448 IP2_23_20
5449 IP2_19_16
5450 IP2_15_12
5451 IP2_11_8
5452 IP2_7_4
5453 IP2_3_0 ))
5454 },
5456 IP3_31_28
5457 IP3_27_24
5458 IP3_23_20
5459 IP3_19_16
5460 IP3_15_12
5461 IP3_11_8
5462 IP3_7_4
5463 IP3_3_0 ))
5464 },
5466 IP4_31_28
5467 IP4_27_24
5468 IP4_23_20
5469 IP4_19_16
5470 IP4_15_12
5471 IP4_11_8
5472 IP4_7_4
5473 IP4_3_0 ))
5474 },
5476 IP5_31_28
5477 IP5_27_24
5478 IP5_23_20
5479 IP5_19_16
5480 IP5_15_12
5481 IP5_11_8
5482 IP5_7_4
5483 IP5_3_0 ))
5484 },
5486 IP6_31_28
5487 IP6_27_24
5488 IP6_23_20
5489 IP6_19_16
5490 IP6_15_12
5491 IP6_11_8
5492 IP6_7_4
5493 IP6_3_0 ))
5494 },
5496 IP7_31_28
5497 IP7_27_24
5498 IP7_23_20
5499 IP7_19_16
5501 IP7_11_8
5502 IP7_7_4
5503 IP7_3_0 ))
5504 },
5506 IP8_31_28
5507 IP8_27_24
5508 IP8_23_20
5509 IP8_19_16
5510 IP8_15_12
5511 IP8_11_8
5512 IP8_7_4
5513 IP8_3_0 ))
5514 },
5516 IP9_31_28
5517 IP9_27_24
5518 IP9_23_20
5519 IP9_19_16
5520 IP9_15_12
5521 IP9_11_8
5522 IP9_7_4
5523 IP9_3_0 ))
5524 },
5526 IP10_31_28
5527 IP10_27_24
5528 IP10_23_20
5529 IP10_19_16
5530 IP10_15_12
5531 IP10_11_8
5532 IP10_7_4
5533 IP10_3_0 ))
5534 },
5536 IP11_31_28
5537 IP11_27_24
5538 IP11_23_20
5539 IP11_19_16
5540 IP11_15_12
5541 IP11_11_8
5542 IP11_7_4
5543 IP11_3_0 ))
5544 },
5546 IP12_31_28
5547 IP12_27_24
5548 IP12_23_20
5549 IP12_19_16
5550 IP12_15_12
5551 IP12_11_8
5552 IP12_7_4
5553 IP12_3_0 ))
5554 },
5556 IP13_31_28
5557 IP13_27_24
5558 IP13_23_20
5559 IP13_19_16
5560 IP13_15_12
5561 IP13_11_8
5562 IP13_7_4
5563 IP13_3_0 ))
5564 },
5566 IP14_31_28
5567 IP14_27_24
5568 IP14_23_20
5569 IP14_19_16
5570 IP14_15_12
5571 IP14_11_8
5572 IP14_7_4
5573 IP14_3_0 ))
5574 },
5576 IP15_31_28
5577 IP15_27_24
5578 IP15_23_20
5579 IP15_19_16
5580 IP15_15_12
5581 IP15_11_8
5582 IP15_7_4
5583 IP15_3_0 ))
5584 },
5586 IP16_31_28
5587 IP16_27_24
5588 IP16_23_20
5589 IP16_19_16
5590 IP16_15_12
5591 IP16_11_8
5592 IP16_7_4
5593 IP16_3_0 ))
5594 },
5596 IP17_31_28
5597 IP17_27_24
5598 IP17_23_20
5599 IP17_19_16
5600 IP17_15_12
5601 IP17_11_8
5602 IP17_7_4
5603 IP17_3_0 ))
5604 },
5612 IP18_7_4
5613 IP18_3_0 ))
5614 },
5615 #undef F_
5616 #undef FM
5618 #define F_(x, y) x,
5619 #define FM(x) FN_##x,
5624 MOD_SEL0_31_30_29
5625 MOD_SEL0_28_27
5626 MOD_SEL0_26_25_24
5627 MOD_SEL0_23
5628 MOD_SEL0_22
5629 MOD_SEL0_21
5630 MOD_SEL0_20
5631 MOD_SEL0_19
5632 MOD_SEL0_18_17
5633 MOD_SEL0_16
5635 MOD_SEL0_14_13
5636 MOD_SEL0_12
5637 MOD_SEL0_11
5638 MOD_SEL0_10
5639 MOD_SEL0_9_8
5640 MOD_SEL0_7_6
5641 MOD_SEL0_5
5642 MOD_SEL0_4_3
5643 /* RESERVED 2, 1, 0 */
5645 },
5650 MOD_SEL1_31_30
5651 MOD_SEL1_29_28_27
5652 MOD_SEL1_26
5653 MOD_SEL1_25_24
5654 MOD_SEL1_23_22_21
5655 MOD_SEL1_20
5656 MOD_SEL1_19
5657 MOD_SEL1_18_17
5658 MOD_SEL1_16
5659 MOD_SEL1_15_14
5660 MOD_SEL1_13
5661 MOD_SEL1_12
5662 MOD_SEL1_11
5663 MOD_SEL1_10
5664 MOD_SEL1_9
5666 MOD_SEL1_6
5667 MOD_SEL1_5
5668 MOD_SEL1_4
5669 MOD_SEL1_3
5670 MOD_SEL1_2
5671 MOD_SEL1_1
5672 MOD_SEL1_0 ))
5673 },
5678 MOD_SEL2_31
5679 MOD_SEL2_30
5680 MOD_SEL2_29
5681 MOD_SEL2_28_27
5682 MOD_SEL2_26
5683 MOD_SEL2_25_24_23
5684 MOD_SEL2_22
5685 MOD_SEL2_21
5686 MOD_SEL2_20
5687 MOD_SEL2_19
5688 MOD_SEL2_18
5689 MOD_SEL2_17
5690 /* RESERVED 16 */
5692 /* RESERVED 15, 14, 13, 12 */
5695 /* RESERVED 11, 10, 9, 8 */
5698 /* RESERVED 7, 6, 5, 4 */
5701 /* RESERVED 3, 2, 1 */
5703 MOD_SEL2_0 ))
5704 },
5705 { },
5706 };
5718 } },
5728 } },
5738 } },
5748 } },
5758 } },
5768 } },
5778 } },
5788 } },
5798 } },
5808 } },
5818 } },
5828 } },
5833 } },
5843 } },
5853 } },
5863 } },
5873 } },
5883 } },
5893 } },
5903 } },
5913 } },
5923 } },
5933 } },
5943 } },
5952 } },
5953 { },
5954 };
5957 POCCTRL,
5958 TDSELCTRL,
5959 };
5965 };
5968 {
5980 }
6016 } },
6050 } },
6084 } },
6118 } },
6152 } },
6186 } },
6220 } },
6222 };
6228 };
6230 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6252 };
6253 #endif
6255 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6279 };
6280 #endif
6282 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6306 };
6307 #endif