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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / renesas / pfc-r8a77995.c
blob672251d86c2de3cd1b961b7d8a9819a952124cee
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77995 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2017 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */
13
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16
17 #include "core.h"
18 #include "sh_pfc.h"
19
20 #define CPU_ALL_GP(fn, sfx) \
21 PORT_GP_9(0, fn, sfx), \
22 PORT_GP_32(1, fn, sfx), \
23 PORT_GP_32(2, fn, sfx), \
24 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_32(4, fn, sfx), \
26 PORT_GP_21(5, fn, sfx), \
27 PORT_GP_14(6, fn, sfx)
28
29 /*
30 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK
32 */
33
34 /* GPSR0 */
35 #define GPSR0_8 F_(MLB_SIG, IP0_27_24)
36 #define GPSR0_7 F_(MLB_DAT, IP0_23_20)
37 #define GPSR0_6 F_(MLB_CLK, IP0_19_16)
38 #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
39 #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
40 #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
41 #define GPSR0_2 F_(IRQ0_A, IP0_3_0)
42 #define GPSR0_1 FM(USB0_OVC)
43 #define GPSR0_0 FM(USB0_PWEN)
44
45 /* GPSR1 */
46 #define GPSR1_31 F_(QPOLB, IP4_27_24)
47 #define GPSR1_30 F_(QPOLA, IP4_23_20)
48 #define GPSR1_29 F_(DU_CDE, IP4_19_16)
49 #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
50 #define GPSR1_27 F_(DU_DISP, IP4_11_8)
51 #define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
52 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
53 #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
54 #define GPSR1_23 F_(DU_DR7, IP3_27_24)
55 #define GPSR1_22 F_(DU_DR6, IP3_23_20)
56 #define GPSR1_21 F_(DU_DR5, IP3_19_16)
57 #define GPSR1_20 F_(DU_DR4, IP3_15_12)
58 #define GPSR1_19 F_(DU_DR3, IP3_11_8)
59 #define GPSR1_18 F_(DU_DR2, IP3_7_4)
60 #define GPSR1_17 F_(DU_DR1, IP3_3_0)
61 #define GPSR1_16 F_(DU_DR0, IP2_31_28)
62 #define GPSR1_15 F_(DU_DG7, IP2_27_24)
63 #define GPSR1_14 F_(DU_DG6, IP2_23_20)
64 #define GPSR1_13 F_(DU_DG5, IP2_19_16)
65 #define GPSR1_12 F_(DU_DG4, IP2_15_12)
66 #define GPSR1_11 F_(DU_DG3, IP2_11_8)
67 #define GPSR1_10 F_(DU_DG2, IP2_7_4)
68 #define GPSR1_9 F_(DU_DG1, IP2_3_0)
69 #define GPSR1_8 F_(DU_DG0, IP1_31_28)
70 #define GPSR1_7 F_(DU_DB7, IP1_27_24)
71 #define GPSR1_6 F_(DU_DB6, IP1_23_20)
72 #define GPSR1_5 F_(DU_DB5, IP1_19_16)
73 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
74 #define GPSR1_3 F_(DU_DB3, IP1_11_8)
75 #define GPSR1_2 F_(DU_DB2, IP1_7_4)
76 #define GPSR1_1 F_(DU_DB1, IP1_3_0)
77 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
78
79 /* GPSR2 */
80 #define GPSR2_31 F_(NFCE_N, IP8_19_16)
81 #define GPSR2_30 F_(NFCLE, IP8_15_12)
82 #define GPSR2_29 F_(NFALE, IP8_11_8)
83 #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
84 #define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
85 #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
86 #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
87 #define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
88 #define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
89 #define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
90 #define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
91 #define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
92 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
93 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
94 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
95 #define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
96 #define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
97 #define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
98 #define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
99 #define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
100 #define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
101 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
102 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
103 #define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
104 #define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
105 #define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
106 #define GPSR2_5 FM(VI4_DATA4)
107 #define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
108 #define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
109 #define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
110 #define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
111 #define GPSR2_0 FM(VI4_CLK)
112
113 /* GPSR3 */
114 #define GPSR3_9 F_(NFDATA7, IP9_31_28)
115 #define GPSR3_8 F_(NFDATA6, IP9_27_24)
116 #define GPSR3_7 F_(NFDATA5, IP9_23_20)
117 #define GPSR3_6 F_(NFDATA4, IP9_19_16)
118 #define GPSR3_5 F_(NFDATA3, IP9_15_12)
119 #define GPSR3_4 F_(NFDATA2, IP9_11_8)
120 #define GPSR3_3 F_(NFDATA1, IP9_7_4)
121 #define GPSR3_2 F_(NFDATA0, IP9_3_0)
122 #define GPSR3_1 F_(NFWE_N, IP8_31_28)
123 #define GPSR3_0 F_(NFRE_N, IP8_27_24)
124
125 /* GPSR4 */
126 #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
127 #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
128 #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
129 #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
130 #define GPSR4_27 FM(TX2)
131 #define GPSR4_26 FM(RX2)
132 #define GPSR4_25 F_(SCK2, IP12_11_8)
133 #define GPSR4_24 F_(TX1_A, IP12_7_4)
134 #define GPSR4_23 F_(RX1_A, IP12_3_0)
135 #define GPSR4_22 F_(SCK1_A, IP11_31_28)
136 #define GPSR4_21 F_(TX0_A, IP11_27_24)
137 #define GPSR4_20 F_(RX0_A, IP11_23_20)
138 #define GPSR4_19 F_(SCK0_A, IP11_19_16)
139 #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
140 #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
141 #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
142 #define GPSR4_15 FM(MSIOF0_RXD)
143 #define GPSR4_14 FM(MSIOF0_TXD)
144 #define GPSR4_13 FM(MSIOF0_SYNC)
145 #define GPSR4_12 FM(MSIOF0_SCK)
146 #define GPSR4_11 F_(SDA1, IP11_3_0)
147 #define GPSR4_10 F_(SCL1, IP10_31_28)
148 #define GPSR4_9 FM(SDA0)
149 #define GPSR4_8 FM(SCL0)
150 #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
151 #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
152 #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
153 #define GPSR4_4 F_(SSI_WS34, IP10_15_12)
154 #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
155 #define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
156 #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
157 #define GPSR4_0 F_(NFRB_N, IP8_23_20)
158
159 /* GPSR5 */
160 #define GPSR5_20 FM(AVB0_LINK)
161 #define GPSR5_19 FM(AVB0_PHY_INT)
162 #define GPSR5_18 FM(AVB0_MAGIC)
163 #define GPSR5_17 FM(AVB0_MDC)
164 #define GPSR5_16 FM(AVB0_MDIO)
165 #define GPSR5_15 FM(AVB0_TXCREFCLK)
166 #define GPSR5_14 FM(AVB0_TD3)
167 #define GPSR5_13 FM(AVB0_TD2)
168 #define GPSR5_12 FM(AVB0_TD1)
169 #define GPSR5_11 FM(AVB0_TD0)
170 #define GPSR5_10 FM(AVB0_TXC)
171 #define GPSR5_9 FM(AVB0_TX_CTL)
172 #define GPSR5_8 FM(AVB0_RD3)
173 #define GPSR5_7 FM(AVB0_RD2)
174 #define GPSR5_6 FM(AVB0_RD1)
175 #define GPSR5_5 FM(AVB0_RD0)
176 #define GPSR5_4 FM(AVB0_RXC)
177 #define GPSR5_3 FM(AVB0_RX_CTL)
178 #define GPSR5_2 F_(CAN_CLK, IP12_23_20)
179 #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
180 #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
181
182 /* GPSR6 */
183 #define GPSR6_13 FM(RPC_INT_N)
184 #define GPSR6_12 FM(RPC_RESET_N)
185 #define GPSR6_11 FM(QSPI1_SSL)
186 #define GPSR6_10 FM(QSPI1_IO3)
187 #define GPSR6_9 FM(QSPI1_IO2)
188 #define GPSR6_8 FM(QSPI1_MISO_IO1)
189 #define GPSR6_7 FM(QSPI1_MOSI_IO0)
190 #define GPSR6_6 FM(QSPI1_SPCLK)
191 #define GPSR6_5 FM(QSPI0_SSL)
192 #define GPSR6_4 FM(QSPI0_IO3)
193 #define GPSR6_3 FM(QSPI0_IO2)
194 #define GPSR6_2 FM(QSPI0_MISO_IO1)
195 #define GPSR6_1 FM(QSPI0_MOSI_IO0)
196 #define GPSR6_0 FM(QSPI0_SPCLK)
197
198 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
199 #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
233 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265
266 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
267 #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299
300 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
301 #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311
312 #define PINMUX_GPSR \
313 \
314 GPSR1_31 GPSR2_31 GPSR4_31 \
315 GPSR1_30 GPSR2_30 GPSR4_30 \
316 GPSR1_29 GPSR2_29 GPSR4_29 \
317 GPSR1_28 GPSR2_28 GPSR4_28 \
318 GPSR1_27 GPSR2_27 GPSR4_27 \
319 GPSR1_26 GPSR2_26 GPSR4_26 \
320 GPSR1_25 GPSR2_25 GPSR4_25 \
321 GPSR1_24 GPSR2_24 GPSR4_24 \
322 GPSR1_23 GPSR2_23 GPSR4_23 \
323 GPSR1_22 GPSR2_22 GPSR4_22 \
324 GPSR1_21 GPSR2_21 GPSR4_21 \
325 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
326 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
327 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
328 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
329 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
330 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
331 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
332 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
333 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
334 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
335 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
336 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
337 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
338 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
339 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
340 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
341 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
342 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
343 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
344 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
345 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
346
347 #define PINMUX_IPSR \
348 \
349 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
350 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
351 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
352 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
353 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
354 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
355 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
356 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
357 \
358 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
359 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
360 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
361 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
362 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
363 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
364 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
365 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
366 \
367 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
368 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
369 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
370 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
371 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
372 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
373 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
374 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
375 \
376 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
377 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
378 FM(IP12_11_8) IP12_11_8 \
379 FM(IP12_15_12) IP12_15_12 \
380 FM(IP12_19_16) IP12_19_16 \
381 FM(IP12_23_20) IP12_23_20 \
382 FM(IP12_27_24) IP12_27_24 \
383 FM(IP12_31_28) IP12_31_28 \
384
385 /* The bit numbering in MOD_SEL fields is reversed */
386 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
387
388 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
389 #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
390 #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
391 #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
392 #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
393 #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
394 #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
395 #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
396 #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
397 #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
398 #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
399 #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
400 #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
401 #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
402 #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
403 #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
404 #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
405 #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
406 #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
407 #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
408 #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
409 #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
410 #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
411
412 #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
413 #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
414 #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
415 #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
416 #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
417 #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
418
419
420 #define PINMUX_MOD_SELS \
421 \
422 MOD_SEL1_31 \
423 MOD_SEL0_30 MOD_SEL1_30 \
424 MOD_SEL0_29 MOD_SEL1_29 \
425 MOD_SEL0_28 MOD_SEL1_28 \
426 MOD_SEL0_27 MOD_SEL1_27 \
427 MOD_SEL0_26 MOD_SEL1_26 \
428 MOD_SEL0_25 \
429 MOD_SEL0_24_23 \
430 MOD_SEL0_22_21 \
431 MOD_SEL0_20_19 \
432 MOD_SEL0_18_17 \
433 MOD_SEL0_15 \
434 MOD_SEL0_14 \
435 MOD_SEL0_13 \
436 MOD_SEL0_12 \
437 MOD_SEL0_11 \
438 MOD_SEL0_10 \
439 MOD_SEL0_5 \
440 MOD_SEL0_4 \
441 MOD_SEL0_3 \
442 MOD_SEL0_2 \
443 MOD_SEL0_1 \
444 MOD_SEL0_0
445
446 enum {
447 PINMUX_RESERVED = 0,
448
449 PINMUX_DATA_BEGIN,
450 GP_ALL(DATA),
451 PINMUX_DATA_END,
452
453 #define F_(x, y)
454 #define FM(x) FN_##x,
455 PINMUX_FUNCTION_BEGIN,
456 GP_ALL(FN),
457 PINMUX_GPSR
458 PINMUX_IPSR
459 PINMUX_MOD_SELS
460 PINMUX_FUNCTION_END,
461 #undef F_
462 #undef FM
463
464 #define F_(x, y)
465 #define FM(x) x##_MARK,
466 PINMUX_MARK_BEGIN,
467 PINMUX_GPSR
468 PINMUX_IPSR
469 PINMUX_MOD_SELS
470 PINMUX_MARK_END,
471 #undef F_
472 #undef FM
473 };
474
475 static const u16 pinmux_data[] = {
476 PINMUX_DATA_GP_ALL(),
477
478 PINMUX_SINGLE(USB0_OVC),
479 PINMUX_SINGLE(USB0_PWEN),
480 PINMUX_SINGLE(VI4_DATA4),
481 PINMUX_SINGLE(VI4_CLK),
482 PINMUX_SINGLE(TX2),
483 PINMUX_SINGLE(RX2),
484 PINMUX_SINGLE(AVB0_LINK),
485 PINMUX_SINGLE(AVB0_PHY_INT),
486 PINMUX_SINGLE(AVB0_MAGIC),
487 PINMUX_SINGLE(AVB0_MDC),
488 PINMUX_SINGLE(AVB0_MDIO),
489 PINMUX_SINGLE(AVB0_TXCREFCLK),
490 PINMUX_SINGLE(AVB0_TD3),
491 PINMUX_SINGLE(AVB0_TD2),
492 PINMUX_SINGLE(AVB0_TD1),
493 PINMUX_SINGLE(AVB0_TD0),
494 PINMUX_SINGLE(AVB0_TXC),
495 PINMUX_SINGLE(AVB0_TX_CTL),
496 PINMUX_SINGLE(AVB0_RD3),
497 PINMUX_SINGLE(AVB0_RD2),
498 PINMUX_SINGLE(AVB0_RD1),
499 PINMUX_SINGLE(AVB0_RD0),
500 PINMUX_SINGLE(AVB0_RXC),
501 PINMUX_SINGLE(AVB0_RX_CTL),
502 PINMUX_SINGLE(RPC_INT_N),
503 PINMUX_SINGLE(RPC_RESET_N),
504 PINMUX_SINGLE(QSPI1_SSL),
505 PINMUX_SINGLE(QSPI1_IO3),
506 PINMUX_SINGLE(QSPI1_IO2),
507 PINMUX_SINGLE(QSPI1_MISO_IO1),
508 PINMUX_SINGLE(QSPI1_MOSI_IO0),
509 PINMUX_SINGLE(QSPI1_SPCLK),
510 PINMUX_SINGLE(QSPI0_SSL),
511 PINMUX_SINGLE(QSPI0_IO3),
512 PINMUX_SINGLE(QSPI0_IO2),
513 PINMUX_SINGLE(QSPI0_MISO_IO1),
514 PINMUX_SINGLE(QSPI0_MOSI_IO0),
515 PINMUX_SINGLE(QSPI0_SPCLK),
516 PINMUX_SINGLE(SCL0),
517 PINMUX_SINGLE(SDA0),
518 PINMUX_SINGLE(MSIOF0_RXD),
519 PINMUX_SINGLE(MSIOF0_TXD),
520 PINMUX_SINGLE(MSIOF0_SYNC),
521 PINMUX_SINGLE(MSIOF0_SCK),
522
523 /* IPSR0 */
524 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
525 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
526
527 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
528
529 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
530 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
531
532 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
533 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
534
535 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
536 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
537 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
538
539 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
540 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
541 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
542 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
543
544 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
545 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
546 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
547 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
548
549 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
550 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
551 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
552
553 /* IPSR1 */
554 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
555 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
556 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
557
558 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
559 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
560 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
561
562 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
563 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
564 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
565
566 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
567 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
568 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
569
570 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
571 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
572 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
573
574 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
575 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
576 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
577
578 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
579 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
580 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
581
582 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
583 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
584 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
585
586 /* IPSR2 */
587 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
588 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
589 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
590
591 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
592 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
593
594 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
595 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
596 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
597
598 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
599 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
600 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
601
602 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
603 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
604 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
605
606 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
607 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
608 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
609
610 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
611 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
612 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
613
614 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
615 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
616 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
617
618 /* IPSR3 */
619 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
620 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
621 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
622
623 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
624 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
625 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
626
627 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
628 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
629 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
630
631 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
632 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
633 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
634
635 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
636 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
637 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
638
639 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
640 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
641 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
642
643 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
644 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
645 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
646
647 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
648 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
649
650 /* IPSR4 */
651 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
652 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
653 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
654
655 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
656 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
657 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
658
659 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
660 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
661 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
662
663 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
664 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
665 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
666 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
667
668 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
669 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
670 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
671
672 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
673 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
674
675 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
676 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
677
678 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
679 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
680
681 /* IPSR5 */
682 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
683 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
684
685 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
686 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
687
688 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
689 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
690
691 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
692 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
693
694 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
695 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
696
697 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
698 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
699
700 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
701
702 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
703 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
704 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
705
706 /* IPSR6 */
707 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
708 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
709
710 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
711 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
712
713 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
714 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
715
716 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
717 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
718 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
719
720 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
721 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
722 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
723
724 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
725 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
726
727 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
728 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
729
730 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
731 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
732
733 /* IPSR7 */
734 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
735 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
736
737 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
738 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
739 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
740
741 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
742 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
743 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
744
745 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
746 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
747
748 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
749 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
750 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
751
752 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
753 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
754 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
755
756 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
757
758 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
759 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
760 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
761
762 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
763 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
764 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
765
766 /* IPSR8 */
767 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
768 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
769 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
770 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
771 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
772
773 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
774 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
775 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
776 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
777
778 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
779 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
780 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
781 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
782
783 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
784 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
785 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
786 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
787
788 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
789 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
790 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
791
792 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
793 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
794 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
795
796 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
797 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
798
799 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
800 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
801
802 /* IPSR9 */
803 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
804 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
805
806 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
807 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
808
809 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
810 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
811
812 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
813 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
814
815 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
816 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
817
818 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
819 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
820
821 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
822 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
823
824 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
825 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
826
827 /* IPSR10 */
828 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
829 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
830
831 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
832 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
833
834 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
835 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
836
837 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
838 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
839
840 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
841 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
842 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
843 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
844 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
845
846 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
847 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
848 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
849 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
850
851 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
852 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
853 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
854 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
855
856 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
857 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
858
859 /* IPSR11 */
860 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
861 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
862
863 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
864 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
865
866 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
867 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
868
869 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
870 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
871
872 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
873 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
874 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
875
876 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
877 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
878 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
879
880 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
881 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
882 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
883
884 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
885 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
886 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
887 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
888 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
889
890 /* IPSR12 */
891 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
892 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
893 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
894
895 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
896 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
897 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
898
899 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
900 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
901 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
902
903 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
904 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
905 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
906
907 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
908 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
909 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
910
911 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
912 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
913 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
914 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
915
916 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
917 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
918 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
919
920 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
921 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
922 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
923
924 /* IPSR13 */
925 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
926 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
927 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
928
929 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
930 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
931 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
932 };
933
934 static const struct sh_pfc_pin pinmux_pins[] = {
935 PINMUX_GPIO_GP_ALL(),
936 };
937
938 /* - AUDIO CLOCK ------------------------------------------------------------- */
939 static const unsigned int audio_clk_a_pins[] = {
940 /* CLK A */
941 RCAR_GP_PIN(4, 1),
942 };
943 static const unsigned int audio_clk_a_mux[] = {
944 AUDIO_CLKA_MARK,
945 };
946 static const unsigned int audio_clk_b_pins[] = {
947 /* CLK B */
948 RCAR_GP_PIN(2, 27),
949 };
950 static const unsigned int audio_clk_b_mux[] = {
951 AUDIO_CLKB_MARK,
952 };
953 static const unsigned int audio_clkout_pins[] = {
954 /* CLKOUT */
955 RCAR_GP_PIN(4, 5),
956 };
957 static const unsigned int audio_clkout_mux[] = {
958 AUDIO_CLKOUT_MARK,
959 };
960 static const unsigned int audio_clkout1_pins[] = {
961 /* CLKOUT1 */
962 RCAR_GP_PIN(4, 22),
963 };
964 static const unsigned int audio_clkout1_mux[] = {
965 AUDIO_CLKOUT1_MARK,
966 };
967
968 /* - EtherAVB --------------------------------------------------------------- */
969 static const unsigned int avb0_link_pins[] = {
970 /* AVB0_LINK */
971 RCAR_GP_PIN(5, 20),
972 };
973 static const unsigned int avb0_link_mux[] = {
974 AVB0_LINK_MARK,
975 };
976 static const unsigned int avb0_magic_pins[] = {
977 /* AVB0_MAGIC */
978 RCAR_GP_PIN(5, 18),
979 };
980 static const unsigned int avb0_magic_mux[] = {
981 AVB0_MAGIC_MARK,
982 };
983 static const unsigned int avb0_phy_int_pins[] = {
984 /* AVB0_PHY_INT */
985 RCAR_GP_PIN(5, 19),
986 };
987 static const unsigned int avb0_phy_int_mux[] = {
988 AVB0_PHY_INT_MARK,
989 };
990 static const unsigned int avb0_mdio_pins[] = {
991 /* AVB0_MDC, AVB0_MDIO */
992 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
993 };
994 static const unsigned int avb0_mdio_mux[] = {
995 AVB0_MDC_MARK, AVB0_MDIO_MARK,
996 };
997 static const unsigned int avb0_mii_pins[] = {
998 /*
999 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
1000 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
1001 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1002 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
1003 * AVB0_TXCREFCLK
1004 */
1005 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1006 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1007 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1008 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1009 RCAR_GP_PIN(5, 15),
1010 };
1011 static const unsigned int avb0_mii_mux[] = {
1012 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1013 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1014 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1015 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1016 AVB0_TXCREFCLK_MARK,
1017 };
1018 static const unsigned int avb0_avtp_pps_a_pins[] = {
1019 /* AVB0_AVTP_PPS_A */
1020 RCAR_GP_PIN(5, 2),
1021 };
1022 static const unsigned int avb0_avtp_pps_a_mux[] = {
1023 AVB0_AVTP_PPS_A_MARK,
1024 };
1025 static const unsigned int avb0_avtp_match_a_pins[] = {
1026 /* AVB0_AVTP_MATCH_A */
1027 RCAR_GP_PIN(5, 1),
1028 };
1029 static const unsigned int avb0_avtp_match_a_mux[] = {
1030 AVB0_AVTP_MATCH_A_MARK,
1031 };
1032 static const unsigned int avb0_avtp_capture_a_pins[] = {
1033 /* AVB0_AVTP_CAPTURE_A */
1034 RCAR_GP_PIN(5, 0),
1035 };
1036 static const unsigned int avb0_avtp_capture_a_mux[] = {
1037 AVB0_AVTP_CAPTURE_A_MARK,
1038 };
1039 static const unsigned int avb0_avtp_pps_b_pins[] = {
1040 /* AVB0_AVTP_PPS_B */
1041 RCAR_GP_PIN(4, 16),
1042 };
1043 static const unsigned int avb0_avtp_pps_b_mux[] = {
1044 AVB0_AVTP_PPS_B_MARK,
1045 };
1046 static const unsigned int avb0_avtp_match_b_pins[] = {
1047 /* AVB0_AVTP_MATCH_B */
1048 RCAR_GP_PIN(4, 18),
1049 };
1050 static const unsigned int avb0_avtp_match_b_mux[] = {
1051 AVB0_AVTP_MATCH_B_MARK,
1052 };
1053 static const unsigned int avb0_avtp_capture_b_pins[] = {
1054 /* AVB0_AVTP_CAPTURE_B */
1055 RCAR_GP_PIN(4, 17),
1056 };
1057 static const unsigned int avb0_avtp_capture_b_mux[] = {
1058 AVB0_AVTP_CAPTURE_B_MARK,
1059 };
1060
1061 /* - CAN ------------------------------------------------------------------ */
1062 static const unsigned int can0_data_a_pins[] = {
1063 /* TX, RX */
1064 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1065 };
1066 static const unsigned int can0_data_a_mux[] = {
1067 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1068 };
1069 static const unsigned int can0_data_b_pins[] = {
1070 /* TX, RX */
1071 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1072 };
1073 static const unsigned int can0_data_b_mux[] = {
1074 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1075 };
1076 static const unsigned int can1_data_a_pins[] = {
1077 /* TX, RX */
1078 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1079 };
1080 static const unsigned int can1_data_a_mux[] = {
1081 CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1082 };
1083 static const unsigned int can1_data_b_pins[] = {
1084 /* TX, RX */
1085 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1086 };
1087 static const unsigned int can1_data_b_mux[] = {
1088 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1089 };
1090
1091 /* - CAN Clock -------------------------------------------------------------- */
1092 static const unsigned int can_clk_pins[] = {
1093 /* CLK */
1094 RCAR_GP_PIN(5, 2),
1095 };
1096 static const unsigned int can_clk_mux[] = {
1097 CAN_CLK_MARK,
1098 };
1099
1100 /* - CAN FD ----------------------------------------------------------------- */
1101 static const unsigned int canfd0_data_pins[] = {
1102 /* TX, RX */
1103 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1104 };
1105 static const unsigned int canfd0_data_mux[] = {
1106 CANFD0_TX_MARK, CANFD0_RX_MARK,
1107 };
1108 static const unsigned int canfd1_data_pins[] = {
1109 /* TX, RX */
1110 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1111 };
1112 static const unsigned int canfd1_data_mux[] = {
1113 CANFD1_TX_MARK, CANFD1_RX_MARK,
1114 };
1115
1116 /* - DU --------------------------------------------------------------------- */
1117 static const unsigned int du_rgb666_pins[] = {
1118 /* R[7:2], G[7:2], B[7:2] */
1119 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1120 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1121 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1122 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1123 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1124 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1125 };
1126 static const unsigned int du_rgb666_mux[] = {
1127 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1128 DU_DR3_MARK, DU_DR2_MARK,
1129 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1130 DU_DG3_MARK, DU_DG2_MARK,
1131 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1132 DU_DB3_MARK, DU_DB2_MARK,
1133 };
1134 static const unsigned int du_rgb888_pins[] = {
1135 /* R[7:0], G[7:0], B[7:0] */
1136 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1137 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1138 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1139 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1140 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1141 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1142 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1143 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1144 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1145 };
1146 static const unsigned int du_rgb888_mux[] = {
1147 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1148 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1149 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1150 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1151 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1152 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1153 };
1154 static const unsigned int du_clk_in_1_pins[] = {
1155 /* CLKIN */
1156 RCAR_GP_PIN(1, 28),
1157 };
1158 static const unsigned int du_clk_in_1_mux[] = {
1159 DU_DOTCLKIN1_MARK
1160 };
1161 static const unsigned int du_clk_out_0_pins[] = {
1162 /* CLKOUT */
1163 RCAR_GP_PIN(1, 24),
1164 };
1165 static const unsigned int du_clk_out_0_mux[] = {
1166 DU_DOTCLKOUT0_MARK
1167 };
1168 static const unsigned int du_sync_pins[] = {
1169 /* VSYNC, HSYNC */
1170 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1171 };
1172 static const unsigned int du_sync_mux[] = {
1173 DU_VSYNC_MARK, DU_HSYNC_MARK
1174 };
1175 static const unsigned int du_disp_cde_pins[] = {
1176 /* DISP_CDE */
1177 RCAR_GP_PIN(1, 28),
1178 };
1179 static const unsigned int du_disp_cde_mux[] = {
1180 DU_DISP_CDE_MARK,
1181 };
1182 static const unsigned int du_cde_pins[] = {
1183 /* CDE */
1184 RCAR_GP_PIN(1, 29),
1185 };
1186 static const unsigned int du_cde_mux[] = {
1187 DU_CDE_MARK,
1188 };
1189 static const unsigned int du_disp_pins[] = {
1190 /* DISP */
1191 RCAR_GP_PIN(1, 27),
1192 };
1193 static const unsigned int du_disp_mux[] = {
1194 DU_DISP_MARK,
1195 };
1196
1197 /* - I2C -------------------------------------------------------------------- */
1198 static const unsigned int i2c0_pins[] = {
1199 /* SCL, SDA */
1200 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1201 };
1202 static const unsigned int i2c0_mux[] = {
1203 SCL0_MARK, SDA0_MARK,
1204 };
1205 static const unsigned int i2c1_pins[] = {
1206 /* SCL, SDA */
1207 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1208 };
1209 static const unsigned int i2c1_mux[] = {
1210 SCL1_MARK, SDA1_MARK,
1211 };
1212 static const unsigned int i2c2_a_pins[] = {
1213 /* SCL, SDA */
1214 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1215 };
1216 static const unsigned int i2c2_a_mux[] = {
1217 SCL2_A_MARK, SDA2_A_MARK,
1218 };
1219 static const unsigned int i2c2_b_pins[] = {
1220 /* SCL, SDA */
1221 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1222 };
1223 static const unsigned int i2c2_b_mux[] = {
1224 SCL2_B_MARK, SDA2_B_MARK,
1225 };
1226 static const unsigned int i2c3_a_pins[] = {
1227 /* SCL, SDA */
1228 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1229 };
1230 static const unsigned int i2c3_a_mux[] = {
1231 SCL3_A_MARK, SDA3_A_MARK,
1232 };
1233 static const unsigned int i2c3_b_pins[] = {
1234 /* SCL, SDA */
1235 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1236 };
1237 static const unsigned int i2c3_b_mux[] = {
1238 SCL3_B_MARK, SDA3_B_MARK,
1239 };
1240
1241 /* - MMC ------------------------------------------------------------------- */
1242 static const unsigned int mmc_data1_pins[] = {
1243 /* D0 */
1244 RCAR_GP_PIN(3, 2),
1245 };
1246 static const unsigned int mmc_data1_mux[] = {
1247 MMC_D0_MARK,
1248 };
1249 static const unsigned int mmc_data4_pins[] = {
1250 /* D[0:3] */
1251 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1252 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1253 };
1254 static const unsigned int mmc_data4_mux[] = {
1255 MMC_D0_MARK, MMC_D1_MARK,
1256 MMC_D2_MARK, MMC_D3_MARK,
1257 };
1258 static const unsigned int mmc_data8_pins[] = {
1259 /* D[0:7] */
1260 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1261 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1262 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1263 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1264 };
1265 static const unsigned int mmc_data8_mux[] = {
1266 MMC_D0_MARK, MMC_D1_MARK,
1267 MMC_D2_MARK, MMC_D3_MARK,
1268 MMC_D4_MARK, MMC_D5_MARK,
1269 MMC_D6_MARK, MMC_D7_MARK,
1270 };
1271 static const unsigned int mmc_ctrl_pins[] = {
1272 /* CLK, CMD */
1273 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1274 };
1275 static const unsigned int mmc_ctrl_mux[] = {
1276 MMC_CLK_MARK, MMC_CMD_MARK,
1277 };
1278
1279 /* - MSIOF0 ----------------------------------------------------------------- */
1280 static const unsigned int msiof0_clk_pins[] = {
1281 /* SCK */
1282 RCAR_GP_PIN(4, 12),
1283 };
1284
1285 static const unsigned int msiof0_clk_mux[] = {
1286 MSIOF0_SCK_MARK,
1287 };
1288
1289 static const unsigned int msiof0_sync_pins[] = {
1290 /* SYNC */
1291 RCAR_GP_PIN(4, 13),
1292 };
1293
1294 static const unsigned int msiof0_sync_mux[] = {
1295 MSIOF0_SYNC_MARK,
1296 };
1297
1298 static const unsigned int msiof0_ss1_pins[] = {
1299 /* SS1 */
1300 RCAR_GP_PIN(4, 20),
1301 };
1302
1303 static const unsigned int msiof0_ss1_mux[] = {
1304 MSIOF0_SS1_MARK,
1305 };
1306
1307 static const unsigned int msiof0_ss2_pins[] = {
1308 /* SS2 */
1309 RCAR_GP_PIN(4, 21),
1310 };
1311
1312 static const unsigned int msiof0_ss2_mux[] = {
1313 MSIOF0_SS2_MARK,
1314 };
1315
1316 static const unsigned int msiof0_txd_pins[] = {
1317 /* TXD */
1318 RCAR_GP_PIN(4, 14),
1319 };
1320
1321 static const unsigned int msiof0_txd_mux[] = {
1322 MSIOF0_TXD_MARK,
1323 };
1324
1325 static const unsigned int msiof0_rxd_pins[] = {
1326 /* RXD */
1327 RCAR_GP_PIN(4, 15),
1328 };
1329
1330 static const unsigned int msiof0_rxd_mux[] = {
1331 MSIOF0_RXD_MARK,
1332 };
1333
1334 /* - MSIOF1 ----------------------------------------------------------------- */
1335 static const unsigned int msiof1_clk_pins[] = {
1336 /* SCK */
1337 RCAR_GP_PIN(4, 16),
1338 };
1339
1340 static const unsigned int msiof1_clk_mux[] = {
1341 MSIOF1_SCK_MARK,
1342 };
1343
1344 static const unsigned int msiof1_sync_pins[] = {
1345 /* SYNC */
1346 RCAR_GP_PIN(4, 19),
1347 };
1348
1349 static const unsigned int msiof1_sync_mux[] = {
1350 MSIOF1_SYNC_MARK,
1351 };
1352
1353 static const unsigned int msiof1_ss1_pins[] = {
1354 /* SS1 */
1355 RCAR_GP_PIN(4, 25),
1356 };
1357
1358 static const unsigned int msiof1_ss1_mux[] = {
1359 MSIOF1_SS1_MARK,
1360 };
1361
1362 static const unsigned int msiof1_ss2_pins[] = {
1363 /* SS2 */
1364 RCAR_GP_PIN(4, 22),
1365 };
1366
1367 static const unsigned int msiof1_ss2_mux[] = {
1368 MSIOF1_SS2_MARK,
1369 };
1370
1371 static const unsigned int msiof1_txd_pins[] = {
1372 /* TXD */
1373 RCAR_GP_PIN(4, 17),
1374 };
1375
1376 static const unsigned int msiof1_txd_mux[] = {
1377 MSIOF1_TXD_MARK,
1378 };
1379
1380 static const unsigned int msiof1_rxd_pins[] = {
1381 /* RXD */
1382 RCAR_GP_PIN(4, 18),
1383 };
1384
1385 static const unsigned int msiof1_rxd_mux[] = {
1386 MSIOF1_RXD_MARK,
1387 };
1388
1389 /* - MSIOF2 ----------------------------------------------------------------- */
1390 static const unsigned int msiof2_clk_pins[] = {
1391 /* SCK */
1392 RCAR_GP_PIN(0, 3),
1393 };
1394
1395 static const unsigned int msiof2_clk_mux[] = {
1396 MSIOF2_SCK_MARK,
1397 };
1398
1399 static const unsigned int msiof2_sync_a_pins[] = {
1400 /* SYNC */
1401 RCAR_GP_PIN(0, 6),
1402 };
1403
1404 static const unsigned int msiof2_sync_a_mux[] = {
1405 MSIOF2_SYNC_A_MARK,
1406 };
1407
1408 static const unsigned int msiof2_sync_b_pins[] = {
1409 /* SYNC */
1410 RCAR_GP_PIN(0, 2),
1411 };
1412
1413 static const unsigned int msiof2_sync_b_mux[] = {
1414 MSIOF2_SYNC_B_MARK,
1415 };
1416
1417 static const unsigned int msiof2_ss1_pins[] = {
1418 /* SS1 */
1419 RCAR_GP_PIN(0, 7),
1420 };
1421
1422 static const unsigned int msiof2_ss1_mux[] = {
1423 MSIOF2_SS1_MARK,
1424 };
1425
1426 static const unsigned int msiof2_ss2_pins[] = {
1427 /* SS2 */
1428 RCAR_GP_PIN(0, 8),
1429 };
1430
1431 static const unsigned int msiof2_ss2_mux[] = {
1432 MSIOF2_SS2_MARK,
1433 };
1434
1435 static const unsigned int msiof2_txd_pins[] = {
1436 /* TXD */
1437 RCAR_GP_PIN(0, 4),
1438 };
1439
1440 static const unsigned int msiof2_txd_mux[] = {
1441 MSIOF2_TXD_MARK,
1442 };
1443
1444 static const unsigned int msiof2_rxd_pins[] = {
1445 /* RXD */
1446 RCAR_GP_PIN(0, 5),
1447 };
1448
1449 static const unsigned int msiof2_rxd_mux[] = {
1450 MSIOF2_RXD_MARK,
1451 };
1452
1453 /* - MSIOF3 ----------------------------------------------------------------- */
1454 static const unsigned int msiof3_clk_a_pins[] = {
1455 /* SCK */
1456 RCAR_GP_PIN(2, 24),
1457 };
1458
1459 static const unsigned int msiof3_clk_a_mux[] = {
1460 MSIOF3_SCK_A_MARK,
1461 };
1462
1463 static const unsigned int msiof3_sync_a_pins[] = {
1464 /* SYNC */
1465 RCAR_GP_PIN(2, 21),
1466 };
1467
1468 static const unsigned int msiof3_sync_a_mux[] = {
1469 MSIOF3_SYNC_A_MARK,
1470 };
1471
1472 static const unsigned int msiof3_ss1_a_pins[] = {
1473 /* SS1 */
1474 RCAR_GP_PIN(2, 14),
1475 };
1476
1477 static const unsigned int msiof3_ss1_a_mux[] = {
1478 MSIOF3_SS1_A_MARK,
1479 };
1480
1481 static const unsigned int msiof3_ss2_a_pins[] = {
1482 /* SS2 */
1483 RCAR_GP_PIN(2, 10),
1484 };
1485
1486 static const unsigned int msiof3_ss2_a_mux[] = {
1487 MSIOF3_SS2_A_MARK,
1488 };
1489
1490 static const unsigned int msiof3_txd_a_pins[] = {
1491 /* TXD */
1492 RCAR_GP_PIN(2, 22),
1493 };
1494
1495 static const unsigned int msiof3_txd_a_mux[] = {
1496 MSIOF3_TXD_A_MARK,
1497 };
1498
1499 static const unsigned int msiof3_rxd_a_pins[] = {
1500 /* RXD */
1501 RCAR_GP_PIN(2, 23),
1502 };
1503
1504 static const unsigned int msiof3_rxd_a_mux[] = {
1505 MSIOF3_RXD_A_MARK,
1506 };
1507
1508 static const unsigned int msiof3_clk_b_pins[] = {
1509 /* SCK */
1510 RCAR_GP_PIN(1, 8),
1511 };
1512
1513 static const unsigned int msiof3_clk_b_mux[] = {
1514 MSIOF3_SCK_B_MARK,
1515 };
1516
1517 static const unsigned int msiof3_sync_b_pins[] = {
1518 /* SYNC */
1519 RCAR_GP_PIN(1, 9),
1520 };
1521
1522 static const unsigned int msiof3_sync_b_mux[] = {
1523 MSIOF3_SYNC_B_MARK,
1524 };
1525
1526 static const unsigned int msiof3_ss1_b_pins[] = {
1527 /* SS1 */
1528 RCAR_GP_PIN(1, 6),
1529 };
1530
1531 static const unsigned int msiof3_ss1_b_mux[] = {
1532 MSIOF3_SS1_B_MARK,
1533 };
1534
1535 static const unsigned int msiof3_ss2_b_pins[] = {
1536 /* SS2 */
1537 RCAR_GP_PIN(1, 7),
1538 };
1539
1540 static const unsigned int msiof3_ss2_b_mux[] = {
1541 MSIOF3_SS2_B_MARK,
1542 };
1543
1544 static const unsigned int msiof3_txd_b_pins[] = {
1545 /* TXD */
1546 RCAR_GP_PIN(1, 0),
1547 };
1548
1549 static const unsigned int msiof3_txd_b_mux[] = {
1550 MSIOF3_TXD_B_MARK,
1551 };
1552
1553 static const unsigned int msiof3_rxd_b_pins[] = {
1554 /* RXD */
1555 RCAR_GP_PIN(1, 1),
1556 };
1557
1558 static const unsigned int msiof3_rxd_b_mux[] = {
1559 MSIOF3_RXD_B_MARK,
1560 };
1561
1562 /* - PWM0 ------------------------------------------------------------------ */
1563 static const unsigned int pwm0_a_pins[] = {
1564 /* PWM */
1565 RCAR_GP_PIN(2, 1),
1566 };
1567
1568 static const unsigned int pwm0_a_mux[] = {
1569 PWM0_A_MARK,
1570 };
1571
1572 static const unsigned int pwm0_b_pins[] = {
1573 /* PWM */
1574 RCAR_GP_PIN(1, 18),
1575 };
1576
1577 static const unsigned int pwm0_b_mux[] = {
1578 PWM0_B_MARK,
1579 };
1580
1581 static const unsigned int pwm0_c_pins[] = {
1582 /* PWM */
1583 RCAR_GP_PIN(2, 29),
1584 };
1585
1586 static const unsigned int pwm0_c_mux[] = {
1587 PWM0_C_MARK,
1588 };
1589
1590 /* - PWM1 ------------------------------------------------------------------ */
1591 static const unsigned int pwm1_a_pins[] = {
1592 /* PWM */
1593 RCAR_GP_PIN(2, 2),
1594 };
1595
1596 static const unsigned int pwm1_a_mux[] = {
1597 PWM1_A_MARK,
1598 };
1599
1600 static const unsigned int pwm1_b_pins[] = {
1601 /* PWM */
1602 RCAR_GP_PIN(1, 19),
1603 };
1604
1605 static const unsigned int pwm1_b_mux[] = {
1606 PWM1_B_MARK,
1607 };
1608
1609 static const unsigned int pwm1_c_pins[] = {
1610 /* PWM */
1611 RCAR_GP_PIN(2, 30),
1612 };
1613
1614 static const unsigned int pwm1_c_mux[] = {
1615 PWM1_C_MARK,
1616 };
1617
1618 /* - PWM2 ------------------------------------------------------------------ */
1619 static const unsigned int pwm2_a_pins[] = {
1620 /* PWM */
1621 RCAR_GP_PIN(2, 3),
1622 };
1623
1624 static const unsigned int pwm2_a_mux[] = {
1625 PWM2_A_MARK,
1626 };
1627
1628 static const unsigned int pwm2_b_pins[] = {
1629 /* PWM */
1630 RCAR_GP_PIN(1, 22),
1631 };
1632
1633 static const unsigned int pwm2_b_mux[] = {
1634 PWM2_B_MARK,
1635 };
1636
1637 static const unsigned int pwm2_c_pins[] = {
1638 /* PWM */
1639 RCAR_GP_PIN(2, 31),
1640 };
1641
1642 static const unsigned int pwm2_c_mux[] = {
1643 PWM2_C_MARK,
1644 };
1645
1646 /* - PWM3 ------------------------------------------------------------------ */
1647 static const unsigned int pwm3_a_pins[] = {
1648 /* PWM */
1649 RCAR_GP_PIN(2, 4),
1650 };
1651
1652 static const unsigned int pwm3_a_mux[] = {
1653 PWM3_A_MARK,
1654 };
1655
1656 static const unsigned int pwm3_b_pins[] = {
1657 /* PWM */
1658 RCAR_GP_PIN(1, 27),
1659 };
1660
1661 static const unsigned int pwm3_b_mux[] = {
1662 PWM3_B_MARK,
1663 };
1664
1665 static const unsigned int pwm3_c_pins[] = {
1666 /* PWM */
1667 RCAR_GP_PIN(4, 0),
1668 };
1669
1670 static const unsigned int pwm3_c_mux[] = {
1671 PWM3_C_MARK,
1672 };
1673
1674 /* - SCIF0 ------------------------------------------------------------------ */
1675 static const unsigned int scif0_data_a_pins[] = {
1676 /* RX, TX */
1677 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1678 };
1679 static const unsigned int scif0_data_a_mux[] = {
1680 RX0_A_MARK, TX0_A_MARK,
1681 };
1682 static const unsigned int scif0_clk_a_pins[] = {
1683 /* SCK */
1684 RCAR_GP_PIN(4, 19),
1685 };
1686 static const unsigned int scif0_clk_a_mux[] = {
1687 SCK0_A_MARK,
1688 };
1689 static const unsigned int scif0_data_b_pins[] = {
1690 /* RX, TX */
1691 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1692 };
1693 static const unsigned int scif0_data_b_mux[] = {
1694 RX0_B_MARK, TX0_B_MARK,
1695 };
1696 static const unsigned int scif0_clk_b_pins[] = {
1697 /* SCK */
1698 RCAR_GP_PIN(5, 2),
1699 };
1700 static const unsigned int scif0_clk_b_mux[] = {
1701 SCK0_B_MARK,
1702 };
1703 static const unsigned int scif0_ctrl_pins[] = {
1704 /* RTS, CTS */
1705 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1706 };
1707 static const unsigned int scif0_ctrl_mux[] = {
1708 RTS0_N_MARK, CTS0_N_MARK,
1709 };
1710 /* - SCIF1 ------------------------------------------------------------------ */
1711 static const unsigned int scif1_data_a_pins[] = {
1712 /* RX, TX */
1713 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1714 };
1715 static const unsigned int scif1_data_a_mux[] = {
1716 RX1_A_MARK, TX1_A_MARK,
1717 };
1718 static const unsigned int scif1_clk_a_pins[] = {
1719 /* SCK */
1720 RCAR_GP_PIN(4, 22),
1721 };
1722 static const unsigned int scif1_clk_a_mux[] = {
1723 SCK1_A_MARK,
1724 };
1725 static const unsigned int scif1_data_b_pins[] = {
1726 /* RX, TX */
1727 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1728 };
1729 static const unsigned int scif1_data_b_mux[] = {
1730 RX1_B_MARK, TX1_B_MARK,
1731 };
1732 static const unsigned int scif1_clk_b_pins[] = {
1733 /* SCK */
1734 RCAR_GP_PIN(2, 25),
1735 };
1736 static const unsigned int scif1_clk_b_mux[] = {
1737 SCK1_B_MARK,
1738 };
1739 static const unsigned int scif1_ctrl_pins[] = {
1740 /* RTS, CTS */
1741 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1742 };
1743 static const unsigned int scif1_ctrl_mux[] = {
1744 RTS1_N_MARK, CTS1_N_MARK,
1745 };
1746
1747 /* - SCIF2 ------------------------------------------------------------------ */
1748 static const unsigned int scif2_data_pins[] = {
1749 /* RX, TX */
1750 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1751 };
1752 static const unsigned int scif2_data_mux[] = {
1753 RX2_MARK, TX2_MARK,
1754 };
1755 static const unsigned int scif2_clk_pins[] = {
1756 /* SCK */
1757 RCAR_GP_PIN(4, 25),
1758 };
1759 static const unsigned int scif2_clk_mux[] = {
1760 SCK2_MARK,
1761 };
1762 /* - SCIF3 ------------------------------------------------------------------ */
1763 static const unsigned int scif3_data_a_pins[] = {
1764 /* RX, TX */
1765 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1766 };
1767 static const unsigned int scif3_data_a_mux[] = {
1768 RX3_A_MARK, TX3_A_MARK,
1769 };
1770 static const unsigned int scif3_clk_a_pins[] = {
1771 /* SCK */
1772 RCAR_GP_PIN(2, 30),
1773 };
1774 static const unsigned int scif3_clk_a_mux[] = {
1775 SCK3_A_MARK,
1776 };
1777 static const unsigned int scif3_data_b_pins[] = {
1778 /* RX, TX */
1779 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1780 };
1781 static const unsigned int scif3_data_b_mux[] = {
1782 RX3_B_MARK, TX3_B_MARK,
1783 };
1784 static const unsigned int scif3_clk_b_pins[] = {
1785 /* SCK */
1786 RCAR_GP_PIN(1, 29),
1787 };
1788 static const unsigned int scif3_clk_b_mux[] = {
1789 SCK3_B_MARK,
1790 };
1791 /* - SCIF4 ------------------------------------------------------------------ */
1792 static const unsigned int scif4_data_a_pins[] = {
1793 /* RX, TX */
1794 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1795 };
1796 static const unsigned int scif4_data_a_mux[] = {
1797 RX4_A_MARK, TX4_A_MARK,
1798 };
1799 static const unsigned int scif4_clk_a_pins[] = {
1800 /* SCK */
1801 RCAR_GP_PIN(2, 6),
1802 };
1803 static const unsigned int scif4_clk_a_mux[] = {
1804 SCK4_A_MARK,
1805 };
1806 static const unsigned int scif4_data_b_pins[] = {
1807 /* RX, TX */
1808 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1809 };
1810 static const unsigned int scif4_data_b_mux[] = {
1811 RX4_B_MARK, TX4_B_MARK,
1812 };
1813 static const unsigned int scif4_clk_b_pins[] = {
1814 /* SCK */
1815 RCAR_GP_PIN(1, 15),
1816 };
1817 static const unsigned int scif4_clk_b_mux[] = {
1818 SCK4_B_MARK,
1819 };
1820 /* - SCIF5 ------------------------------------------------------------------ */
1821 static const unsigned int scif5_data_a_pins[] = {
1822 /* RX, TX */
1823 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1824 };
1825 static const unsigned int scif5_data_a_mux[] = {
1826 RX5_A_MARK, TX5_A_MARK,
1827 };
1828 static const unsigned int scif5_clk_a_pins[] = {
1829 /* SCK */
1830 RCAR_GP_PIN(0, 6),
1831 };
1832 static const unsigned int scif5_clk_a_mux[] = {
1833 SCK5_A_MARK,
1834 };
1835 static const unsigned int scif5_data_b_pins[] = {
1836 /* RX, TX */
1837 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1838 };
1839 static const unsigned int scif5_data_b_mux[] = {
1840 RX5_B_MARK, TX5_B_MARK,
1841 };
1842 static const unsigned int scif5_clk_b_pins[] = {
1843 /* SCK */
1844 RCAR_GP_PIN(1, 3),
1845 };
1846 static const unsigned int scif5_clk_b_mux[] = {
1847 SCK5_B_MARK,
1848 };
1849 /* - SCIF Clock ------------------------------------------------------------- */
1850 static const unsigned int scif_clk_pins[] = {
1851 /* SCIF_CLK */
1852 RCAR_GP_PIN(2, 27),
1853 };
1854 static const unsigned int scif_clk_mux[] = {
1855 SCIF_CLK_MARK,
1856 };
1857
1858 /* - SSI ---------------------------------------------------------------*/
1859 static const unsigned int ssi3_data_pins[] = {
1860 /* SDATA */
1861 RCAR_GP_PIN(4, 3),
1862 };
1863 static const unsigned int ssi3_data_mux[] = {
1864 SSI_SDATA3_MARK,
1865 };
1866 static const unsigned int ssi34_ctrl_pins[] = {
1867 /* SCK, WS */
1868 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1869 };
1870 static const unsigned int ssi34_ctrl_mux[] = {
1871 SSI_SCK34_MARK, SSI_WS34_MARK,
1872 };
1873 static const unsigned int ssi4_ctrl_a_pins[] = {
1874 /* SCK, WS */
1875 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1876 };
1877 static const unsigned int ssi4_ctrl_a_mux[] = {
1878 SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1879 };
1880 static const unsigned int ssi4_data_a_pins[] = {
1881 /* SDATA */
1882 RCAR_GP_PIN(4, 6),
1883 };
1884 static const unsigned int ssi4_data_a_mux[] = {
1885 SSI_SDATA4_A_MARK,
1886 };
1887 static const unsigned int ssi4_ctrl_b_pins[] = {
1888 /* SCK, WS */
1889 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1890 };
1891 static const unsigned int ssi4_ctrl_b_mux[] = {
1892 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1893 };
1894 static const unsigned int ssi4_data_b_pins[] = {
1895 /* SDATA */
1896 RCAR_GP_PIN(2, 16),
1897 };
1898 static const unsigned int ssi4_data_b_mux[] = {
1899 SSI_SDATA4_B_MARK,
1900 };
1901
1902 /* - USB0 ------------------------------------------------------------------- */
1903 static const unsigned int usb0_pins[] = {
1904 /* PWEN, OVC */
1905 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1906 };
1907 static const unsigned int usb0_mux[] = {
1908 USB0_PWEN_MARK, USB0_OVC_MARK,
1909 };
1910
1911 /* - VIN4 ------------------------------------------------------------------- */
1912 static const unsigned int vin4_data18_pins[] = {
1913 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1914 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1915 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1916 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1917 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1918 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1919 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1920 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1921 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1922 };
1923 static const unsigned int vin4_data18_mux[] = {
1924 VI4_DATA2_MARK, VI4_DATA3_MARK,
1925 VI4_DATA4_MARK, VI4_DATA5_MARK,
1926 VI4_DATA6_MARK, VI4_DATA7_MARK,
1927 VI4_DATA10_MARK, VI4_DATA11_MARK,
1928 VI4_DATA12_MARK, VI4_DATA13_MARK,
1929 VI4_DATA14_MARK, VI4_DATA15_MARK,
1930 VI4_DATA18_MARK, VI4_DATA19_MARK,
1931 VI4_DATA20_MARK, VI4_DATA21_MARK,
1932 VI4_DATA22_MARK, VI4_DATA23_MARK,
1933 };
1934 static const union vin_data vin4_data_pins = {
1935 .data24 = {
1936 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1937 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1938 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1939 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1940 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1941 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1942 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1943 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1944 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1945 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1946 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1947 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1948 },
1949 };
1950 static const union vin_data vin4_data_mux = {
1951 .data24 = {
1952 VI4_DATA0_MARK, VI4_DATA1_MARK,
1953 VI4_DATA2_MARK, VI4_DATA3_MARK,
1954 VI4_DATA4_MARK, VI4_DATA5_MARK,
1955 VI4_DATA6_MARK, VI4_DATA7_MARK,
1956 VI4_DATA8_MARK, VI4_DATA9_MARK,
1957 VI4_DATA10_MARK, VI4_DATA11_MARK,
1958 VI4_DATA12_MARK, VI4_DATA13_MARK,
1959 VI4_DATA14_MARK, VI4_DATA15_MARK,
1960 VI4_DATA16_MARK, VI4_DATA17_MARK,
1961 VI4_DATA18_MARK, VI4_DATA19_MARK,
1962 VI4_DATA20_MARK, VI4_DATA21_MARK,
1963 VI4_DATA22_MARK, VI4_DATA23_MARK,
1964 },
1965 };
1966 static const unsigned int vin4_sync_pins[] = {
1967 /* HSYNC#, VSYNC# */
1968 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1969 };
1970 static const unsigned int vin4_sync_mux[] = {
1971 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1972 };
1973 static const unsigned int vin4_field_pins[] = {
1974 /* FIELD */
1975 RCAR_GP_PIN(2, 27),
1976 };
1977 static const unsigned int vin4_field_mux[] = {
1978 VI4_FIELD_MARK,
1979 };
1980 static const unsigned int vin4_clkenb_pins[] = {
1981 /* CLKENB */
1982 RCAR_GP_PIN(2, 28),
1983 };
1984 static const unsigned int vin4_clkenb_mux[] = {
1985 VI4_CLKENB_MARK,
1986 };
1987 static const unsigned int vin4_clk_pins[] = {
1988 /* CLK */
1989 RCAR_GP_PIN(2, 0),
1990 };
1991 static const unsigned int vin4_clk_mux[] = {
1992 VI4_CLK_MARK,
1993 };
1994
1995 static const struct sh_pfc_pin_group pinmux_groups[] = {
1996 SH_PFC_PIN_GROUP(audio_clk_a),
1997 SH_PFC_PIN_GROUP(audio_clk_b),
1998 SH_PFC_PIN_GROUP(audio_clkout),
1999 SH_PFC_PIN_GROUP(audio_clkout1),
2000 SH_PFC_PIN_GROUP(avb0_link),
2001 SH_PFC_PIN_GROUP(avb0_magic),
2002 SH_PFC_PIN_GROUP(avb0_phy_int),
2003 SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
2004 SH_PFC_PIN_GROUP(avb0_mdio),
2005 SH_PFC_PIN_GROUP(avb0_mii),
2006 SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
2007 SH_PFC_PIN_GROUP(avb0_avtp_match_a),
2008 SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
2009 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
2010 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
2011 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
2012 SH_PFC_PIN_GROUP(can0_data_a),
2013 SH_PFC_PIN_GROUP(can0_data_b),
2014 SH_PFC_PIN_GROUP(can1_data_a),
2015 SH_PFC_PIN_GROUP(can1_data_b),
2016 SH_PFC_PIN_GROUP(can_clk),
2017 SH_PFC_PIN_GROUP(canfd0_data),
2018 SH_PFC_PIN_GROUP(canfd1_data),
2019 SH_PFC_PIN_GROUP(du_rgb666),
2020 SH_PFC_PIN_GROUP(du_rgb888),
2021 SH_PFC_PIN_GROUP(du_clk_in_1),
2022 SH_PFC_PIN_GROUP(du_clk_out_0),
2023 SH_PFC_PIN_GROUP(du_sync),
2024 SH_PFC_PIN_GROUP(du_disp_cde),
2025 SH_PFC_PIN_GROUP(du_cde),
2026 SH_PFC_PIN_GROUP(du_disp),
2027 SH_PFC_PIN_GROUP(i2c0),
2028 SH_PFC_PIN_GROUP(i2c1),
2029 SH_PFC_PIN_GROUP(i2c2_a),
2030 SH_PFC_PIN_GROUP(i2c2_b),
2031 SH_PFC_PIN_GROUP(i2c3_a),
2032 SH_PFC_PIN_GROUP(i2c3_b),
2033 SH_PFC_PIN_GROUP(mmc_data1),
2034 SH_PFC_PIN_GROUP(mmc_data4),
2035 SH_PFC_PIN_GROUP(mmc_data8),
2036 SH_PFC_PIN_GROUP(mmc_ctrl),
2037 SH_PFC_PIN_GROUP(msiof0_clk),
2038 SH_PFC_PIN_GROUP(msiof0_sync),
2039 SH_PFC_PIN_GROUP(msiof0_ss1),
2040 SH_PFC_PIN_GROUP(msiof0_ss2),
2041 SH_PFC_PIN_GROUP(msiof0_txd),
2042 SH_PFC_PIN_GROUP(msiof0_rxd),
2043 SH_PFC_PIN_GROUP(msiof1_clk),
2044 SH_PFC_PIN_GROUP(msiof1_sync),
2045 SH_PFC_PIN_GROUP(msiof1_ss1),
2046 SH_PFC_PIN_GROUP(msiof1_ss2),
2047 SH_PFC_PIN_GROUP(msiof1_txd),
2048 SH_PFC_PIN_GROUP(msiof1_rxd),
2049 SH_PFC_PIN_GROUP(msiof2_clk),
2050 SH_PFC_PIN_GROUP(msiof2_sync_a),
2051 SH_PFC_PIN_GROUP(msiof2_sync_b),
2052 SH_PFC_PIN_GROUP(msiof2_ss1),
2053 SH_PFC_PIN_GROUP(msiof2_ss2),
2054 SH_PFC_PIN_GROUP(msiof2_txd),
2055 SH_PFC_PIN_GROUP(msiof2_rxd),
2056 SH_PFC_PIN_GROUP(msiof3_clk_a),
2057 SH_PFC_PIN_GROUP(msiof3_sync_a),
2058 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2059 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2060 SH_PFC_PIN_GROUP(msiof3_txd_a),
2061 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2062 SH_PFC_PIN_GROUP(msiof3_clk_b),
2063 SH_PFC_PIN_GROUP(msiof3_sync_b),
2064 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2065 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2066 SH_PFC_PIN_GROUP(msiof3_txd_b),
2067 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2068 SH_PFC_PIN_GROUP(pwm0_a),
2069 SH_PFC_PIN_GROUP(pwm0_b),
2070 SH_PFC_PIN_GROUP(pwm0_c),
2071 SH_PFC_PIN_GROUP(pwm1_a),
2072 SH_PFC_PIN_GROUP(pwm1_b),
2073 SH_PFC_PIN_GROUP(pwm1_c),
2074 SH_PFC_PIN_GROUP(pwm2_a),
2075 SH_PFC_PIN_GROUP(pwm2_b),
2076 SH_PFC_PIN_GROUP(pwm2_c),
2077 SH_PFC_PIN_GROUP(pwm3_a),
2078 SH_PFC_PIN_GROUP(pwm3_b),
2079 SH_PFC_PIN_GROUP(pwm3_c),
2080 SH_PFC_PIN_GROUP(scif0_data_a),
2081 SH_PFC_PIN_GROUP(scif0_clk_a),
2082 SH_PFC_PIN_GROUP(scif0_data_b),
2083 SH_PFC_PIN_GROUP(scif0_clk_b),
2084 SH_PFC_PIN_GROUP(scif0_ctrl),
2085 SH_PFC_PIN_GROUP(scif1_data_a),
2086 SH_PFC_PIN_GROUP(scif1_clk_a),
2087 SH_PFC_PIN_GROUP(scif1_data_b),
2088 SH_PFC_PIN_GROUP(scif1_clk_b),
2089 SH_PFC_PIN_GROUP(scif1_ctrl),
2090 SH_PFC_PIN_GROUP(scif2_data),
2091 SH_PFC_PIN_GROUP(scif2_clk),
2092 SH_PFC_PIN_GROUP(scif3_data_a),
2093 SH_PFC_PIN_GROUP(scif3_clk_a),
2094 SH_PFC_PIN_GROUP(scif3_data_b),
2095 SH_PFC_PIN_GROUP(scif3_clk_b),
2096 SH_PFC_PIN_GROUP(scif4_data_a),
2097 SH_PFC_PIN_GROUP(scif4_clk_a),
2098 SH_PFC_PIN_GROUP(scif4_data_b),
2099 SH_PFC_PIN_GROUP(scif4_clk_b),
2100 SH_PFC_PIN_GROUP(scif5_data_a),
2101 SH_PFC_PIN_GROUP(scif5_clk_a),
2102 SH_PFC_PIN_GROUP(scif5_data_b),
2103 SH_PFC_PIN_GROUP(scif5_clk_b),
2104 SH_PFC_PIN_GROUP(scif_clk),
2105 SH_PFC_PIN_GROUP(ssi3_data),
2106 SH_PFC_PIN_GROUP(ssi34_ctrl),
2107 SH_PFC_PIN_GROUP(ssi4_ctrl_a),
2108 SH_PFC_PIN_GROUP(ssi4_data_a),
2109 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
2110 SH_PFC_PIN_GROUP(ssi4_data_b),
2111 SH_PFC_PIN_GROUP(usb0),
2112 VIN_DATA_PIN_GROUP(vin4_data, 8),
2113 VIN_DATA_PIN_GROUP(vin4_data, 10),
2114 VIN_DATA_PIN_GROUP(vin4_data, 12),
2115 VIN_DATA_PIN_GROUP(vin4_data, 16),
2116 SH_PFC_PIN_GROUP(vin4_data18),
2117 VIN_DATA_PIN_GROUP(vin4_data, 20),
2118 VIN_DATA_PIN_GROUP(vin4_data, 24),
2119 SH_PFC_PIN_GROUP(vin4_sync),
2120 SH_PFC_PIN_GROUP(vin4_field),
2121 SH_PFC_PIN_GROUP(vin4_clkenb),
2122 SH_PFC_PIN_GROUP(vin4_clk),
2123 };
2124
2125 static const char * const audio_clk_groups[] = {
2126 "audio_clk_a",
2127 "audio_clk_b",
2128 "audio_clkout",
2129 "audio_clkout1",
2130 };
2131
2132 static const char * const avb0_groups[] = {
2133 "avb0_link",
2134 "avb0_magic",
2135 "avb0_phy_int",
2136 "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
2137 "avb0_mdio",
2138 "avb0_mii",
2139 "avb0_avtp_pps_a",
2140 "avb0_avtp_match_a",
2141 "avb0_avtp_capture_a",
2142 "avb0_avtp_pps_b",
2143 "avb0_avtp_match_b",
2144 "avb0_avtp_capture_b",
2145 };
2146
2147 static const char * const can0_groups[] = {
2148 "can0_data_a",
2149 "can0_data_b",
2150 };
2151 static const char * const can1_groups[] = {
2152 "can1_data_a",
2153 "can1_data_b",
2154 };
2155 static const char * const can_clk_groups[] = {
2156 "can_clk",
2157 };
2158
2159 static const char * const canfd0_groups[] = {
2160 "canfd0_data",
2161 };
2162 static const char * const canfd1_groups[] = {
2163 "canfd1_data",
2164 };
2165
2166 static const char * const du_groups[] = {
2167 "du_rgb666",
2168 "du_rgb888",
2169 "du_clk_in_1",
2170 "du_clk_out_0",
2171 "du_sync",
2172 "du_disp_cde",
2173 "du_cde",
2174 "du_disp",
2175 };
2176
2177 static const char * const i2c0_groups[] = {
2178 "i2c0",
2179 };
2180 static const char * const i2c1_groups[] = {
2181 "i2c1",
2182 };
2183
2184 static const char * const i2c2_groups[] = {
2185 "i2c2_a",
2186 "i2c2_b",
2187 };
2188
2189 static const char * const i2c3_groups[] = {
2190 "i2c3_a",
2191 "i2c3_b",
2192 };
2193
2194 static const char * const mmc_groups[] = {
2195 "mmc_data1",
2196 "mmc_data4",
2197 "mmc_data8",
2198 "mmc_ctrl",
2199 };
2200
2201 static const char * const pwm0_groups[] = {
2202 "pwm0_a",
2203 "pwm0_b",
2204 "pwm0_c",
2205 };
2206
2207 static const char * const pwm1_groups[] = {
2208 "pwm1_a",
2209 "pwm1_b",
2210 "pwm1_c",
2211 };
2212
2213 static const char * const pwm2_groups[] = {
2214 "pwm2_a",
2215 "pwm2_b",
2216 "pwm2_c",
2217 };
2218
2219 static const char * const pwm3_groups[] = {
2220 "pwm3_a",
2221 "pwm3_b",
2222 "pwm3_c",
2223 };
2224
2225 static const char * const scif0_groups[] = {
2226 "scif0_data_a",
2227 "scif0_clk_a",
2228 "scif0_data_b",
2229 "scif0_clk_b",
2230 "scif0_ctrl",
2231 };
2232
2233 static const char * const scif1_groups[] = {
2234 "scif1_data_a",
2235 "scif1_clk_a",
2236 "scif1_data_b",
2237 "scif1_clk_b",
2238 "scif1_ctrl",
2239 };
2240
2241 static const char * const scif2_groups[] = {
2242 "scif2_data",
2243 "scif2_clk",
2244 };
2245
2246 static const char * const scif3_groups[] = {
2247 "scif3_data_a",
2248 "scif3_clk_a",
2249 "scif3_data_b",
2250 "scif3_clk_b",
2251 };
2252
2253 static const char * const scif4_groups[] = {
2254 "scif4_data_a",
2255 "scif4_clk_a",
2256 "scif4_data_b",
2257 "scif4_clk_b",
2258 };
2259
2260 static const char * const scif5_groups[] = {
2261 "scif5_data_a",
2262 "scif5_clk_a",
2263 "scif5_data_b",
2264 "scif5_clk_b",
2265 };
2266
2267 static const char * const scif_clk_groups[] = {
2268 "scif_clk",
2269 };
2270
2271 static const char * const ssi_groups[] = {
2272 "ssi3_data",
2273 "ssi34_ctrl",
2274 "ssi4_ctrl_a",
2275 "ssi4_data_a",
2276 "ssi4_ctrl_b",
2277 "ssi4_data_b",
2278 };
2279
2280 static const char * const usb0_groups[] = {
2281 "usb0",
2282 };
2283
2284 static const char * const vin4_groups[] = {
2285 "vin4_data8",
2286 "vin4_data10",
2287 "vin4_data12",
2288 "vin4_data16",
2289 "vin4_data18",
2290 "vin4_data20",
2291 "vin4_data24",
2292 "vin4_sync",
2293 "vin4_field",
2294 "vin4_clkenb",
2295 "vin4_clk",
2296 };
2297
2298 static const char * const msiof0_groups[] = {
2299 "msiof0_clk",
2300 "msiof0_sync",
2301 "msiof0_ss1",
2302 "msiof0_ss2",
2303 "msiof0_txd",
2304 "msiof0_rxd",
2305 };
2306
2307 static const char * const msiof1_groups[] = {
2308 "msiof1_clk",
2309 "msiof1_sync",
2310 "msiof1_ss1",
2311 "msiof1_ss2",
2312 "msiof1_txd",
2313 "msiof1_rxd",
2314 };
2315
2316 static const char * const msiof2_groups[] = {
2317 "msiof2_clk",
2318 "msiof2_sync_a",
2319 "msiof2_sync_b",
2320 "msiof2_ss1",
2321 "msiof2_ss2",
2322 "msiof2_txd",
2323 "msiof2_rxd",
2324 };
2325
2326 static const char * const msiof3_groups[] = {
2327 "msiof3_clk_a",
2328 "msiof3_sync_a",
2329 "msiof3_ss1_a",
2330 "msiof3_ss2_a",
2331 "msiof3_txd_a",
2332 "msiof3_rxd_a",
2333 "msiof3_clk_b",
2334 "msiof3_sync_b",
2335 "msiof3_ss1_b",
2336 "msiof3_ss2_b",
2337 "msiof3_txd_b",
2338 "msiof3_rxd_b",
2339 };
2340
2341 static const struct sh_pfc_function pinmux_functions[] = {
2342 SH_PFC_FUNCTION(audio_clk),
2343 SH_PFC_FUNCTION(avb0),
2344 SH_PFC_FUNCTION(can0),
2345 SH_PFC_FUNCTION(can1),
2346 SH_PFC_FUNCTION(can_clk),
2347 SH_PFC_FUNCTION(canfd0),
2348 SH_PFC_FUNCTION(canfd1),
2349 SH_PFC_FUNCTION(du),
2350 SH_PFC_FUNCTION(i2c0),
2351 SH_PFC_FUNCTION(i2c1),
2352 SH_PFC_FUNCTION(i2c2),
2353 SH_PFC_FUNCTION(i2c3),
2354 SH_PFC_FUNCTION(mmc),
2355 SH_PFC_FUNCTION(msiof0),
2356 SH_PFC_FUNCTION(msiof1),
2357 SH_PFC_FUNCTION(msiof2),
2358 SH_PFC_FUNCTION(msiof3),
2359 SH_PFC_FUNCTION(pwm0),
2360 SH_PFC_FUNCTION(pwm1),
2361 SH_PFC_FUNCTION(pwm2),
2362 SH_PFC_FUNCTION(pwm3),
2363 SH_PFC_FUNCTION(scif0),
2364 SH_PFC_FUNCTION(scif1),
2365 SH_PFC_FUNCTION(scif2),
2366 SH_PFC_FUNCTION(scif3),
2367 SH_PFC_FUNCTION(scif4),
2368 SH_PFC_FUNCTION(scif5),
2369 SH_PFC_FUNCTION(scif_clk),
2370 SH_PFC_FUNCTION(ssi),
2371 SH_PFC_FUNCTION(usb0),
2372 SH_PFC_FUNCTION(vin4),
2373 };
2374
2375 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2376 #define F_(x, y) FN_##y
2377 #define FM(x) FN_##x
2378 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2379 0, 0,
2380 0, 0,
2381 0, 0,
2382 0, 0,
2383 0, 0,
2384 0, 0,
2385 0, 0,
2386 0, 0,
2387 0, 0,
2388 0, 0,
2389 0, 0,
2390 0, 0,
2391 0, 0,
2392 0, 0,
2393 0, 0,
2394 0, 0,
2395 0, 0,
2396 0, 0,
2397 0, 0,
2398 0, 0,
2399 0, 0,
2400 0, 0,
2401 0, 0,
2402 GP_0_8_FN, GPSR0_8,
2403 GP_0_7_FN, GPSR0_7,
2404 GP_0_6_FN, GPSR0_6,
2405 GP_0_5_FN, GPSR0_5,
2406 GP_0_4_FN, GPSR0_4,
2407 GP_0_3_FN, GPSR0_3,
2408 GP_0_2_FN, GPSR0_2,
2409 GP_0_1_FN, GPSR0_1,
2410 GP_0_0_FN, GPSR0_0, ))
2411 },
2412 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2413 GP_1_31_FN, GPSR1_31,
2414 GP_1_30_FN, GPSR1_30,
2415 GP_1_29_FN, GPSR1_29,
2416 GP_1_28_FN, GPSR1_28,
2417 GP_1_27_FN, GPSR1_27,
2418 GP_1_26_FN, GPSR1_26,
2419 GP_1_25_FN, GPSR1_25,
2420 GP_1_24_FN, GPSR1_24,
2421 GP_1_23_FN, GPSR1_23,
2422 GP_1_22_FN, GPSR1_22,
2423 GP_1_21_FN, GPSR1_21,
2424 GP_1_20_FN, GPSR1_20,
2425 GP_1_19_FN, GPSR1_19,
2426 GP_1_18_FN, GPSR1_18,
2427 GP_1_17_FN, GPSR1_17,
2428 GP_1_16_FN, GPSR1_16,
2429 GP_1_15_FN, GPSR1_15,
2430 GP_1_14_FN, GPSR1_14,
2431 GP_1_13_FN, GPSR1_13,
2432 GP_1_12_FN, GPSR1_12,
2433 GP_1_11_FN, GPSR1_11,
2434 GP_1_10_FN, GPSR1_10,
2435 GP_1_9_FN, GPSR1_9,
2436 GP_1_8_FN, GPSR1_8,
2437 GP_1_7_FN, GPSR1_7,
2438 GP_1_6_FN, GPSR1_6,
2439 GP_1_5_FN, GPSR1_5,
2440 GP_1_4_FN, GPSR1_4,
2441 GP_1_3_FN, GPSR1_3,
2442 GP_1_2_FN, GPSR1_2,
2443 GP_1_1_FN, GPSR1_1,
2444 GP_1_0_FN, GPSR1_0, ))
2445 },
2446 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2447 GP_2_31_FN, GPSR2_31,
2448 GP_2_30_FN, GPSR2_30,
2449 GP_2_29_FN, GPSR2_29,
2450 GP_2_28_FN, GPSR2_28,
2451 GP_2_27_FN, GPSR2_27,
2452 GP_2_26_FN, GPSR2_26,
2453 GP_2_25_FN, GPSR2_25,
2454 GP_2_24_FN, GPSR2_24,
2455 GP_2_23_FN, GPSR2_23,
2456 GP_2_22_FN, GPSR2_22,
2457 GP_2_21_FN, GPSR2_21,
2458 GP_2_20_FN, GPSR2_20,
2459 GP_2_19_FN, GPSR2_19,
2460 GP_2_18_FN, GPSR2_18,
2461 GP_2_17_FN, GPSR2_17,
2462 GP_2_16_FN, GPSR2_16,
2463 GP_2_15_FN, GPSR2_15,
2464 GP_2_14_FN, GPSR2_14,
2465 GP_2_13_FN, GPSR2_13,
2466 GP_2_12_FN, GPSR2_12,
2467 GP_2_11_FN, GPSR2_11,
2468 GP_2_10_FN, GPSR2_10,
2469 GP_2_9_FN, GPSR2_9,
2470 GP_2_8_FN, GPSR2_8,
2471 GP_2_7_FN, GPSR2_7,
2472 GP_2_6_FN, GPSR2_6,
2473 GP_2_5_FN, GPSR2_5,
2474 GP_2_4_FN, GPSR2_4,
2475 GP_2_3_FN, GPSR2_3,
2476 GP_2_2_FN, GPSR2_2,
2477 GP_2_1_FN, GPSR2_1,
2478 GP_2_0_FN, GPSR2_0, ))
2479 },
2480 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2481 0, 0,
2482 0, 0,
2483 0, 0,
2484 0, 0,
2485 0, 0,
2486 0, 0,
2487 0, 0,
2488 0, 0,
2489 0, 0,
2490 0, 0,
2491 0, 0,
2492 0, 0,
2493 0, 0,
2494 0, 0,
2495 0, 0,
2496 0, 0,
2497 0, 0,
2498 0, 0,
2499 0, 0,
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 GP_3_9_FN, GPSR3_9,
2504 GP_3_8_FN, GPSR3_8,
2505 GP_3_7_FN, GPSR3_7,
2506 GP_3_6_FN, GPSR3_6,
2507 GP_3_5_FN, GPSR3_5,
2508 GP_3_4_FN, GPSR3_4,
2509 GP_3_3_FN, GPSR3_3,
2510 GP_3_2_FN, GPSR3_2,
2511 GP_3_1_FN, GPSR3_1,
2512 GP_3_0_FN, GPSR3_0, ))
2513 },
2514 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2515 GP_4_31_FN, GPSR4_31,
2516 GP_4_30_FN, GPSR4_30,
2517 GP_4_29_FN, GPSR4_29,
2518 GP_4_28_FN, GPSR4_28,
2519 GP_4_27_FN, GPSR4_27,
2520 GP_4_26_FN, GPSR4_26,
2521 GP_4_25_FN, GPSR4_25,
2522 GP_4_24_FN, GPSR4_24,
2523 GP_4_23_FN, GPSR4_23,
2524 GP_4_22_FN, GPSR4_22,
2525 GP_4_21_FN, GPSR4_21,
2526 GP_4_20_FN, GPSR4_20,
2527 GP_4_19_FN, GPSR4_19,
2528 GP_4_18_FN, GPSR4_18,
2529 GP_4_17_FN, GPSR4_17,
2530 GP_4_16_FN, GPSR4_16,
2531 GP_4_15_FN, GPSR4_15,
2532 GP_4_14_FN, GPSR4_14,
2533 GP_4_13_FN, GPSR4_13,
2534 GP_4_12_FN, GPSR4_12,
2535 GP_4_11_FN, GPSR4_11,
2536 GP_4_10_FN, GPSR4_10,
2537 GP_4_9_FN, GPSR4_9,
2538 GP_4_8_FN, GPSR4_8,
2539 GP_4_7_FN, GPSR4_7,
2540 GP_4_6_FN, GPSR4_6,
2541 GP_4_5_FN, GPSR4_5,
2542 GP_4_4_FN, GPSR4_4,
2543 GP_4_3_FN, GPSR4_3,
2544 GP_4_2_FN, GPSR4_2,
2545 GP_4_1_FN, GPSR4_1,
2546 GP_4_0_FN, GPSR4_0, ))
2547 },
2548 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2549 0, 0,
2550 0, 0,
2551 0, 0,
2552 0, 0,
2553 0, 0,
2554 0, 0,
2555 0, 0,
2556 0, 0,
2557 0, 0,
2558 0, 0,
2559 0, 0,
2560 GP_5_20_FN, GPSR5_20,
2561 GP_5_19_FN, GPSR5_19,
2562 GP_5_18_FN, GPSR5_18,
2563 GP_5_17_FN, GPSR5_17,
2564 GP_5_16_FN, GPSR5_16,
2565 GP_5_15_FN, GPSR5_15,
2566 GP_5_14_FN, GPSR5_14,
2567 GP_5_13_FN, GPSR5_13,
2568 GP_5_12_FN, GPSR5_12,
2569 GP_5_11_FN, GPSR5_11,
2570 GP_5_10_FN, GPSR5_10,
2571 GP_5_9_FN, GPSR5_9,
2572 GP_5_8_FN, GPSR5_8,
2573 GP_5_7_FN, GPSR5_7,
2574 GP_5_6_FN, GPSR5_6,
2575 GP_5_5_FN, GPSR5_5,
2576 GP_5_4_FN, GPSR5_4,
2577 GP_5_3_FN, GPSR5_3,
2578 GP_5_2_FN, GPSR5_2,
2579 GP_5_1_FN, GPSR5_1,
2580 GP_5_0_FN, GPSR5_0, ))
2581 },
2582 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
2583 0, 0,
2584 0, 0,
2585 0, 0,
2586 0, 0,
2587 0, 0,
2588 0, 0,
2589 0, 0,
2590 0, 0,
2591 0, 0,
2592 0, 0,
2593 0, 0,
2594 0, 0,
2595 0, 0,
2596 0, 0,
2597 0, 0,
2598 0, 0,
2599 0, 0,
2600 0, 0,
2601 GP_6_13_FN, GPSR6_13,
2602 GP_6_12_FN, GPSR6_12,
2603 GP_6_11_FN, GPSR6_11,
2604 GP_6_10_FN, GPSR6_10,
2605 GP_6_9_FN, GPSR6_9,
2606 GP_6_8_FN, GPSR6_8,
2607 GP_6_7_FN, GPSR6_7,
2608 GP_6_6_FN, GPSR6_6,
2609 GP_6_5_FN, GPSR6_5,
2610 GP_6_4_FN, GPSR6_4,
2611 GP_6_3_FN, GPSR6_3,
2612 GP_6_2_FN, GPSR6_2,
2613 GP_6_1_FN, GPSR6_1,
2614 GP_6_0_FN, GPSR6_0, ))
2615 },
2616 #undef F_
2617 #undef FM
2618
2619 #define F_(x, y) x,
2620 #define FM(x) FN_##x,
2621 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2622 IP0_31_28
2623 IP0_27_24
2624 IP0_23_20
2625 IP0_19_16
2626 IP0_15_12
2627 IP0_11_8
2628 IP0_7_4
2629 IP0_3_0 ))
2630 },
2631 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2632 IP1_31_28
2633 IP1_27_24
2634 IP1_23_20
2635 IP1_19_16
2636 IP1_15_12
2637 IP1_11_8
2638 IP1_7_4
2639 IP1_3_0 ))
2640 },
2641 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2642 IP2_31_28
2643 IP2_27_24
2644 IP2_23_20
2645 IP2_19_16
2646 IP2_15_12
2647 IP2_11_8
2648 IP2_7_4
2649 IP2_3_0 ))
2650 },
2651 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2652 IP3_31_28
2653 IP3_27_24
2654 IP3_23_20
2655 IP3_19_16
2656 IP3_15_12
2657 IP3_11_8
2658 IP3_7_4
2659 IP3_3_0 ))
2660 },
2661 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2662 IP4_31_28
2663 IP4_27_24
2664 IP4_23_20
2665 IP4_19_16
2666 IP4_15_12
2667 IP4_11_8
2668 IP4_7_4
2669 IP4_3_0 ))
2670 },
2671 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2672 IP5_31_28
2673 IP5_27_24
2674 IP5_23_20
2675 IP5_19_16
2676 IP5_15_12
2677 IP5_11_8
2678 IP5_7_4
2679 IP5_3_0 ))
2680 },
2681 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2682 IP6_31_28
2683 IP6_27_24
2684 IP6_23_20
2685 IP6_19_16
2686 IP6_15_12
2687 IP6_11_8
2688 IP6_7_4
2689 IP6_3_0 ))
2690 },
2691 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2692 IP7_31_28
2693 IP7_27_24
2694 IP7_23_20
2695 IP7_19_16
2696 IP7_15_12
2697 IP7_11_8
2698 IP7_7_4
2699 IP7_3_0 ))
2700 },
2701 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2702 IP8_31_28
2703 IP8_27_24
2704 IP8_23_20
2705 IP8_19_16
2706 IP8_15_12
2707 IP8_11_8
2708 IP8_7_4
2709 IP8_3_0 ))
2710 },
2711 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2712 IP9_31_28
2713 IP9_27_24
2714 IP9_23_20
2715 IP9_19_16
2716 IP9_15_12
2717 IP9_11_8
2718 IP9_7_4
2719 IP9_3_0 ))
2720 },
2721 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2722 IP10_31_28
2723 IP10_27_24
2724 IP10_23_20
2725 IP10_19_16
2726 IP10_15_12
2727 IP10_11_8
2728 IP10_7_4
2729 IP10_3_0 ))
2730 },
2731 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2732 IP11_31_28
2733 IP11_27_24
2734 IP11_23_20
2735 IP11_19_16
2736 IP11_15_12
2737 IP11_11_8
2738 IP11_7_4
2739 IP11_3_0 ))
2740 },
2741 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2742 IP12_31_28
2743 IP12_27_24
2744 IP12_23_20
2745 IP12_19_16
2746 IP12_15_12
2747 IP12_11_8
2748 IP12_7_4
2749 IP12_3_0 ))
2750 },
2751 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
2752 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2753 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2754 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2755 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2756 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2757 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2758 IP13_7_4
2759 IP13_3_0 ))
2760 },
2761 #undef F_
2762 #undef FM
2763
2764 #define F_(x, y) x,
2765 #define FM(x) FN_##x,
2766 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2767 GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
2768 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
2769 GROUP(
2770 /* RESERVED 31 */
2771 0, 0,
2772 MOD_SEL0_30
2773 MOD_SEL0_29
2774 MOD_SEL0_28
2775 MOD_SEL0_27
2776 MOD_SEL0_26
2777 MOD_SEL0_25
2778 MOD_SEL0_24_23
2779 MOD_SEL0_22_21
2780 MOD_SEL0_20_19
2781 MOD_SEL0_18_17
2782 /* RESERVED 16 */
2783 0, 0,
2784 MOD_SEL0_15
2785 MOD_SEL0_14
2786 MOD_SEL0_13
2787 MOD_SEL0_12
2788 MOD_SEL0_11
2789 MOD_SEL0_10
2790 /* RESERVED 9, 8, 7, 6 */
2791 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2792 MOD_SEL0_5
2793 MOD_SEL0_4
2794 MOD_SEL0_3
2795 MOD_SEL0_2
2796 MOD_SEL0_1
2797 MOD_SEL0_0 ))
2798 },
2799 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2800 GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
2801 GROUP(
2802 MOD_SEL1_31
2803 MOD_SEL1_30
2804 MOD_SEL1_29
2805 MOD_SEL1_28
2806 MOD_SEL1_27
2807 MOD_SEL1_26
2808 /* RESERVED 25, 24 */
2809 0, 0, 0, 0,
2810 /* RESERVED 23, 22, 21, 20 */
2811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2812 /* RESERVED 19, 18, 17, 16 */
2813 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2814 /* RESERVED 15, 14, 13, 12 */
2815 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2816 /* RESERVED 11, 10, 9, 8 */
2817 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2818 /* RESERVED 7, 6, 5, 4 */
2819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2820 /* RESERVED 3, 2, 1, 0 */
2821 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
2822 },
2823 { },
2824 };
2825
2826 static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2827 {
2828 int bit = -EINVAL;
2829
2830 *pocctrl = 0xe6060380;
2831
2832 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
2833 bit = 29 - (pin - RCAR_GP_PIN(3, 0));
2834
2835 return bit;
2836 }
2837
2838 enum ioctrl_regs {
2839 TDSELCTRL,
2840 };
2841
2842 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2843 [TDSELCTRL] = { 0xe60603c0, },
2844 { /* sentinel */ },
2845 };
2846
2847 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
2848 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
2849 };
2850
2851 const struct sh_pfc_soc_info r8a77995_pinmux_info = {
2852 .name = "r8a77995_pfc",
2853 .ops = &r8a77995_pinmux_ops,
2854 .unlock_reg = 0xe6060000, /* PMMR */
2855
2856 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2857
2858 .pins = pinmux_pins,
2859 .nr_pins = ARRAY_SIZE(pinmux_pins),
2860 .groups = pinmux_groups,
2861 .nr_groups = ARRAY_SIZE(pinmux_groups),
2862 .functions = pinmux_functions,
2863 .nr_functions = ARRAY_SIZE(pinmux_functions),
2864
2865 .cfg_regs = pinmux_config_regs,
2866 .ioctrl_regs = pinmux_ioctrl_regs,
2867
2868 .pinmux_data = pinmux_data,
2869 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2870 };
Linux with added FPC-III support