drivers/pinctrl/samsung/pinctrl-s3c24xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // S3C24XX specific support for Samsung pinctrl/gpiolib driver.
   4 //
   5 // Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   6 //
   7 // This file contains the SamsungS3C24XX specific information required by the
   8 // Samsung pinctrl/gpiolib driver. It also includes the implementation of
   9 // external gpio and wakeup interrupt support.
  10
  11 #include <linux/init.h>
  12 #include <linux/device.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/irq.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21
  22 #include "pinctrl-samsung.h"
  23
  24 #define NUM_EINT        24
  25 #define NUM_EINT_IRQ    6
  26 #define EINT_MAX_PER_GROUP      8
  27
  28 #define EINTPEND_REG    0xa8
  29 #define EINTMASK_REG    0xa4
  30
  31 #define EINT_GROUP(i)           ((int)((i) / EINT_MAX_PER_GROUP))
  32 #define EINT_REG(i)             ((EINT_GROUP(i) * 4) + 0x88)
  33 #define EINT_OFFS(i)            ((i) % EINT_MAX_PER_GROUP * 4)
  34
  35 #define EINT_LEVEL_LOW          0
  36 #define EINT_LEVEL_HIGH         1
  37 #define EINT_EDGE_FALLING       2
  38 #define EINT_EDGE_RISING        4
  39 #define EINT_EDGE_BOTH          6
  40 #define EINT_MASK               0xf
  41
  42 static const struct samsung_pin_bank_type bank_type_1bit = {
  43         .fld_width = { 1, 1, },
  44         .reg_offset = { 0x00, 0x04, },
  45 };
  46
  47 static const struct samsung_pin_bank_type bank_type_2bit = {
  48         .fld_width = { 2, 1, 2, },
  49         .reg_offset = { 0x00, 0x04, 0x08, },
  50 };
  51
  52 #define PIN_BANK_A(pins, reg, id)               \
  53         {                                               \
  54                 .type           = &bank_type_1bit,      \
  55                 .pctl_offset    = reg,                  \
  56                 .nr_pins        = pins,                 \
  57                 .eint_type      = EINT_TYPE_NONE,       \
  58                 .name           = id                    \
  59         }
  60
  61 #define PIN_BANK_2BIT(pins, reg, id)            \
  62         {                                               \
  63                 .type           = &bank_type_2bit,      \
  64                 .pctl_offset    = reg,                  \
  65                 .nr_pins        = pins,                 \
  66                 .eint_type      = EINT_TYPE_NONE,       \
  67                 .name           = id                    \
  68         }
  69
  70 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
  71         {                                               \
  72                 .type           = &bank_type_2bit,      \
  73                 .pctl_offset    = reg,                  \
  74                 .nr_pins        = pins,                 \
  75                 .eint_type      = EINT_TYPE_WKUP,       \
  76                 .eint_func      = 2,                    \
  77                 .eint_mask      = emask,                \
  78                 .eint_offset    = eoffs,                \
  79                 .name           = id                    \
  80         }
  81
  82 /**
  83  * struct s3c24xx_eint_data - EINT common data
  84  * @drvdata: pin controller driver data
  85  * @domains: IRQ domains of particular EINT interrupts
  86  * @parents: mapped parent irqs in the main interrupt controller
  87  */
  88 struct s3c24xx_eint_data {
  89         struct samsung_pinctrl_drv_data *drvdata;
  90         struct irq_domain *domains[NUM_EINT];
  91         int parents[NUM_EINT_IRQ];
  92 };
  93
  94 /**
  95  * struct s3c24xx_eint_domain_data - per irq-domain data
  96  * @bank: pin bank related to the domain
  97  * @eint_data: common data
  98  * @eint0_3_parent_only: live eints 0-3 only in the main intc
  99  */
 100 struct s3c24xx_eint_domain_data {
 101         struct samsung_pin_bank *bank;
 102         struct s3c24xx_eint_data *eint_data;
 103         bool eint0_3_parent_only;
 104 };
 105
 106 static int s3c24xx_eint_get_trigger(unsigned int type)
 107 {
 108         switch (type) {
 109         case IRQ_TYPE_EDGE_RISING:
 110                 return EINT_EDGE_RISING;
 111         case IRQ_TYPE_EDGE_FALLING:
 112                 return EINT_EDGE_FALLING;
 113         case IRQ_TYPE_EDGE_BOTH:
 114                 return EINT_EDGE_BOTH;
 115         case IRQ_TYPE_LEVEL_HIGH:
 116                 return EINT_LEVEL_HIGH;
 117         case IRQ_TYPE_LEVEL_LOW:
 118                 return EINT_LEVEL_LOW;
 119         default:
 120                 return -EINVAL;
 121         }
 122 }
 123
 124 static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
 125 {
 126         /* Edge- and level-triggered interrupts need different handlers */
 127         if (type & IRQ_TYPE_EDGE_BOTH)
 128                 irq_set_handler_locked(d, handle_edge_irq);
 129         else
 130                 irq_set_handler_locked(d, handle_level_irq);
 131 }
 132
 133 static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
 134                                         struct samsung_pin_bank *bank, int pin)
 135 {
 136         const struct samsung_pin_bank_type *bank_type = bank->type;
 137         unsigned long flags;
 138         void __iomem *reg;
 139         u8 shift;
 140         u32 mask;
 141         u32 val;
 142
 143         /* Make sure that pin is configured as interrupt */
 144         reg = d->virt_base + bank->pctl_offset;
 145         shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
 146         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 147
 148         spin_lock_irqsave(&bank->slock, flags);
 149
 150         val = readl(reg);
 151         val &= ~(mask << shift);
 152         val |= bank->eint_func << shift;
 153         writel(val, reg);
 154
 155         spin_unlock_irqrestore(&bank->slock, flags);
 156 }
 157
 158 static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
 159 {
 160         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 161         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 162         int index = bank->eint_offset + data->hwirq;
 163         void __iomem *reg;
 164         int trigger;
 165         u8 shift;
 166         u32 val;
 167
 168         trigger = s3c24xx_eint_get_trigger(type);
 169         if (trigger < 0) {
 170                 dev_err(d->dev, "unsupported external interrupt type\n");
 171                 return -EINVAL;
 172         }
 173
 174         s3c24xx_eint_set_handler(data, type);
 175
 176         /* Set up interrupt trigger */
 177         reg = d->virt_base + EINT_REG(index);
 178         shift = EINT_OFFS(index);
 179
 180         val = readl(reg);
 181         val &= ~(EINT_MASK << shift);
 182         val |= trigger << shift;
 183         writel(val, reg);
 184
 185         s3c24xx_eint_set_function(d, bank, data->hwirq);
 186
 187         return 0;
 188 }
 189
 190 /* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
 191
 192 static void s3c2410_eint0_3_ack(struct irq_data *data)
 193 {
 194         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 195         struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
 196         struct s3c24xx_eint_data *eint_data = ddata->eint_data;
 197         int parent_irq = eint_data->parents[data->hwirq];
 198         struct irq_chip *parent_chip = irq_get_chip(parent_irq);
 199
 200         parent_chip->irq_ack(irq_get_irq_data(parent_irq));
 201 }
 202
 203 static void s3c2410_eint0_3_mask(struct irq_data *data)
 204 {
 205         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 206         struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
 207         struct s3c24xx_eint_data *eint_data = ddata->eint_data;
 208         int parent_irq = eint_data->parents[data->hwirq];
 209         struct irq_chip *parent_chip = irq_get_chip(parent_irq);
 210
 211         parent_chip->irq_mask(irq_get_irq_data(parent_irq));
 212 }
 213
 214 static void s3c2410_eint0_3_unmask(struct irq_data *data)
 215 {
 216         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 217         struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
 218         struct s3c24xx_eint_data *eint_data = ddata->eint_data;
 219         int parent_irq = eint_data->parents[data->hwirq];
 220         struct irq_chip *parent_chip = irq_get_chip(parent_irq);
 221
 222         parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
 223 }
 224
 225 static struct irq_chip s3c2410_eint0_3_chip = {
 226         .name           = "s3c2410-eint0_3",
 227         .irq_ack        = s3c2410_eint0_3_ack,
 228         .irq_mask       = s3c2410_eint0_3_mask,
 229         .irq_unmask     = s3c2410_eint0_3_unmask,
 230         .irq_set_type   = s3c24xx_eint_type,
 231 };
 232
 233 static void s3c2410_demux_eint0_3(struct irq_desc *desc)
 234 {
 235         struct irq_data *data = irq_desc_get_irq_data(desc);
 236         struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
 237         unsigned int virq;
 238
 239         /* the first 4 eints have a simple 1 to 1 mapping */
 240         virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
 241         /* Something must be really wrong if an unmapped EINT is unmasked */
 242         BUG_ON(!virq);
 243
 244         generic_handle_irq(virq);
 245 }
 246
 247 /* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
 248
 249 static void s3c2412_eint0_3_ack(struct irq_data *data)
 250 {
 251         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 252         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 253
 254         unsigned long bitval = 1UL << data->hwirq;
 255         writel(bitval, d->virt_base + EINTPEND_REG);
 256 }
 257
 258 static void s3c2412_eint0_3_mask(struct irq_data *data)
 259 {
 260         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 261         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 262         unsigned long mask;
 263
 264         mask = readl(d->virt_base + EINTMASK_REG);
 265         mask |= (1UL << data->hwirq);
 266         writel(mask, d->virt_base + EINTMASK_REG);
 267 }
 268
 269 static void s3c2412_eint0_3_unmask(struct irq_data *data)
 270 {
 271         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 272         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 273         unsigned long mask;
 274
 275         mask = readl(d->virt_base + EINTMASK_REG);
 276         mask &= ~(1UL << data->hwirq);
 277         writel(mask, d->virt_base + EINTMASK_REG);
 278 }
 279
 280 static struct irq_chip s3c2412_eint0_3_chip = {
 281         .name           = "s3c2412-eint0_3",
 282         .irq_ack        = s3c2412_eint0_3_ack,
 283         .irq_mask       = s3c2412_eint0_3_mask,
 284         .irq_unmask     = s3c2412_eint0_3_unmask,
 285         .irq_set_type   = s3c24xx_eint_type,
 286 };
 287
 288 static void s3c2412_demux_eint0_3(struct irq_desc *desc)
 289 {
 290         struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
 291         struct irq_data *data = irq_desc_get_irq_data(desc);
 292         struct irq_chip *chip = irq_data_get_irq_chip(data);
 293         unsigned int virq;
 294
 295         chained_irq_enter(chip, desc);
 296
 297         /* the first 4 eints have a simple 1 to 1 mapping */
 298         virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
 299         /* Something must be really wrong if an unmapped EINT is unmasked */
 300         BUG_ON(!virq);
 301
 302         generic_handle_irq(virq);
 303
 304         chained_irq_exit(chip, desc);
 305 }
 306
 307 /* Handling of all other eints */
 308
 309 static void s3c24xx_eint_ack(struct irq_data *data)
 310 {
 311         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 312         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 313         unsigned char index = bank->eint_offset + data->hwirq;
 314
 315         writel(1UL << index, d->virt_base + EINTPEND_REG);
 316 }
 317
 318 static void s3c24xx_eint_mask(struct irq_data *data)
 319 {
 320         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 321         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 322         unsigned char index = bank->eint_offset + data->hwirq;
 323         unsigned long mask;
 324
 325         mask = readl(d->virt_base + EINTMASK_REG);
 326         mask |= (1UL << index);
 327         writel(mask, d->virt_base + EINTMASK_REG);
 328 }
 329
 330 static void s3c24xx_eint_unmask(struct irq_data *data)
 331 {
 332         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
 333         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 334         unsigned char index = bank->eint_offset + data->hwirq;
 335         unsigned long mask;
 336
 337         mask = readl(d->virt_base + EINTMASK_REG);
 338         mask &= ~(1UL << index);
 339         writel(mask, d->virt_base + EINTMASK_REG);
 340 }
 341
 342 static struct irq_chip s3c24xx_eint_chip = {
 343         .name           = "s3c-eint",
 344         .irq_ack        = s3c24xx_eint_ack,
 345         .irq_mask       = s3c24xx_eint_mask,
 346         .irq_unmask     = s3c24xx_eint_unmask,
 347         .irq_set_type   = s3c24xx_eint_type,
 348 };
 349
 350 static inline void s3c24xx_demux_eint(struct irq_desc *desc,
 351                                       u32 offset, u32 range)
 352 {
 353         struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
 354         struct irq_chip *chip = irq_desc_get_chip(desc);
 355         struct samsung_pinctrl_drv_data *d = data->drvdata;
 356         unsigned int pend, mask;
 357
 358         chained_irq_enter(chip, desc);
 359
 360         pend = readl(d->virt_base + EINTPEND_REG);
 361         mask = readl(d->virt_base + EINTMASK_REG);
 362
 363         pend &= ~mask;
 364         pend &= range;
 365
 366         while (pend) {
 367                 unsigned int virq, irq;
 368
 369                 irq = __ffs(pend);
 370                 pend &= ~(1 << irq);
 371                 virq = irq_linear_revmap(data->domains[irq], irq - offset);
 372                 /* Something is really wrong if an unmapped EINT is unmasked */
 373                 BUG_ON(!virq);
 374
 375                 generic_handle_irq(virq);
 376         }
 377
 378         chained_irq_exit(chip, desc);
 379 }
 380
 381 static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
 382 {
 383         s3c24xx_demux_eint(desc, 0, 0xf0);
 384 }
 385
 386 static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
 387 {
 388         s3c24xx_demux_eint(desc, 8, 0xffff00);
 389 }
 390
 391 static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
 392         s3c2410_demux_eint0_3,
 393         s3c2410_demux_eint0_3,
 394         s3c2410_demux_eint0_3,
 395         s3c2410_demux_eint0_3,
 396         s3c24xx_demux_eint4_7,
 397         s3c24xx_demux_eint8_23,
 398 };
 399
 400 static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
 401         s3c2412_demux_eint0_3,
 402         s3c2412_demux_eint0_3,
 403         s3c2412_demux_eint0_3,
 404         s3c2412_demux_eint0_3,
 405         s3c24xx_demux_eint4_7,
 406         s3c24xx_demux_eint8_23,
 407 };
 408
 409 static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
 410                                         irq_hw_number_t hw)
 411 {
 412         struct s3c24xx_eint_domain_data *ddata = h->host_data;
 413         struct samsung_pin_bank *bank = ddata->bank;
 414
 415         if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
 416                 return -EINVAL;
 417
 418         if (hw <= 3) {
 419                 if (ddata->eint0_3_parent_only)
 420                         irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
 421                                                  handle_edge_irq);
 422                 else
 423                         irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
 424                                                  handle_edge_irq);
 425         } else {
 426                 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
 427                                          handle_edge_irq);
 428         }
 429         irq_set_chip_data(virq, bank);
 430         return 0;
 431 }
 432
 433 static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
 434         .map    = s3c24xx_gpf_irq_map,
 435         .xlate  = irq_domain_xlate_twocell,
 436 };
 437
 438 static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
 439                                         irq_hw_number_t hw)
 440 {
 441         struct s3c24xx_eint_domain_data *ddata = h->host_data;
 442         struct samsung_pin_bank *bank = ddata->bank;
 443
 444         if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
 445                 return -EINVAL;
 446
 447         irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
 448         irq_set_chip_data(virq, bank);
 449         return 0;
 450 }
 451
 452 static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
 453         .map    = s3c24xx_gpg_irq_map,
 454         .xlate  = irq_domain_xlate_twocell,
 455 };
 456
 457 static const struct of_device_id s3c24xx_eint_irq_ids[] = {
 458         { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
 459         { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
 460         { }
 461 };
 462
 463 static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
 464 {
 465         struct device *dev = d->dev;
 466         const struct of_device_id *match;
 467         struct device_node *eint_np = NULL;
 468         struct device_node *np;
 469         struct samsung_pin_bank *bank;
 470         struct s3c24xx_eint_data *eint_data;
 471         const struct irq_domain_ops *ops;
 472         unsigned int i;
 473         bool eint0_3_parent_only;
 474         irq_flow_handler_t *handlers;
 475
 476         for_each_child_of_node(dev->of_node, np) {
 477                 match = of_match_node(s3c24xx_eint_irq_ids, np);
 478                 if (match) {
 479                         eint_np = np;
 480                         eint0_3_parent_only = (bool)match->data;
 481                         break;
 482                 }
 483         }
 484         if (!eint_np)
 485                 return -ENODEV;
 486
 487         eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
 488         if (!eint_data) {
 489                 of_node_put(eint_np);
 490                 return -ENOMEM;
 491         }
 492
 493         eint_data->drvdata = d;
 494
 495         handlers = eint0_3_parent_only ? s3c2410_eint_handlers
 496                                        : s3c2412_eint_handlers;
 497         for (i = 0; i < NUM_EINT_IRQ; ++i) {
 498                 unsigned int irq;
 499
 500                 irq = irq_of_parse_and_map(eint_np, i);
 501                 if (!irq) {
 502                         dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
 503                         of_node_put(eint_np);
 504                         return -ENXIO;
 505                 }
 506
 507                 eint_data->parents[i] = irq;
 508                 irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
 509         }
 510         of_node_put(eint_np);
 511
 512         bank = d->pin_banks;
 513         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 514                 struct s3c24xx_eint_domain_data *ddata;
 515                 unsigned int mask;
 516                 unsigned int irq;
 517                 unsigned int pin;
 518
 519                 if (bank->eint_type != EINT_TYPE_WKUP)
 520                         continue;
 521
 522                 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 523                 if (!ddata)
 524                         return -ENOMEM;
 525
 526                 ddata->bank = bank;
 527                 ddata->eint_data = eint_data;
 528                 ddata->eint0_3_parent_only = eint0_3_parent_only;
 529
 530                 ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
 531                                                : &s3c24xx_gpg_irq_ops;
 532
 533                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 534                                 bank->nr_pins, ops, ddata);
 535                 if (!bank->irq_domain) {
 536                         dev_err(dev, "wkup irq domain add failed\n");
 537                         return -ENXIO;
 538                 }
 539
 540                 irq = bank->eint_offset;
 541                 mask = bank->eint_mask;
 542                 for (pin = 0; mask; ++pin, mask >>= 1) {
 543                         if (irq >= NUM_EINT)
 544                                 break;
 545                         if (!(mask & 1))
 546                                 continue;
 547                         eint_data->domains[irq] = bank->irq_domain;
 548                         ++irq;
 549                 }
 550         }
 551
 552         return 0;
 553 }
 554
 555 static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
 556         PIN_BANK_A(23, 0x000, "gpa"),
 557         PIN_BANK_2BIT(11, 0x010, "gpb"),
 558         PIN_BANK_2BIT(16, 0x020, "gpc"),
 559         PIN_BANK_2BIT(16, 0x030, "gpd"),
 560         PIN_BANK_2BIT(16, 0x040, "gpe"),
 561         PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
 562         PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
 563         PIN_BANK_2BIT(11, 0x070, "gph"),
 564         PIN_BANK_2BIT(13, 0x080, "gpj"),
 565 };
 566
 567 static const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
 568         {
 569                 .pin_banks      = s3c2412_pin_banks,
 570                 .nr_banks       = ARRAY_SIZE(s3c2412_pin_banks),
 571                 .eint_wkup_init = s3c24xx_eint_init,
 572         },
 573 };
 574
 575 const struct samsung_pinctrl_of_match_data s3c2412_of_data __initconst = {
 576         .ctrl           = s3c2412_pin_ctrl,
 577         .num_ctrl       = ARRAY_SIZE(s3c2412_pin_ctrl),
 578 };
 579
 580 static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
 581         PIN_BANK_A(27, 0x000, "gpa"),
 582         PIN_BANK_2BIT(11, 0x010, "gpb"),
 583         PIN_BANK_2BIT(16, 0x020, "gpc"),
 584         PIN_BANK_2BIT(16, 0x030, "gpd"),
 585         PIN_BANK_2BIT(16, 0x040, "gpe"),
 586         PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
 587         PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
 588         PIN_BANK_2BIT(15, 0x070, "gph"),
 589         PIN_BANK_2BIT(16, 0x0e0, "gpk"),
 590         PIN_BANK_2BIT(14, 0x0f0, "gpl"),
 591         PIN_BANK_2BIT(2, 0x100, "gpm"),
 592 };
 593
 594 static const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
 595         {
 596                 .pin_banks      = s3c2416_pin_banks,
 597                 .nr_banks       = ARRAY_SIZE(s3c2416_pin_banks),
 598                 .eint_wkup_init = s3c24xx_eint_init,
 599         },
 600 };
 601
 602 const struct samsung_pinctrl_of_match_data s3c2416_of_data __initconst = {
 603         .ctrl           = s3c2416_pin_ctrl,
 604         .num_ctrl       = ARRAY_SIZE(s3c2416_pin_ctrl),
 605 };
 606
 607 static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
 608         PIN_BANK_A(25, 0x000, "gpa"),
 609         PIN_BANK_2BIT(11, 0x010, "gpb"),
 610         PIN_BANK_2BIT(16, 0x020, "gpc"),
 611         PIN_BANK_2BIT(16, 0x030, "gpd"),
 612         PIN_BANK_2BIT(16, 0x040, "gpe"),
 613         PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
 614         PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
 615         PIN_BANK_2BIT(11, 0x070, "gph"),
 616         PIN_BANK_2BIT(13, 0x0d0, "gpj"),
 617 };
 618
 619 static const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
 620         {
 621                 .pin_banks      = s3c2440_pin_banks,
 622                 .nr_banks       = ARRAY_SIZE(s3c2440_pin_banks),
 623                 .eint_wkup_init = s3c24xx_eint_init,
 624         },
 625 };
 626
 627 const struct samsung_pinctrl_of_match_data s3c2440_of_data __initconst = {
 628         .ctrl           = s3c2440_pin_ctrl,
 629         .num_ctrl       = ARRAY_SIZE(s3c2440_pin_ctrl),
 630 };
 631
 632 static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
 633         PIN_BANK_A(28, 0x000, "gpa"),
 634         PIN_BANK_2BIT(11, 0x010, "gpb"),
 635         PIN_BANK_2BIT(16, 0x020, "gpc"),
 636         PIN_BANK_2BIT(16, 0x030, "gpd"),
 637         PIN_BANK_2BIT(16, 0x040, "gpe"),
 638         PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
 639         PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
 640         PIN_BANK_2BIT(15, 0x070, "gph"),
 641         PIN_BANK_2BIT(16, 0x0d0, "gpj"),
 642         PIN_BANK_2BIT(16, 0x0e0, "gpk"),
 643         PIN_BANK_2BIT(15, 0x0f0, "gpl"),
 644         PIN_BANK_2BIT(2, 0x100, "gpm"),
 645 };
 646
 647 static const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
 648         {
 649                 .pin_banks      = s3c2450_pin_banks,
 650                 .nr_banks       = ARRAY_SIZE(s3c2450_pin_banks),
 651                 .eint_wkup_init = s3c24xx_eint_init,
 652         },
 653 };
 654
 655 const struct samsung_pinctrl_of_match_data s3c2450_of_data __initconst = {
 656         .ctrl           = s3c2450_pin_ctrl,
 657         .num_ctrl       = ARRAY_SIZE(s3c2450_pin_ctrl),
 658 };