1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2012 Linaro Ltd
8 * http://www.linaro.org
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
13 #ifndef __PINCTRL_SAMSUNG_H
14 #define __PINCTRL_SAMSUNG_H
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/gpio/driver.h>
25 * enum pincfg_type - possible pin configuration types supported.
26 * @PINCFG_TYPE_FUNC: Function configuration.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
28 * @PINCFG_TYPE_PUD: Pull up/down configuration.
29 * @PINCFG_TYPE_DRV: Drive strength configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
31 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
45 * pin configuration (pull up/down and drive strength) type and its value are
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
49 #define PINCFG_TYPE_MASK 0xFF
50 #define PINCFG_VALUE_SHIFT 8
51 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
52 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
53 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
54 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
63 * Samsung GPIO controller groups all the available pins into banks. The pins
64 * in a pin bank can support external gpio interrupts or external wakeup
65 * interrupts or no interrupts at all. From a software perspective, the only
66 * difference between external gpio and external wakeup interrupts is that
67 * the wakeup interrupts can additionally wakeup the system if it is in
77 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
78 #define PIN_NAME_LENGTH 10
80 #define PIN_GROUP(n, p, f) \
84 .num_pins = ARRAY_SIZE(p), \
88 #define PMX_FUNC(n, g) \
92 .num_groups = ARRAY_SIZE(g), \
95 struct samsung_pinctrl_drv_data
;
98 * struct samsung_pin_bank_type: pin bank type description
99 * @fld_width: widths of configuration bitfields (0 if unavailable)
100 * @reg_offset: offsets of configuration registers (don't care of width is 0)
102 struct samsung_pin_bank_type
{
103 u8 fld_width
[PINCFG_TYPE_NUM
];
104 u8 reg_offset
[PINCFG_TYPE_NUM
];
108 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
109 * @type: type of the bank (register offsets and bitfield widths)
110 * @pctl_offset: starting offset of the pin-bank registers.
111 * @pctl_res_idx: index of base address for pin-bank registers.
112 * @nr_pins: number of pins included in this bank.
113 * @eint_func: function to set in CON register to configure pin as EINT.
114 * @eint_type: type of the external interrupt supported by the bank.
115 * @eint_mask: bit mask of pins which support EINT function.
116 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
117 * @name: name to be prefixed for each pin in this pin bank.
119 struct samsung_pin_bank_data
{
120 const struct samsung_pin_bank_type
*type
;
125 enum eint_type eint_type
;
132 * struct samsung_pin_bank: represent a controller pin-bank.
133 * @type: type of the bank (register offsets and bitfield widths)
134 * @pctl_base: base address of the pin-bank registers
135 * @pctl_offset: starting offset of the pin-bank registers.
136 * @nr_pins: number of pins included in this bank.
137 * @eint_base: base address of the pin-bank EINT registers.
138 * @eint_func: function to set in CON register to configure pin as EINT.
139 * @eint_type: type of the external interrupt supported by the bank.
140 * @eint_mask: bit mask of pins which support EINT function.
141 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
142 * @name: name to be prefixed for each pin in this pin bank.
143 * @pin_base: starting pin number of the bank.
144 * @soc_priv: per-bank private data for SoC-specific code.
145 * @of_node: OF node of the bank.
146 * @drvdata: link to controller driver data
147 * @irq_domain: IRQ domain of the bank.
148 * @gpio_chip: GPIO chip of the bank.
149 * @grange: linux gpio pin range supported by this bank.
150 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
151 * @slock: spinlock protecting bank registers
152 * @pm_save: saved register values during suspend
154 struct samsung_pin_bank
{
155 const struct samsung_pin_bank_type
*type
;
156 void __iomem
*pctl_base
;
159 void __iomem
*eint_base
;
161 enum eint_type eint_type
;
168 struct device_node
*of_node
;
169 struct samsung_pinctrl_drv_data
*drvdata
;
170 struct irq_domain
*irq_domain
;
171 struct gpio_chip gpio_chip
;
172 struct pinctrl_gpio_range grange
;
173 struct exynos_irq_chip
*irq_chip
;
176 u32 pm_save
[PINCFG_TYPE_NUM
+ 1]; /* +1 to handle double CON registers*/
180 * struct samsung_retention_data: runtime pin-bank retention control data.
181 * @regs: array of PMU registers to control pad retention.
182 * @nr_regs: number of registers in @regs array.
183 * @value: value to store to registers to turn off retention.
184 * @refcnt: atomic counter if retention control affects more than one bank.
185 * @priv: retention control code private data
186 * @enable: platform specific callback to enter retention mode.
187 * @disable: platform specific callback to exit retention mode.
189 struct samsung_retention_ctrl
{
195 void (*enable
)(struct samsung_pinctrl_drv_data
*);
196 void (*disable
)(struct samsung_pinctrl_drv_data
*);
200 * struct samsung_retention_data: represent a pin-bank retention control data.
201 * @regs: array of PMU registers to control pad retention.
202 * @nr_regs: number of registers in @regs array.
203 * @value: value to store to registers to turn off retention.
204 * @refcnt: atomic counter if retention control affects more than one bank.
205 * @init: platform specific callback to initialize retention control.
207 struct samsung_retention_data
{
212 struct samsung_retention_ctrl
*(*init
)(struct samsung_pinctrl_drv_data
*,
213 const struct samsung_retention_data
*);
217 * struct samsung_pin_ctrl: represent a pin controller.
218 * @pin_banks: list of pin banks included in this controller.
219 * @nr_banks: number of pin banks.
220 * @nr_ext_resources: number of the extra base address for pin banks.
221 * @retention_data: configuration data for retention control.
222 * @eint_gpio_init: platform specific callback to setup the external gpio
223 * interrupts for the controller.
224 * @eint_wkup_init: platform specific callback to setup the external wakeup
225 * interrupts for the controller.
226 * @suspend: platform specific suspend callback, executed during pin controller
227 * device suspend, see samsung_pinctrl_suspend()
228 * @resume: platform specific resume callback, executed during pin controller
229 * device suspend, see samsung_pinctrl_resume()
231 * External wakeup interrupts must define at least eint_wkup_init,
232 * retention_data and suspend in order for proper suspend/resume to work.
234 struct samsung_pin_ctrl
{
235 const struct samsung_pin_bank_data
*pin_banks
;
236 unsigned int nr_banks
;
237 unsigned int nr_ext_resources
;
238 const struct samsung_retention_data
*retention_data
;
240 int (*eint_gpio_init
)(struct samsung_pinctrl_drv_data
*);
241 int (*eint_wkup_init
)(struct samsung_pinctrl_drv_data
*);
242 void (*suspend
)(struct samsung_pinctrl_drv_data
*);
243 void (*resume
)(struct samsung_pinctrl_drv_data
*);
247 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
248 * @node: global list node
249 * @virt_base: register base address of the controller; this will be equal
250 * to each bank samsung_pin_bank->pctl_base and used on legacy
251 * platforms (like S3C24XX or S3C64XX) which has to access the base
252 * through samsung_pinctrl_drv_data, not samsung_pin_bank).
253 * @dev: device instance representing the controller.
254 * @irq: interrpt number used by the controller to notify gpio interrupts.
255 * @ctrl: pin controller instance managed by the driver.
256 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
257 * @pctl_dev: cookie representing pinctrl device instance.
258 * @pin_groups: list of pin groups available to the driver.
259 * @nr_groups: number of such pin groups.
260 * @pmx_functions: list of pin functions available to the driver.
261 * @nr_function: number of such pin functions.
262 * @pin_base: starting system wide pin number.
263 * @nr_pins: number of pins supported by the controller.
264 * @retention_ctrl: retention control runtime data.
265 * @suspend: platform specific suspend callback, executed during pin controller
266 * device suspend, see samsung_pinctrl_suspend()
267 * @resume: platform specific resume callback, executed during pin controller
268 * device suspend, see samsung_pinctrl_resume()
270 struct samsung_pinctrl_drv_data
{
271 struct list_head node
;
272 void __iomem
*virt_base
;
276 struct pinctrl_desc pctl
;
277 struct pinctrl_dev
*pctl_dev
;
279 const struct samsung_pin_group
*pin_groups
;
280 unsigned int nr_groups
;
281 const struct samsung_pmx_func
*pmx_functions
;
282 unsigned int nr_functions
;
284 struct samsung_pin_bank
*pin_banks
;
285 unsigned int nr_banks
;
286 unsigned int pin_base
;
287 unsigned int nr_pins
;
289 struct samsung_retention_ctrl
*retention_ctrl
;
291 void (*suspend
)(struct samsung_pinctrl_drv_data
*);
292 void (*resume
)(struct samsung_pinctrl_drv_data
*);
296 * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
297 * @ctrl: array of pin controller data.
298 * @num_ctrl: size of array @ctrl.
300 struct samsung_pinctrl_of_match_data
{
301 const struct samsung_pin_ctrl
*ctrl
;
302 unsigned int num_ctrl
;
306 * struct samsung_pin_group: represent group of pins of a pinmux function.
307 * @name: name of the pin group, used to lookup the group.
308 * @pins: the pins included in this group.
309 * @num_pins: number of pins included in this group.
310 * @func: the function number to be programmed when selected.
312 struct samsung_pin_group
{
314 const unsigned int *pins
;
320 * struct samsung_pmx_func: represent a pin function.
321 * @name: name of the pin function, used to lookup the function.
322 * @groups: one or more names of pin groups that provide this function.
323 * @num_groups: number of groups included in @groups.
325 struct samsung_pmx_func
{
332 /* list of all exported SoC specific data */
333 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data
;
334 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data
;
335 extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data
;
336 extern const struct samsung_pinctrl_of_match_data exynos5250_of_data
;
337 extern const struct samsung_pinctrl_of_match_data exynos5260_of_data
;
338 extern const struct samsung_pinctrl_of_match_data exynos5410_of_data
;
339 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data
;
340 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data
;
341 extern const struct samsung_pinctrl_of_match_data exynos7_of_data
;
342 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data
;
343 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data
;
344 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data
;
345 extern const struct samsung_pinctrl_of_match_data s3c2440_of_data
;
346 extern const struct samsung_pinctrl_of_match_data s3c2450_of_data
;
347 extern const struct samsung_pinctrl_of_match_data s5pv210_of_data
;
349 #endif /* __PINCTRL_SAMSUNG_H */