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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / sirf / pinctrl-atlas7.c
blobe54a6e3cafd2389a407a9ceb4966916de20a2541
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * pinctrl pads, groups, functions for CSR SiRFatlasVII
4 *
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6 * company.
7 */
8
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/io.h>
12 #include <linux/bitops.h>
13 #include <linux/irq.h>
14 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/gpio/driver.h>
28
29 /* Definition of Pad&Mux Properties */
30 #define N 0
31
32 /* The Bank contains input-disable regisgers */
33 #define BANK_DS 0
34
35 /* Clear Register offset */
36 #define CLR_REG(r) ((r) + 0x04)
37
38 /* Definition of multiple function select register */
39 #define FUNC_CLEAR_MASK 0x7
40 #define FUNC_GPIO 0
41 #define FUNC_ANALOGUE 0x8
42 #define ANA_CLEAR_MASK 0x1
43
44 /* The Atlas7's Pad Type List */
45 enum altas7_pad_type {
46 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
47 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
48 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
49 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
50 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
51 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
52 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
53 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
54 };
55
56 /* Raw value of Driver-Strength Bits */
57 #define DS3 BIT(3)
58 #define DS2 BIT(2)
59 #define DS1 BIT(1)
60 #define DS0 BIT(0)
61 #define DSZ 0
62
63 /* Drive-Strength Intermediate Values */
64 #define DS_NULL -1
65 #define DS_1BIT_IM_VAL DS0
66 #define DS_1BIT_MASK 0x1
67 #define DS_2BIT_IM_VAL (DS1 | DS0)
68 #define DS_2BIT_MASK 0x3
69 #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
70 #define DS_4BIT_MASK 0xf
71
72 /* The Drive-Strength of 4WE Pad DS1 0 CO */
73 #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
74 #define DS_4WE_2 (DS1) /* 1 0 2 */
75 #define DS_4WE_1 (DS0) /* 0 1 1 */
76 #define DS_4WE_0 (DSZ) /* 0 0 0 */
77
78 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
79 #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
80 #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
81 #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
82 #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
83 #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
84 #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
85 #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
86 #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
87 #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
88 #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
89 #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
90 #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
91 #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
92 #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
93 #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
94 #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
95
96 /* The Drive-Strength of M31 Pad DS0 CO */
97 #define DS_M31_0 (DSZ) /* 0 0 */
98 #define DS_M31_1 (DS0) /* 1 1 */
99
100 /* Raw values of Pull Option Bits */
101 #define PUN BIT(1)
102 #define PD BIT(0)
103 #define PE BIT(0)
104 #define PZ 0
105
106 /* Definition of Pull Types */
107 #define PULL_UP 0
108 #define HIGH_HYSTERESIS 1
109 #define HIGH_Z 2
110 #define PULL_DOWN 3
111 #define PULL_DISABLE 4
112 #define PULL_ENABLE 5
113 #define PULL_UNKNOWN -1
114
115 /* Pull Options for 4WE Pad PUN PD CO */
116 #define P4WE_PULL_MASK 0x3
117 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
118 #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
119 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
120 #define P4WE_PULL_UP (PZ) /* 0 0 0 */
121
122 /* Pull Options for 16ST Pad PUN PD CO */
123 #define P16ST_PULL_MASK 0x3
124 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
125 #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
126 #define P16ST_PULL_UP (PZ) /* 0 0 0 */
127
128 /* Pull Options for M31 Pad PE */
129 #define PM31_PULL_MASK 0x1
130 #define PM31_PULL_ENABLED (PE) /* 1 */
131 #define PM31_PULL_DISABLED (PZ) /* 0 */
132
133 /* Pull Options for A/D Pad PUN PD CO */
134 #define PANGD_PULL_MASK 0x3
135 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
136 #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
137 #define PANGD_PULL_UP (PZ) /* 0 0 0 */
138
139 /* Definition of Input Disable */
140 #define DI_MASK 0x1
141 #define DI_DISABLE 0x1
142 #define DI_ENABLE 0x0
143
144 /* Definition of Input Disable Value */
145 #define DIV_MASK 0x1
146 #define DIV_DISABLE 0x1
147 #define DIV_ENABLE 0x0
148
149 /* Number of Function input disable registers */
150 #define NUM_OF_IN_DISABLE_REG 0x2
151
152 /* Offset of Function input disable registers */
153 #define IN_DISABLE_0_REG_SET 0x0A00
154 #define IN_DISABLE_0_REG_CLR 0x0A04
155 #define IN_DISABLE_1_REG_SET 0x0A08
156 #define IN_DISABLE_1_REG_CLR 0x0A0C
157 #define IN_DISABLE_VAL_0_REG_SET 0x0A80
158 #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
159 #define IN_DISABLE_VAL_1_REG_SET 0x0A88
160 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
161
162 /* Offset of the SDIO9SEL*/
163 #define SYS2PCI_SDIO9SEL 0x14
164
165 struct dt_params {
166 const char *property;
167 int value;
168 };
169
170 /**
171 * struct atlas7_pad_conf - Atlas7 Pad Configuration
172 * @id: The ID of this Pad.
173 * @type: The type of this Pad.
174 * @mux_reg: The mux register offset.
175 * This register contains the mux.
176 * @pupd_reg: The pull-up/down register offset.
177 * @drvstr_reg: The drive-strength register offset.
178 * @ad_ctrl_reg: The Analogue/Digital Control register.
179 *
180 * @mux_bit: The start bit of mux register.
181 * @pupd_bit: The start bit of pull-up/down register.
182 * @drvstr_bit: The start bit of drive-strength register.
183 * @ad_ctrl_bit: The start bit of analogue/digital register.
184 */
185 struct atlas7_pad_config {
186 const u32 id;
187 u32 type;
188 u32 mux_reg;
189 u32 pupd_reg;
190 u32 drvstr_reg;
191 u32 ad_ctrl_reg;
192 /* bits in register */
193 u8 mux_bit;
194 u8 pupd_bit;
195 u8 drvstr_bit;
196 u8 ad_ctrl_bit;
197 };
198
199 #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
200 { \
201 .id = pad, \
202 .type = t, \
203 .mux_reg = mr, \
204 .pupd_reg = pr, \
205 .drvstr_reg = dsr, \
206 .ad_ctrl_reg = adr, \
207 .mux_bit = mb, \
208 .pupd_bit = pb, \
209 .drvstr_bit = dsb, \
210 .ad_ctrl_bit = adb, \
211 }
212
213 /*
214 * struct atlas7_pad_status - Atlas7 Pad status
215 */
216 struct atlas7_pad_status {
217 u8 func;
218 u8 pull;
219 u8 dstr;
220 u8 reserved;
221 };
222
223 /**
224 * struct atlas7_pad_mux - Atlas7 mux
225 * @bank: The bank of this pad's registers on.
226 * @pin : The ID of this Pad.
227 * @func: The mux func on this Pad.
228 * @dinput_reg: The Input-Disable register offset.
229 * @dinput_bit: The start bit of Input-Disable register.
230 * @dinput_val_reg: The Input-Disable-value register offset.
231 * This register is used to set the value of this pad
232 * if this pad was disabled.
233 * @dinput_val_bit: The start bit of Input-Disable Value register.
234 */
235 struct atlas7_pad_mux {
236 u32 bank;
237 u32 pin;
238 u32 func;
239 u32 dinput_reg;
240 u32 dinput_bit;
241 u32 dinput_val_reg;
242 u32 dinput_val_bit;
243 };
244
245 #define MUX(b, pad, f, dr, db, dvr, dvb) \
246 { \
247 .bank = b, \
248 .pin = pad, \
249 .func = f, \
250 .dinput_reg = dr, \
251 .dinput_bit = db, \
252 .dinput_val_reg = dvr, \
253 .dinput_val_bit = dvb, \
254 }
255
256 struct atlas7_grp_mux {
257 unsigned int group;
258 unsigned int pad_mux_count;
259 const struct atlas7_pad_mux *pad_mux_list;
260 };
261
262 /**
263 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
264 * @name: the name of this specific pin group
265 * @pins: an array of discrete physical pins used in this group, taken
266 * from the driver-local pin enumeration space
267 * @num_pins: the number of pins in this group array, i.e. the number of
268 * elements in .pins so we can iterate over that array
269 */
270 struct atlas7_pin_group {
271 const char *name;
272 const unsigned int *pins;
273 const unsigned num_pins;
274 };
275
276 #define GROUP(n, p) \
277 { \
278 .name = n, \
279 .pins = p, \
280 .num_pins = ARRAY_SIZE(p), \
281 }
282
283 struct atlas7_pmx_func {
284 const char *name;
285 const char * const *groups;
286 const unsigned num_groups;
287 const struct atlas7_grp_mux *grpmux;
288 };
289
290 #define FUNCTION(n, g, m) \
291 { \
292 .name = n, \
293 .groups = g, \
294 .num_groups = ARRAY_SIZE(g), \
295 .grpmux = m, \
296 }
297
298 struct atlas7_pinctrl_data {
299 struct pinctrl_pin_desc *pads;
300 int pads_cnt;
301 struct atlas7_pin_group *grps;
302 int grps_cnt;
303 struct atlas7_pmx_func *funcs;
304 int funcs_cnt;
305 struct atlas7_pad_config *confs;
306 int confs_cnt;
307 };
308
309 /* Platform info of atlas7 pinctrl */
310 #define ATLAS7_PINCTRL_REG_BANKS 2
311 #define ATLAS7_PINCTRL_BANK_0_PINS 18
312 #define ATLAS7_PINCTRL_BANK_1_PINS 141
313 #define ATLAS7_PINCTRL_TOTAL_PINS \
314 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
315
316 /**
317 * Atlas7 GPIO Chip
318 */
319
320 #define NGPIO_OF_BANK 32
321 #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
322
323 /* Registers of GPIO Controllers */
324 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
325 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
326 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
327
328 /* Definition bits of GPIO Control Registers */
329 #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
330 #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
331 #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
332 #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
333 #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
334 #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
335 #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
336 #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
337
338 struct atlas7_gpio_bank {
339 int id;
340 int irq;
341 void __iomem *base;
342 unsigned int gpio_offset;
343 unsigned int ngpio;
344 const unsigned int *gpio_pins;
345 u32 sleep_data[NGPIO_OF_BANK];
346 };
347
348 struct atlas7_gpio_chip {
349 const char *name;
350 void __iomem *reg;
351 struct clk *clk;
352 int nbank;
353 raw_spinlock_t lock;
354 struct gpio_chip chip;
355 struct atlas7_gpio_bank banks[];
356 };
357
358 struct atlas7_pmx {
359 struct device *dev;
360 struct pinctrl_dev *pctl;
361 struct pinctrl_desc pctl_desc;
362 struct atlas7_pinctrl_data *pctl_data;
363 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
364 void __iomem *sys2pci_base;
365 u32 status_ds[NUM_OF_IN_DISABLE_REG];
366 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
367 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
368 };
369
370 /*
371 * Pad list for the pinmux subsystem
372 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
373 */
374
375 /* Pads in IOC RTC & TOP */
376 static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
377 /* RTC PADs */
378 PINCTRL_PIN(0, "rtc_gpio_0"),
379 PINCTRL_PIN(1, "rtc_gpio_1"),
380 PINCTRL_PIN(2, "rtc_gpio_2"),
381 PINCTRL_PIN(3, "rtc_gpio_3"),
382 PINCTRL_PIN(4, "low_bat_ind_b"),
383 PINCTRL_PIN(5, "on_key_b"),
384 PINCTRL_PIN(6, "ext_on"),
385 PINCTRL_PIN(7, "mem_on"),
386 PINCTRL_PIN(8, "core_on"),
387 PINCTRL_PIN(9, "io_on"),
388 PINCTRL_PIN(10, "can0_tx"),
389 PINCTRL_PIN(11, "can0_rx"),
390 PINCTRL_PIN(12, "spi0_clk"),
391 PINCTRL_PIN(13, "spi0_cs_b"),
392 PINCTRL_PIN(14, "spi0_io_0"),
393 PINCTRL_PIN(15, "spi0_io_1"),
394 PINCTRL_PIN(16, "spi0_io_2"),
395 PINCTRL_PIN(17, "spi0_io_3"),
396
397 /* TOP PADs */
398 PINCTRL_PIN(18, "spi1_en"),
399 PINCTRL_PIN(19, "spi1_clk"),
400 PINCTRL_PIN(20, "spi1_din"),
401 PINCTRL_PIN(21, "spi1_dout"),
402 PINCTRL_PIN(22, "trg_spi_clk"),
403 PINCTRL_PIN(23, "trg_spi_di"),
404 PINCTRL_PIN(24, "trg_spi_do"),
405 PINCTRL_PIN(25, "trg_spi_cs_b"),
406 PINCTRL_PIN(26, "trg_acq_d1"),
407 PINCTRL_PIN(27, "trg_irq_b"),
408 PINCTRL_PIN(28, "trg_acq_d0"),
409 PINCTRL_PIN(29, "trg_acq_clk"),
410 PINCTRL_PIN(30, "trg_shutdown_b_out"),
411 PINCTRL_PIN(31, "sdio2_clk"),
412 PINCTRL_PIN(32, "sdio2_cmd"),
413 PINCTRL_PIN(33, "sdio2_dat_0"),
414 PINCTRL_PIN(34, "sdio2_dat_1"),
415 PINCTRL_PIN(35, "sdio2_dat_2"),
416 PINCTRL_PIN(36, "sdio2_dat_3"),
417 PINCTRL_PIN(37, "df_ad_7"),
418 PINCTRL_PIN(38, "df_ad_6"),
419 PINCTRL_PIN(39, "df_ad_5"),
420 PINCTRL_PIN(40, "df_ad_4"),
421 PINCTRL_PIN(41, "df_ad_3"),
422 PINCTRL_PIN(42, "df_ad_2"),
423 PINCTRL_PIN(43, "df_ad_1"),
424 PINCTRL_PIN(44, "df_ad_0"),
425 PINCTRL_PIN(45, "df_dqs"),
426 PINCTRL_PIN(46, "df_cle"),
427 PINCTRL_PIN(47, "df_ale"),
428 PINCTRL_PIN(48, "df_we_b"),
429 PINCTRL_PIN(49, "df_re_b"),
430 PINCTRL_PIN(50, "df_ry_by"),
431 PINCTRL_PIN(51, "df_cs_b_1"),
432 PINCTRL_PIN(52, "df_cs_b_0"),
433 PINCTRL_PIN(53, "l_pclk"),
434 PINCTRL_PIN(54, "l_lck"),
435 PINCTRL_PIN(55, "l_fck"),
436 PINCTRL_PIN(56, "l_de"),
437 PINCTRL_PIN(57, "ldd_0"),
438 PINCTRL_PIN(58, "ldd_1"),
439 PINCTRL_PIN(59, "ldd_2"),
440 PINCTRL_PIN(60, "ldd_3"),
441 PINCTRL_PIN(61, "ldd_4"),
442 PINCTRL_PIN(62, "ldd_5"),
443 PINCTRL_PIN(63, "ldd_6"),
444 PINCTRL_PIN(64, "ldd_7"),
445 PINCTRL_PIN(65, "ldd_8"),
446 PINCTRL_PIN(66, "ldd_9"),
447 PINCTRL_PIN(67, "ldd_10"),
448 PINCTRL_PIN(68, "ldd_11"),
449 PINCTRL_PIN(69, "ldd_12"),
450 PINCTRL_PIN(70, "ldd_13"),
451 PINCTRL_PIN(71, "ldd_14"),
452 PINCTRL_PIN(72, "ldd_15"),
453 PINCTRL_PIN(73, "lcd_gpio_20"),
454 PINCTRL_PIN(74, "vip_0"),
455 PINCTRL_PIN(75, "vip_1"),
456 PINCTRL_PIN(76, "vip_2"),
457 PINCTRL_PIN(77, "vip_3"),
458 PINCTRL_PIN(78, "vip_4"),
459 PINCTRL_PIN(79, "vip_5"),
460 PINCTRL_PIN(80, "vip_6"),
461 PINCTRL_PIN(81, "vip_7"),
462 PINCTRL_PIN(82, "vip_pxclk"),
463 PINCTRL_PIN(83, "vip_hsync"),
464 PINCTRL_PIN(84, "vip_vsync"),
465 PINCTRL_PIN(85, "sdio3_clk"),
466 PINCTRL_PIN(86, "sdio3_cmd"),
467 PINCTRL_PIN(87, "sdio3_dat_0"),
468 PINCTRL_PIN(88, "sdio3_dat_1"),
469 PINCTRL_PIN(89, "sdio3_dat_2"),
470 PINCTRL_PIN(90, "sdio3_dat_3"),
471 PINCTRL_PIN(91, "sdio5_clk"),
472 PINCTRL_PIN(92, "sdio5_cmd"),
473 PINCTRL_PIN(93, "sdio5_dat_0"),
474 PINCTRL_PIN(94, "sdio5_dat_1"),
475 PINCTRL_PIN(95, "sdio5_dat_2"),
476 PINCTRL_PIN(96, "sdio5_dat_3"),
477 PINCTRL_PIN(97, "rgmii_txd_0"),
478 PINCTRL_PIN(98, "rgmii_txd_1"),
479 PINCTRL_PIN(99, "rgmii_txd_2"),
480 PINCTRL_PIN(100, "rgmii_txd_3"),
481 PINCTRL_PIN(101, "rgmii_txclk"),
482 PINCTRL_PIN(102, "rgmii_tx_ctl"),
483 PINCTRL_PIN(103, "rgmii_rxd_0"),
484 PINCTRL_PIN(104, "rgmii_rxd_1"),
485 PINCTRL_PIN(105, "rgmii_rxd_2"),
486 PINCTRL_PIN(106, "rgmii_rxd_3"),
487 PINCTRL_PIN(107, "rgmii_rx_clk"),
488 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
489 PINCTRL_PIN(109, "rgmii_mdio"),
490 PINCTRL_PIN(110, "rgmii_mdc"),
491 PINCTRL_PIN(111, "rgmii_intr_n"),
492 PINCTRL_PIN(112, "i2s_mclk"),
493 PINCTRL_PIN(113, "i2s_bclk"),
494 PINCTRL_PIN(114, "i2s_ws"),
495 PINCTRL_PIN(115, "i2s_dout0"),
496 PINCTRL_PIN(116, "i2s_dout1"),
497 PINCTRL_PIN(117, "i2s_dout2"),
498 PINCTRL_PIN(118, "i2s_din"),
499 PINCTRL_PIN(119, "gpio_0"),
500 PINCTRL_PIN(120, "gpio_1"),
501 PINCTRL_PIN(121, "gpio_2"),
502 PINCTRL_PIN(122, "gpio_3"),
503 PINCTRL_PIN(123, "gpio_4"),
504 PINCTRL_PIN(124, "gpio_5"),
505 PINCTRL_PIN(125, "gpio_6"),
506 PINCTRL_PIN(126, "gpio_7"),
507 PINCTRL_PIN(127, "sda_0"),
508 PINCTRL_PIN(128, "scl_0"),
509 PINCTRL_PIN(129, "coex_pio_0"),
510 PINCTRL_PIN(130, "coex_pio_1"),
511 PINCTRL_PIN(131, "coex_pio_2"),
512 PINCTRL_PIN(132, "coex_pio_3"),
513 PINCTRL_PIN(133, "uart0_tx"),
514 PINCTRL_PIN(134, "uart0_rx"),
515 PINCTRL_PIN(135, "uart1_tx"),
516 PINCTRL_PIN(136, "uart1_rx"),
517 PINCTRL_PIN(137, "uart3_tx"),
518 PINCTRL_PIN(138, "uart3_rx"),
519 PINCTRL_PIN(139, "uart4_tx"),
520 PINCTRL_PIN(140, "uart4_rx"),
521 PINCTRL_PIN(141, "usp0_clk"),
522 PINCTRL_PIN(142, "usp0_tx"),
523 PINCTRL_PIN(143, "usp0_rx"),
524 PINCTRL_PIN(144, "usp0_fs"),
525 PINCTRL_PIN(145, "usp1_clk"),
526 PINCTRL_PIN(146, "usp1_tx"),
527 PINCTRL_PIN(147, "usp1_rx"),
528 PINCTRL_PIN(148, "usp1_fs"),
529 PINCTRL_PIN(149, "lvds_tx0d4p"),
530 PINCTRL_PIN(150, "lvds_tx0d4n"),
531 PINCTRL_PIN(151, "lvds_tx0d3p"),
532 PINCTRL_PIN(152, "lvds_tx0d3n"),
533 PINCTRL_PIN(153, "lvds_tx0d2p"),
534 PINCTRL_PIN(154, "lvds_tx0d2n"),
535 PINCTRL_PIN(155, "lvds_tx0d1p"),
536 PINCTRL_PIN(156, "lvds_tx0d1n"),
537 PINCTRL_PIN(157, "lvds_tx0d0p"),
538 PINCTRL_PIN(158, "lvds_tx0d0n"),
539 PINCTRL_PIN(159, "jtag_tdo"),
540 PINCTRL_PIN(160, "jtag_tms"),
541 PINCTRL_PIN(161, "jtag_tck"),
542 PINCTRL_PIN(162, "jtag_tdi"),
543 PINCTRL_PIN(163, "jtag_trstn"),
544 };
545
546 static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
547 /* The Configuration of IOC_RTC Pads */
548 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
549 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
550 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
551 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
552 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
553 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
554 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
555 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
556 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
557 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
558 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
559 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
560 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
561 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
562 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
563 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
564 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
565 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
566 /* The Configuration of IOC_TOP Pads */
567 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
568 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
569 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
570 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
571 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
572 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
573 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
574 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
575 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
576 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
577 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
578 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
579 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
580 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
581 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
582 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
583 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
584 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
585 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
586 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
587 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
588 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
589 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
590 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
591 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
592 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
593 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
594 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
595 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
596 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
597 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
598 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
599 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
600 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
601 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
602 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
603 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
604 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
605 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
606 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
607 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
608 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
609 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
610 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
611 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
612 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
613 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
614 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
615 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
616 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
617 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
618 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
619 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
620 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
621 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
622 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
623 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
624 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
625 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
626 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
627 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
628 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
629 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
630 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
631 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
632 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
633 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
634 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
635 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
636 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
637 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
638 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
639 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
640 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
641 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
642 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
643 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
644 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
645 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
646 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
647 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
648 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
649 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
650 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
651 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
652 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
653 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
654 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
655 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
656 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
657 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
658 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
659 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
660 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
661 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
662 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
663 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
664 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
665 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
666 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
667 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
668 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
669 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
670 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
671 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
672 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
673 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
674 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
675 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
676 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
677 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
678 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
679 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
680 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
681 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
682 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
683 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
684 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
685 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
686 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
687 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
688 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
689 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
690 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
691 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
692 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
693 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
694 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
695 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
696 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
697 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
698 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
699 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
700 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
701 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
702 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
703 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
704 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
705 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
706 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
707 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
708 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
709 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
710 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
711 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
712 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
713 };
714
715 /* pin list of each pin group */
716 static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
717 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
718 static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
719 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
720 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
721 static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
722 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
723 95, 96, 112, 113, 114, 115, 116, 117, 118, };
724 static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
725 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
726 141, 142, 143, 144, 145, 146, 147, 148, };
727 static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
728 151, 152, 149, 150, };
729 static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
730 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
731 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
732 static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
733 14, 15, 16, 17, 9, };
734 static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
735 static const unsigned int audio_digmic_pins0[] = { 51, };
736 static const unsigned int audio_digmic_pins1[] = { 122, };
737 static const unsigned int audio_digmic_pins2[] = { 161, };
738 static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
739 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
740 115, 49, 50, 142, 143, 80, };
741 static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
742 114, };
743 static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
744 static const unsigned int audio_i2s_extclk_pins[] = { 112, };
745 static const unsigned int audio_spdif_out_pins0[] = { 112, };
746 static const unsigned int audio_spdif_out_pins1[] = { 116, };
747 static const unsigned int audio_spdif_out_pins2[] = { 142, };
748 static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
749 static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
750 static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
751 static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
752 static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
753 static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
754 static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
755 static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
756 static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
757 static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
758 static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
759 static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
760 static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
761 static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
762 static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
763 static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
764 static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
765 static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
766 static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
767 static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
768 static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
769 static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
770 static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
771 static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
772 static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
773 static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
774 static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
775 static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
776 static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
777 static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
778 static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
779 static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
780 static const unsigned int c1_can_rxd_pins0[] = { 138, };
781 static const unsigned int c1_can_rxd_pins1[] = { 147, };
782 static const unsigned int c1_can_rxd_pins2[] = { 2, };
783 static const unsigned int c1_can_rxd_pins3[] = { 162, };
784 static const unsigned int c1_can_txd_pins0[] = { 137, };
785 static const unsigned int c1_can_txd_pins1[] = { 146, };
786 static const unsigned int c1_can_txd_pins2[] = { 3, };
787 static const unsigned int c1_can_txd_pins3[] = { 161, };
788 static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
789 69, 70, 71, };
790 static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
791 static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
792 static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
793 static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
794 static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
795 49, 50, 54, 55, 56, };
796 static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
797 static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
798 static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
799 76, 77, };
800 static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
801 static const unsigned int clkc_pins0[] = { 30, 47, };
802 static const unsigned int clkc_pins1[] = { 78, 54, };
803 static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
804 static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
805 static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
806 static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
807 static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
808 static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
809 79, 80, 81, 83, 84, 73, 55, 56, };
810 static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
811 static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
812 static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
813 static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
814 static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
815 static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
816 static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
817 static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
818 static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
819 static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
820 static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
821 static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
822 static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
823 static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
824 static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
825 static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
826 static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
827 120, };
828 static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
829 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
830 static const unsigned int gn_gnss_eclk_pins[] = { 113, };
831 static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
832 static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
833 static const unsigned int gn_gnss_tm_pins[] = { 115, };
834 static const unsigned int gn_gnss_tsync_pins[] = { 114, };
835 static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
836 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
837 static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
838 static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
839 static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
840 static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
841 static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
842 static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
843 static const unsigned int i2c0_pins[] = { 128, 127, };
844 static const unsigned int i2c1_pins[] = { 126, 125, };
845 static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
846 static const unsigned int i2s1_basic_pins[] = { 95, 96, };
847 static const unsigned int i2s1_rxd0_pins0[] = { 61, };
848 static const unsigned int i2s1_rxd0_pins1[] = { 131, };
849 static const unsigned int i2s1_rxd0_pins2[] = { 129, };
850 static const unsigned int i2s1_rxd0_pins3[] = { 117, };
851 static const unsigned int i2s1_rxd0_pins4[] = { 83, };
852 static const unsigned int i2s1_rxd1_pins0[] = { 72, };
853 static const unsigned int i2s1_rxd1_pins1[] = { 132, };
854 static const unsigned int i2s1_rxd1_pins2[] = { 130, };
855 static const unsigned int i2s1_rxd1_pins3[] = { 118, };
856 static const unsigned int i2s1_rxd1_pins4[] = { 84, };
857 static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
858 static const unsigned int jtag_ntrst_pins0[] = { 4, };
859 static const unsigned int jtag_ntrst_pins1[] = { 163, };
860 static const unsigned int jtag_swdiotms_pins0[] = { 2, };
861 static const unsigned int jtag_swdiotms_pins1[] = { 160, };
862 static const unsigned int jtag_tck_pins0[] = { 0, };
863 static const unsigned int jtag_tck_pins1[] = { 161, };
864 static const unsigned int jtag_tdi_pins0[] = { 1, };
865 static const unsigned int jtag_tdi_pins1[] = { 162, };
866 static const unsigned int jtag_tdo_pins0[] = { 3, };
867 static const unsigned int jtag_tdo_pins1[] = { 159, };
868 static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
869 static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
870 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
871 81, 56, 53, };
872 static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
873 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
874 static const unsigned int ld_ldd_fck_pins[] = { 55, };
875 static const unsigned int ld_ldd_lck_pins[] = { 54, };
876 static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
877 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
878 static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
879 155, 156, 157, 158, };
880 static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
881 37, 47, 46, 52, 45, 49, 50, 48, };
882 static const unsigned int nd_df_wp_pins[] = { 124, };
883 static const unsigned int nd_df_cs_pins[] = { 51, };
884 static const unsigned int ps_pins[] = { 120, 119, 121, };
885 static const unsigned int ps_no_dir_pins[] = { 119, };
886 static const unsigned int pwc_core_on_pins[] = { 8, };
887 static const unsigned int pwc_ext_on_pins[] = { 6, };
888 static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
889 static const unsigned int pwc_io_on_pins[] = { 9, };
890 static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
891 static const unsigned int pwc_mem_on_pins[] = { 7, };
892 static const unsigned int pwc_on_key_b_pins0[] = { 5, };
893 static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
894 static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
895 static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
896 static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
897 static const unsigned int pw_cko0_pins0[] = { 123, };
898 static const unsigned int pw_cko0_pins1[] = { 101, };
899 static const unsigned int pw_cko0_pins2[] = { 82, };
900 static const unsigned int pw_cko0_pins3[] = { 162, };
901 static const unsigned int pw_cko1_pins0[] = { 124, };
902 static const unsigned int pw_cko1_pins1[] = { 110, };
903 static const unsigned int pw_cko1_pins2[] = { 163, };
904 static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
905 static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
906 static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
907 static const unsigned int pw_pwm0_pins0[] = { 119, };
908 static const unsigned int pw_pwm0_pins1[] = { 159, };
909 static const unsigned int pw_pwm1_pins0[] = { 120, };
910 static const unsigned int pw_pwm1_pins1[] = { 160, };
911 static const unsigned int pw_pwm1_pins2[] = { 131, };
912 static const unsigned int pw_pwm2_pins0[] = { 121, };
913 static const unsigned int pw_pwm2_pins1[] = { 98, };
914 static const unsigned int pw_pwm2_pins2[] = { 161, };
915 static const unsigned int pw_pwm3_pins0[] = { 122, };
916 static const unsigned int pw_pwm3_pins1[] = { 73, };
917 static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
918 static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
919 static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
920 static const unsigned int pw_backlight_pins0[] = { 122, };
921 static const unsigned int pw_backlight_pins1[] = { 73, };
922 static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
923 102, 97, 98, 99, 100, 101, };
924 static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
925 static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
926 static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
927 static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
928 static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
929 37, };
930 static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
931 static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
932 37, };
933 static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
934 static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
935 static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
936 static const unsigned int sd2_cdb_pins0[] = { 124, };
937 static const unsigned int sd2_cdb_pins1[] = { 161, };
938 static const unsigned int sd2_wpb_pins0[] = { 123, };
939 static const unsigned int sd2_wpb_pins1[] = { 163, };
940 static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
941 static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
942 static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
943 static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
944 static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
945 static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
946 static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
947 static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
948 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
949 static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
950 static const unsigned int uart0_nopause_pins[] = { 134, 133, };
951 static const unsigned int uart1_pins[] = { 136, 135, };
952 static const unsigned int uart2_cts_pins0[] = { 132, };
953 static const unsigned int uart2_cts_pins1[] = { 162, };
954 static const unsigned int uart2_rts_pins0[] = { 131, };
955 static const unsigned int uart2_rts_pins1[] = { 161, };
956 static const unsigned int uart2_rxd_pins0[] = { 11, };
957 static const unsigned int uart2_rxd_pins1[] = { 160, };
958 static const unsigned int uart2_rxd_pins2[] = { 130, };
959 static const unsigned int uart2_txd_pins0[] = { 10, };
960 static const unsigned int uart2_txd_pins1[] = { 159, };
961 static const unsigned int uart2_txd_pins2[] = { 129, };
962 static const unsigned int uart3_cts_pins0[] = { 125, };
963 static const unsigned int uart3_cts_pins1[] = { 111, };
964 static const unsigned int uart3_cts_pins2[] = { 140, };
965 static const unsigned int uart3_rts_pins0[] = { 126, };
966 static const unsigned int uart3_rts_pins1[] = { 109, };
967 static const unsigned int uart3_rts_pins2[] = { 139, };
968 static const unsigned int uart3_rxd_pins0[] = { 138, };
969 static const unsigned int uart3_rxd_pins1[] = { 84, };
970 static const unsigned int uart3_rxd_pins2[] = { 162, };
971 static const unsigned int uart3_txd_pins0[] = { 137, };
972 static const unsigned int uart3_txd_pins1[] = { 83, };
973 static const unsigned int uart3_txd_pins2[] = { 161, };
974 static const unsigned int uart4_basic_pins[] = { 140, 139, };
975 static const unsigned int uart4_cts_pins0[] = { 122, };
976 static const unsigned int uart4_cts_pins1[] = { 100, };
977 static const unsigned int uart4_cts_pins2[] = { 117, };
978 static const unsigned int uart4_rts_pins0[] = { 123, };
979 static const unsigned int uart4_rts_pins1[] = { 99, };
980 static const unsigned int uart4_rts_pins2[] = { 116, };
981 static const unsigned int usb0_drvvbus_pins0[] = { 51, };
982 static const unsigned int usb0_drvvbus_pins1[] = { 162, };
983 static const unsigned int usb1_drvvbus_pins0[] = { 134, };
984 static const unsigned int usb1_drvvbus_pins1[] = { 163, };
985 static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
986 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
987 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
988 static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
989 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
990 static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
991 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
992 99, 100, };
993 static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
994 80, 81, 82, 83, 84, };
995 static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
996 105, 106, 107, 102, 97, 98, };
997
998 /* definition of pin group table */
999 static struct atlas7_pin_group altas7_pin_groups[] = {
1000 GROUP("gnss_gpio_grp", gnss_gpio_pins),
1001 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1002 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1003 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1004 GROUP("lvds_gpio_grp", lvds_gpio_pins),
1005 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1006 GROUP("rtc_gpio_grp", rtc_gpio_pins),
1007 GROUP("audio_ac97_grp", audio_ac97_pins),
1008 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1009 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1010 GROUP("audio_digmic_grp2", audio_digmic_pins2),
1011 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1012 GROUP("audio_i2s_grp", audio_i2s_pins),
1013 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1014 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1015 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1016 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1017 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1018 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1019 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1020 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1021 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1022 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1023 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1024 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1025 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1026 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1027 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1028 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1029 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1030 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1031 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1032 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1033 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1034 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1035 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1036 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1037 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1038 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1039 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1040 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1041 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1042 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1043 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1044 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1045 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1046 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1047 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1048 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1049 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1050 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1051 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1052 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1053 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1054 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1055 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1056 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1057 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1058 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1059 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1060 GROUP("ca_coex_grp", ca_coex_pins),
1061 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1062 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1063 GROUP("ca_pio_grp", ca_pio_pins),
1064 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1065 GROUP("ca_spi_grp", ca_spi_pins),
1066 GROUP("ca_trb_grp", ca_trb_pins),
1067 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1068 GROUP("clkc_grp0", clkc_pins0),
1069 GROUP("clkc_grp1", clkc_pins1),
1070 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1071 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1072 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1073 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1074 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1075 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1076 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1077 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1078 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1079 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1080 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1081 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1082 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1083 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1084 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1085 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1086 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1087 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1088 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1089 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1090 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1091 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1092 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1093 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1094 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1095 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1096 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1097 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1098 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1099 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1100 GROUP("gn_trg_grp0", gn_trg_pins0),
1101 GROUP("gn_trg_grp1", gn_trg_pins1),
1102 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1103 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1104 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1105 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1106 GROUP("i2c0_grp", i2c0_pins),
1107 GROUP("i2c1_grp", i2c1_pins),
1108 GROUP("i2s0_grp", i2s0_pins),
1109 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1110 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1111 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1112 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1113 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1114 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1115 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1116 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1117 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1118 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1119 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1120 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1121 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1122 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1123 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1124 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1125 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1126 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1127 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1128 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1129 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1130 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1131 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1132 GROUP("ld_ldd_grp", ld_ldd_pins),
1133 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1134 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1135 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1136 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1137 GROUP("lvds_analog_grp", lvds_analog_pins),
1138 GROUP("nd_df_basic_grp", nd_df_basic_pins),
1139 GROUP("nd_df_wp_grp", nd_df_wp_pins),
1140 GROUP("nd_df_cs_grp", nd_df_cs_pins),
1141 GROUP("ps_grp", ps_pins),
1142 GROUP("ps_no_dir_grp", ps_no_dir_pins),
1143 GROUP("pwc_core_on_grp", pwc_core_on_pins),
1144 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1145 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1146 GROUP("pwc_io_on_grp", pwc_io_on_pins),
1147 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1148 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1149 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1150 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1151 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1152 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1153 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1154 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1155 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1156 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1157 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1158 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1159 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1160 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1161 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1162 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1163 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1164 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1165 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1166 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1167 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1168 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1169 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1170 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1171 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1172 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1173 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1174 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1175 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1176 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1177 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1178 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1179 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1180 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1181 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1182 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1183 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1184 GROUP("sd0_grp", sd0_pins),
1185 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1186 GROUP("sd1_grp", sd1_pins),
1187 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1188 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1189 GROUP("sd2_basic_grp", sd2_basic_pins),
1190 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1191 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1192 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1193 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1194 GROUP("sd3_9_grp", sd3_9_pins),
1195 GROUP("sd5_grp", sd5_pins),
1196 GROUP("sd6_grp0", sd6_pins0),
1197 GROUP("sd6_grp1", sd6_pins1),
1198 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1199 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1200 GROUP("sp1_spi_grp", sp1_spi_pins),
1201 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1202 GROUP("uart0_grp", uart0_pins),
1203 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1204 GROUP("uart1_grp", uart1_pins),
1205 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1206 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1207 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1208 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1209 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1210 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1211 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1212 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1213 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1214 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1215 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1216 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1217 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1218 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1219 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1220 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1221 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1222 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1223 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1224 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1225 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1226 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1227 GROUP("uart4_basic_grp", uart4_basic_pins),
1228 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1229 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1230 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1231 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1232 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1233 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1234 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1235 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1236 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1237 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1238 GROUP("visbus_dout_grp", visbus_dout_pins),
1239 GROUP("vi_vip1_grp", vi_vip1_pins),
1240 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1241 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1242 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1243 };
1244
1245 /* How many groups that a function can use */
1246 static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1247 static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1248 static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1249 static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1250 static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1251 static const char * const jtag_uart_nand_gpio_grp[] = {
1252 "jtag_uart_nand_gpio_grp", };
1253 static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1254 static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1255 static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1256 static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1257 static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1258 static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1259 static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1260 static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1261 static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1262 static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1263 static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1264 static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1265 static const char * const audio_uart0_basic_grp[] = {
1266 "audio_uart0_basic_grp", };
1267 static const char * const audio_uart0_urfs_grp0[] = {
1268 "audio_uart0_urfs_grp0", };
1269 static const char * const audio_uart0_urfs_grp1[] = {
1270 "audio_uart0_urfs_grp1", };
1271 static const char * const audio_uart0_urfs_grp2[] = {
1272 "audio_uart0_urfs_grp2", };
1273 static const char * const audio_uart0_urfs_grp3[] = {
1274 "audio_uart0_urfs_grp3", };
1275 static const char * const audio_uart1_basic_grp[] = {
1276 "audio_uart1_basic_grp", };
1277 static const char * const audio_uart1_urfs_grp0[] = {
1278 "audio_uart1_urfs_grp0", };
1279 static const char * const audio_uart1_urfs_grp1[] = {
1280 "audio_uart1_urfs_grp1", };
1281 static const char * const audio_uart1_urfs_grp2[] = {
1282 "audio_uart1_urfs_grp2", };
1283 static const char * const audio_uart2_urfs_grp0[] = {
1284 "audio_uart2_urfs_grp0", };
1285 static const char * const audio_uart2_urfs_grp1[] = {
1286 "audio_uart2_urfs_grp1", };
1287 static const char * const audio_uart2_urfs_grp2[] = {
1288 "audio_uart2_urfs_grp2", };
1289 static const char * const audio_uart2_urxd_grp0[] = {
1290 "audio_uart2_urxd_grp0", };
1291 static const char * const audio_uart2_urxd_grp1[] = {
1292 "audio_uart2_urxd_grp1", };
1293 static const char * const audio_uart2_urxd_grp2[] = {
1294 "audio_uart2_urxd_grp2", };
1295 static const char * const audio_uart2_usclk_grp0[] = {
1296 "audio_uart2_usclk_grp0", };
1297 static const char * const audio_uart2_usclk_grp1[] = {
1298 "audio_uart2_usclk_grp1", };
1299 static const char * const audio_uart2_usclk_grp2[] = {
1300 "audio_uart2_usclk_grp2", };
1301 static const char * const audio_uart2_utfs_grp0[] = {
1302 "audio_uart2_utfs_grp0", };
1303 static const char * const audio_uart2_utfs_grp1[] = {
1304 "audio_uart2_utfs_grp1", };
1305 static const char * const audio_uart2_utfs_grp2[] = {
1306 "audio_uart2_utfs_grp2", };
1307 static const char * const audio_uart2_utxd_grp0[] = {
1308 "audio_uart2_utxd_grp0", };
1309 static const char * const audio_uart2_utxd_grp1[] = {
1310 "audio_uart2_utxd_grp1", };
1311 static const char * const audio_uart2_utxd_grp2[] = {
1312 "audio_uart2_utxd_grp2", };
1313 static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1314 static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1315 static const char * const c_can_trnsvr_intr_grp[] = {
1316 "c_can_trnsvr_intr_grp", };
1317 static const char * const c_can_trnsvr_stb_n_grp[] = {
1318 "c_can_trnsvr_stb_n_grp", };
1319 static const char * const c0_can_rxd_trnsv0_grp[] = {
1320 "c0_can_rxd_trnsv0_grp", };
1321 static const char * const c0_can_rxd_trnsv1_grp[] = {
1322 "c0_can_rxd_trnsv1_grp", };
1323 static const char * const c0_can_txd_trnsv0_grp[] = {
1324 "c0_can_txd_trnsv0_grp", };
1325 static const char * const c0_can_txd_trnsv1_grp[] = {
1326 "c0_can_txd_trnsv1_grp", };
1327 static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1328 static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1329 static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1330 static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1331 static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1332 static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1333 static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1334 static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1335 static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1336 static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1337 static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1338 static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1339 static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1340 static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1341 static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1342 static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1343 static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1344 static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1345 static const char * const clkc_grp0[] = { "clkc_grp0", };
1346 static const char * const clkc_grp1[] = { "clkc_grp1", };
1347 static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1348 static const char * const gn_gnss_uart_nopause_grp[] = {
1349 "gn_gnss_uart_nopause_grp", };
1350 static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1351 static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1352 static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1353 static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1354 static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1355 static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1356 static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1357 static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1358 static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1359 static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1360 static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1361 static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1362 static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1363 static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1364 static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1365 static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1366 static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1367 static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1368 static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1369 static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1370 static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1371 static const char * const gn_gnss_sw_status_grp[] = {
1372 "gn_gnss_sw_status_grp", };
1373 static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1374 static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1375 static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1376 static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1377 static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1378 static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1379 "gn_io_gnsssys_sw_cfg_grp", };
1380 static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1381 static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1382 static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1383 static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1384 static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1385 static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1386 static const char * const i2c0_grp[] = { "i2c0_grp", };
1387 static const char * const i2c1_grp[] = { "i2c1_grp", };
1388 static const char * const i2s0_grp[] = { "i2s0_grp", };
1389 static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1390 static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1391 static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1392 static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1393 static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1394 static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1395 static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1396 static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1397 static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1398 static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1399 static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1400 static const char * const jtag_jt_dbg_nsrst_grp[] = {
1401 "jtag_jt_dbg_nsrst_grp", };
1402 static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1403 static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1404 static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1405 static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1406 static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1407 static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1408 static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1409 static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1410 static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1411 static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1412 static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1413 static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1414 static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1415 static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1416 static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1417 static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1418 static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1419 static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
1420 static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
1421 static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
1422 static const char * const ps_grp[] = { "ps_grp", };
1423 static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
1424 static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1425 static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1426 static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1427 static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1428 static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1429 static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1430 static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1431 static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1432 static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1433 static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1434 static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1435 static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1436 static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1437 static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1438 static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1439 static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1440 static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1441 static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1442 static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1443 static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1444 static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1445 static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1446 static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1447 static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1448 static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1449 static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1450 static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1451 static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1452 static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1453 static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1454 static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1455 static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1456 static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1457 static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1458 static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1459 static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1460 static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1461 static const char * const rg_gmac_phy_intr_n_grp[] = {
1462 "rg_gmac_phy_intr_n_grp", };
1463 static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1464 static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1465 "rg_rgmii_phy_ref_clk_grp0", };
1466 static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1467 "rg_rgmii_phy_ref_clk_grp1", };
1468 static const char * const sd0_grp[] = { "sd0_grp", };
1469 static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1470 static const char * const sd1_grp[] = { "sd1_grp", };
1471 static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1472 static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1473 static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1474 static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1475 static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1476 static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1477 static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1478 static const char * const sd3_9_grp[] = { "sd3_9_grp", };
1479 static const char * const sd5_grp[] = { "sd5_grp", };
1480 static const char * const sd6_grp0[] = { "sd6_grp0", };
1481 static const char * const sd6_grp1[] = { "sd6_grp1", };
1482 static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1483 static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1484 static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1485 static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1486 static const char * const uart0_grp[] = { "uart0_grp", };
1487 static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1488 static const char * const uart1_grp[] = { "uart1_grp", };
1489 static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1490 static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1491 static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1492 static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1493 static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1494 static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1495 static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1496 static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1497 static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1498 static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1499 static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1500 static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1501 static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1502 static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1503 static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1504 static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1505 static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1506 static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1507 static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1508 static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1509 static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1510 static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1511 static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1512 static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1513 static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1514 static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1515 static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1516 static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1517 static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1518 static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1519 static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1520 static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1521 static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1522 static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1523 static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1524 static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1525 static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1526 static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1527
1528 static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1529 MUX(1, 119, 0, N, N, N, N),
1530 MUX(1, 120, 0, N, N, N, N),
1531 MUX(1, 121, 0, N, N, N, N),
1532 MUX(1, 122, 0, N, N, N, N),
1533 MUX(1, 123, 0, N, N, N, N),
1534 MUX(1, 124, 0, N, N, N, N),
1535 MUX(1, 125, 0, N, N, N, N),
1536 MUX(1, 126, 0, N, N, N, N),
1537 MUX(1, 127, 0, N, N, N, N),
1538 MUX(1, 128, 0, N, N, N, N),
1539 MUX(1, 22, 0, N, N, N, N),
1540 MUX(1, 23, 0, N, N, N, N),
1541 MUX(1, 24, 0, N, N, N, N),
1542 MUX(1, 25, 0, N, N, N, N),
1543 MUX(1, 26, 0, N, N, N, N),
1544 MUX(1, 27, 0, N, N, N, N),
1545 MUX(1, 28, 0, N, N, N, N),
1546 MUX(1, 29, 0, N, N, N, N),
1547 MUX(1, 30, 0, N, N, N, N),
1548 };
1549
1550 static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1551 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1552 .pad_mux_list = gnss_gpio_grp_pad_mux,
1553 };
1554
1555 static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1556 MUX(1, 74, 0, N, N, N, N),
1557 MUX(1, 75, 0, N, N, N, N),
1558 MUX(1, 76, 0, N, N, N, N),
1559 MUX(1, 77, 0, N, N, N, N),
1560 MUX(1, 78, 0, N, N, N, N),
1561 MUX(1, 79, 0, N, N, N, N),
1562 MUX(1, 80, 0, N, N, N, N),
1563 MUX(1, 81, 0, N, N, N, N),
1564 MUX(1, 82, 0, N, N, N, N),
1565 MUX(1, 83, 0, N, N, N, N),
1566 MUX(1, 84, 0, N, N, N, N),
1567 MUX(1, 53, 0, N, N, N, N),
1568 MUX(1, 54, 0, N, N, N, N),
1569 MUX(1, 55, 0, N, N, N, N),
1570 MUX(1, 56, 0, N, N, N, N),
1571 MUX(1, 57, 0, N, N, N, N),
1572 MUX(1, 58, 0, N, N, N, N),
1573 MUX(1, 59, 0, N, N, N, N),
1574 MUX(1, 60, 0, N, N, N, N),
1575 MUX(1, 61, 0, N, N, N, N),
1576 MUX(1, 62, 0, N, N, N, N),
1577 MUX(1, 63, 0, N, N, N, N),
1578 MUX(1, 64, 0, N, N, N, N),
1579 MUX(1, 65, 0, N, N, N, N),
1580 MUX(1, 66, 0, N, N, N, N),
1581 MUX(1, 67, 0, N, N, N, N),
1582 MUX(1, 68, 0, N, N, N, N),
1583 MUX(1, 69, 0, N, N, N, N),
1584 MUX(1, 70, 0, N, N, N, N),
1585 MUX(1, 71, 0, N, N, N, N),
1586 MUX(1, 72, 0, N, N, N, N),
1587 MUX(1, 73, 0, N, N, N, N),
1588 };
1589
1590 static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1591 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1592 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1593 };
1594
1595 static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1596 MUX(1, 31, 0, N, N, N, N),
1597 MUX(1, 32, 0, N, N, N, N),
1598 MUX(1, 33, 0, N, N, N, N),
1599 MUX(1, 34, 0, N, N, N, N),
1600 MUX(1, 35, 0, N, N, N, N),
1601 MUX(1, 36, 0, N, N, N, N),
1602 MUX(1, 85, 0, N, N, N, N),
1603 MUX(1, 86, 0, N, N, N, N),
1604 MUX(1, 87, 0, N, N, N, N),
1605 MUX(1, 88, 0, N, N, N, N),
1606 MUX(1, 89, 0, N, N, N, N),
1607 MUX(1, 90, 0, N, N, N, N),
1608 MUX(1, 129, 0, N, N, N, N),
1609 MUX(1, 130, 0, N, N, N, N),
1610 MUX(1, 131, 0, N, N, N, N),
1611 MUX(1, 132, 0, N, N, N, N),
1612 MUX(1, 91, 0, N, N, N, N),
1613 MUX(1, 92, 0, N, N, N, N),
1614 MUX(1, 93, 0, N, N, N, N),
1615 MUX(1, 94, 0, N, N, N, N),
1616 MUX(1, 95, 0, N, N, N, N),
1617 MUX(1, 96, 0, N, N, N, N),
1618 MUX(1, 112, 0, N, N, N, N),
1619 MUX(1, 113, 0, N, N, N, N),
1620 MUX(1, 114, 0, N, N, N, N),
1621 MUX(1, 115, 0, N, N, N, N),
1622 MUX(1, 116, 0, N, N, N, N),
1623 MUX(1, 117, 0, N, N, N, N),
1624 MUX(1, 118, 0, N, N, N, N),
1625 };
1626
1627 static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1628 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1629 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1630 };
1631
1632 static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1633 MUX(1, 97, 0, N, N, N, N),
1634 MUX(1, 98, 0, N, N, N, N),
1635 MUX(1, 99, 0, N, N, N, N),
1636 MUX(1, 100, 0, N, N, N, N),
1637 MUX(1, 101, 0, N, N, N, N),
1638 MUX(1, 102, 0, N, N, N, N),
1639 MUX(1, 103, 0, N, N, N, N),
1640 MUX(1, 104, 0, N, N, N, N),
1641 MUX(1, 105, 0, N, N, N, N),
1642 MUX(1, 106, 0, N, N, N, N),
1643 MUX(1, 107, 0, N, N, N, N),
1644 MUX(1, 108, 0, N, N, N, N),
1645 MUX(1, 109, 0, N, N, N, N),
1646 MUX(1, 110, 0, N, N, N, N),
1647 MUX(1, 111, 0, N, N, N, N),
1648 MUX(1, 18, 0, N, N, N, N),
1649 MUX(1, 19, 0, N, N, N, N),
1650 MUX(1, 20, 0, N, N, N, N),
1651 MUX(1, 21, 0, N, N, N, N),
1652 MUX(1, 141, 0, N, N, N, N),
1653 MUX(1, 142, 0, N, N, N, N),
1654 MUX(1, 143, 0, N, N, N, N),
1655 MUX(1, 144, 0, N, N, N, N),
1656 MUX(1, 145, 0, N, N, N, N),
1657 MUX(1, 146, 0, N, N, N, N),
1658 MUX(1, 147, 0, N, N, N, N),
1659 MUX(1, 148, 0, N, N, N, N),
1660 };
1661
1662 static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1663 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1664 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1665 };
1666
1667 static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1668 MUX(1, 157, 0, N, N, N, N),
1669 MUX(1, 158, 0, N, N, N, N),
1670 MUX(1, 155, 0, N, N, N, N),
1671 MUX(1, 156, 0, N, N, N, N),
1672 MUX(1, 153, 0, N, N, N, N),
1673 MUX(1, 154, 0, N, N, N, N),
1674 MUX(1, 151, 0, N, N, N, N),
1675 MUX(1, 152, 0, N, N, N, N),
1676 MUX(1, 149, 0, N, N, N, N),
1677 MUX(1, 150, 0, N, N, N, N),
1678 };
1679
1680 static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1681 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1682 .pad_mux_list = lvds_gpio_grp_pad_mux,
1683 };
1684
1685 static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1686 MUX(1, 44, 0, N, N, N, N),
1687 MUX(1, 43, 0, N, N, N, N),
1688 MUX(1, 42, 0, N, N, N, N),
1689 MUX(1, 41, 0, N, N, N, N),
1690 MUX(1, 40, 0, N, N, N, N),
1691 MUX(1, 39, 0, N, N, N, N),
1692 MUX(1, 38, 0, N, N, N, N),
1693 MUX(1, 37, 0, N, N, N, N),
1694 MUX(1, 46, 0, N, N, N, N),
1695 MUX(1, 47, 0, N, N, N, N),
1696 MUX(1, 48, 0, N, N, N, N),
1697 MUX(1, 49, 0, N, N, N, N),
1698 MUX(1, 50, 0, N, N, N, N),
1699 MUX(1, 52, 0, N, N, N, N),
1700 MUX(1, 51, 0, N, N, N, N),
1701 MUX(1, 45, 0, N, N, N, N),
1702 MUX(1, 133, 0, N, N, N, N),
1703 MUX(1, 134, 0, N, N, N, N),
1704 MUX(1, 135, 0, N, N, N, N),
1705 MUX(1, 136, 0, N, N, N, N),
1706 MUX(1, 137, 0, N, N, N, N),
1707 MUX(1, 138, 0, N, N, N, N),
1708 MUX(1, 139, 0, N, N, N, N),
1709 MUX(1, 140, 0, N, N, N, N),
1710 MUX(1, 159, 0, N, N, N, N),
1711 MUX(1, 160, 0, N, N, N, N),
1712 MUX(1, 161, 0, N, N, N, N),
1713 MUX(1, 162, 0, N, N, N, N),
1714 MUX(1, 163, 0, N, N, N, N),
1715 };
1716
1717 static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1718 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1719 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1720 };
1721
1722 static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1723 MUX(0, 0, 0, N, N, N, N),
1724 MUX(0, 1, 0, N, N, N, N),
1725 MUX(0, 2, 0, N, N, N, N),
1726 MUX(0, 3, 0, N, N, N, N),
1727 MUX(0, 4, 0, N, N, N, N),
1728 MUX(0, 10, 0, N, N, N, N),
1729 MUX(0, 11, 0, N, N, N, N),
1730 MUX(0, 12, 0, N, N, N, N),
1731 MUX(0, 13, 0, N, N, N, N),
1732 MUX(0, 14, 0, N, N, N, N),
1733 MUX(0, 15, 0, N, N, N, N),
1734 MUX(0, 16, 0, N, N, N, N),
1735 MUX(0, 17, 0, N, N, N, N),
1736 MUX(0, 9, 0, N, N, N, N),
1737 };
1738
1739 static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1740 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1741 .pad_mux_list = rtc_gpio_grp_pad_mux,
1742 };
1743
1744 static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1745 MUX(1, 113, 2, N, N, N, N),
1746 MUX(1, 118, 2, N, N, N, N),
1747 MUX(1, 115, 2, N, N, N, N),
1748 MUX(1, 114, 2, N, N, N, N),
1749 };
1750
1751 static struct atlas7_grp_mux audio_ac97_grp_mux = {
1752 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1753 .pad_mux_list = audio_ac97_grp_pad_mux,
1754 };
1755
1756 static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1757 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1758 };
1759
1760 static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1761 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1762 .pad_mux_list = audio_digmic_grp0_pad_mux,
1763 };
1764
1765 static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1766 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1767 };
1768
1769 static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1770 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1771 .pad_mux_list = audio_digmic_grp1_pad_mux,
1772 };
1773
1774 static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1775 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1776 };
1777
1778 static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1779 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1780 .pad_mux_list = audio_digmic_grp2_pad_mux,
1781 };
1782
1783 static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1784 MUX(1, 141, 4, N, N, N, N),
1785 MUX(1, 144, 4, N, N, N, N),
1786 MUX(1, 44, 6, N, N, N, N),
1787 MUX(1, 43, 6, N, N, N, N),
1788 MUX(1, 42, 6, N, N, N, N),
1789 MUX(1, 41, 6, N, N, N, N),
1790 MUX(1, 40, 6, N, N, N, N),
1791 MUX(1, 39, 6, N, N, N, N),
1792 MUX(1, 38, 6, N, N, N, N),
1793 MUX(1, 37, 6, N, N, N, N),
1794 MUX(1, 74, 6, N, N, N, N),
1795 MUX(1, 75, 6, N, N, N, N),
1796 MUX(1, 76, 6, N, N, N, N),
1797 MUX(1, 77, 6, N, N, N, N),
1798 MUX(1, 78, 6, N, N, N, N),
1799 MUX(1, 79, 6, N, N, N, N),
1800 MUX(1, 81, 6, N, N, N, N),
1801 MUX(1, 113, 6, N, N, N, N),
1802 MUX(1, 114, 6, N, N, N, N),
1803 MUX(1, 118, 6, N, N, N, N),
1804 MUX(1, 115, 6, N, N, N, N),
1805 MUX(1, 49, 6, N, N, N, N),
1806 MUX(1, 50, 6, N, N, N, N),
1807 MUX(1, 142, 4, N, N, N, N),
1808 MUX(1, 143, 4, N, N, N, N),
1809 MUX(1, 80, 6, N, N, N, N),
1810 };
1811
1812 static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1813 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1814 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1815 };
1816
1817 static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1818 MUX(1, 118, 1, N, N, N, N),
1819 MUX(1, 115, 1, N, N, N, N),
1820 MUX(1, 116, 1, N, N, N, N),
1821 MUX(1, 117, 1, N, N, N, N),
1822 MUX(1, 112, 1, N, N, N, N),
1823 MUX(1, 113, 1, N, N, N, N),
1824 MUX(1, 114, 1, N, N, N, N),
1825 };
1826
1827 static struct atlas7_grp_mux audio_i2s_grp_mux = {
1828 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1829 .pad_mux_list = audio_i2s_grp_pad_mux,
1830 };
1831
1832 static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1833 MUX(1, 118, 1, N, N, N, N),
1834 MUX(1, 115, 1, N, N, N, N),
1835 MUX(1, 112, 1, N, N, N, N),
1836 MUX(1, 113, 1, N, N, N, N),
1837 MUX(1, 114, 1, N, N, N, N),
1838 };
1839
1840 static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1841 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1842 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1843 };
1844
1845 static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1846 MUX(1, 112, 2, N, N, N, N),
1847 };
1848
1849 static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1850 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1851 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1852 };
1853
1854 static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1855 MUX(1, 112, 3, N, N, N, N),
1856 };
1857
1858 static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1859 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1860 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1861 };
1862
1863 static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1864 MUX(1, 116, 3, N, N, N, N),
1865 };
1866
1867 static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1868 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1869 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1870 };
1871
1872 static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1873 MUX(1, 142, 3, N, N, N, N),
1874 };
1875
1876 static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1877 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1878 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1879 };
1880
1881 static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1882 MUX(1, 143, 1, N, N, N, N),
1883 MUX(1, 142, 1, N, N, N, N),
1884 MUX(1, 141, 1, N, N, N, N),
1885 MUX(1, 144, 1, N, N, N, N),
1886 };
1887
1888 static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1889 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1890 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1891 };
1892
1893 static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1894 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1895 };
1896
1897 static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1898 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1899 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1900 };
1901
1902 static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1903 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1904 };
1905
1906 static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1907 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1908 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1909 };
1910
1911 static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1912 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1913 };
1914
1915 static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1916 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1917 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1918 };
1919
1920 static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1921 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1922 };
1923
1924 static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1925 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1926 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1927 };
1928
1929 static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1930 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1931 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1932 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1933 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1934 };
1935
1936 static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1937 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1938 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1939 };
1940
1941 static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1942 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1943 };
1944
1945 static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1946 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1947 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1948 };
1949
1950 static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1951 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1952 };
1953
1954 static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1955 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1956 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1957 };
1958
1959 static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1960 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1961 };
1962
1963 static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1964 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1965 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1966 };
1967
1968 static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1969 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1970 };
1971
1972 static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1973 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1974 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1975 };
1976
1977 static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1978 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1979 };
1980
1981 static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1982 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1983 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1984 };
1985
1986 static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1987 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1988 };
1989
1990 static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1991 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1992 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1993 };
1994
1995 static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
1996 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
1997 };
1998
1999 static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2000 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2001 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2002 };
2003
2004 static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2005 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2006 };
2007
2008 static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2009 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2010 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2011 };
2012
2013 static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2014 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2015 };
2016
2017 static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2018 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2019 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2020 };
2021
2022 static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2023 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2024 };
2025
2026 static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2027 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2028 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2029 };
2030
2031 static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2032 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2033 };
2034
2035 static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2036 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2037 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2038 };
2039
2040 static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2041 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2042 };
2043
2044 static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2045 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2046 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2047 };
2048
2049 static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2050 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2051 };
2052
2053 static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2054 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2055 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2056 };
2057
2058 static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2059 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2060 };
2061
2062 static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2063 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2064 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2065 };
2066
2067 static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2068 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2069 };
2070
2071 static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2072 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2073 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2074 };
2075
2076 static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2077 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2078 };
2079
2080 static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2081 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2082 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2083 };
2084
2085 static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2086 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2087 };
2088
2089 static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2090 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2091 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2092 };
2093
2094 static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2095 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2096 };
2097
2098 static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2099 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2100 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2101 };
2102
2103 static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2104 MUX(0, 2, 6, N, N, N, N),
2105 };
2106
2107 static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2108 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2109 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2110 };
2111
2112 static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2113 MUX(0, 0, 2, N, N, N, N),
2114 };
2115
2116 static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2117 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2118 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2119 };
2120
2121 static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2122 MUX(0, 1, 2, N, N, N, N),
2123 };
2124
2125 static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2126 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2127 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2128 };
2129
2130 static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2131 MUX(0, 3, 6, N, N, N, N),
2132 };
2133
2134 static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2135 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2136 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2137 };
2138
2139 static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2140 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2141 };
2142
2143 static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2144 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2145 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2146 };
2147
2148 static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2149 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2150 };
2151
2152 static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2153 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2154 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2155 };
2156
2157 static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2158 MUX(0, 10, 1, N, N, N, N),
2159 };
2160
2161 static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2162 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2163 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2164 };
2165
2166 static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2167 MUX(0, 3, 5, N, N, N, N),
2168 };
2169
2170 static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2171 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2172 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2173 };
2174
2175 static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2176 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2177 };
2178
2179 static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2180 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2181 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2182 };
2183
2184 static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2185 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2186 };
2187
2188 static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2189 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2190 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2191 };
2192
2193 static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2194 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2195 };
2196
2197 static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2198 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2199 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2200 };
2201
2202 static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2203 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2204 };
2205
2206 static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2207 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2208 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2209 };
2210
2211 static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2212 MUX(1, 137, 2, N, N, N, N),
2213 };
2214
2215 static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2216 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2217 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2218 };
2219
2220 static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2221 MUX(1, 146, 2, N, N, N, N),
2222 };
2223
2224 static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2225 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2226 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2227 };
2228
2229 static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2230 MUX(0, 3, 2, N, N, N, N),
2231 };
2232
2233 static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2234 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2235 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2236 };
2237
2238 static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2239 MUX(1, 161, 4, N, N, N, N),
2240 };
2241
2242 static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2243 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2244 .pad_mux_list = c1_can_txd_grp3_pad_mux,
2245 };
2246
2247 static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2248 MUX(1, 62, 4, N, N, N, N),
2249 MUX(1, 63, 4, N, N, N, N),
2250 MUX(1, 64, 4, N, N, N, N),
2251 MUX(1, 65, 4, N, N, N, N),
2252 MUX(1, 66, 4, N, N, N, N),
2253 MUX(1, 67, 4, N, N, N, N),
2254 MUX(1, 68, 4, N, N, N, N),
2255 MUX(1, 69, 4, N, N, N, N),
2256 MUX(1, 70, 4, N, N, N, N),
2257 MUX(1, 71, 4, N, N, N, N),
2258 };
2259
2260 static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2261 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2262 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2263 };
2264
2265 static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2266 MUX(1, 85, 5, N, N, N, N),
2267 MUX(1, 86, 5, N, N, N, N),
2268 MUX(1, 87, 5, N, N, N, N),
2269 MUX(1, 88, 5, N, N, N, N),
2270 MUX(1, 89, 5, N, N, N, N),
2271 MUX(1, 90, 5, N, N, N, N),
2272 };
2273
2274 static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2275 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2276 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2277 };
2278
2279 static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2280 MUX(1, 129, 1, N, N, N, N),
2281 MUX(1, 130, 1, N, N, N, N),
2282 MUX(1, 131, 1, N, N, N, N),
2283 MUX(1, 132, 1, N, N, N, N),
2284 };
2285
2286 static struct atlas7_grp_mux ca_coex_grp_mux = {
2287 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2288 .pad_mux_list = ca_coex_grp_pad_mux,
2289 };
2290
2291 static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2292 MUX(1, 57, 4, N, N, N, N),
2293 MUX(1, 58, 4, N, N, N, N),
2294 MUX(1, 59, 4, N, N, N, N),
2295 MUX(1, 60, 4, N, N, N, N),
2296 };
2297
2298 static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2299 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2300 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2301 };
2302
2303 static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2304 MUX(1, 91, 5, N, N, N, N),
2305 MUX(1, 93, 5, N, N, N, N),
2306 MUX(1, 94, 5, N, N, N, N),
2307 MUX(1, 92, 5, N, N, N, N),
2308 };
2309
2310 static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2311 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2312 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2313 };
2314
2315 static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2316 MUX(1, 121, 2, N, N, N, N),
2317 MUX(1, 122, 2, N, N, N, N),
2318 MUX(1, 125, 6, N, N, N, N),
2319 MUX(1, 126, 6, N, N, N, N),
2320 MUX(1, 38, 5, N, N, N, N),
2321 MUX(1, 37, 5, N, N, N, N),
2322 MUX(1, 47, 5, N, N, N, N),
2323 MUX(1, 49, 5, N, N, N, N),
2324 MUX(1, 50, 5, N, N, N, N),
2325 MUX(1, 54, 4, N, N, N, N),
2326 MUX(1, 55, 4, N, N, N, N),
2327 MUX(1, 56, 4, N, N, N, N),
2328 };
2329
2330 static struct atlas7_grp_mux ca_pio_grp_mux = {
2331 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2332 .pad_mux_list = ca_pio_grp_pad_mux,
2333 };
2334
2335 static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2336 MUX(1, 40, 5, N, N, N, N),
2337 MUX(1, 39, 5, N, N, N, N),
2338 MUX(1, 44, 5, N, N, N, N),
2339 MUX(1, 43, 5, N, N, N, N),
2340 MUX(1, 42, 5, N, N, N, N),
2341 MUX(1, 41, 5, N, N, N, N),
2342 };
2343
2344 static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2345 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2346 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2347 };
2348
2349 static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2350 MUX(1, 82, 5, N, N, N, N),
2351 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2352 MUX(1, 80, 5, N, N, N, N),
2353 MUX(1, 81, 5, N, N, N, N),
2354 };
2355
2356 static struct atlas7_grp_mux ca_spi_grp_mux = {
2357 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2358 .pad_mux_list = ca_spi_grp_pad_mux,
2359 };
2360
2361 static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2362 MUX(1, 91, 4, N, N, N, N),
2363 MUX(1, 93, 4, N, N, N, N),
2364 MUX(1, 94, 4, N, N, N, N),
2365 MUX(1, 95, 4, N, N, N, N),
2366 MUX(1, 96, 4, N, N, N, N),
2367 MUX(1, 78, 5, N, N, N, N),
2368 MUX(1, 74, 5, N, N, N, N),
2369 MUX(1, 75, 5, N, N, N, N),
2370 MUX(1, 76, 5, N, N, N, N),
2371 MUX(1, 77, 5, N, N, N, N),
2372 };
2373
2374 static struct atlas7_grp_mux ca_trb_grp_mux = {
2375 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2376 .pad_mux_list = ca_trb_grp_pad_mux,
2377 };
2378
2379 static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2380 MUX(1, 136, 3, N, N, N, N),
2381 MUX(1, 135, 3, N, N, N, N),
2382 MUX(1, 134, 3, N, N, N, N),
2383 MUX(1, 133, 3, N, N, N, N),
2384 };
2385
2386 static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2387 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2388 .pad_mux_list = ca_uart_debug_grp_pad_mux,
2389 };
2390
2391 static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2392 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2393 MUX(1, 47, 6, N, N, N, N),
2394 };
2395
2396 static struct atlas7_grp_mux clkc_grp0_mux = {
2397 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2398 .pad_mux_list = clkc_grp0_pad_mux,
2399 };
2400
2401 static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2402 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2403 MUX(1, 54, 5, N, N, N, N),
2404 };
2405
2406 static struct atlas7_grp_mux clkc_grp1_mux = {
2407 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2408 .pad_mux_list = clkc_grp1_pad_mux,
2409 };
2410
2411 static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2412 MUX(1, 128, 2, N, N, N, N),
2413 MUX(1, 127, 2, N, N, N, N),
2414 };
2415
2416 static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2417 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2418 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2419 };
2420
2421 static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2422 MUX(1, 134, 4, N, N, N, N),
2423 MUX(1, 133, 4, N, N, N, N),
2424 };
2425
2426 static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2427 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2428 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2429 };
2430
2431 static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2432 MUX(1, 134, 4, N, N, N, N),
2433 MUX(1, 133, 4, N, N, N, N),
2434 MUX(1, 136, 4, N, N, N, N),
2435 MUX(1, 135, 4, N, N, N, N),
2436 };
2437
2438 static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2439 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2440 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2441 };
2442
2443 static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2444 MUX(1, 22, 1, N, N, N, N),
2445 MUX(1, 25, 1, N, N, N, N),
2446 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2447 MUX(1, 24, 1, N, N, N, N),
2448 };
2449
2450 static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2451 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2452 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2453 };
2454
2455 static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2456 MUX(1, 82, 3, N, N, N, N),
2457 MUX(1, 79, 3, N, N, N, N),
2458 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2459 MUX(1, 81, 3, N, N, N, N),
2460 };
2461
2462 static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2463 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2464 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2465 };
2466
2467 static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2468 MUX(1, 54, 3, N, N, N, N),
2469 MUX(1, 53, 3, N, N, N, N),
2470 MUX(1, 82, 7, N, N, N, N),
2471 MUX(1, 74, 7, N, N, N, N),
2472 MUX(1, 75, 7, N, N, N, N),
2473 MUX(1, 76, 7, N, N, N, N),
2474 MUX(1, 77, 7, N, N, N, N),
2475 MUX(1, 78, 7, N, N, N, N),
2476 MUX(1, 79, 7, N, N, N, N),
2477 MUX(1, 80, 7, N, N, N, N),
2478 MUX(1, 81, 7, N, N, N, N),
2479 MUX(1, 83, 7, N, N, N, N),
2480 MUX(1, 84, 7, N, N, N, N),
2481 MUX(1, 73, 3, N, N, N, N),
2482 MUX(1, 55, 3, N, N, N, N),
2483 MUX(1, 56, 3, N, N, N, N),
2484 };
2485
2486 static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2487 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2488 .pad_mux_list = cvbs_dbg_grp_pad_mux,
2489 };
2490
2491 static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2492 MUX(1, 57, 3, N, N, N, N),
2493 };
2494
2495 static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2496 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2497 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2498 };
2499
2500 static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2501 MUX(1, 58, 3, N, N, N, N),
2502 };
2503
2504 static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2505 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2506 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2507 };
2508
2509 static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2510 MUX(1, 59, 3, N, N, N, N),
2511 };
2512
2513 static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2514 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2515 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2516 };
2517
2518 static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2519 MUX(1, 60, 3, N, N, N, N),
2520 };
2521
2522 static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2523 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2524 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2525 };
2526
2527 static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2528 MUX(1, 61, 3, N, N, N, N),
2529 };
2530
2531 static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2532 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2533 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2534 };
2535
2536 static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2537 MUX(1, 62, 3, N, N, N, N),
2538 };
2539
2540 static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2541 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2542 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2543 };
2544
2545 static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2546 MUX(1, 63, 3, N, N, N, N),
2547 };
2548
2549 static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2550 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2551 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2552 };
2553
2554 static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2555 MUX(1, 64, 3, N, N, N, N),
2556 };
2557
2558 static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2559 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2560 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2561 };
2562
2563 static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2564 MUX(1, 65, 3, N, N, N, N),
2565 };
2566
2567 static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2568 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2569 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2570 };
2571
2572 static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2573 MUX(1, 66, 3, N, N, N, N),
2574 };
2575
2576 static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2577 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2578 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2579 };
2580
2581 static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2582 MUX(1, 67, 3, N, N, N, N),
2583 };
2584
2585 static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2586 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2587 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2588 };
2589
2590 static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2591 MUX(1, 68, 3, N, N, N, N),
2592 };
2593
2594 static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2595 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2596 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2597 };
2598
2599 static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2600 MUX(1, 69, 3, N, N, N, N),
2601 };
2602
2603 static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2604 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2605 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2606 };
2607
2608 static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2609 MUX(1, 70, 3, N, N, N, N),
2610 };
2611
2612 static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2613 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2614 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2615 };
2616
2617 static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2618 MUX(1, 71, 3, N, N, N, N),
2619 };
2620
2621 static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2622 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2623 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2624 };
2625
2626 static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2627 MUX(1, 72, 3, N, N, N, N),
2628 };
2629
2630 static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2631 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2632 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2633 };
2634
2635 static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2636 MUX(1, 123, 7, N, N, N, N),
2637 MUX(1, 124, 7, N, N, N, N),
2638 MUX(1, 121, 7, N, N, N, N),
2639 MUX(1, 122, 7, N, N, N, N),
2640 MUX(1, 125, 7, N, N, N, N),
2641 MUX(1, 120, 7, N, N, N, N),
2642 };
2643
2644 static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2645 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2646 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2647 };
2648
2649 static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2650 MUX(1, 57, 7, N, N, N, N),
2651 MUX(1, 58, 7, N, N, N, N),
2652 MUX(1, 59, 7, N, N, N, N),
2653 MUX(1, 60, 7, N, N, N, N),
2654 MUX(1, 61, 7, N, N, N, N),
2655 MUX(1, 62, 7, N, N, N, N),
2656 MUX(1, 63, 7, N, N, N, N),
2657 MUX(1, 64, 7, N, N, N, N),
2658 MUX(1, 65, 7, N, N, N, N),
2659 MUX(1, 66, 7, N, N, N, N),
2660 MUX(1, 67, 7, N, N, N, N),
2661 MUX(1, 68, 7, N, N, N, N),
2662 MUX(1, 69, 7, N, N, N, N),
2663 MUX(1, 70, 7, N, N, N, N),
2664 MUX(1, 71, 7, N, N, N, N),
2665 MUX(1, 72, 7, N, N, N, N),
2666 MUX(1, 53, 7, N, N, N, N),
2667 MUX(1, 55, 7, N, N, N, N),
2668 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2669 MUX(1, 54, 7, N, N, N, N),
2670 };
2671
2672 static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2673 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2674 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2675 };
2676
2677 static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2678 MUX(1, 113, 4, N, N, N, N),
2679 };
2680
2681 static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2682 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2683 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2684 };
2685
2686 static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2687 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2688 };
2689
2690 static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2691 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2692 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2693 };
2694
2695 static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2696 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2697 };
2698
2699 static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2700 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2701 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2702 };
2703
2704 static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2705 MUX(1, 115, 4, N, N, N, N),
2706 };
2707
2708 static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2709 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2710 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2711 };
2712
2713 static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2714 MUX(1, 114, 4, N, N, N, N),
2715 };
2716
2717 static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2718 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2719 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2720 };
2721
2722 static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2723 MUX(1, 44, 7, N, N, N, N),
2724 MUX(1, 43, 7, N, N, N, N),
2725 MUX(1, 42, 7, N, N, N, N),
2726 MUX(1, 41, 7, N, N, N, N),
2727 MUX(1, 40, 7, N, N, N, N),
2728 MUX(1, 39, 7, N, N, N, N),
2729 MUX(1, 38, 7, N, N, N, N),
2730 MUX(1, 37, 7, N, N, N, N),
2731 MUX(1, 49, 7, N, N, N, N),
2732 MUX(1, 50, 7, N, N, N, N),
2733 MUX(1, 91, 7, N, N, N, N),
2734 MUX(1, 92, 7, N, N, N, N),
2735 MUX(1, 93, 7, N, N, N, N),
2736 MUX(1, 94, 7, N, N, N, N),
2737 MUX(1, 95, 7, N, N, N, N),
2738 MUX(1, 96, 7, N, N, N, N),
2739 };
2740
2741 static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2742 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2743 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2744 };
2745
2746 static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2747 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2748 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2749 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2750 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2751 };
2752
2753 static struct atlas7_grp_mux gn_trg_grp0_mux = {
2754 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2755 .pad_mux_list = gn_trg_grp0_pad_mux,
2756 };
2757
2758 static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2759 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2760 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2761 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2762 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2763 };
2764
2765 static struct atlas7_grp_mux gn_trg_grp1_mux = {
2766 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2767 .pad_mux_list = gn_trg_grp1_pad_mux,
2768 };
2769
2770 static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2771 MUX(1, 30, 1, N, N, N, N),
2772 };
2773
2774 static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2775 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2776 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2777 };
2778
2779 static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2780 MUX(1, 83, 3, N, N, N, N),
2781 };
2782
2783 static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2784 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2785 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2786 };
2787
2788 static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2789 MUX(1, 117, 4, N, N, N, N),
2790 };
2791
2792 static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2793 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2794 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2795 };
2796
2797 static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2798 MUX(1, 123, 5, N, N, N, N),
2799 };
2800
2801 static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2802 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2803 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2804 };
2805
2806 static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2807 MUX(1, 128, 1, N, N, N, N),
2808 MUX(1, 127, 1, N, N, N, N),
2809 };
2810
2811 static struct atlas7_grp_mux i2c0_grp_mux = {
2812 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2813 .pad_mux_list = i2c0_grp_pad_mux,
2814 };
2815
2816 static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2817 MUX(1, 126, 4, N, N, N, N),
2818 MUX(1, 125, 4, N, N, N, N),
2819 };
2820
2821 static struct atlas7_grp_mux i2c1_grp_mux = {
2822 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2823 .pad_mux_list = i2c1_grp_pad_mux,
2824 };
2825
2826 static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2827 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2828 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2829 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2830 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2831 };
2832
2833 static struct atlas7_grp_mux i2s0_grp_mux = {
2834 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2835 .pad_mux_list = i2s0_grp_pad_mux,
2836 };
2837
2838 static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2839 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2840 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2841 };
2842
2843 static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2844 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2845 .pad_mux_list = i2s1_basic_grp_pad_mux,
2846 };
2847
2848 static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2849 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2850 };
2851
2852 static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2853 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2854 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2855 };
2856
2857 static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2858 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2859 };
2860
2861 static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2862 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2863 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2864 };
2865
2866 static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2867 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2868 };
2869
2870 static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2871 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2872 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2873 };
2874
2875 static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2876 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2877 };
2878
2879 static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2880 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2881 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2882 };
2883
2884 static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2885 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2886 };
2887
2888 static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2889 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2890 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2891 };
2892
2893 static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2894 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2895 };
2896
2897 static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2898 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2899 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2900 };
2901
2902 static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2903 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2904 };
2905
2906 static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2907 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2908 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2909 };
2910
2911 static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2912 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2913 };
2914
2915 static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2916 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2917 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2918 };
2919
2920 static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2921 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2922 };
2923
2924 static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2925 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2926 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2927 };
2928
2929 static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2930 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2931 };
2932
2933 static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2934 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2935 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2936 };
2937
2938 static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2939 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2940 };
2941
2942 static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2943 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2944 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2945 };
2946
2947 static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2948 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2949 };
2950
2951 static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2952 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2953 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2954 };
2955
2956 static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2957 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2958 };
2959
2960 static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2961 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2962 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2963 };
2964
2965 static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2966 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2967 };
2968
2969 static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2970 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2971 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2972 };
2973
2974 static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2975 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2976 };
2977
2978 static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2979 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2980 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2981 };
2982
2983 static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2984 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2985 };
2986
2987 static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2988 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2989 .pad_mux_list = jtag_tck_grp0_pad_mux,
2990 };
2991
2992 static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2993 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
2994 };
2995
2996 static struct atlas7_grp_mux jtag_tck_grp1_mux = {
2997 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
2998 .pad_mux_list = jtag_tck_grp1_pad_mux,
2999 };
3000
3001 static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3002 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3003 };
3004
3005 static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3006 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3007 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3008 };
3009
3010 static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3011 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3012 };
3013
3014 static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3015 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3016 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3017 };
3018
3019 static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3020 MUX(0, 3, 3, N, N, N, N),
3021 };
3022
3023 static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3024 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3025 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3026 };
3027
3028 static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3029 MUX(1, 159, 1, N, N, N, N),
3030 };
3031
3032 static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3033 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3034 .pad_mux_list = jtag_tdo_grp1_pad_mux,
3035 };
3036
3037 static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3038 MUX(1, 141, 2, N, N, N, N),
3039 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3040 MUX(1, 143, 2, N, N, N, N),
3041 MUX(1, 142, 2, N, N, N, N),
3042 };
3043
3044 static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3045 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3046 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3047 };
3048
3049 static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3050 MUX(1, 57, 1, N, N, N, N),
3051 MUX(1, 58, 1, N, N, N, N),
3052 MUX(1, 59, 1, N, N, N, N),
3053 MUX(1, 60, 1, N, N, N, N),
3054 MUX(1, 61, 1, N, N, N, N),
3055 MUX(1, 62, 1, N, N, N, N),
3056 MUX(1, 63, 1, N, N, N, N),
3057 MUX(1, 64, 1, N, N, N, N),
3058 MUX(1, 65, 1, N, N, N, N),
3059 MUX(1, 66, 1, N, N, N, N),
3060 MUX(1, 67, 1, N, N, N, N),
3061 MUX(1, 68, 1, N, N, N, N),
3062 MUX(1, 69, 1, N, N, N, N),
3063 MUX(1, 70, 1, N, N, N, N),
3064 MUX(1, 71, 1, N, N, N, N),
3065 MUX(1, 72, 1, N, N, N, N),
3066 MUX(1, 74, 2, N, N, N, N),
3067 MUX(1, 75, 2, N, N, N, N),
3068 MUX(1, 76, 2, N, N, N, N),
3069 MUX(1, 77, 2, N, N, N, N),
3070 MUX(1, 78, 2, N, N, N, N),
3071 MUX(1, 79, 2, N, N, N, N),
3072 MUX(1, 80, 2, N, N, N, N),
3073 MUX(1, 81, 2, N, N, N, N),
3074 MUX(1, 56, 1, N, N, N, N),
3075 MUX(1, 53, 1, N, N, N, N),
3076 };
3077
3078 static struct atlas7_grp_mux ld_ldd_grp_mux = {
3079 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3080 .pad_mux_list = ld_ldd_grp_pad_mux,
3081 };
3082
3083 static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3084 MUX(1, 57, 1, N, N, N, N),
3085 MUX(1, 58, 1, N, N, N, N),
3086 MUX(1, 59, 1, N, N, N, N),
3087 MUX(1, 60, 1, N, N, N, N),
3088 MUX(1, 61, 1, N, N, N, N),
3089 MUX(1, 62, 1, N, N, N, N),
3090 MUX(1, 63, 1, N, N, N, N),
3091 MUX(1, 64, 1, N, N, N, N),
3092 MUX(1, 65, 1, N, N, N, N),
3093 MUX(1, 66, 1, N, N, N, N),
3094 MUX(1, 67, 1, N, N, N, N),
3095 MUX(1, 68, 1, N, N, N, N),
3096 MUX(1, 69, 1, N, N, N, N),
3097 MUX(1, 70, 1, N, N, N, N),
3098 MUX(1, 71, 1, N, N, N, N),
3099 MUX(1, 72, 1, N, N, N, N),
3100 MUX(1, 56, 1, N, N, N, N),
3101 MUX(1, 53, 1, N, N, N, N),
3102 };
3103
3104 static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3105 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3106 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3107 };
3108
3109 static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3110 MUX(1, 55, 1, N, N, N, N),
3111 };
3112
3113 static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3114 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3115 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3116 };
3117
3118 static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3119 MUX(1, 54, 1, N, N, N, N),
3120 };
3121
3122 static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3123 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3124 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3125 };
3126
3127 static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3128 MUX(1, 73, 2, N, N, N, N),
3129 MUX(1, 54, 2, N, N, N, N),
3130 MUX(1, 57, 2, N, N, N, N),
3131 MUX(1, 58, 2, N, N, N, N),
3132 MUX(1, 59, 2, N, N, N, N),
3133 MUX(1, 60, 2, N, N, N, N),
3134 MUX(1, 61, 2, N, N, N, N),
3135 MUX(1, 62, 2, N, N, N, N),
3136 MUX(1, 63, 2, N, N, N, N),
3137 MUX(1, 64, 2, N, N, N, N),
3138 MUX(1, 65, 2, N, N, N, N),
3139 MUX(1, 66, 2, N, N, N, N),
3140 MUX(1, 67, 2, N, N, N, N),
3141 MUX(1, 68, 2, N, N, N, N),
3142 MUX(1, 69, 2, N, N, N, N),
3143 MUX(1, 70, 2, N, N, N, N),
3144 MUX(1, 71, 2, N, N, N, N),
3145 MUX(1, 72, 2, N, N, N, N),
3146 MUX(1, 56, 2, N, N, N, N),
3147 MUX(1, 53, 2, N, N, N, N),
3148 MUX(1, 55, 2, N, N, N, N),
3149 };
3150
3151 static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3152 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3153 .pad_mux_list = lr_lcdrom_grp_pad_mux,
3154 };
3155
3156 static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3157 MUX(1, 149, 8, N, N, N, N),
3158 MUX(1, 150, 8, N, N, N, N),
3159 MUX(1, 151, 8, N, N, N, N),
3160 MUX(1, 152, 8, N, N, N, N),
3161 MUX(1, 153, 8, N, N, N, N),
3162 MUX(1, 154, 8, N, N, N, N),
3163 MUX(1, 155, 8, N, N, N, N),
3164 MUX(1, 156, 8, N, N, N, N),
3165 MUX(1, 157, 8, N, N, N, N),
3166 MUX(1, 158, 8, N, N, N, N),
3167 };
3168
3169 static struct atlas7_grp_mux lvds_analog_grp_mux = {
3170 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3171 .pad_mux_list = lvds_analog_grp_pad_mux,
3172 };
3173
3174 static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
3175 MUX(1, 44, 1, N, N, N, N),
3176 MUX(1, 43, 1, N, N, N, N),
3177 MUX(1, 42, 1, N, N, N, N),
3178 MUX(1, 41, 1, N, N, N, N),
3179 MUX(1, 40, 1, N, N, N, N),
3180 MUX(1, 39, 1, N, N, N, N),
3181 MUX(1, 38, 1, N, N, N, N),
3182 MUX(1, 37, 1, N, N, N, N),
3183 MUX(1, 47, 1, N, N, N, N),
3184 MUX(1, 46, 1, N, N, N, N),
3185 MUX(1, 52, 1, N, N, N, N),
3186 MUX(1, 45, 1, N, N, N, N),
3187 MUX(1, 49, 1, N, N, N, N),
3188 MUX(1, 50, 1, N, N, N, N),
3189 MUX(1, 48, 1, N, N, N, N),
3190 };
3191
3192 static struct atlas7_grp_mux nd_df_basic_grp_mux = {
3193 .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
3194 .pad_mux_list = nd_df_basic_grp_pad_mux,
3195 };
3196
3197 static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
3198 MUX(1, 124, 4, N, N, N, N),
3199 };
3200
3201 static struct atlas7_grp_mux nd_df_wp_grp_mux = {
3202 .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
3203 .pad_mux_list = nd_df_wp_grp_pad_mux,
3204 };
3205
3206 static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
3207 MUX(1, 51, 1, N, N, N, N),
3208 };
3209
3210 static struct atlas7_grp_mux nd_df_cs_grp_mux = {
3211 .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
3212 .pad_mux_list = nd_df_cs_grp_pad_mux,
3213 };
3214
3215 static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3216 MUX(1, 120, 2, N, N, N, N),
3217 MUX(1, 119, 2, N, N, N, N),
3218 MUX(1, 121, 5, N, N, N, N),
3219 };
3220
3221 static struct atlas7_grp_mux ps_grp_mux = {
3222 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3223 .pad_mux_list = ps_grp_pad_mux,
3224 };
3225
3226 static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
3227 MUX(1, 119, 2, N, N, N, N),
3228 };
3229
3230 static struct atlas7_grp_mux ps_no_dir_grp_mux = {
3231 .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
3232 .pad_mux_list = ps_no_dir_grp_pad_mux,
3233 };
3234
3235 static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3236 MUX(0, 8, 1, N, N, N, N),
3237 };
3238
3239 static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3240 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3241 .pad_mux_list = pwc_core_on_grp_pad_mux,
3242 };
3243
3244 static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3245 MUX(0, 6, 1, N, N, N, N),
3246 };
3247
3248 static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3249 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3250 .pad_mux_list = pwc_ext_on_grp_pad_mux,
3251 };
3252
3253 static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3254 MUX(0, 3, 4, N, N, N, N),
3255 };
3256
3257 static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3258 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3259 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3260 };
3261
3262 static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3263 MUX(0, 9, 1, N, N, N, N),
3264 };
3265
3266 static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3267 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3268 .pad_mux_list = pwc_io_on_grp_pad_mux,
3269 };
3270
3271 static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3272 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3273 };
3274
3275 static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3276 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3277 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3278 };
3279
3280 static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3281 MUX(0, 7, 1, N, N, N, N),
3282 };
3283
3284 static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3285 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3286 .pad_mux_list = pwc_mem_on_grp_pad_mux,
3287 };
3288
3289 static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3290 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3291 };
3292
3293 static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3294 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3295 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3296 };
3297
3298 static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3299 MUX(0, 0, 1, N, N, N, N),
3300 };
3301
3302 static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3303 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3304 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3305 };
3306
3307 static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3308 MUX(0, 1, 1, N, N, N, N),
3309 };
3310
3311 static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3312 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3313 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3314 };
3315
3316 static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3317 MUX(0, 2, 1, N, N, N, N),
3318 };
3319
3320 static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3321 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3322 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3323 };
3324
3325 static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3326 MUX(0, 3, 1, N, N, N, N),
3327 };
3328
3329 static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3330 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3331 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3332 };
3333
3334 static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3335 MUX(1, 123, 3, N, N, N, N),
3336 };
3337
3338 static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3339 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3340 .pad_mux_list = pw_cko0_grp0_pad_mux,
3341 };
3342
3343 static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3344 MUX(1, 101, 4, N, N, N, N),
3345 };
3346
3347 static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3348 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3349 .pad_mux_list = pw_cko0_grp1_pad_mux,
3350 };
3351
3352 static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3353 MUX(1, 82, 2, N, N, N, N),
3354 };
3355
3356 static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3357 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3358 .pad_mux_list = pw_cko0_grp2_pad_mux,
3359 };
3360
3361 static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3362 MUX(1, 162, 5, N, N, N, N),
3363 };
3364
3365 static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3366 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3367 .pad_mux_list = pw_cko0_grp3_pad_mux,
3368 };
3369
3370 static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3371 MUX(1, 124, 3, N, N, N, N),
3372 };
3373
3374 static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3375 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3376 .pad_mux_list = pw_cko1_grp0_pad_mux,
3377 };
3378
3379 static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3380 MUX(1, 110, 4, N, N, N, N),
3381 };
3382
3383 static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3384 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3385 .pad_mux_list = pw_cko1_grp1_pad_mux,
3386 };
3387
3388 static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3389 MUX(1, 163, 5, N, N, N, N),
3390 };
3391
3392 static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3393 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3394 .pad_mux_list = pw_cko1_grp2_pad_mux,
3395 };
3396
3397 static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3398 MUX(1, 125, 3, N, N, N, N),
3399 };
3400
3401 static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3402 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3403 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3404 };
3405
3406 static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3407 MUX(1, 117, 3, N, N, N, N),
3408 };
3409
3410 static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3411 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3412 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3413 };
3414
3415 static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3416 MUX(1, 132, 2, N, N, N, N),
3417 };
3418
3419 static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3420 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3421 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3422 };
3423
3424 static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3425 MUX(1, 119, 3, N, N, N, N),
3426 };
3427
3428 static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3429 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3430 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3431 };
3432
3433 static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3434 MUX(1, 159, 5, N, N, N, N),
3435 };
3436
3437 static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3438 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3439 .pad_mux_list = pw_pwm0_grp1_pad_mux,
3440 };
3441
3442 static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3443 MUX(1, 120, 3, N, N, N, N),
3444 };
3445
3446 static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3447 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3448 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3449 };
3450
3451 static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3452 MUX(1, 160, 5, N, N, N, N),
3453 };
3454
3455 static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3456 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3457 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3458 };
3459
3460 static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3461 MUX(1, 131, 2, N, N, N, N),
3462 };
3463
3464 static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3465 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3466 .pad_mux_list = pw_pwm1_grp2_pad_mux,
3467 };
3468
3469 static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3470 MUX(1, 121, 3, N, N, N, N),
3471 };
3472
3473 static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3474 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3475 .pad_mux_list = pw_pwm2_grp0_pad_mux,
3476 };
3477
3478 static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3479 MUX(1, 98, 3, N, N, N, N),
3480 };
3481
3482 static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3483 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3484 .pad_mux_list = pw_pwm2_grp1_pad_mux,
3485 };
3486
3487 static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3488 MUX(1, 161, 5, N, N, N, N),
3489 };
3490
3491 static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3492 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3493 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3494 };
3495
3496 static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3497 MUX(1, 122, 3, N, N, N, N),
3498 };
3499
3500 static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3501 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3502 .pad_mux_list = pw_pwm3_grp0_pad_mux,
3503 };
3504
3505 static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3506 MUX(1, 73, 4, N, N, N, N),
3507 };
3508
3509 static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3510 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3511 .pad_mux_list = pw_pwm3_grp1_pad_mux,
3512 };
3513
3514 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3515 MUX(1, 121, 3, N, N, N, N),
3516 };
3517
3518 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3519 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3520 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3521 };
3522
3523 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3524 MUX(1, 98, 3, N, N, N, N),
3525 };
3526
3527 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3528 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3529 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3530 };
3531
3532 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3533 MUX(1, 161, 5, N, N, N, N),
3534 };
3535
3536 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3537 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3538 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3539 };
3540
3541 static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3542 MUX(1, 122, 3, N, N, N, N),
3543 };
3544
3545 static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3546 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3547 .pad_mux_list = pw_backlight_grp0_pad_mux,
3548 };
3549
3550 static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3551 MUX(1, 73, 4, N, N, N, N),
3552 };
3553
3554 static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3555 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3556 .pad_mux_list = pw_backlight_grp1_pad_mux,
3557 };
3558
3559 static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3560 MUX(1, 108, 1, N, N, N, N),
3561 MUX(1, 103, 1, N, N, N, N),
3562 MUX(1, 104, 1, N, N, N, N),
3563 MUX(1, 105, 1, N, N, N, N),
3564 MUX(1, 106, 1, N, N, N, N),
3565 MUX(1, 107, 1, N, N, N, N),
3566 MUX(1, 102, 1, N, N, N, N),
3567 MUX(1, 97, 1, N, N, N, N),
3568 MUX(1, 98, 1, N, N, N, N),
3569 MUX(1, 99, 1, N, N, N, N),
3570 MUX(1, 100, 1, N, N, N, N),
3571 MUX(1, 101, 1, N, N, N, N),
3572 };
3573
3574 static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3575 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3576 .pad_mux_list = rg_eth_mac_grp_pad_mux,
3577 };
3578
3579 static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3580 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3581 };
3582
3583 static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3584 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3585 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3586 };
3587
3588 static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3589 MUX(1, 109, 1, N, N, N, N),
3590 MUX(1, 110, 1, N, N, N, N),
3591 };
3592
3593 static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3594 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3595 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3596 };
3597
3598 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3599 MUX(1, 111, 5, N, N, N, N),
3600 };
3601
3602 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3603 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3604 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3605 };
3606
3607 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3608 MUX(1, 53, 4, N, N, N, N),
3609 };
3610
3611 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3612 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3613 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3614 };
3615
3616 static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3617 MUX(1, 46, 2, N, N, N, N),
3618 MUX(1, 47, 2, N, N, N, N),
3619 MUX(1, 44, 2, N, N, N, N),
3620 MUX(1, 43, 2, N, N, N, N),
3621 MUX(1, 42, 2, N, N, N, N),
3622 MUX(1, 41, 2, N, N, N, N),
3623 MUX(1, 40, 2, N, N, N, N),
3624 MUX(1, 39, 2, N, N, N, N),
3625 MUX(1, 38, 2, N, N, N, N),
3626 MUX(1, 37, 2, N, N, N, N),
3627 };
3628
3629 static struct atlas7_grp_mux sd0_grp_mux = {
3630 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3631 .pad_mux_list = sd0_grp_pad_mux,
3632 };
3633
3634 static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3635 MUX(1, 46, 2, N, N, N, N),
3636 MUX(1, 47, 2, N, N, N, N),
3637 MUX(1, 44, 2, N, N, N, N),
3638 MUX(1, 43, 2, N, N, N, N),
3639 MUX(1, 42, 2, N, N, N, N),
3640 MUX(1, 41, 2, N, N, N, N),
3641 };
3642
3643 static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3644 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3645 .pad_mux_list = sd0_4bit_grp_pad_mux,
3646 };
3647
3648 static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3649 MUX(1, 48, 3, N, N, N, N),
3650 MUX(1, 49, 3, N, N, N, N),
3651 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3652 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3653 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3654 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3655 MUX(1, 40, 3, N, N, N, N),
3656 MUX(1, 39, 3, N, N, N, N),
3657 MUX(1, 38, 3, N, N, N, N),
3658 MUX(1, 37, 3, N, N, N, N),
3659 };
3660
3661 static struct atlas7_grp_mux sd1_grp_mux = {
3662 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3663 .pad_mux_list = sd1_grp_pad_mux,
3664 };
3665
3666 static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3667 MUX(1, 48, 3, N, N, N, N),
3668 MUX(1, 49, 3, N, N, N, N),
3669 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3670 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3671 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3672 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3673 };
3674
3675 static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3676 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3677 .pad_mux_list = sd1_4bit_grp0_pad_mux,
3678 };
3679
3680 static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3681 MUX(1, 48, 3, N, N, N, N),
3682 MUX(1, 49, 3, N, N, N, N),
3683 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3684 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3685 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3686 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3687 };
3688
3689 static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3690 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3691 .pad_mux_list = sd1_4bit_grp1_pad_mux,
3692 };
3693
3694 static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3695 MUX(1, 31, 1, N, N, N, N),
3696 MUX(1, 32, 1, N, N, N, N),
3697 MUX(1, 33, 1, N, N, N, N),
3698 MUX(1, 34, 1, N, N, N, N),
3699 MUX(1, 35, 1, N, N, N, N),
3700 MUX(1, 36, 1, N, N, N, N),
3701 };
3702
3703 static struct atlas7_grp_mux sd2_basic_grp_mux = {
3704 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3705 .pad_mux_list = sd2_basic_grp_pad_mux,
3706 };
3707
3708 static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3709 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3710 };
3711
3712 static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3713 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3714 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3715 };
3716
3717 static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3718 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3719 };
3720
3721 static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3722 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3723 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3724 };
3725
3726 static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3727 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3728 };
3729
3730 static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3731 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3732 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3733 };
3734
3735 static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3736 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3737 };
3738
3739 static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3740 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3741 .pad_mux_list = sd2_wpb_grp1_pad_mux,
3742 };
3743
3744 static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
3745 MUX(1, 85, 1, N, N, N, N),
3746 MUX(1, 86, 1, N, N, N, N),
3747 MUX(1, 87, 1, N, N, N, N),
3748 MUX(1, 88, 1, N, N, N, N),
3749 MUX(1, 89, 1, N, N, N, N),
3750 MUX(1, 90, 1, N, N, N, N),
3751 };
3752
3753 static struct atlas7_grp_mux sd3_9_grp_mux = {
3754 .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
3755 .pad_mux_list = sd3_9_grp_pad_mux,
3756 };
3757
3758 static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3759 MUX(1, 91, 1, N, N, N, N),
3760 MUX(1, 92, 1, N, N, N, N),
3761 MUX(1, 93, 1, N, N, N, N),
3762 MUX(1, 94, 1, N, N, N, N),
3763 MUX(1, 95, 1, N, N, N, N),
3764 MUX(1, 96, 1, N, N, N, N),
3765 };
3766
3767 static struct atlas7_grp_mux sd5_grp_mux = {
3768 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3769 .pad_mux_list = sd5_grp_pad_mux,
3770 };
3771
3772 static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3773 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3774 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3775 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3776 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3777 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3778 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3779 };
3780
3781 static struct atlas7_grp_mux sd6_grp0_mux = {
3782 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3783 .pad_mux_list = sd6_grp0_pad_mux,
3784 };
3785
3786 static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3787 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3788 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3789 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3790 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3791 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3792 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3793 };
3794
3795 static struct atlas7_grp_mux sd6_grp1_mux = {
3796 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3797 .pad_mux_list = sd6_grp1_pad_mux,
3798 };
3799
3800 static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3801 MUX(0, 4, 2, N, N, N, N),
3802 };
3803
3804 static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3805 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3806 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3807 };
3808
3809 static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3810 MUX(0, 12, 1, N, N, N, N),
3811 MUX(0, 13, 1, N, N, N, N),
3812 MUX(0, 14, 1, N, N, N, N),
3813 MUX(0, 15, 1, N, N, N, N),
3814 MUX(0, 16, 1, N, N, N, N),
3815 MUX(0, 17, 1, N, N, N, N),
3816 };
3817
3818 static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3819 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3820 .pad_mux_list = sp0_qspi_grp_pad_mux,
3821 };
3822
3823 static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3824 MUX(1, 19, 1, N, N, N, N),
3825 MUX(1, 20, 1, N, N, N, N),
3826 MUX(1, 21, 1, N, N, N, N),
3827 MUX(1, 18, 1, N, N, N, N),
3828 };
3829
3830 static struct atlas7_grp_mux sp1_spi_grp_mux = {
3831 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3832 .pad_mux_list = sp1_spi_grp_pad_mux,
3833 };
3834
3835 static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3836 MUX(1, 53, 5, N, N, N, N),
3837 MUX(1, 56, 5, N, N, N, N),
3838 MUX(1, 57, 5, N, N, N, N),
3839 MUX(1, 58, 5, N, N, N, N),
3840 MUX(1, 59, 5, N, N, N, N),
3841 MUX(1, 60, 5, N, N, N, N),
3842 MUX(1, 61, 5, N, N, N, N),
3843 MUX(1, 62, 5, N, N, N, N),
3844 MUX(1, 63, 5, N, N, N, N),
3845 MUX(1, 64, 5, N, N, N, N),
3846 MUX(1, 65, 5, N, N, N, N),
3847 MUX(1, 66, 5, N, N, N, N),
3848 MUX(1, 67, 5, N, N, N, N),
3849 MUX(1, 68, 5, N, N, N, N),
3850 MUX(1, 69, 5, N, N, N, N),
3851 MUX(1, 70, 5, N, N, N, N),
3852 MUX(1, 71, 5, N, N, N, N),
3853 MUX(1, 72, 5, N, N, N, N),
3854 };
3855
3856 static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3857 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3858 .pad_mux_list = tpiu_trace_grp_pad_mux,
3859 };
3860
3861 static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3862 MUX(1, 121, 4, N, N, N, N),
3863 MUX(1, 120, 4, N, N, N, N),
3864 MUX(1, 134, 1, N, N, N, N),
3865 MUX(1, 133, 1, N, N, N, N),
3866 };
3867
3868 static struct atlas7_grp_mux uart0_grp_mux = {
3869 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3870 .pad_mux_list = uart0_grp_pad_mux,
3871 };
3872
3873 static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3874 MUX(1, 134, 1, N, N, N, N),
3875 MUX(1, 133, 1, N, N, N, N),
3876 };
3877
3878 static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3879 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3880 .pad_mux_list = uart0_nopause_grp_pad_mux,
3881 };
3882
3883 static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3884 MUX(1, 136, 1, N, N, N, N),
3885 MUX(1, 135, 1, N, N, N, N),
3886 };
3887
3888 static struct atlas7_grp_mux uart1_grp_mux = {
3889 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3890 .pad_mux_list = uart1_grp_pad_mux,
3891 };
3892
3893 static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3894 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3895 };
3896
3897 static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3898 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3899 .pad_mux_list = uart2_cts_grp0_pad_mux,
3900 };
3901
3902 static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3903 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3904 };
3905
3906 static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3907 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3908 .pad_mux_list = uart2_cts_grp1_pad_mux,
3909 };
3910
3911 static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3912 MUX(1, 131, 3, N, N, N, N),
3913 };
3914
3915 static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3916 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3917 .pad_mux_list = uart2_rts_grp0_pad_mux,
3918 };
3919
3920 static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3921 MUX(1, 161, 2, N, N, N, N),
3922 };
3923
3924 static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3925 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3926 .pad_mux_list = uart2_rts_grp1_pad_mux,
3927 };
3928
3929 static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3930 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3931 };
3932
3933 static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3934 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3935 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3936 };
3937
3938 static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3939 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3940 };
3941
3942 static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3943 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3944 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3945 };
3946
3947 static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3948 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3949 };
3950
3951 static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3952 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3953 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3954 };
3955
3956 static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3957 MUX(0, 10, 2, N, N, N, N),
3958 };
3959
3960 static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3961 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3962 .pad_mux_list = uart2_txd_grp0_pad_mux,
3963 };
3964
3965 static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3966 MUX(1, 159, 2, N, N, N, N),
3967 };
3968
3969 static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3970 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3971 .pad_mux_list = uart2_txd_grp1_pad_mux,
3972 };
3973
3974 static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3975 MUX(1, 129, 3, N, N, N, N),
3976 };
3977
3978 static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3979 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3980 .pad_mux_list = uart2_txd_grp2_pad_mux,
3981 };
3982
3983 static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3984 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3985 };
3986
3987 static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3988 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3989 .pad_mux_list = uart3_cts_grp0_pad_mux,
3990 };
3991
3992 static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3993 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3994 };
3995
3996 static struct atlas7_grp_mux uart3_cts_grp1_mux = {
3997 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
3998 .pad_mux_list = uart3_cts_grp1_pad_mux,
3999 };
4000
4001 static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4002 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4003 };
4004
4005 static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4006 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4007 .pad_mux_list = uart3_cts_grp2_pad_mux,
4008 };
4009
4010 static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4011 MUX(1, 126, 2, N, N, N, N),
4012 };
4013
4014 static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4015 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4016 .pad_mux_list = uart3_rts_grp0_pad_mux,
4017 };
4018
4019 static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4020 MUX(1, 109, 4, N, N, N, N),
4021 };
4022
4023 static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4024 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4025 .pad_mux_list = uart3_rts_grp1_pad_mux,
4026 };
4027
4028 static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4029 MUX(1, 139, 2, N, N, N, N),
4030 };
4031
4032 static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4033 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4034 .pad_mux_list = uart3_rts_grp2_pad_mux,
4035 };
4036
4037 static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4038 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4039 };
4040
4041 static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4042 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4043 .pad_mux_list = uart3_rxd_grp0_pad_mux,
4044 };
4045
4046 static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4047 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4048 };
4049
4050 static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4051 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4052 .pad_mux_list = uart3_rxd_grp1_pad_mux,
4053 };
4054
4055 static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4056 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4057 };
4058
4059 static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4060 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4061 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4062 };
4063
4064 static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4065 MUX(1, 137, 1, N, N, N, N),
4066 };
4067
4068 static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4069 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4070 .pad_mux_list = uart3_txd_grp0_pad_mux,
4071 };
4072
4073 static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4074 MUX(1, 83, 2, N, N, N, N),
4075 };
4076
4077 static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4078 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4079 .pad_mux_list = uart3_txd_grp1_pad_mux,
4080 };
4081
4082 static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4083 MUX(1, 161, 3, N, N, N, N),
4084 };
4085
4086 static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4087 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4088 .pad_mux_list = uart3_txd_grp2_pad_mux,
4089 };
4090
4091 static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4092 MUX(1, 140, 1, N, N, N, N),
4093 MUX(1, 139, 1, N, N, N, N),
4094 };
4095
4096 static struct atlas7_grp_mux uart4_basic_grp_mux = {
4097 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4098 .pad_mux_list = uart4_basic_grp_pad_mux,
4099 };
4100
4101 static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4102 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4103 };
4104
4105 static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4106 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4107 .pad_mux_list = uart4_cts_grp0_pad_mux,
4108 };
4109
4110 static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4111 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4112 };
4113
4114 static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4115 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4116 .pad_mux_list = uart4_cts_grp1_pad_mux,
4117 };
4118
4119 static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4120 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4121 };
4122
4123 static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4124 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4125 .pad_mux_list = uart4_cts_grp2_pad_mux,
4126 };
4127
4128 static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4129 MUX(1, 123, 4, N, N, N, N),
4130 };
4131
4132 static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4133 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4134 .pad_mux_list = uart4_rts_grp0_pad_mux,
4135 };
4136
4137 static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4138 MUX(1, 99, 4, N, N, N, N),
4139 };
4140
4141 static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4142 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4143 .pad_mux_list = uart4_rts_grp1_pad_mux,
4144 };
4145
4146 static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4147 MUX(1, 116, 2, N, N, N, N),
4148 };
4149
4150 static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4151 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4152 .pad_mux_list = uart4_rts_grp2_pad_mux,
4153 };
4154
4155 static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4156 MUX(1, 51, 2, N, N, N, N),
4157 };
4158
4159 static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4160 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4161 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4162 };
4163
4164 static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4165 MUX(1, 162, 7, N, N, N, N),
4166 };
4167
4168 static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4169 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4170 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4171 };
4172
4173 static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4174 MUX(1, 134, 2, N, N, N, N),
4175 };
4176
4177 static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4178 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4179 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4180 };
4181
4182 static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4183 MUX(1, 163, 2, N, N, N, N),
4184 };
4185
4186 static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4187 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4188 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4189 };
4190
4191 static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4192 MUX(1, 57, 6, N, N, N, N),
4193 MUX(1, 58, 6, N, N, N, N),
4194 MUX(1, 59, 6, N, N, N, N),
4195 MUX(1, 60, 6, N, N, N, N),
4196 MUX(1, 61, 6, N, N, N, N),
4197 MUX(1, 62, 6, N, N, N, N),
4198 MUX(1, 63, 6, N, N, N, N),
4199 MUX(1, 64, 6, N, N, N, N),
4200 MUX(1, 65, 6, N, N, N, N),
4201 MUX(1, 66, 6, N, N, N, N),
4202 MUX(1, 67, 6, N, N, N, N),
4203 MUX(1, 68, 6, N, N, N, N),
4204 MUX(1, 69, 6, N, N, N, N),
4205 MUX(1, 70, 6, N, N, N, N),
4206 MUX(1, 71, 6, N, N, N, N),
4207 MUX(1, 72, 6, N, N, N, N),
4208 MUX(1, 53, 6, N, N, N, N),
4209 MUX(1, 54, 6, N, N, N, N),
4210 MUX(1, 55, 6, N, N, N, N),
4211 MUX(1, 56, 6, N, N, N, N),
4212 MUX(1, 85, 6, N, N, N, N),
4213 MUX(1, 86, 6, N, N, N, N),
4214 MUX(1, 87, 6, N, N, N, N),
4215 MUX(1, 88, 6, N, N, N, N),
4216 MUX(1, 89, 6, N, N, N, N),
4217 MUX(1, 90, 6, N, N, N, N),
4218 MUX(1, 91, 6, N, N, N, N),
4219 MUX(1, 92, 6, N, N, N, N),
4220 MUX(1, 93, 6, N, N, N, N),
4221 MUX(1, 94, 6, N, N, N, N),
4222 MUX(1, 95, 6, N, N, N, N),
4223 MUX(1, 96, 6, N, N, N, N),
4224 };
4225
4226 static struct atlas7_grp_mux visbus_dout_grp_mux = {
4227 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4228 .pad_mux_list = visbus_dout_grp_pad_mux,
4229 };
4230
4231 static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4232 MUX(1, 74, 1, N, N, N, N),
4233 MUX(1, 75, 1, N, N, N, N),
4234 MUX(1, 76, 1, N, N, N, N),
4235 MUX(1, 77, 1, N, N, N, N),
4236 MUX(1, 78, 1, N, N, N, N),
4237 MUX(1, 79, 1, N, N, N, N),
4238 MUX(1, 80, 1, N, N, N, N),
4239 MUX(1, 81, 1, N, N, N, N),
4240 MUX(1, 82, 1, N, N, N, N),
4241 MUX(1, 83, 1, N, N, N, N),
4242 MUX(1, 84, 1, N, N, N, N),
4243 MUX(1, 103, 2, N, N, N, N),
4244 MUX(1, 104, 2, N, N, N, N),
4245 MUX(1, 105, 2, N, N, N, N),
4246 MUX(1, 106, 2, N, N, N, N),
4247 MUX(1, 107, 2, N, N, N, N),
4248 MUX(1, 102, 2, N, N, N, N),
4249 MUX(1, 97, 2, N, N, N, N),
4250 MUX(1, 98, 2, N, N, N, N),
4251 };
4252
4253 static struct atlas7_grp_mux vi_vip1_grp_mux = {
4254 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4255 .pad_mux_list = vi_vip1_grp_pad_mux,
4256 };
4257
4258 static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4259 MUX(1, 74, 1, N, N, N, N),
4260 MUX(1, 75, 1, N, N, N, N),
4261 MUX(1, 76, 1, N, N, N, N),
4262 MUX(1, 77, 1, N, N, N, N),
4263 MUX(1, 78, 1, N, N, N, N),
4264 MUX(1, 79, 1, N, N, N, N),
4265 MUX(1, 80, 1, N, N, N, N),
4266 MUX(1, 81, 1, N, N, N, N),
4267 MUX(1, 82, 1, N, N, N, N),
4268 MUX(1, 83, 1, N, N, N, N),
4269 MUX(1, 84, 1, N, N, N, N),
4270 MUX(1, 108, 2, N, N, N, N),
4271 MUX(1, 103, 2, N, N, N, N),
4272 MUX(1, 104, 2, N, N, N, N),
4273 MUX(1, 105, 2, N, N, N, N),
4274 MUX(1, 106, 2, N, N, N, N),
4275 MUX(1, 107, 2, N, N, N, N),
4276 MUX(1, 102, 2, N, N, N, N),
4277 MUX(1, 97, 2, N, N, N, N),
4278 MUX(1, 98, 2, N, N, N, N),
4279 MUX(1, 99, 2, N, N, N, N),
4280 MUX(1, 100, 2, N, N, N, N),
4281 };
4282
4283 static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4284 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4285 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4286 };
4287
4288 static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4289 MUX(1, 74, 1, N, N, N, N),
4290 MUX(1, 75, 1, N, N, N, N),
4291 MUX(1, 76, 1, N, N, N, N),
4292 MUX(1, 77, 1, N, N, N, N),
4293 MUX(1, 78, 1, N, N, N, N),
4294 MUX(1, 79, 1, N, N, N, N),
4295 MUX(1, 80, 1, N, N, N, N),
4296 MUX(1, 81, 1, N, N, N, N),
4297 MUX(1, 82, 1, N, N, N, N),
4298 MUX(1, 83, 1, N, N, N, N),
4299 MUX(1, 84, 1, N, N, N, N),
4300 };
4301
4302 static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4303 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4304 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4305 };
4306
4307 static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4308 MUX(1, 82, 1, N, N, N, N),
4309 MUX(1, 83, 1, N, N, N, N),
4310 MUX(1, 84, 1, N, N, N, N),
4311 MUX(1, 103, 2, N, N, N, N),
4312 MUX(1, 104, 2, N, N, N, N),
4313 MUX(1, 105, 2, N, N, N, N),
4314 MUX(1, 106, 2, N, N, N, N),
4315 MUX(1, 107, 2, N, N, N, N),
4316 MUX(1, 102, 2, N, N, N, N),
4317 MUX(1, 97, 2, N, N, N, N),
4318 MUX(1, 98, 2, N, N, N, N),
4319 };
4320
4321 static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4322 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4323 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4324 };
4325
4326 static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4327 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4328 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4329 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4330 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4331 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4332 FUNCTION("jtag_uart_nand_gpio",
4333 jtag_uart_nand_gpio_grp,
4334 &jtag_uart_nand_gpio_grp_mux),
4335 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4336 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4337 FUNCTION("audio_digmic_m0",
4338 audio_digmic_grp0,
4339 &audio_digmic_grp0_mux),
4340 FUNCTION("audio_digmic_m1",
4341 audio_digmic_grp1,
4342 &audio_digmic_grp1_mux),
4343 FUNCTION("audio_digmic_m2",
4344 audio_digmic_grp2,
4345 &audio_digmic_grp2_mux),
4346 FUNCTION("audio_func_dbg",
4347 audio_func_dbg_grp,
4348 &audio_func_dbg_grp_mux),
4349 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4350 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4351 FUNCTION("audio_i2s_extclk",
4352 audio_i2s_extclk_grp,
4353 &audio_i2s_extclk_grp_mux),
4354 FUNCTION("audio_spdif_out_m0",
4355 audio_spdif_out_grp0,
4356 &audio_spdif_out_grp0_mux),
4357 FUNCTION("audio_spdif_out_m1",
4358 audio_spdif_out_grp1,
4359 &audio_spdif_out_grp1_mux),
4360 FUNCTION("audio_spdif_out_m2",
4361 audio_spdif_out_grp2,
4362 &audio_spdif_out_grp2_mux),
4363 FUNCTION("audio_uart0_basic",
4364 audio_uart0_basic_grp,
4365 &audio_uart0_basic_grp_mux),
4366 FUNCTION("audio_uart0_urfs_m0",
4367 audio_uart0_urfs_grp0,
4368 &audio_uart0_urfs_grp0_mux),
4369 FUNCTION("audio_uart0_urfs_m1",
4370 audio_uart0_urfs_grp1,
4371 &audio_uart0_urfs_grp1_mux),
4372 FUNCTION("audio_uart0_urfs_m2",
4373 audio_uart0_urfs_grp2,
4374 &audio_uart0_urfs_grp2_mux),
4375 FUNCTION("audio_uart0_urfs_m3",
4376 audio_uart0_urfs_grp3,
4377 &audio_uart0_urfs_grp3_mux),
4378 FUNCTION("audio_uart1_basic",
4379 audio_uart1_basic_grp,
4380 &audio_uart1_basic_grp_mux),
4381 FUNCTION("audio_uart1_urfs_m0",
4382 audio_uart1_urfs_grp0,
4383 &audio_uart1_urfs_grp0_mux),
4384 FUNCTION("audio_uart1_urfs_m1",
4385 audio_uart1_urfs_grp1,
4386 &audio_uart1_urfs_grp1_mux),
4387 FUNCTION("audio_uart1_urfs_m2",
4388 audio_uart1_urfs_grp2,
4389 &audio_uart1_urfs_grp2_mux),
4390 FUNCTION("audio_uart2_urfs_m0",
4391 audio_uart2_urfs_grp0,
4392 &audio_uart2_urfs_grp0_mux),
4393 FUNCTION("audio_uart2_urfs_m1",
4394 audio_uart2_urfs_grp1,
4395 &audio_uart2_urfs_grp1_mux),
4396 FUNCTION("audio_uart2_urfs_m2",
4397 audio_uart2_urfs_grp2,
4398 &audio_uart2_urfs_grp2_mux),
4399 FUNCTION("audio_uart2_urxd_m0",
4400 audio_uart2_urxd_grp0,
4401 &audio_uart2_urxd_grp0_mux),
4402 FUNCTION("audio_uart2_urxd_m1",
4403 audio_uart2_urxd_grp1,
4404 &audio_uart2_urxd_grp1_mux),
4405 FUNCTION("audio_uart2_urxd_m2",
4406 audio_uart2_urxd_grp2,
4407 &audio_uart2_urxd_grp2_mux),
4408 FUNCTION("audio_uart2_usclk_m0",
4409 audio_uart2_usclk_grp0,
4410 &audio_uart2_usclk_grp0_mux),
4411 FUNCTION("audio_uart2_usclk_m1",
4412 audio_uart2_usclk_grp1,
4413 &audio_uart2_usclk_grp1_mux),
4414 FUNCTION("audio_uart2_usclk_m2",
4415 audio_uart2_usclk_grp2,
4416 &audio_uart2_usclk_grp2_mux),
4417 FUNCTION("audio_uart2_utfs_m0",
4418 audio_uart2_utfs_grp0,
4419 &audio_uart2_utfs_grp0_mux),
4420 FUNCTION("audio_uart2_utfs_m1",
4421 audio_uart2_utfs_grp1,
4422 &audio_uart2_utfs_grp1_mux),
4423 FUNCTION("audio_uart2_utfs_m2",
4424 audio_uart2_utfs_grp2,
4425 &audio_uart2_utfs_grp2_mux),
4426 FUNCTION("audio_uart2_utxd_m0",
4427 audio_uart2_utxd_grp0,
4428 &audio_uart2_utxd_grp0_mux),
4429 FUNCTION("audio_uart2_utxd_m1",
4430 audio_uart2_utxd_grp1,
4431 &audio_uart2_utxd_grp1_mux),
4432 FUNCTION("audio_uart2_utxd_m2",
4433 audio_uart2_utxd_grp2,
4434 &audio_uart2_utxd_grp2_mux),
4435 FUNCTION("c_can_trnsvr_en_m0",
4436 c_can_trnsvr_en_grp0,
4437 &c_can_trnsvr_en_grp0_mux),
4438 FUNCTION("c_can_trnsvr_en_m1",
4439 c_can_trnsvr_en_grp1,
4440 &c_can_trnsvr_en_grp1_mux),
4441 FUNCTION("c_can_trnsvr_intr",
4442 c_can_trnsvr_intr_grp,
4443 &c_can_trnsvr_intr_grp_mux),
4444 FUNCTION("c_can_trnsvr_stb_n",
4445 c_can_trnsvr_stb_n_grp,
4446 &c_can_trnsvr_stb_n_grp_mux),
4447 FUNCTION("c0_can_rxd_trnsv0",
4448 c0_can_rxd_trnsv0_grp,
4449 &c0_can_rxd_trnsv0_grp_mux),
4450 FUNCTION("c0_can_rxd_trnsv1",
4451 c0_can_rxd_trnsv1_grp,
4452 &c0_can_rxd_trnsv1_grp_mux),
4453 FUNCTION("c0_can_txd_trnsv0",
4454 c0_can_txd_trnsv0_grp,
4455 &c0_can_txd_trnsv0_grp_mux),
4456 FUNCTION("c0_can_txd_trnsv1",
4457 c0_can_txd_trnsv1_grp,
4458 &c0_can_txd_trnsv1_grp_mux),
4459 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4460 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4461 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4462 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4463 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4464 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4465 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4466 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4467 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4468 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4469 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4470 FUNCTION("ca_curator_lpc",
4471 ca_curator_lpc_grp,
4472 &ca_curator_lpc_grp_mux),
4473 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4474 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4475 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4476 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4477 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4478 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4479 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4480 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4481 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4482 FUNCTION("gn_gnss_uart_nopause",
4483 gn_gnss_uart_nopause_grp,
4484 &gn_gnss_uart_nopause_grp_mux),
4485 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4486 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4487 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4488 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4489 FUNCTION("cvbs_dbg_test_m0",
4490 cvbs_dbg_test_grp0,
4491 &cvbs_dbg_test_grp0_mux),
4492 FUNCTION("cvbs_dbg_test_m1",
4493 cvbs_dbg_test_grp1,
4494 &cvbs_dbg_test_grp1_mux),
4495 FUNCTION("cvbs_dbg_test_m2",
4496 cvbs_dbg_test_grp2,
4497 &cvbs_dbg_test_grp2_mux),
4498 FUNCTION("cvbs_dbg_test_m3",
4499 cvbs_dbg_test_grp3,
4500 &cvbs_dbg_test_grp3_mux),
4501 FUNCTION("cvbs_dbg_test_m4",
4502 cvbs_dbg_test_grp4,
4503 &cvbs_dbg_test_grp4_mux),
4504 FUNCTION("cvbs_dbg_test_m5",
4505 cvbs_dbg_test_grp5,
4506 &cvbs_dbg_test_grp5_mux),
4507 FUNCTION("cvbs_dbg_test_m6",
4508 cvbs_dbg_test_grp6,
4509 &cvbs_dbg_test_grp6_mux),
4510 FUNCTION("cvbs_dbg_test_m7",
4511 cvbs_dbg_test_grp7,
4512 &cvbs_dbg_test_grp7_mux),
4513 FUNCTION("cvbs_dbg_test_m8",
4514 cvbs_dbg_test_grp8,
4515 &cvbs_dbg_test_grp8_mux),
4516 FUNCTION("cvbs_dbg_test_m9",
4517 cvbs_dbg_test_grp9,
4518 &cvbs_dbg_test_grp9_mux),
4519 FUNCTION("cvbs_dbg_test_m10",
4520 cvbs_dbg_test_grp10,
4521 &cvbs_dbg_test_grp10_mux),
4522 FUNCTION("cvbs_dbg_test_m11",
4523 cvbs_dbg_test_grp11,
4524 &cvbs_dbg_test_grp11_mux),
4525 FUNCTION("cvbs_dbg_test_m12",
4526 cvbs_dbg_test_grp12,
4527 &cvbs_dbg_test_grp12_mux),
4528 FUNCTION("cvbs_dbg_test_m13",
4529 cvbs_dbg_test_grp13,
4530 &cvbs_dbg_test_grp13_mux),
4531 FUNCTION("cvbs_dbg_test_m14",
4532 cvbs_dbg_test_grp14,
4533 &cvbs_dbg_test_grp14_mux),
4534 FUNCTION("cvbs_dbg_test_m15",
4535 cvbs_dbg_test_grp15,
4536 &cvbs_dbg_test_grp15_mux),
4537 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4538 FUNCTION("gn_gnss_sw_status",
4539 gn_gnss_sw_status_grp,
4540 &gn_gnss_sw_status_grp_mux),
4541 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4542 FUNCTION("gn_gnss_irq1_m0",
4543 gn_gnss_irq1_grp0,
4544 &gn_gnss_irq1_grp0_mux),
4545 FUNCTION("gn_gnss_irq2_m0",
4546 gn_gnss_irq2_grp0,
4547 &gn_gnss_irq2_grp0_mux),
4548 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4549 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4550 FUNCTION("gn_io_gnsssys_sw_cfg",
4551 gn_io_gnsssys_sw_cfg_grp,
4552 &gn_io_gnsssys_sw_cfg_grp_mux),
4553 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4554 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4555 FUNCTION("gn_trg_shutdown_m0",
4556 gn_trg_shutdown_grp0,
4557 &gn_trg_shutdown_grp0_mux),
4558 FUNCTION("gn_trg_shutdown_m1",
4559 gn_trg_shutdown_grp1,
4560 &gn_trg_shutdown_grp1_mux),
4561 FUNCTION("gn_trg_shutdown_m2",
4562 gn_trg_shutdown_grp2,
4563 &gn_trg_shutdown_grp2_mux),
4564 FUNCTION("gn_trg_shutdown_m3",
4565 gn_trg_shutdown_grp3,
4566 &gn_trg_shutdown_grp3_mux),
4567 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4568 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4569 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4570 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4571 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4572 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4573 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4574 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4575 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4576 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4577 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4578 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4579 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4580 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4581 FUNCTION("jtag_jt_dbg_nsrst",
4582 jtag_jt_dbg_nsrst_grp,
4583 &jtag_jt_dbg_nsrst_grp_mux),
4584 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4585 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4586 FUNCTION("jtag_swdiotms_m0",
4587 jtag_swdiotms_grp0,
4588 &jtag_swdiotms_grp0_mux),
4589 FUNCTION("jtag_swdiotms_m1",
4590 jtag_swdiotms_grp1,
4591 &jtag_swdiotms_grp1_mux),
4592 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4593 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4594 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4595 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4596 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4597 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4598 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4599 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4600 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4601 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4602 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4603 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4604 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4605 FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
4606 FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
4607 FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
4608 FUNCTION("ps", ps_grp, &ps_grp_mux),
4609 FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
4610 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4611 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4612 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4613 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4614 FUNCTION("pwc_lowbatt_b_m0",
4615 pwc_lowbatt_b_grp0,
4616 &pwc_lowbatt_b_grp0_mux),
4617 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4618 FUNCTION("pwc_on_key_b_m0",
4619 pwc_on_key_b_grp0,
4620 &pwc_on_key_b_grp0_mux),
4621 FUNCTION("pwc_wakeup_src0",
4622 pwc_wakeup_src0_grp,
4623 &pwc_wakeup_src0_grp_mux),
4624 FUNCTION("pwc_wakeup_src1",
4625 pwc_wakeup_src1_grp,
4626 &pwc_wakeup_src1_grp_mux),
4627 FUNCTION("pwc_wakeup_src2",
4628 pwc_wakeup_src2_grp,
4629 &pwc_wakeup_src2_grp_mux),
4630 FUNCTION("pwc_wakeup_src3",
4631 pwc_wakeup_src3_grp,
4632 &pwc_wakeup_src3_grp_mux),
4633 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4634 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4635 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4636 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4637 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4638 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4639 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4640 FUNCTION("pw_i2s01_clk_m0",
4641 pw_i2s01_clk_grp0,
4642 &pw_i2s01_clk_grp0_mux),
4643 FUNCTION("pw_i2s01_clk_m1",
4644 pw_i2s01_clk_grp1,
4645 &pw_i2s01_clk_grp1_mux),
4646 FUNCTION("pw_i2s01_clk_m2",
4647 pw_i2s01_clk_grp2,
4648 &pw_i2s01_clk_grp2_mux),
4649 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4650 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4651 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4652 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4653 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4654 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4655 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4656 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4657 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4658 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4659 FUNCTION("pw_pwm_cpu_vol_m0",
4660 pw_pwm_cpu_vol_grp0,
4661 &pw_pwm_cpu_vol_grp0_mux),
4662 FUNCTION("pw_pwm_cpu_vol_m1",
4663 pw_pwm_cpu_vol_grp1,
4664 &pw_pwm_cpu_vol_grp1_mux),
4665 FUNCTION("pw_pwm_cpu_vol_m2",
4666 pw_pwm_cpu_vol_grp2,
4667 &pw_pwm_cpu_vol_grp2_mux),
4668 FUNCTION("pw_backlight_m0",
4669 pw_backlight_grp0,
4670 &pw_backlight_grp0_mux),
4671 FUNCTION("pw_backlight_m1",
4672 pw_backlight_grp1,
4673 &pw_backlight_grp1_mux),
4674 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4675 FUNCTION("rg_gmac_phy_intr_n",
4676 rg_gmac_phy_intr_n_grp,
4677 &rg_gmac_phy_intr_n_grp_mux),
4678 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4679 FUNCTION("rg_rgmii_phy_ref_clk_m0",
4680 rg_rgmii_phy_ref_clk_grp0,
4681 &rg_rgmii_phy_ref_clk_grp0_mux),
4682 FUNCTION("rg_rgmii_phy_ref_clk_m1",
4683 rg_rgmii_phy_ref_clk_grp1,
4684 &rg_rgmii_phy_ref_clk_grp1_mux),
4685 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4686 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4687 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4688 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4689 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4690 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4691 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4692 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4693 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4694 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4695 FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
4696 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4697 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4698 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4699 FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
4700 FUNCTION("sp0_ext_ldo_on",
4701 sp0_ext_ldo_on_grp,
4702 &sp0_ext_ldo_on_grp_mux),
4703 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4704 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4705 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4706 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4707 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4708 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4709 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4710 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4711 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4712 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4713 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4714 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4715 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4716 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4717 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4718 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4719 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4720 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4721 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4722 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4723 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4724 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4725 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4726 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4727 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4728 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4729 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4730 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4731 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4732 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4733 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4734 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4735 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4736 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4737 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4738 FUNCTION("usb0_drvvbus_m0",
4739 usb0_drvvbus_grp0,
4740 &usb0_drvvbus_grp0_mux),
4741 FUNCTION("usb0_drvvbus_m1",
4742 usb0_drvvbus_grp1,
4743 &usb0_drvvbus_grp1_mux),
4744 FUNCTION("usb1_drvvbus_m0",
4745 usb1_drvvbus_grp0,
4746 &usb1_drvvbus_grp0_mux),
4747 FUNCTION("usb1_drvvbus_m1",
4748 usb1_drvvbus_grp1,
4749 &usb1_drvvbus_grp1_mux),
4750 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4751 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4752 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4753 FUNCTION("vi_vip1_low8bit",
4754 vi_vip1_low8bit_grp,
4755 &vi_vip1_low8bit_grp_mux),
4756 FUNCTION("vi_vip1_high8bit",
4757 vi_vip1_high8bit_grp,
4758 &vi_vip1_high8bit_grp_mux),
4759 };
4760
4761 static struct atlas7_pinctrl_data atlas7_ioc_data = {
4762 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4763 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4764 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4765 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4766 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4767 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4768 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4769 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4770 };
4771
4772 /* Simple map data structure */
4773 struct map_data {
4774 u8 idx;
4775 u8 data;
4776 };
4777
4778 /**
4779 * struct atlas7_pull_info - Atlas7 Pad pull info
4780 * @pad_type: The type of this Pad.
4781 * @mask: The mas value of this pin's pull bits.
4782 * @v2s: The map of pull register value to pull status.
4783 * @s2v: The map of pull status to pull register value.
4784 */
4785 struct atlas7_pull_info {
4786 u8 pad_type;
4787 u8 mask;
4788 const struct map_data *v2s;
4789 const struct map_data *s2v;
4790 };
4791
4792 /* Pull Register value map to status */
4793 static const struct map_data p4we_pull_v2s[] = {
4794 { P4WE_PULL_UP, PULL_UP },
4795 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4796 { P4WE_HIGH_Z, HIGH_Z },
4797 { P4WE_PULL_DOWN, PULL_DOWN },
4798 };
4799
4800 static const struct map_data p16st_pull_v2s[] = {
4801 { P16ST_PULL_UP, PULL_UP },
4802 { PD, PULL_UNKNOWN },
4803 { P16ST_HIGH_Z, HIGH_Z },
4804 { P16ST_PULL_DOWN, PULL_DOWN },
4805 };
4806
4807 static const struct map_data pm31_pull_v2s[] = {
4808 { PM31_PULL_DISABLED, PULL_DOWN },
4809 { PM31_PULL_ENABLED, PULL_UP },
4810 };
4811
4812 static const struct map_data pangd_pull_v2s[] = {
4813 { PANGD_PULL_UP, PULL_UP },
4814 { PD, PULL_UNKNOWN },
4815 { PANGD_HIGH_Z, HIGH_Z },
4816 { PANGD_PULL_DOWN, PULL_DOWN },
4817 };
4818
4819 /* Pull status map to register value */
4820 static const struct map_data p4we_pull_s2v[] = {
4821 { PULL_UP, P4WE_PULL_UP },
4822 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4823 { HIGH_Z, P4WE_HIGH_Z },
4824 { PULL_DOWN, P4WE_PULL_DOWN },
4825 { PULL_DISABLE, -1 },
4826 { PULL_ENABLE, -1 },
4827 };
4828
4829 static const struct map_data p16st_pull_s2v[] = {
4830 { PULL_UP, P16ST_PULL_UP },
4831 { HIGH_HYSTERESIS, -1 },
4832 { HIGH_Z, P16ST_HIGH_Z },
4833 { PULL_DOWN, P16ST_PULL_DOWN },
4834 { PULL_DISABLE, -1 },
4835 { PULL_ENABLE, -1 },
4836 };
4837
4838 static const struct map_data pm31_pull_s2v[] = {
4839 { PULL_UP, PM31_PULL_ENABLED },
4840 { HIGH_HYSTERESIS, -1 },
4841 { HIGH_Z, -1 },
4842 { PULL_DOWN, PM31_PULL_DISABLED },
4843 { PULL_DISABLE, -1 },
4844 { PULL_ENABLE, -1 },
4845 };
4846
4847 static const struct map_data pangd_pull_s2v[] = {
4848 { PULL_UP, PANGD_PULL_UP },
4849 { HIGH_HYSTERESIS, -1 },
4850 { HIGH_Z, PANGD_HIGH_Z },
4851 { PULL_DOWN, PANGD_PULL_DOWN },
4852 { PULL_DISABLE, -1 },
4853 { PULL_ENABLE, -1 },
4854 };
4855
4856 static const struct atlas7_pull_info atlas7_pull_map[] = {
4857 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4858 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4859 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4860 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4861 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4862 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4863 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4864 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4865 };
4866
4867 /**
4868 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4869 * @ma: The Drive Strength in current value .
4870 * @ds_16st: The correspond raw value of 16st pad.
4871 * @ds_4we: The correspond raw value of 4we pad.
4872 * @ds_0204m31: The correspond raw value of 0204m31 pad.
4873 * @ds_0610m31: The correspond raw value of 0610m31 pad.
4874 */
4875 struct atlas7_ds_ma_info {
4876 u32 ma;
4877 u32 ds_16st;
4878 u32 ds_4we;
4879 u32 ds_0204m31;
4880 u32 ds_0610m31;
4881 };
4882
4883 static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4884 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4885 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4886 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4887 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4888 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4889 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4890 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4891 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4892 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4893 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4894 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4895 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4896 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4897 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4898 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4899 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4900 };
4901
4902 /**
4903 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4904 * @type: The type of this Pad.
4905 * @mask: The mask value of this pin's pull bits.
4906 * @imval: The immediate value of drives trength register.
4907 * @reserved: Reserved space
4908 */
4909 struct atlas7_ds_info {
4910 u8 type;
4911 u8 mask;
4912 u8 imval;
4913 u8 reserved;
4914 };
4915
4916 static const struct atlas7_ds_info atlas7_ds_map[] = {
4917 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4918 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4919 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4920 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4921 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4922 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4923 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4924 { PAD_T_AD, DS_NULL, DS_NULL },
4925 };
4926
4927 static inline u32 atlas7_pin_to_bank(u32 pin)
4928 {
4929 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4930 }
4931
4932 static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4933 {
4934 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4935
4936 return pmx->pctl_data->funcs_cnt;
4937 }
4938
4939 static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
4940 u32 selector)
4941 {
4942 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4943
4944 return pmx->pctl_data->funcs[selector].name;
4945 }
4946
4947 static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4948 u32 selector, const char * const **groups,
4949 u32 * const num_groups)
4950 {
4951 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4952
4953 *groups = pmx->pctl_data->funcs[selector].groups;
4954 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4955
4956 return 0;
4957 }
4958
4959 static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4960 const struct atlas7_pad_mux *mux)
4961 {
4962 /* Set Input Disable to avoid input glitches
4963 *
4964 * All Input-Disable Control registers are located on IOCRTC.
4965 * So the regs bank is always 0.
4966 *
4967 */
4968 if (mux->dinput_reg && mux->dinput_val_reg) {
4969 writel(DI_MASK << mux->dinput_bit,
4970 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4971 writel(DI_DISABLE << mux->dinput_bit,
4972 pmx->regs[BANK_DS] + mux->dinput_reg);
4973
4974
4975 writel(DIV_MASK << mux->dinput_val_bit,
4976 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4977 writel(DIV_DISABLE << mux->dinput_val_bit,
4978 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4979 }
4980 }
4981
4982 static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4983 const struct atlas7_pad_mux *mux)
4984 {
4985 /* Clear Input Disable to avoid input glitches */
4986 if (mux->dinput_reg && mux->dinput_val_reg) {
4987 writel(DI_MASK << mux->dinput_bit,
4988 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4989 writel(DI_ENABLE << mux->dinput_bit,
4990 pmx->regs[BANK_DS] + mux->dinput_reg);
4991
4992 writel(DIV_MASK << mux->dinput_val_bit,
4993 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4994 writel(DIV_ENABLE << mux->dinput_val_bit,
4995 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4996 }
4997 }
4998
4999 static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
5000 struct atlas7_pad_config *conf,
5001 u32 bank, u32 ad_sel)
5002 {
5003 unsigned long regv;
5004
5005 /* Write to clear register to clear A/D selector */
5006 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
5007 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
5008
5009 /* Set target pad A/D selector */
5010 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5011 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
5012 writel(regv | (ad_sel << conf->ad_ctrl_bit),
5013 pmx->regs[bank] + conf->ad_ctrl_reg);
5014
5015 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5016 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5017 bank, conf->ad_ctrl_reg, regv);
5018 return 0;
5019 }
5020
5021 static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
5022 struct atlas7_pad_config *conf, u32 bank)
5023 {
5024 /* Only PAD_T_AD pins can change between Analogue&Digital */
5025 if (conf->type != PAD_T_AD)
5026 return -EINVAL;
5027
5028 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
5029 }
5030
5031 static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
5032 struct atlas7_pad_config *conf, u32 bank)
5033 {
5034 /* Other type pads are always digital */
5035 if (conf->type != PAD_T_AD)
5036 return 0;
5037
5038 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
5039 }
5040
5041 static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
5042 u32 pin, u32 func)
5043 {
5044 struct atlas7_pad_config *conf;
5045 u32 bank;
5046 int ret;
5047 unsigned long regv;
5048
5049 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
5050 pin, func);
5051
5052 /* Get this Pad's descriptor from PINCTRL */
5053 conf = &pmx->pctl_data->confs[pin];
5054 bank = atlas7_pin_to_bank(pin);
5055
5056 /* Just enable the analog function of this pad */
5057 if (FUNC_ANALOGUE == func) {
5058 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
5059 if (ret)
5060 dev_err(pmx->dev,
5061 "Convert pad#%d to analog failed, ret=%d\n",
5062 pin, ret);
5063 return ret;
5064 }
5065
5066 /* Set Pads from analog to digital */
5067 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
5068 if (ret) {
5069 dev_err(pmx->dev,
5070 "Convert pad#%d to digital failed, ret=%d\n",
5071 pin, ret);
5072 return ret;
5073 }
5074
5075 /* Write to clear register to clear current function */
5076 writel(FUNC_CLEAR_MASK << conf->mux_bit,
5077 pmx->regs[bank] + CLR_REG(conf->mux_reg));
5078
5079 /* Set target pad mux function */
5080 regv = readl(pmx->regs[bank] + conf->mux_reg);
5081 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
5082 writel(regv | (func << conf->mux_bit),
5083 pmx->regs[bank] + conf->mux_reg);
5084
5085 regv = readl(pmx->regs[bank] + conf->mux_reg);
5086 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5087 bank, conf->mux_reg, regv);
5088
5089 return 0;
5090 }
5091
5092 static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
5093 u32 func_selector, u32 group_selector)
5094 {
5095 int idx, ret;
5096 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5097 struct atlas7_pmx_func *pmx_func;
5098 struct atlas7_pin_group *pin_grp;
5099 const struct atlas7_grp_mux *grp_mux;
5100 const struct atlas7_pad_mux *mux;
5101
5102 pmx_func = &pmx->pctl_data->funcs[func_selector];
5103 pin_grp = &pmx->pctl_data->grps[group_selector];
5104
5105 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
5106 pmx_func->name, pin_grp->name);
5107
5108 /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
5109 if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
5110 if (!strcmp(pmx_func->name, "sd9"))
5111 writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5112 else
5113 writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5114 }
5115
5116 grp_mux = pmx_func->grpmux;
5117
5118 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
5119 mux = &grp_mux->pad_mux_list[idx];
5120 __atlas7_pmx_pin_input_disable_set(pmx, mux);
5121 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
5122 if (ret) {
5123 dev_err(pmx->dev,
5124 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
5125 pmx_func->name, pin_grp->name,
5126 mux->pin, mux->func, ret);
5127 BUG_ON(1);
5128 }
5129 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
5130 }
5131 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
5132 pmx_func->name, pin_grp->name);
5133
5134 return 0;
5135 }
5136
5137 static u32 convert_current_to_drive_strength(u32 type, u32 ma)
5138 {
5139 int idx;
5140
5141 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
5142 if (atlas7_ma2ds_map[idx].ma != ma)
5143 continue;
5144
5145 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
5146 return atlas7_ma2ds_map[idx].ds_4we;
5147 else if (type == PAD_T_16ST)
5148 return atlas7_ma2ds_map[idx].ds_16st;
5149 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
5150 return atlas7_ma2ds_map[idx].ds_0204m31;
5151 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
5152 return atlas7_ma2ds_map[idx].ds_0610m31;
5153 }
5154
5155 return DS_NULL;
5156 }
5157
5158 static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
5159 u32 pin, u32 sel)
5160 {
5161 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5162 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5163 const struct atlas7_pull_info *pull_info;
5164 u32 bank;
5165 unsigned long regv;
5166 void __iomem *pull_sel_reg;
5167
5168 bank = atlas7_pin_to_bank(pin);
5169 pull_info = &atlas7_pull_map[conf->type];
5170 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
5171
5172 /* Retrieve correspond register value from table by sel */
5173 regv = pull_info->s2v[sel].data & pull_info->mask;
5174
5175 /* Clear & Set new value to pull register */
5176 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
5177 writel(regv << conf->pupd_bit, pull_sel_reg);
5178
5179 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
5180 pin, sel);
5181 return 0;
5182 }
5183
5184 static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5185 u32 pin, u32 sel)
5186 {
5187 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5188 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5189 const struct atlas7_ds_info *ds_info;
5190 u32 bank;
5191 void __iomem *ds_sel_reg;
5192
5193 ds_info = &atlas7_ds_map[conf->type];
5194 if (sel & (~(ds_info->mask)))
5195 goto unsupport;
5196
5197 bank = atlas7_pin_to_bank(pin);
5198 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
5199
5200 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
5201 writel(sel << conf->drvstr_bit, ds_sel_reg);
5202
5203 return 0;
5204
5205 unsupport:
5206 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
5207 pin, conf->type, sel);
5208 return -ENOTSUPP;
5209 }
5210
5211 static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5212 u32 pin, u32 ma)
5213 {
5214 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5215 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5216 u32 type = conf->type;
5217 u32 sel;
5218 int ret;
5219
5220 sel = convert_current_to_drive_strength(conf->type, ma);
5221 if (DS_NULL == sel) {
5222 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
5223 pin, type, ma);
5224 return -ENOTSUPP;
5225 }
5226
5227 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
5228 pin, sel);
5229 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
5230 pin, sel, ma, ret?"FAILED":"OK");
5231 return ret;
5232 }
5233
5234 static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
5235 struct pinctrl_gpio_range *range, u32 pin)
5236 {
5237 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5238 u32 idx;
5239
5240 dev_dbg(pmx->dev,
5241 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
5242 for (idx = 0; idx < range->npins; idx++) {
5243 if (pin == range->pins[idx])
5244 break;
5245 }
5246
5247 if (idx >= range->npins) {
5248 dev_err(pmx->dev,
5249 "The pin#%d could not be requested as GPIO!!\n",
5250 pin);
5251 return -EPERM;
5252 }
5253
5254 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
5255
5256 return 0;
5257 }
5258
5259 static const struct pinmux_ops atlas7_pinmux_ops = {
5260 .get_functions_count = atlas7_pmx_get_funcs_count,
5261 .get_function_name = atlas7_pmx_get_func_name,
5262 .get_function_groups = atlas7_pmx_get_func_groups,
5263 .set_mux = atlas7_pmx_set_mux,
5264 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
5265 };
5266
5267 static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
5268 {
5269 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5270
5271 return pmx->pctl_data->grps_cnt;
5272 }
5273
5274 static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
5275 u32 group)
5276 {
5277 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5278
5279 return pmx->pctl_data->grps[group].name;
5280 }
5281
5282 static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
5283 u32 group, const u32 **pins, u32 *num_pins)
5284 {
5285 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5286
5287 *num_pins = pmx->pctl_data->grps[group].num_pins;
5288 *pins = pmx->pctl_data->grps[group].pins;
5289
5290 return 0;
5291 }
5292
5293 static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
5294 struct device_node *np_config,
5295 struct pinctrl_map **map,
5296 u32 *num_maps)
5297 {
5298 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
5299 num_maps, PIN_MAP_TYPE_INVALID);
5300 }
5301
5302 static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
5303 struct pinctrl_map *map, u32 num_maps)
5304 {
5305 kfree(map);
5306 }
5307
5308 static const struct pinctrl_ops atlas7_pinctrl_ops = {
5309 .get_groups_count = atlas7_pinctrl_get_groups_count,
5310 .get_group_name = atlas7_pinctrl_get_group_name,
5311 .get_group_pins = atlas7_pinctrl_get_group_pins,
5312 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
5313 .dt_free_map = atlas7_pinctrl_dt_free_map,
5314 };
5315
5316 static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
5317 unsigned pin, unsigned long *configs,
5318 unsigned num_configs)
5319 {
5320 u16 param;
5321 u32 arg;
5322 int idx, err;
5323
5324 for (idx = 0; idx < num_configs; idx++) {
5325 param = pinconf_to_config_param(configs[idx]);
5326 arg = pinconf_to_config_argument(configs[idx]);
5327
5328 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
5329 pin, atlas7_ioc_pads[pin].name, param, arg);
5330 switch (param) {
5331 case PIN_CONFIG_BIAS_PULL_UP:
5332 err = altas7_pinctrl_set_pull_sel(pctldev,
5333 pin, PULL_UP);
5334 if (err)
5335 return err;
5336 break;
5337
5338 case PIN_CONFIG_BIAS_PULL_DOWN:
5339 err = altas7_pinctrl_set_pull_sel(pctldev,
5340 pin, PULL_DOWN);
5341 if (err)
5342 return err;
5343 break;
5344
5345 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
5346 err = altas7_pinctrl_set_pull_sel(pctldev,
5347 pin, HIGH_HYSTERESIS);
5348 if (err)
5349 return err;
5350 break;
5351 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
5352 err = altas7_pinctrl_set_pull_sel(pctldev,
5353 pin, HIGH_Z);
5354 if (err)
5355 return err;
5356 break;
5357
5358 case PIN_CONFIG_DRIVE_STRENGTH:
5359 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
5360 pin, arg);
5361 if (err)
5362 return err;
5363 break;
5364 default:
5365 return -ENOTSUPP;
5366 }
5367 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
5368 pin, atlas7_ioc_pads[pin].name, param, arg);
5369 }
5370
5371 return 0;
5372 }
5373
5374 static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
5375 unsigned group, unsigned long *configs,
5376 unsigned num_configs)
5377 {
5378 const unsigned *pins;
5379 unsigned npins;
5380 int i, ret;
5381
5382 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
5383 if (ret)
5384 return ret;
5385 for (i = 0; i < npins; i++) {
5386 if (atlas7_pin_config_set(pctldev, pins[i],
5387 configs, num_configs))
5388 return -ENOTSUPP;
5389 }
5390 return 0;
5391 }
5392
5393 static const struct pinconf_ops atlas7_pinconf_ops = {
5394 .pin_config_set = atlas7_pin_config_set,
5395 .pin_config_group_set = atlas7_pin_config_group_set,
5396 .is_generic = true,
5397 };
5398
5399 static int atlas7_pinmux_probe(struct platform_device *pdev)
5400 {
5401 int ret, idx;
5402 struct atlas7_pmx *pmx;
5403 struct device_node *np = pdev->dev.of_node;
5404 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
5405 struct device_node *sys2pci_np;
5406 struct resource res;
5407
5408 /* Create state holders etc for this driver */
5409 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
5410 if (!pmx)
5411 return -ENOMEM;
5412
5413 /* The sd3 and sd9 shared all pins, and the function select by
5414 * SYS2PCI_SDIO9SEL register
5415 */
5416 sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
5417 if (!sys2pci_np)
5418 return -EINVAL;
5419
5420 ret = of_address_to_resource(sys2pci_np, 0, &res);
5421 of_node_put(sys2pci_np);
5422 if (ret)
5423 return ret;
5424
5425 pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
5426 if (IS_ERR(pmx->sys2pci_base))
5427 return -ENOMEM;
5428
5429 pmx->dev = &pdev->dev;
5430
5431 pmx->pctl_data = &atlas7_ioc_data;
5432 pmx->pctl_desc.name = "pinctrl-atlas7";
5433 pmx->pctl_desc.pins = pmx->pctl_data->pads;
5434 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
5435 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
5436 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
5437 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
5438
5439 for (idx = 0; idx < banks; idx++) {
5440 pmx->regs[idx] = of_iomap(np, idx);
5441 if (!pmx->regs[idx]) {
5442 dev_err(&pdev->dev,
5443 "can't map ioc bank#%d registers\n", idx);
5444 ret = -ENOMEM;
5445 goto unmap_io;
5446 }
5447 }
5448
5449 /* Now register the pin controller and all pins it handles */
5450 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
5451 if (IS_ERR(pmx->pctl)) {
5452 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
5453 ret = PTR_ERR(pmx->pctl);
5454 goto unmap_io;
5455 }
5456
5457 platform_set_drvdata(pdev, pmx);
5458
5459 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
5460
5461 return 0;
5462
5463 unmap_io:
5464 for (idx = 0; idx < banks; idx++) {
5465 if (!pmx->regs[idx])
5466 break;
5467 iounmap(pmx->regs[idx]);
5468 }
5469
5470 return ret;
5471 }
5472
5473 #ifdef CONFIG_PM_SLEEP
5474 static int atlas7_pinmux_suspend_noirq(struct device *dev)
5475 {
5476 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5477 struct atlas7_pad_status *status;
5478 struct atlas7_pad_config *conf;
5479 const struct atlas7_ds_info *ds_info;
5480 const struct atlas7_pull_info *pull_info;
5481 int idx;
5482 u32 bank;
5483 unsigned long regv;
5484
5485 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5486 /* Get this Pad's descriptor from PINCTRL */
5487 conf = &pmx->pctl_data->confs[idx];
5488 bank = atlas7_pin_to_bank(idx);
5489 status = &pmx->sleep_data[idx];
5490
5491 /* Save Function selector */
5492 regv = readl(pmx->regs[bank] + conf->mux_reg);
5493 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
5494
5495 /* Check if Pad is in Analogue selector */
5496 if (conf->ad_ctrl_reg == -1)
5497 goto save_ds_sel;
5498
5499 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5500 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
5501 status->func = FUNC_ANALOGUE;
5502
5503 save_ds_sel:
5504 if (conf->drvstr_reg == -1)
5505 goto save_pull_sel;
5506
5507 /* Save Drive Strength selector */
5508 ds_info = &atlas7_ds_map[conf->type];
5509 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
5510 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
5511
5512 save_pull_sel:
5513 /* Save Pull selector */
5514 pull_info = &atlas7_pull_map[conf->type];
5515 regv = readl(pmx->regs[bank] + conf->pupd_reg);
5516 regv = (regv >> conf->pupd_bit) & pull_info->mask;
5517 status->pull = pull_info->v2s[regv].data;
5518 }
5519
5520 /*
5521 * Save disable input selector, this selector is not for Pin,
5522 * but for Mux function.
5523 */
5524 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5525 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
5526 IN_DISABLE_0_REG_SET + 0x8 * idx);
5527 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
5528 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5529 }
5530
5531 return 0;
5532 }
5533
5534 static int atlas7_pinmux_resume_noirq(struct device *dev)
5535 {
5536 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5537 struct atlas7_pad_status *status;
5538 int idx;
5539
5540 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5541 /* Get this Pad's descriptor from PINCTRL */
5542 status = &pmx->sleep_data[idx];
5543
5544 /* Restore Function selector */
5545 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
5546
5547 if (FUNC_ANALOGUE == status->func)
5548 goto restore_pull_sel;
5549
5550 /* Restore Drive Strength selector */
5551 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
5552 (u32)status->dstr & 0xff);
5553
5554 restore_pull_sel:
5555 /* Restore Pull selector */
5556 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
5557 (u32)status->pull & 0xff);
5558 }
5559
5560 /*
5561 * Restore disable input selector, this selector is not for Pin,
5562 * but for Mux function
5563 */
5564 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5565 writel(~0, pmx->regs[BANK_DS] +
5566 IN_DISABLE_0_REG_CLR + 0x8 * idx);
5567 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
5568 IN_DISABLE_0_REG_SET + 0x8 * idx);
5569 writel(~0, pmx->regs[BANK_DS] +
5570 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
5571 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
5572 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5573 }
5574
5575 return 0;
5576 }
5577
5578 static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
5579 .suspend_noirq = atlas7_pinmux_suspend_noirq,
5580 .resume_noirq = atlas7_pinmux_resume_noirq,
5581 .freeze_noirq = atlas7_pinmux_suspend_noirq,
5582 .restore_noirq = atlas7_pinmux_resume_noirq,
5583 };
5584 #endif
5585
5586 static const struct of_device_id atlas7_pinmux_ids[] = {
5587 { .compatible = "sirf,atlas7-ioc",},
5588 {},
5589 };
5590
5591 static struct platform_driver atlas7_pinmux_driver = {
5592 .driver = {
5593 .name = "atlas7-ioc",
5594 .of_match_table = atlas7_pinmux_ids,
5595 #ifdef CONFIG_PM_SLEEP
5596 .pm = &atlas7_pinmux_pm_ops,
5597 #endif
5598 },
5599 .probe = atlas7_pinmux_probe,
5600 };
5601
5602 static int __init atlas7_pinmux_init(void)
5603 {
5604 return platform_driver_register(&atlas7_pinmux_driver);
5605 }
5606 arch_initcall(atlas7_pinmux_init);
5607
5608
5609 /*
5610 * The Following is GPIO Code
5611 */
5612 static inline struct
5613 atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
5614 {
5615 return &a7gc->banks[GPIO_TO_BANK(gpio)];
5616 }
5617
5618 static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
5619 {
5620 struct atlas7_gpio_bank *bank;
5621 u32 ofs;
5622
5623 bank = atlas7_gpio_to_bank(a7gc, gpio);
5624 ofs = gpio - bank->gpio_offset;
5625 if (ofs >= bank->ngpio)
5626 return -ENODEV;
5627
5628 return bank->gpio_pins[ofs];
5629 }
5630
5631 static void atlas7_gpio_irq_ack(struct irq_data *d)
5632 {
5633 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5634 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5635 struct atlas7_gpio_bank *bank;
5636 void __iomem *ctrl_reg;
5637 u32 val, pin_in_bank;
5638 unsigned long flags;
5639
5640 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5641 pin_in_bank = d->hwirq - bank->gpio_offset;
5642 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5643
5644 raw_spin_lock_irqsave(&a7gc->lock, flags);
5645
5646 val = readl(ctrl_reg);
5647 /* clear interrupt status */
5648 writel(val, ctrl_reg);
5649
5650 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5651 }
5652
5653 static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
5654 {
5655 struct atlas7_gpio_bank *bank;
5656 void __iomem *ctrl_reg;
5657 u32 val, pin_in_bank;
5658
5659 bank = atlas7_gpio_to_bank(a7gc, idx);
5660 pin_in_bank = idx - bank->gpio_offset;
5661 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5662
5663 val = readl(ctrl_reg);
5664 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
5665 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
5666 writel(val, ctrl_reg);
5667 }
5668
5669 static void atlas7_gpio_irq_mask(struct irq_data *d)
5670 {
5671 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5672 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5673 unsigned long flags;
5674
5675 raw_spin_lock_irqsave(&a7gc->lock, flags);
5676
5677 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
5678
5679 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5680 }
5681
5682 static void atlas7_gpio_irq_unmask(struct irq_data *d)
5683 {
5684 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5685 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5686 struct atlas7_gpio_bank *bank;
5687 void __iomem *ctrl_reg;
5688 u32 val, pin_in_bank;
5689 unsigned long flags;
5690
5691 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5692 pin_in_bank = d->hwirq - bank->gpio_offset;
5693 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5694
5695 raw_spin_lock_irqsave(&a7gc->lock, flags);
5696
5697 val = readl(ctrl_reg);
5698 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
5699 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
5700 writel(val, ctrl_reg);
5701
5702 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5703 }
5704
5705 static int atlas7_gpio_irq_type(struct irq_data *d,
5706 unsigned int type)
5707 {
5708 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5709 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5710 struct atlas7_gpio_bank *bank;
5711 void __iomem *ctrl_reg;
5712 u32 val, pin_in_bank;
5713 unsigned long flags;
5714
5715 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5716 pin_in_bank = d->hwirq - bank->gpio_offset;
5717 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5718
5719 raw_spin_lock_irqsave(&a7gc->lock, flags);
5720
5721 val = readl(ctrl_reg);
5722 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
5723 ATLAS7_GPIO_CTL_INTR_EN_MASK);
5724
5725 switch (type) {
5726 case IRQ_TYPE_NONE:
5727 break;
5728
5729 case IRQ_TYPE_EDGE_RISING:
5730 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5731 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5732 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5733 break;
5734
5735 case IRQ_TYPE_EDGE_FALLING:
5736 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5737 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5738 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5739 break;
5740
5741 case IRQ_TYPE_EDGE_BOTH:
5742 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5743 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5744 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5745 break;
5746
5747 case IRQ_TYPE_LEVEL_LOW:
5748 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5749 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5750 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5751 break;
5752
5753 case IRQ_TYPE_LEVEL_HIGH:
5754 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5755 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5756 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5757 break;
5758 }
5759
5760 writel(val, ctrl_reg);
5761
5762 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5763
5764 return 0;
5765 }
5766
5767 static struct irq_chip atlas7_gpio_irq_chip = {
5768 .name = "atlas7-gpio-irq",
5769 .irq_ack = atlas7_gpio_irq_ack,
5770 .irq_mask = atlas7_gpio_irq_mask,
5771 .irq_unmask = atlas7_gpio_irq_unmask,
5772 .irq_set_type = atlas7_gpio_irq_type,
5773 };
5774
5775 static void atlas7_gpio_handle_irq(struct irq_desc *desc)
5776 {
5777 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5778 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5779 struct atlas7_gpio_bank *bank = NULL;
5780 u32 status, ctrl;
5781 int pin_in_bank = 0, idx;
5782 struct irq_chip *chip = irq_desc_get_chip(desc);
5783 unsigned int irq = irq_desc_get_irq(desc);
5784
5785 for (idx = 0; idx < a7gc->nbank; idx++) {
5786 bank = &a7gc->banks[idx];
5787 if (bank->irq == irq)
5788 break;
5789 }
5790 BUG_ON(idx == a7gc->nbank);
5791
5792 chained_irq_enter(chip, desc);
5793
5794 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
5795 if (!status) {
5796 pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
5797 __func__, gc->label, status);
5798 handle_bad_irq(desc);
5799 return;
5800 }
5801
5802 while (status) {
5803 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5804
5805 /*
5806 * Here we must check whether the corresponding GPIO's
5807 * interrupt has been enabled, otherwise just skip it
5808 */
5809 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
5810 pr_debug("%s: chip[%s] gpio:%d happens\n",
5811 __func__, gc->label,
5812 bank->gpio_offset + pin_in_bank);
5813 generic_handle_irq(
5814 irq_find_mapping(gc->irq.domain,
5815 bank->gpio_offset + pin_in_bank));
5816 }
5817
5818 if (++pin_in_bank >= bank->ngpio)
5819 break;
5820
5821 status = status >> 1;
5822 }
5823
5824 chained_irq_exit(chip, desc);
5825 }
5826
5827 static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
5828 unsigned int gpio)
5829 {
5830 struct atlas7_gpio_bank *bank;
5831 void __iomem *ctrl_reg;
5832 u32 val, pin_in_bank;
5833
5834 bank = atlas7_gpio_to_bank(a7gc, gpio);
5835 pin_in_bank = gpio - bank->gpio_offset;
5836 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5837
5838 val = readl(ctrl_reg);
5839 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
5840 writel(val, ctrl_reg);
5841 }
5842
5843 static int atlas7_gpio_request(struct gpio_chip *chip,
5844 unsigned int gpio)
5845 {
5846 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5847 int ret;
5848 unsigned long flags;
5849
5850 ret = __atlas7_gpio_to_pin(a7gc, gpio);
5851 if (ret < 0)
5852 return ret;
5853
5854 if (pinctrl_gpio_request(chip->base + gpio))
5855 return -ENODEV;
5856
5857 raw_spin_lock_irqsave(&a7gc->lock, flags);
5858
5859 /*
5860 * default status:
5861 * set direction as input and mask irq
5862 */
5863 __atlas7_gpio_set_input(a7gc, gpio);
5864 __atlas7_gpio_irq_mask(a7gc, gpio);
5865
5866 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5867
5868 return 0;
5869 }
5870
5871 static void atlas7_gpio_free(struct gpio_chip *chip,
5872 unsigned int gpio)
5873 {
5874 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5875 unsigned long flags;
5876
5877 raw_spin_lock_irqsave(&a7gc->lock, flags);
5878
5879 __atlas7_gpio_irq_mask(a7gc, gpio);
5880 __atlas7_gpio_set_input(a7gc, gpio);
5881
5882 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5883
5884 pinctrl_gpio_free(chip->base + gpio);
5885 }
5886
5887 static int atlas7_gpio_direction_input(struct gpio_chip *chip,
5888 unsigned int gpio)
5889 {
5890 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5891 unsigned long flags;
5892
5893 raw_spin_lock_irqsave(&a7gc->lock, flags);
5894
5895 __atlas7_gpio_set_input(a7gc, gpio);
5896
5897 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5898
5899 return 0;
5900 }
5901
5902 static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
5903 unsigned int gpio, int value)
5904 {
5905 struct atlas7_gpio_bank *bank;
5906 void __iomem *ctrl_reg;
5907 u32 out_ctrl, pin_in_bank;
5908
5909 bank = atlas7_gpio_to_bank(a7gc, gpio);
5910 pin_in_bank = gpio - bank->gpio_offset;
5911 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5912
5913 out_ctrl = readl(ctrl_reg);
5914 if (value)
5915 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5916 else
5917 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5918
5919 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
5920 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
5921 writel(out_ctrl, ctrl_reg);
5922 }
5923
5924 static int atlas7_gpio_direction_output(struct gpio_chip *chip,
5925 unsigned int gpio, int value)
5926 {
5927 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5928 unsigned long flags;
5929
5930 raw_spin_lock_irqsave(&a7gc->lock, flags);
5931
5932 __atlas7_gpio_set_output(a7gc, gpio, value);
5933
5934 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5935
5936 return 0;
5937 }
5938
5939 static int atlas7_gpio_get_value(struct gpio_chip *chip,
5940 unsigned int gpio)
5941 {
5942 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5943 struct atlas7_gpio_bank *bank;
5944 u32 val, pin_in_bank;
5945 unsigned long flags;
5946
5947 bank = atlas7_gpio_to_bank(a7gc, gpio);
5948 pin_in_bank = gpio - bank->gpio_offset;
5949
5950 raw_spin_lock_irqsave(&a7gc->lock, flags);
5951
5952 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5953
5954 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5955
5956 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
5957 }
5958
5959 static void atlas7_gpio_set_value(struct gpio_chip *chip,
5960 unsigned int gpio, int value)
5961 {
5962 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5963 struct atlas7_gpio_bank *bank;
5964 void __iomem *ctrl_reg;
5965 u32 ctrl, pin_in_bank;
5966 unsigned long flags;
5967
5968 bank = atlas7_gpio_to_bank(a7gc, gpio);
5969 pin_in_bank = gpio - bank->gpio_offset;
5970 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5971
5972 raw_spin_lock_irqsave(&a7gc->lock, flags);
5973
5974 ctrl = readl(ctrl_reg);
5975 if (value)
5976 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5977 else
5978 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5979 writel(ctrl, ctrl_reg);
5980
5981 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5982 }
5983
5984 static const struct of_device_id atlas7_gpio_ids[] = {
5985 { .compatible = "sirf,atlas7-gpio", },
5986 {},
5987 };
5988
5989 static int atlas7_gpio_probe(struct platform_device *pdev)
5990 {
5991 struct device_node *np = pdev->dev.of_node;
5992 struct atlas7_gpio_chip *a7gc;
5993 struct gpio_chip *chip;
5994 u32 nbank;
5995 int ret, idx;
5996 struct gpio_irq_chip *girq;
5997
5998 ret = of_property_read_u32(np, "gpio-banks", &nbank);
5999 if (ret) {
6000 dev_err(&pdev->dev,
6001 "Could not find GPIO bank info,ret=%d!\n",
6002 ret);
6003 return ret;
6004 }
6005
6006 /* retrieve gpio descriptor data */
6007 a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
6008 GFP_KERNEL);
6009 if (!a7gc)
6010 return -ENOMEM;
6011
6012 /* Get Gpio clk */
6013 a7gc->clk = of_clk_get(np, 0);
6014 if (!IS_ERR(a7gc->clk)) {
6015 ret = clk_prepare_enable(a7gc->clk);
6016 if (ret) {
6017 dev_err(&pdev->dev,
6018 "Could not enable clock!\n");
6019 return ret;
6020 }
6021 }
6022
6023 /* Get Gpio Registers */
6024 a7gc->reg = of_iomap(np, 0);
6025 if (!a7gc->reg) {
6026 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
6027 return -ENOMEM;
6028 }
6029
6030 a7gc->nbank = nbank;
6031 raw_spin_lock_init(&a7gc->lock);
6032
6033 /* Setup GPIO Chip */
6034 chip = &a7gc->chip;
6035 chip->request = atlas7_gpio_request;
6036 chip->free = atlas7_gpio_free;
6037 chip->direction_input = atlas7_gpio_direction_input;
6038 chip->get = atlas7_gpio_get_value;
6039 chip->direction_output = atlas7_gpio_direction_output;
6040 chip->set = atlas7_gpio_set_value;
6041 chip->base = -1;
6042 /* Each chip can support 32 pins at one bank */
6043 chip->ngpio = NGPIO_OF_BANK * nbank;
6044 chip->label = kstrdup(np->name, GFP_KERNEL);
6045 chip->of_node = np;
6046 chip->of_gpio_n_cells = 2;
6047 chip->parent = &pdev->dev;
6048
6049 girq = &chip->irq;
6050 girq->chip = &atlas7_gpio_irq_chip;
6051 girq->parent_handler = atlas7_gpio_handle_irq;
6052 girq->num_parents = nbank;
6053 girq->parents = devm_kcalloc(&pdev->dev, nbank,
6054 sizeof(*girq->parents),
6055 GFP_KERNEL);
6056 if (!girq->parents)
6057 return -ENOMEM;
6058 for (idx = 0; idx < nbank; idx++) {
6059 struct atlas7_gpio_bank *bank;
6060
6061 bank = &a7gc->banks[idx];
6062 /* Set ctrl registers' base of this bank */
6063 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6064 bank->gpio_offset = idx * NGPIO_OF_BANK;
6065
6066 /* Get interrupt number from DTS */
6067 ret = of_irq_get(np, idx);
6068 if (ret <= 0) {
6069 dev_err(&pdev->dev,
6070 "Unable to find IRQ number. ret=%d\n", ret);
6071 if (!ret)
6072 ret = -ENXIO;
6073 goto failed;
6074 }
6075 bank->irq = ret;
6076 girq->parents[idx] = ret;
6077 }
6078 girq->default_type = IRQ_TYPE_NONE;
6079 girq->handler = handle_level_irq;
6080
6081 /* Add gpio chip to system */
6082 ret = gpiochip_add_data(chip, a7gc);
6083 if (ret) {
6084 dev_err(&pdev->dev,
6085 "%pOF: error in probe function with status %d\n",
6086 np, ret);
6087 goto failed;
6088 }
6089
6090 platform_set_drvdata(pdev, a7gc);
6091 dev_info(&pdev->dev, "add to system.\n");
6092 return 0;
6093 failed:
6094 return ret;
6095 }
6096
6097 #ifdef CONFIG_PM_SLEEP
6098 static int atlas7_gpio_suspend_noirq(struct device *dev)
6099 {
6100 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6101 struct atlas7_gpio_bank *bank;
6102 void __iomem *ctrl_reg;
6103 u32 idx, pin;
6104
6105 for (idx = 0; idx < a7gc->nbank; idx++) {
6106 bank = &a7gc->banks[idx];
6107 for (pin = 0; pin < bank->ngpio; pin++) {
6108 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6109 bank->sleep_data[pin] = readl(ctrl_reg);
6110 }
6111 }
6112
6113 return 0;
6114 }
6115
6116 static int atlas7_gpio_resume_noirq(struct device *dev)
6117 {
6118 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6119 struct atlas7_gpio_bank *bank;
6120 void __iomem *ctrl_reg;
6121 u32 idx, pin;
6122
6123 for (idx = 0; idx < a7gc->nbank; idx++) {
6124 bank = &a7gc->banks[idx];
6125 for (pin = 0; pin < bank->ngpio; pin++) {
6126 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6127 writel(bank->sleep_data[pin], ctrl_reg);
6128 }
6129 }
6130
6131 return 0;
6132 }
6133
6134 static const struct dev_pm_ops atlas7_gpio_pm_ops = {
6135 .suspend_noirq = atlas7_gpio_suspend_noirq,
6136 .resume_noirq = atlas7_gpio_resume_noirq,
6137 .freeze_noirq = atlas7_gpio_suspend_noirq,
6138 .restore_noirq = atlas7_gpio_resume_noirq,
6139 };
6140 #endif
6141
6142 static struct platform_driver atlas7_gpio_driver = {
6143 .driver = {
6144 .name = "atlas7-gpio",
6145 .of_match_table = atlas7_gpio_ids,
6146 #ifdef CONFIG_PM_SLEEP
6147 .pm = &atlas7_gpio_pm_ops,
6148 #endif
6149 },
6150 .probe = atlas7_gpio_probe,
6151 };
6152
6153 static int __init atlas7_gpio_init(void)
6154 {
6155 return platform_driver_register(&atlas7_gpio_driver);
6156 }
6157 subsys_initcall(atlas7_gpio_init);
Linux with added FPC-III support