drivers/pinctrl/sunxi/pinctrl-sunxi.h

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #ifndef __PINCTRL_SUNXI_H
  14 #define __PINCTRL_SUNXI_H
  15
  16 #include <linux/kernel.h>
  17 #include <linux/spinlock.h>
  18
  19 #define PA_BASE 0
  20 #define PB_BASE 32
  21 #define PC_BASE 64
  22 #define PD_BASE 96
  23 #define PE_BASE 128
  24 #define PF_BASE 160
  25 #define PG_BASE 192
  26 #define PH_BASE 224
  27 #define PI_BASE 256
  28 #define PL_BASE 352
  29 #define PM_BASE 384
  30 #define PN_BASE 416
  31
  32 #define SUNXI_PINCTRL_PIN(bank, pin)            \
  33         PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
  34
  35 #define SUNXI_PIN_NAME_MAX_LEN  5
  36
  37 #define BANK_MEM_SIZE           0x24
  38 #define MUX_REGS_OFFSET         0x0
  39 #define DATA_REGS_OFFSET        0x10
  40 #define DLEVEL_REGS_OFFSET      0x14
  41 #define PULL_REGS_OFFSET        0x1c
  42
  43 #define PINS_PER_BANK           32
  44 #define MUX_PINS_PER_REG        8
  45 #define MUX_PINS_BITS           4
  46 #define MUX_PINS_MASK           0x0f
  47 #define DATA_PINS_PER_REG       32
  48 #define DATA_PINS_BITS          1
  49 #define DATA_PINS_MASK          0x01
  50 #define DLEVEL_PINS_PER_REG     16
  51 #define DLEVEL_PINS_BITS        2
  52 #define DLEVEL_PINS_MASK        0x03
  53 #define PULL_PINS_PER_REG       16
  54 #define PULL_PINS_BITS          2
  55 #define PULL_PINS_MASK          0x03
  56
  57 #define IRQ_PER_BANK            32
  58
  59 #define IRQ_CFG_REG             0x200
  60 #define IRQ_CFG_IRQ_PER_REG             8
  61 #define IRQ_CFG_IRQ_BITS                4
  62 #define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
  63 #define IRQ_CTRL_REG            0x210
  64 #define IRQ_CTRL_IRQ_PER_REG            32
  65 #define IRQ_CTRL_IRQ_BITS               1
  66 #define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
  67 #define IRQ_STATUS_REG          0x214
  68 #define IRQ_STATUS_IRQ_PER_REG          32
  69 #define IRQ_STATUS_IRQ_BITS             1
  70 #define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
  71
  72 #define IRQ_DEBOUNCE_REG        0x218
  73
  74 #define IRQ_MEM_SIZE            0x20
  75
  76 #define IRQ_EDGE_RISING         0x00
  77 #define IRQ_EDGE_FALLING        0x01
  78 #define IRQ_LEVEL_HIGH          0x02
  79 #define IRQ_LEVEL_LOW           0x03
  80 #define IRQ_EDGE_BOTH           0x04
  81
  82 #define GRP_CFG_REG             0x300
  83
  84 #define IO_BIAS_MASK            GENMASK(3, 0)
  85
  86 #define SUN4I_FUNC_INPUT        0
  87 #define SUN4I_FUNC_IRQ          6
  88
  89 #define PINCTRL_SUN5I_A10S      BIT(1)
  90 #define PINCTRL_SUN5I_A13       BIT(2)
  91 #define PINCTRL_SUN5I_GR8       BIT(3)
  92 #define PINCTRL_SUN6I_A31       BIT(4)
  93 #define PINCTRL_SUN6I_A31S      BIT(5)
  94 #define PINCTRL_SUN4I_A10       BIT(6)
  95 #define PINCTRL_SUN7I_A20       BIT(7)
  96 #define PINCTRL_SUN8I_R40       BIT(8)
  97 #define PINCTRL_SUN8I_V3        BIT(9)
  98 #define PINCTRL_SUN8I_V3S       BIT(10)
  99
 100 #define PIO_POW_MOD_SEL_REG     0x340
 101
 102 enum sunxi_desc_bias_voltage {
 103         BIAS_VOLTAGE_NONE,
 104         /*
 105          * Bias voltage configuration is done through
 106          * Pn_GRP_CONFIG registers, as seen on A80 SoC.
 107          */
 108         BIAS_VOLTAGE_GRP_CONFIG,
 109         /*
 110          * Bias voltage is set through PIO_POW_MOD_SEL_REG
 111          * register, as seen on H6 SoC, for example.
 112          */
 113         BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 114 };
 115
 116 struct sunxi_desc_function {
 117         unsigned long   variant;
 118         const char      *name;
 119         u8              muxval;
 120         u8              irqbank;
 121         u8              irqnum;
 122 };
 123
 124 struct sunxi_desc_pin {
 125         struct pinctrl_pin_desc         pin;
 126         unsigned long                   variant;
 127         struct sunxi_desc_function      *functions;
 128 };
 129
 130 struct sunxi_pinctrl_desc {
 131         const struct sunxi_desc_pin     *pins;
 132         int                             npins;
 133         unsigned                        pin_base;
 134         unsigned                        irq_banks;
 135         const unsigned int              *irq_bank_map;
 136         bool                            irq_read_needs_mux;
 137         bool                            disable_strict_mode;
 138         enum sunxi_desc_bias_voltage    io_bias_cfg_variant;
 139 };
 140
 141 struct sunxi_pinctrl_function {
 142         const char      *name;
 143         const char      **groups;
 144         unsigned        ngroups;
 145 };
 146
 147 struct sunxi_pinctrl_group {
 148         const char      *name;
 149         unsigned        pin;
 150 };
 151
 152 struct sunxi_pinctrl_regulator {
 153         struct regulator        *regulator;
 154         refcount_t              refcount;
 155 };
 156
 157 struct sunxi_pinctrl {
 158         void __iomem                    *membase;
 159         struct gpio_chip                *chip;
 160         const struct sunxi_pinctrl_desc *desc;
 161         struct device                   *dev;
 162         struct sunxi_pinctrl_regulator  regulators[9];
 163         struct irq_domain               *domain;
 164         struct sunxi_pinctrl_function   *functions;
 165         unsigned                        nfunctions;
 166         struct sunxi_pinctrl_group      *groups;
 167         unsigned                        ngroups;
 168         int                             *irq;
 169         unsigned                        *irq_array;
 170         raw_spinlock_t                  lock;
 171         struct pinctrl_dev              *pctl_dev;
 172         unsigned long                   variant;
 173 };
 174
 175 #define SUNXI_PIN(_pin, ...)                                    \
 176         {                                                       \
 177                 .pin = _pin,                                    \
 178                 .functions = (struct sunxi_desc_function[]){    \
 179                         __VA_ARGS__, { } },                     \
 180         }
 181
 182 #define SUNXI_PIN_VARIANT(_pin, _variant, ...)                  \
 183         {                                                       \
 184                 .pin = _pin,                                    \
 185                 .variant = _variant,                            \
 186                 .functions = (struct sunxi_desc_function[]){    \
 187                         __VA_ARGS__, { } },                     \
 188         }
 189
 190 #define SUNXI_FUNCTION(_val, _name)                             \
 191         {                                                       \
 192                 .name = _name,                                  \
 193                 .muxval = _val,                                 \
 194         }
 195
 196 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant)           \
 197         {                                                       \
 198                 .name = _name,                                  \
 199                 .muxval = _val,                                 \
 200                 .variant = _variant,                            \
 201         }
 202
 203 #define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
 204         {                                                       \
 205                 .name = "irq",                                  \
 206                 .muxval = _val,                                 \
 207                 .irqnum = _irq,                                 \
 208         }
 209
 210 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)              \
 211         {                                                       \
 212                 .name = "irq",                                  \
 213                 .muxval = _val,                                 \
 214                 .irqbank = _bank,                               \
 215                 .irqnum = _irq,                                 \
 216         }
 217
 218 /*
 219  * The sunXi PIO registers are organized as is:
 220  * 0x00 - 0x0c  Muxing values.
 221  *              8 pins per register, each pin having a 4bits value
 222  * 0x10         Pin values
 223  *              32 bits per register, each pin corresponding to one bit
 224  * 0x14 - 0x18  Drive level
 225  *              16 pins per register, each pin having a 2bits value
 226  * 0x1c - 0x20  Pull-Up values
 227  *              16 pins per register, each pin having a 2bits value
 228  *
 229  * This is for the first bank. Each bank will have the same layout,
 230  * with an offset being a multiple of 0x24.
 231  *
 232  * The following functions calculate from the pin number the register
 233  * and the bit offset that we should access.
 234  */
 235 static inline u32 sunxi_mux_reg(u16 pin)
 236 {
 237         u8 bank = pin / PINS_PER_BANK;
 238         u32 offset = bank * BANK_MEM_SIZE;
 239         offset += MUX_REGS_OFFSET;
 240         offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
 241         return round_down(offset, 4);
 242 }
 243
 244 static inline u32 sunxi_mux_offset(u16 pin)
 245 {
 246         u32 pin_num = pin % MUX_PINS_PER_REG;
 247         return pin_num * MUX_PINS_BITS;
 248 }
 249
 250 static inline u32 sunxi_data_reg(u16 pin)
 251 {
 252         u8 bank = pin / PINS_PER_BANK;
 253         u32 offset = bank * BANK_MEM_SIZE;
 254         offset += DATA_REGS_OFFSET;
 255         offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
 256         return round_down(offset, 4);
 257 }
 258
 259 static inline u32 sunxi_data_offset(u16 pin)
 260 {
 261         u32 pin_num = pin % DATA_PINS_PER_REG;
 262         return pin_num * DATA_PINS_BITS;
 263 }
 264
 265 static inline u32 sunxi_dlevel_reg(u16 pin)
 266 {
 267         u8 bank = pin / PINS_PER_BANK;
 268         u32 offset = bank * BANK_MEM_SIZE;
 269         offset += DLEVEL_REGS_OFFSET;
 270         offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
 271         return round_down(offset, 4);
 272 }
 273
 274 static inline u32 sunxi_dlevel_offset(u16 pin)
 275 {
 276         u32 pin_num = pin % DLEVEL_PINS_PER_REG;
 277         return pin_num * DLEVEL_PINS_BITS;
 278 }
 279
 280 static inline u32 sunxi_pull_reg(u16 pin)
 281 {
 282         u8 bank = pin / PINS_PER_BANK;
 283         u32 offset = bank * BANK_MEM_SIZE;
 284         offset += PULL_REGS_OFFSET;
 285         offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
 286         return round_down(offset, 4);
 287 }
 288
 289 static inline u32 sunxi_pull_offset(u16 pin)
 290 {
 291         u32 pin_num = pin % PULL_PINS_PER_REG;
 292         return pin_num * PULL_PINS_BITS;
 293 }
 294
 295 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
 296 {
 297         if (!desc->irq_bank_map)
 298                 return bank;
 299         else
 300                 return desc->irq_bank_map[bank];
 301 }
 302
 303 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
 304                                     u16 irq)
 305 {
 306         u8 bank = irq / IRQ_PER_BANK;
 307         u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
 308
 309         return IRQ_CFG_REG +
 310                sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
 311 }
 312
 313 static inline u32 sunxi_irq_cfg_offset(u16 irq)
 314 {
 315         u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
 316         return irq_num * IRQ_CFG_IRQ_BITS;
 317 }
 318
 319 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 320 {
 321         return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
 322 }
 323
 324 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
 325                                      u16 irq)
 326 {
 327         u8 bank = irq / IRQ_PER_BANK;
 328
 329         return sunxi_irq_ctrl_reg_from_bank(desc, bank);
 330 }
 331
 332 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
 333 {
 334         u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
 335         return irq_num * IRQ_CTRL_IRQ_BITS;
 336 }
 337
 338 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 339 {
 340         return IRQ_DEBOUNCE_REG +
 341                sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
 342 }
 343
 344 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
 345 {
 346         return IRQ_STATUS_REG +
 347                sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
 348 }
 349
 350 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
 351                                        u16 irq)
 352 {
 353         u8 bank = irq / IRQ_PER_BANK;
 354
 355         return sunxi_irq_status_reg_from_bank(desc, bank);
 356 }
 357
 358 static inline u32 sunxi_irq_status_offset(u16 irq)
 359 {
 360         u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
 361         return irq_num * IRQ_STATUS_IRQ_BITS;
 362 }
 363
 364 static inline u32 sunxi_grp_config_reg(u16 pin)
 365 {
 366         u8 bank = pin / PINS_PER_BANK;
 367
 368         return GRP_CFG_REG + bank * 0x4;
 369 }
 370
 371 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
 372                                     const struct sunxi_pinctrl_desc *desc,
 373                                     unsigned long variant);
 374
 375 #define sunxi_pinctrl_init(_dev, _desc) \
 376         sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
 377
 378 #endif /* __PINCTRL_SUNXI_H */