1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
12 #include "bfa_modules.h"
15 BFA_TRC_FILE(HAL
, IOCFC_CT
);
18 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
21 bfa_hwct_msix_dummy(struct bfa_s
*bfa
, int vec
)
26 bfa_hwct_reginit(struct bfa_s
*bfa
)
28 struct bfa_iocfc_regs_s
*bfa_regs
= &bfa
->iocfc
.bfa_regs
;
29 void __iomem
*kva
= bfa_ioc_bar0(&bfa
->ioc
);
30 int fn
= bfa_ioc_pcifn(&bfa
->ioc
);
33 bfa_regs
->intr_status
= (kva
+ HOSTFN0_INT_STATUS
);
34 bfa_regs
->intr_mask
= (kva
+ HOSTFN0_INT_MSK
);
36 bfa_regs
->intr_status
= (kva
+ HOSTFN1_INT_STATUS
);
37 bfa_regs
->intr_mask
= (kva
+ HOSTFN1_INT_MSK
);
42 bfa_hwct2_reginit(struct bfa_s
*bfa
)
44 struct bfa_iocfc_regs_s
*bfa_regs
= &bfa
->iocfc
.bfa_regs
;
45 void __iomem
*kva
= bfa_ioc_bar0(&bfa
->ioc
);
47 bfa_regs
->intr_status
= (kva
+ CT2_HOSTFN_INT_STATUS
);
48 bfa_regs
->intr_mask
= (kva
+ CT2_HOSTFN_INTR_MASK
);
52 bfa_hwct_reqq_ack(struct bfa_s
*bfa
, int reqq
)
56 r32
= readl(bfa
->iocfc
.bfa_regs
.cpe_q_ctrl
[reqq
]);
57 writel(r32
, bfa
->iocfc
.bfa_regs
.cpe_q_ctrl
[reqq
]);
61 * Actions to respond RME Interrupt for Catapult ASIC:
62 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
63 * - Acknowledge by writing to RME Queue Control register
67 bfa_hwct_rspq_ack(struct bfa_s
*bfa
, int rspq
, u32 ci
)
71 r32
= readl(bfa
->iocfc
.bfa_regs
.rme_q_ctrl
[rspq
]);
72 writel(r32
, bfa
->iocfc
.bfa_regs
.rme_q_ctrl
[rspq
]);
74 bfa_rspq_ci(bfa
, rspq
) = ci
;
75 writel(ci
, bfa
->iocfc
.bfa_regs
.rme_q_ci
[rspq
]);
79 * Actions to respond RME Interrupt for Catapult2 ASIC:
80 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
84 bfa_hwct2_rspq_ack(struct bfa_s
*bfa
, int rspq
, u32 ci
)
86 bfa_rspq_ci(bfa
, rspq
) = ci
;
87 writel(ci
, bfa
->iocfc
.bfa_regs
.rme_q_ci
[rspq
]);
91 bfa_hwct_msix_getvecs(struct bfa_s
*bfa
, u32
*msix_vecs_bmap
,
92 u32
*num_vecs
, u32
*max_vec_bit
)
94 *msix_vecs_bmap
= (1 << BFI_MSIX_CT_MAX
) - 1;
95 *max_vec_bit
= (1 << (BFI_MSIX_CT_MAX
- 1));
96 *num_vecs
= BFI_MSIX_CT_MAX
;
100 * Setup MSI-X vector for catapult
103 bfa_hwct_msix_init(struct bfa_s
*bfa
, int nvecs
)
105 WARN_ON((nvecs
!= 1) && (nvecs
!= BFI_MSIX_CT_MAX
));
108 bfa
->msix
.nvecs
= nvecs
;
109 bfa_hwct_msix_uninstall(bfa
);
113 bfa_hwct_msix_ctrl_install(struct bfa_s
*bfa
)
115 if (bfa
->msix
.nvecs
== 0)
118 if (bfa
->msix
.nvecs
== 1)
119 bfa
->msix
.handler
[BFI_MSIX_LPU_ERR_CT
] = bfa_msix_all
;
121 bfa
->msix
.handler
[BFI_MSIX_LPU_ERR_CT
] = bfa_msix_lpu_err
;
125 bfa_hwct_msix_queue_install(struct bfa_s
*bfa
)
129 if (bfa
->msix
.nvecs
== 0)
132 if (bfa
->msix
.nvecs
== 1) {
133 for (i
= BFI_MSIX_CPE_QMIN_CT
; i
< BFI_MSIX_CT_MAX
; i
++)
134 bfa
->msix
.handler
[i
] = bfa_msix_all
;
138 for (i
= BFI_MSIX_CPE_QMIN_CT
; i
<= BFI_MSIX_CPE_QMAX_CT
; i
++)
139 bfa
->msix
.handler
[i
] = bfa_msix_reqq
;
141 for (i
= BFI_MSIX_RME_QMIN_CT
; i
<= BFI_MSIX_RME_QMAX_CT
; i
++)
142 bfa
->msix
.handler
[i
] = bfa_msix_rspq
;
146 bfa_hwct_msix_uninstall(struct bfa_s
*bfa
)
150 for (i
= 0; i
< BFI_MSIX_CT_MAX
; i
++)
151 bfa
->msix
.handler
[i
] = bfa_hwct_msix_dummy
;
155 * Enable MSI-X vectors
158 bfa_hwct_isr_mode_set(struct bfa_s
*bfa
, bfa_boolean_t msix
)
161 bfa_ioc_isr_mode_set(&bfa
->ioc
, msix
);
165 bfa_hwct_msix_get_rme_range(struct bfa_s
*bfa
, u32
*start
, u32
*end
)
167 *start
= BFI_MSIX_RME_QMIN_CT
;
168 *end
= BFI_MSIX_RME_QMAX_CT
;