drivers/scsi/ipr.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * ipr.h -- driver for IBM Power Linux RAID adapters
   4  *
   5  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
   6  *
   7  * Copyright (C) 2003, 2004 IBM Corporation
   8  *
   9  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
  10  *                              that broke 64bit platforms.
  11  */
  12
  13 #ifndef _IPR_H
  14 #define _IPR_H
  15
  16 #include <asm/unaligned.h>
  17 #include <linux/types.h>
  18 #include <linux/completion.h>
  19 #include <linux/libata.h>
  20 #include <linux/list.h>
  21 #include <linux/kref.h>
  22 #include <linux/irq_poll.h>
  23 #include <scsi/scsi.h>
  24 #include <scsi/scsi_cmnd.h>
  25
  26 /*
  27  * Literals
  28  */
  29 #define IPR_DRIVER_VERSION "2.6.4"
  30 #define IPR_DRIVER_DATE "(March 14, 2017)"
  31
  32 /*
  33  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  34  *      ops per device for devices not running tagged command queuing.
  35  *      This can be adjusted at runtime through sysfs device attributes.
  36  */
  37 #define IPR_MAX_CMD_PER_LUN                             6
  38 #define IPR_MAX_CMD_PER_ATA_LUN                 1
  39
  40 /*
  41  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  42  *      ops the mid-layer can send to the adapter.
  43  */
  44 #define IPR_NUM_BASE_CMD_BLKS                   (ioa_cfg->max_cmds)
  45
  46 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E    0x0339
  47
  48 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
  49 #define PCI_DEVICE_ID_IBM_CROCODILE             0x034A
  50 #define PCI_DEVICE_ID_IBM_RATTLESNAKE           0x04DA
  51
  52 #define IPR_SUBS_DEV_ID_2780    0x0264
  53 #define IPR_SUBS_DEV_ID_5702    0x0266
  54 #define IPR_SUBS_DEV_ID_5703    0x0278
  55 #define IPR_SUBS_DEV_ID_572E    0x028D
  56 #define IPR_SUBS_DEV_ID_573E    0x02D3
  57 #define IPR_SUBS_DEV_ID_573D    0x02D4
  58 #define IPR_SUBS_DEV_ID_571A    0x02C0
  59 #define IPR_SUBS_DEV_ID_571B    0x02BE
  60 #define IPR_SUBS_DEV_ID_571E    0x02BF
  61 #define IPR_SUBS_DEV_ID_571F    0x02D5
  62 #define IPR_SUBS_DEV_ID_572A    0x02C1
  63 #define IPR_SUBS_DEV_ID_572B    0x02C2
  64 #define IPR_SUBS_DEV_ID_572F    0x02C3
  65 #define IPR_SUBS_DEV_ID_574E    0x030A
  66 #define IPR_SUBS_DEV_ID_575B    0x030D
  67 #define IPR_SUBS_DEV_ID_575C    0x0338
  68 #define IPR_SUBS_DEV_ID_57B3    0x033A
  69 #define IPR_SUBS_DEV_ID_57B7    0x0360
  70 #define IPR_SUBS_DEV_ID_57B8    0x02C2
  71
  72 #define IPR_SUBS_DEV_ID_57B4    0x033B
  73 #define IPR_SUBS_DEV_ID_57B2    0x035F
  74 #define IPR_SUBS_DEV_ID_57C0    0x0352
  75 #define IPR_SUBS_DEV_ID_57C3    0x0353
  76 #define IPR_SUBS_DEV_ID_57C4    0x0354
  77 #define IPR_SUBS_DEV_ID_57C6    0x0357
  78 #define IPR_SUBS_DEV_ID_57CC    0x035C
  79
  80 #define IPR_SUBS_DEV_ID_57B5    0x033C
  81 #define IPR_SUBS_DEV_ID_57CE    0x035E
  82 #define IPR_SUBS_DEV_ID_57B1    0x0355
  83
  84 #define IPR_SUBS_DEV_ID_574D    0x0356
  85 #define IPR_SUBS_DEV_ID_57C8    0x035D
  86
  87 #define IPR_SUBS_DEV_ID_57D5    0x03FB
  88 #define IPR_SUBS_DEV_ID_57D6    0x03FC
  89 #define IPR_SUBS_DEV_ID_57D7    0x03FF
  90 #define IPR_SUBS_DEV_ID_57D8    0x03FE
  91 #define IPR_SUBS_DEV_ID_57D9    0x046D
  92 #define IPR_SUBS_DEV_ID_57DA    0x04CA
  93 #define IPR_SUBS_DEV_ID_57EB    0x0474
  94 #define IPR_SUBS_DEV_ID_57EC    0x0475
  95 #define IPR_SUBS_DEV_ID_57ED    0x0499
  96 #define IPR_SUBS_DEV_ID_57EE    0x049A
  97 #define IPR_SUBS_DEV_ID_57EF    0x049B
  98 #define IPR_SUBS_DEV_ID_57F0    0x049C
  99 #define IPR_SUBS_DEV_ID_2CCA    0x04C7
 100 #define IPR_SUBS_DEV_ID_2CD2    0x04C8
 101 #define IPR_SUBS_DEV_ID_2CCD    0x04C9
 102 #define IPR_SUBS_DEV_ID_580A    0x04FC
 103 #define IPR_SUBS_DEV_ID_580B    0x04FB
 104 #define IPR_NAME                                "ipr"
 105
 106 /*
 107  * Return codes
 108  */
 109 #define IPR_RC_JOB_CONTINUE             1
 110 #define IPR_RC_JOB_RETURN               2
 111
 112 /*
 113  * IOASCs
 114  */
 115 #define IPR_IOASC_NR_INIT_CMD_REQUIRED          0x02040200
 116 #define IPR_IOASC_NR_IOA_RESET_REQUIRED         0x02048000
 117 #define IPR_IOASC_SYNC_REQUIRED                 0x023f0000
 118 #define IPR_IOASC_MED_DO_NOT_REALLOC            0x03110C00
 119 #define IPR_IOASC_HW_SEL_TIMEOUT                        0x04050000
 120 #define IPR_IOASC_HW_DEV_BUS_STATUS                     0x04448500
 121 #define IPR_IOASC_IOASC_MASK                    0xFFFFFF00
 122 #define IPR_IOASC_SCSI_STATUS_MASK              0x000000FF
 123 #define IPR_IOASC_HW_CMD_FAILED                 0x046E0000
 124 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT    0x05240000
 125 #define IPR_IOASC_IR_RESOURCE_HANDLE            0x05250000
 126 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA         0x05258100
 127 #define IPR_IOASA_IR_DUAL_IOA_DISABLED          0x052C8000
 128 #define IPR_IOASC_BUS_WAS_RESET                 0x06290000
 129 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER                0x06298000
 130 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST      0x0B5A0000
 131 #define IPR_IOASC_IR_NON_OPTIMIZED              0x05258200
 132
 133 #define IPR_FIRST_DRIVER_IOASC                  0x10000000
 134 #define IPR_IOASC_IOA_WAS_RESET                 0x10000001
 135 #define IPR_IOASC_PCI_ACCESS_ERROR                      0x10000002
 136
 137 /* Driver data flags */
 138 #define IPR_USE_LONG_TRANSOP_TIMEOUT            0x00000001
 139 #define IPR_USE_PCI_WARM_RESET                  0x00000002
 140
 141 #define IPR_DEFAULT_MAX_ERROR_DUMP                      984
 142 #define IPR_NUM_LOG_HCAMS                               2
 143 #define IPR_NUM_CFG_CHG_HCAMS                           2
 144 #define IPR_NUM_HCAM_QUEUE                              12
 145 #define IPR_NUM_HCAMS   (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
 146 #define IPR_MAX_HCAMS   (IPR_NUM_HCAMS + IPR_NUM_HCAM_QUEUE)
 147
 148 #define IPR_MAX_SIS64_TARGETS_PER_BUS                   1024
 149 #define IPR_MAX_SIS64_LUNS_PER_TARGET                   0xffffffff
 150
 151 #define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 152 #define IPR_MAX_NUM_LUNS_PER_TARGET                     256
 153 #define IPR_VSET_BUS                                    0xff
 154 #define IPR_IOA_BUS                                             0xff
 155 #define IPR_IOA_TARGET                                  0xff
 156 #define IPR_IOA_LUN                                             0xff
 157 #define IPR_MAX_NUM_BUSES                               16
 158
 159 #define IPR_NUM_RESET_RELOAD_RETRIES            3
 160
 161 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
 162 #define IPR_NUM_INTERNAL_CMD_BLKS       (IPR_NUM_HCAMS + \
 163                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 164
 165 #define IPR_MAX_COMMANDS                100
 166 #define IPR_NUM_CMD_BLKS                (IPR_NUM_BASE_CMD_BLKS + \
 167                                                 IPR_NUM_INTERNAL_CMD_BLKS)
 168
 169 #define IPR_MAX_PHYSICAL_DEVS                           192
 170 #define IPR_DEFAULT_SIS64_DEVS                          1024
 171 #define IPR_MAX_SIS64_DEVS                              4096
 172
 173 #define IPR_MAX_SGLIST                                  64
 174 #define IPR_IOA_MAX_SECTORS                             32767
 175 #define IPR_VSET_MAX_SECTORS                            512
 176 #define IPR_MAX_CDB_LEN                                 16
 177 #define IPR_MAX_HRRQ_RETRIES                            3
 178
 179 #define IPR_DEFAULT_BUS_WIDTH                           16
 180 #define IPR_80MBs_SCSI_RATE             ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 181 #define IPR_U160_SCSI_RATE      ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 182 #define IPR_U320_SCSI_RATE      ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 183 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
 184
 185 #define IPR_IOA_RES_HANDLE                              0xffffffff
 186 #define IPR_INVALID_RES_HANDLE                  0
 187 #define IPR_IOA_RES_ADDR                                0x00ffffff
 188
 189 /*
 190  * Adapter Commands
 191  */
 192 #define IPR_CANCEL_REQUEST                              0xC0
 193 #define IPR_CANCEL_64BIT_IOARCB                 0x01
 194 #define IPR_QUERY_RSRC_STATE                            0xC2
 195 #define IPR_RESET_DEVICE                                0xC3
 196 #define IPR_RESET_TYPE_SELECT                           0x80
 197 #define IPR_LUN_RESET                                   0x40
 198 #define IPR_TARGET_RESET                                        0x20
 199 #define IPR_BUS_RESET                                   0x10
 200 #define IPR_ATA_PHY_RESET                                       0x80
 201 #define IPR_ID_HOST_RR_Q                                0xC4
 202 #define IPR_QUERY_IOA_CONFIG                            0xC5
 203 #define IPR_CANCEL_ALL_REQUESTS                 0xCE
 204 #define IPR_HOST_CONTROLLED_ASYNC                       0xCF
 205 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE      0x01
 206 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA           0x02
 207 #define IPR_SET_SUPPORTED_DEVICES                       0xFB
 208 #define IPR_SET_ALL_SUPPORTED_DEVICES                   0x80
 209 #define IPR_IOA_SHUTDOWN                                0xF7
 210 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE                    0x05
 211 #define IPR_IOA_SERVICE_ACTION                          0xD2
 212
 213 /* IOA Service Actions */
 214 #define IPR_IOA_SA_CHANGE_CACHE_PARAMS                  0x14
 215
 216 /*
 217  * Timeouts
 218  */
 219 #define IPR_SHUTDOWN_TIMEOUT                    (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
 220 #define IPR_VSET_RW_TIMEOUT                     (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
 221 #define IPR_ABBREV_SHUTDOWN_TIMEOUT             (10 * HZ)
 222 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO   (2 * 60 * HZ)
 223 #define IPR_DEVICE_RESET_TIMEOUT                (ipr_fastfail ? 10 * HZ : 30 * HZ)
 224 #define IPR_CANCEL_TIMEOUT                      (ipr_fastfail ? 10 * HZ : 30 * HZ)
 225 #define IPR_CANCEL_ALL_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 226 #define IPR_ABORT_TASK_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 227 #define IPR_INTERNAL_TIMEOUT                    (ipr_fastfail ? 10 * HZ : 30 * HZ)
 228 #define IPR_WRITE_BUFFER_TIMEOUT                (30 * 60 * HZ)
 229 #define IPR_SET_SUP_DEVICE_TIMEOUT              (2 * 60 * HZ)
 230 #define IPR_REQUEST_SENSE_TIMEOUT               (10 * HZ)
 231 #define IPR_OPERATIONAL_TIMEOUT         (5 * 60)
 232 #define IPR_LONG_OPERATIONAL_TIMEOUT    (12 * 60)
 233 #define IPR_WAIT_FOR_RESET_TIMEOUT              (2 * HZ)
 234 #define IPR_CHECK_FOR_RESET_TIMEOUT             (HZ / 10)
 235 #define IPR_WAIT_FOR_BIST_TIMEOUT               (2 * HZ)
 236 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT  (120 * HZ)
 237 #define IPR_PCI_RESET_TIMEOUT                   (HZ / 2)
 238 #define IPR_SIS32_DUMP_TIMEOUT                  (15 * HZ)
 239 #define IPR_SIS64_DUMP_TIMEOUT                  (40 * HZ)
 240 #define IPR_DUMP_DELAY_SECONDS                  4
 241 #define IPR_DUMP_DELAY_TIMEOUT                  (IPR_DUMP_DELAY_SECONDS * HZ)
 242
 243 /*
 244  * SCSI Literals
 245  */
 246 #define IPR_VENDOR_ID_LEN                       8
 247 #define IPR_PROD_ID_LEN                         16
 248 #define IPR_SERIAL_NUM_LEN                      8
 249
 250 /*
 251  * Hardware literals
 252  */
 253 #define IPR_FMT2_MBX_ADDR_MASK                          0x0fffffff
 254 #define IPR_FMT2_MBX_BAR_SEL_MASK                       0xf0000000
 255 #define IPR_FMT2_MKR_BAR_SEL_SHIFT                      28
 256 #define IPR_GET_FMT2_BAR_SEL(mbx) \
 257 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
 258 #define IPR_SDT_FMT2_BAR0_SEL                           0x0
 259 #define IPR_SDT_FMT2_BAR1_SEL                           0x1
 260 #define IPR_SDT_FMT2_BAR2_SEL                           0x2
 261 #define IPR_SDT_FMT2_BAR3_SEL                           0x3
 262 #define IPR_SDT_FMT2_BAR4_SEL                           0x4
 263 #define IPR_SDT_FMT2_BAR5_SEL                           0x5
 264 #define IPR_SDT_FMT2_EXP_ROM_SEL                        0x8
 265 #define IPR_FMT2_SDT_READY_TO_USE                       0xC4D4E3F2
 266 #define IPR_FMT3_SDT_READY_TO_USE                       0xC4D4E3F3
 267 #define IPR_DOORBELL                                    0x82800000
 268 #define IPR_RUNTIME_RESET                               0x40000000
 269
 270 #define IPR_IPL_INIT_MIN_STAGE_TIME                     5
 271 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 30
 272 #define IPR_IPL_INIT_STAGE_UNKNOWN                      0x0
 273 #define IPR_IPL_INIT_STAGE_TRANSOP                      0xB0000000
 274 #define IPR_IPL_INIT_STAGE_MASK                         0xff000000
 275 #define IPR_IPL_INIT_STAGE_TIME_MASK                    0x0000ffff
 276 #define IPR_PCII_IPL_STAGE_CHANGE                       (0x80000000 >> 0)
 277
 278 #define IPR_PCII_MAILBOX_STABLE                         (0x80000000 >> 4)
 279 #define IPR_WAIT_FOR_MAILBOX                            (2 * HZ)
 280
 281 #define IPR_PCII_IOA_TRANS_TO_OPER                      (0x80000000 >> 0)
 282 #define IPR_PCII_IOARCB_XFER_FAILED                     (0x80000000 >> 3)
 283 #define IPR_PCII_IOA_UNIT_CHECKED                       (0x80000000 >> 4)
 284 #define IPR_PCII_NO_HOST_RRQ                            (0x80000000 >> 5)
 285 #define IPR_PCII_CRITICAL_OPERATION                     (0x80000000 >> 6)
 286 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE           (0x80000000 >> 7)
 287 #define IPR_PCII_IOARRIN_LOST                           (0x80000000 >> 27)
 288 #define IPR_PCII_MMIO_ERROR                             (0x80000000 >> 28)
 289 #define IPR_PCII_PROC_ERR_STATE                 (0x80000000 >> 29)
 290 #define IPR_PCII_HRRQ_UPDATED                           (0x80000000 >> 30)
 291 #define IPR_PCII_CORE_ISSUED_RST_REQ            (0x80000000 >> 31)
 292
 293 #define IPR_PCII_ERROR_INTERRUPTS \
 294 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
 295 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
 296
 297 #define IPR_PCII_OPER_INTERRUPTS \
 298 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
 299
 300 #define IPR_UPROCI_RESET_ALERT                  (0x80000000 >> 7)
 301 #define IPR_UPROCI_IO_DEBUG_ALERT                       (0x80000000 >> 9)
 302 #define IPR_UPROCI_SIS64_START_BIST                     (0x80000000 >> 23)
 303
 304 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC            200000  /* 200 ms */
 305 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC           200000  /* 200 ms */
 306
 307 /*
 308  * Dump literals
 309  */
 310 #define IPR_FMT2_MAX_IOA_DUMP_SIZE                      (4 * 1024 * 1024)
 311 #define IPR_FMT3_MAX_IOA_DUMP_SIZE                      (80 * 1024 * 1024)
 312 #define IPR_FMT2_NUM_SDT_ENTRIES                        511
 313 #define IPR_FMT3_NUM_SDT_ENTRIES                        0xFFF
 314 #define IPR_FMT2_MAX_NUM_DUMP_PAGES     ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 315 #define IPR_FMT3_MAX_NUM_DUMP_PAGES     ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 316
 317 /*
 318  * Misc literals
 319  */
 320 #define IPR_NUM_IOADL_ENTRIES                   IPR_MAX_SGLIST
 321 #define IPR_MAX_MSIX_VECTORS            0x10
 322 #define IPR_MAX_HRRQ_NUM                0x10
 323 #define IPR_INIT_HRRQ                   0x0
 324
 325 /*
 326  * Adapter interface types
 327  */
 328
 329 struct ipr_res_addr {
 330         u8 reserved;
 331         u8 bus;
 332         u8 target;
 333         u8 lun;
 334 #define IPR_GET_PHYS_LOC(res_addr) \
 335         (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
 336 }__attribute__((packed, aligned (4)));
 337
 338 struct ipr_std_inq_vpids {
 339         u8 vendor_id[IPR_VENDOR_ID_LEN];
 340         u8 product_id[IPR_PROD_ID_LEN];
 341 }__attribute__((packed));
 342
 343 struct ipr_vpd {
 344         struct ipr_std_inq_vpids vpids;
 345         u8 sn[IPR_SERIAL_NUM_LEN];
 346 }__attribute__((packed));
 347
 348 struct ipr_ext_vpd {
 349         struct ipr_vpd vpd;
 350         __be32 wwid[2];
 351 }__attribute__((packed));
 352
 353 struct ipr_ext_vpd64 {
 354         struct ipr_vpd vpd;
 355         __be32 wwid[4];
 356 }__attribute__((packed));
 357
 358 struct ipr_std_inq_data {
 359         u8 peri_qual_dev_type;
 360 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
 361 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
 362
 363         u8 removeable_medium_rsvd;
 364 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
 365
 366 #define IPR_IS_DASD_DEVICE(std_inq) \
 367 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
 368 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
 369
 370 #define IPR_IS_SES_DEVICE(std_inq) \
 371 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
 372
 373         u8 version;
 374         u8 aen_naca_fmt;
 375         u8 additional_len;
 376         u8 sccs_rsvd;
 377         u8 bq_enc_multi;
 378         u8 sync_cmdq_flags;
 379
 380         struct ipr_std_inq_vpids vpids;
 381
 382         u8 ros_rsvd_ram_rsvd[4];
 383
 384         u8 serial_num[IPR_SERIAL_NUM_LEN];
 385 }__attribute__ ((packed));
 386
 387 #define IPR_RES_TYPE_AF_DASD            0x00
 388 #define IPR_RES_TYPE_GENERIC_SCSI       0x01
 389 #define IPR_RES_TYPE_VOLUME_SET         0x02
 390 #define IPR_RES_TYPE_REMOTE_AF_DASD     0x03
 391 #define IPR_RES_TYPE_GENERIC_ATA        0x04
 392 #define IPR_RES_TYPE_ARRAY              0x05
 393 #define IPR_RES_TYPE_IOAFP              0xff
 394
 395 struct ipr_config_table_entry {
 396         u8 proto;
 397 #define IPR_PROTO_SATA                  0x02
 398 #define IPR_PROTO_SATA_ATAPI            0x03
 399 #define IPR_PROTO_SAS_STP               0x06
 400 #define IPR_PROTO_SAS_STP_ATAPI         0x07
 401         u8 array_id;
 402         u8 flags;
 403 #define IPR_IS_IOA_RESOURCE             0x80
 404         u8 rsvd_subtype;
 405
 406 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
 407 #define IPR_QUEUE_FROZEN_MODEL          0
 408 #define IPR_QUEUE_NACA_MODEL            1
 409
 410         struct ipr_res_addr res_addr;
 411         __be32 res_handle;
 412         __be32 lun_wwn[2];
 413         struct ipr_std_inq_data std_inq_data;
 414 }__attribute__ ((packed, aligned (4)));
 415
 416 struct ipr_config_table_entry64 {
 417         u8 res_type;
 418         u8 proto;
 419         u8 vset_num;
 420         u8 array_id;
 421         __be16 flags;
 422         __be16 res_flags;
 423 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
 424         __be32 res_handle;
 425         u8 dev_id_type;
 426         u8 reserved[3];
 427         __be64 dev_id;
 428         __be64 lun;
 429         __be64 lun_wwn[2];
 430 #define IPR_MAX_RES_PATH_LENGTH         48
 431         __be64 res_path;
 432         struct ipr_std_inq_data std_inq_data;
 433         u8 reserved2[4];
 434         __be64 reserved3[2];
 435         u8 reserved4[8];
 436 }__attribute__ ((packed, aligned (8)));
 437
 438 struct ipr_config_table_hdr {
 439         u8 num_entries;
 440         u8 flags;
 441 #define IPR_UCODE_DOWNLOAD_REQ  0x10
 442         __be16 reserved;
 443 }__attribute__((packed, aligned (4)));
 444
 445 struct ipr_config_table_hdr64 {
 446         __be16 num_entries;
 447         __be16 reserved;
 448         u8 flags;
 449         u8 reserved2[11];
 450 }__attribute__((packed, aligned (4)));
 451
 452 struct ipr_config_table {
 453         struct ipr_config_table_hdr hdr;
 454         struct ipr_config_table_entry dev[];
 455 }__attribute__((packed, aligned (4)));
 456
 457 struct ipr_config_table64 {
 458         struct ipr_config_table_hdr64 hdr64;
 459         struct ipr_config_table_entry64 dev[];
 460 }__attribute__((packed, aligned (8)));
 461
 462 struct ipr_config_table_entry_wrapper {
 463         union {
 464                 struct ipr_config_table_entry *cfgte;
 465                 struct ipr_config_table_entry64 *cfgte64;
 466         } u;
 467 };
 468
 469 struct ipr_hostrcb_cfg_ch_not {
 470         union {
 471                 struct ipr_config_table_entry cfgte;
 472                 struct ipr_config_table_entry64 cfgte64;
 473         } u;
 474         u8 reserved[936];
 475 }__attribute__((packed, aligned (4)));
 476
 477 struct ipr_supported_device {
 478         __be16 data_length;
 479         u8 reserved;
 480         u8 num_records;
 481         struct ipr_std_inq_vpids vpids;
 482         u8 reserved2[16];
 483 }__attribute__((packed, aligned (4)));
 484
 485 struct ipr_hrr_queue {
 486         struct ipr_ioa_cfg *ioa_cfg;
 487         __be32 *host_rrq;
 488         dma_addr_t host_rrq_dma;
 489 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK   0xfffffffc
 490 #define IPR_HRRQ_RESP_BIT_SET           0x00000002
 491 #define IPR_HRRQ_TOGGLE_BIT             0x00000001
 492 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT  2
 493 #define IPR_ID_HRRQ_SELE_ENABLE         0x02
 494         volatile __be32 *hrrq_start;
 495         volatile __be32 *hrrq_end;
 496         volatile __be32 *hrrq_curr;
 497
 498         struct list_head hrrq_free_q;
 499         struct list_head hrrq_pending_q;
 500         spinlock_t _lock;
 501         spinlock_t *lock;
 502
 503         volatile u32 toggle_bit;
 504         u32 size;
 505         u32 min_cmd_id;
 506         u32 max_cmd_id;
 507         u8 allow_interrupts:1;
 508         u8 ioa_is_dead:1;
 509         u8 allow_cmds:1;
 510         u8 removing_ioa:1;
 511
 512         struct irq_poll iopoll;
 513 };
 514
 515 /* Command packet structure */
 516 struct ipr_cmd_pkt {
 517         u8 reserved;            /* Reserved by IOA */
 518         u8 hrrq_id;
 519         u8 request_type;
 520 #define IPR_RQTYPE_SCSICDB              0x00
 521 #define IPR_RQTYPE_IOACMD               0x01
 522 #define IPR_RQTYPE_HCAM                 0x02
 523 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
 524 #define IPR_RQTYPE_PIPE                 0x05
 525
 526         u8 reserved2;
 527
 528         u8 flags_hi;
 529 #define IPR_FLAGS_HI_WRITE_NOT_READ             0x80
 530 #define IPR_FLAGS_HI_NO_ULEN_CHK                0x20
 531 #define IPR_FLAGS_HI_SYNC_OVERRIDE              0x10
 532 #define IPR_FLAGS_HI_SYNC_COMPLETE              0x08
 533 #define IPR_FLAGS_HI_NO_LINK_DESC               0x04
 534
 535         u8 flags_lo;
 536 #define IPR_FLAGS_LO_ALIGNED_BFR                0x20
 537 #define IPR_FLAGS_LO_DELAY_AFTER_RST            0x10
 538 #define IPR_FLAGS_LO_UNTAGGED_TASK              0x00
 539 #define IPR_FLAGS_LO_SIMPLE_TASK                0x02
 540 #define IPR_FLAGS_LO_ORDERED_TASK               0x04
 541 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK             0x06
 542 #define IPR_FLAGS_LO_ACA_TASK                   0x08
 543
 544         u8 cdb[16];
 545         __be16 timeout;
 546 }__attribute__ ((packed, aligned(4)));
 547
 548 struct ipr_ioarcb_ata_regs {    /* 22 bytes */
 549         u8 flags;
 550 #define IPR_ATA_FLAG_PACKET_CMD                 0x80
 551 #define IPR_ATA_FLAG_XFER_TYPE_DMA                      0x40
 552 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION  0x20
 553         u8 reserved[3];
 554
 555         __be16 data;
 556         u8 feature;
 557         u8 nsect;
 558         u8 lbal;
 559         u8 lbam;
 560         u8 lbah;
 561         u8 device;
 562         u8 command;
 563         u8 reserved2[3];
 564         u8 hob_feature;
 565         u8 hob_nsect;
 566         u8 hob_lbal;
 567         u8 hob_lbam;
 568         u8 hob_lbah;
 569         u8 ctl;
 570 }__attribute__ ((packed, aligned(2)));
 571
 572 struct ipr_ioadl_desc {
 573         __be32 flags_and_data_len;
 574 #define IPR_IOADL_FLAGS_MASK            0xff000000
 575 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
 576 #define IPR_IOADL_DATA_LEN_MASK         0x00ffffff
 577 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
 578 #define IPR_IOADL_FLAGS_READ            0x48000000
 579 #define IPR_IOADL_FLAGS_READ_LAST       0x49000000
 580 #define IPR_IOADL_FLAGS_WRITE           0x68000000
 581 #define IPR_IOADL_FLAGS_WRITE_LAST      0x69000000
 582 #define IPR_IOADL_FLAGS_LAST            0x01000000
 583
 584         __be32 address;
 585 }__attribute__((packed, aligned (8)));
 586
 587 struct ipr_ioadl64_desc {
 588         __be32 flags;
 589         __be32 data_len;
 590         __be64 address;
 591 }__attribute__((packed, aligned (16)));
 592
 593 struct ipr_ata64_ioadl {
 594         struct ipr_ioarcb_ata_regs regs;
 595         u16 reserved[5];
 596         struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
 597 }__attribute__((packed, aligned (16)));
 598
 599 struct ipr_ioarcb_add_data {
 600         union {
 601                 struct ipr_ioarcb_ata_regs regs;
 602                 struct ipr_ioadl_desc ioadl[5];
 603                 __be32 add_cmd_parms[10];
 604         } u;
 605 }__attribute__ ((packed, aligned (4)));
 606
 607 struct ipr_ioarcb_sis64_add_addr_ecb {
 608         __be64 ioasa_host_pci_addr;
 609         __be64 data_ioadl_addr;
 610         __be64 reserved;
 611         __be32 ext_control_buf[4];
 612 }__attribute__((packed, aligned (8)));
 613
 614 /* IOA Request Control Block    128 bytes  */
 615 struct ipr_ioarcb {
 616         union {
 617                 __be32 ioarcb_host_pci_addr;
 618                 __be64 ioarcb_host_pci_addr64;
 619         } a;
 620         __be32 res_handle;
 621         __be32 host_response_handle;
 622         __be32 reserved1;
 623         __be32 reserved2;
 624         __be32 reserved3;
 625
 626         __be32 data_transfer_length;
 627         __be32 read_data_transfer_length;
 628         __be32 write_ioadl_addr;
 629         __be32 ioadl_len;
 630         __be32 read_ioadl_addr;
 631         __be32 read_ioadl_len;
 632
 633         __be32 ioasa_host_pci_addr;
 634         __be16 ioasa_len;
 635         __be16 reserved4;
 636
 637         struct ipr_cmd_pkt cmd_pkt;
 638
 639         __be16 add_cmd_parms_offset;
 640         __be16 add_cmd_parms_len;
 641
 642         union {
 643                 struct ipr_ioarcb_add_data add_data;
 644                 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
 645         } u;
 646
 647 }__attribute__((packed, aligned (4)));
 648
 649 struct ipr_ioasa_vset {
 650         __be32 failing_lba_hi;
 651         __be32 failing_lba_lo;
 652         __be32 reserved;
 653 }__attribute__((packed, aligned (4)));
 654
 655 struct ipr_ioasa_af_dasd {
 656         __be32 failing_lba;
 657         __be32 reserved[2];
 658 }__attribute__((packed, aligned (4)));
 659
 660 struct ipr_ioasa_gpdd {
 661         u8 end_state;
 662         u8 bus_phase;
 663         __be16 reserved;
 664         __be32 ioa_data[2];
 665 }__attribute__((packed, aligned (4)));
 666
 667 struct ipr_ioasa_gata {
 668         u8 error;
 669         u8 nsect;               /* Interrupt reason */
 670         u8 lbal;
 671         u8 lbam;
 672         u8 lbah;
 673         u8 device;
 674         u8 status;
 675         u8 alt_status;  /* ATA CTL */
 676         u8 hob_nsect;
 677         u8 hob_lbal;
 678         u8 hob_lbam;
 679         u8 hob_lbah;
 680 }__attribute__((packed, aligned (4)));
 681
 682 struct ipr_auto_sense {
 683         __be16 auto_sense_len;
 684         __be16 ioa_data_len;
 685         __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
 686 };
 687
 688 struct ipr_ioasa_hdr {
 689         __be32 ioasc;
 690 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
 691 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
 692 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
 693 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
 694
 695         __be16 ret_stat_len;    /* Length of the returned IOASA */
 696
 697         __be16 avail_stat_len;  /* Total Length of status available. */
 698
 699         __be32 residual_data_len;       /* number of bytes in the host data */
 700         /* buffers that were not used by the IOARCB command. */
 701
 702         __be32 ilid;
 703 #define IPR_NO_ILID                     0
 704 #define IPR_DRIVER_ILID         0xffffffff
 705
 706         __be32 fd_ioasc;
 707
 708         __be32 fd_phys_locator;
 709
 710         __be32 fd_res_handle;
 711
 712         __be32 ioasc_specific;  /* status code specific field */
 713 #define IPR_ADDITIONAL_STATUS_FMT               0x80000000
 714 #define IPR_AUTOSENSE_VALID                     0x40000000
 715 #define IPR_ATA_DEVICE_WAS_RESET                0x20000000
 716 #define IPR_IOASC_SPECIFIC_MASK         0x00ffffff
 717 #define IPR_FIELD_POINTER_VALID         (0x80000000 >> 8)
 718 #define IPR_FIELD_POINTER_MASK          0x0000ffff
 719
 720 }__attribute__((packed, aligned (4)));
 721
 722 struct ipr_ioasa {
 723         struct ipr_ioasa_hdr hdr;
 724
 725         union {
 726                 struct ipr_ioasa_vset vset;
 727                 struct ipr_ioasa_af_dasd dasd;
 728                 struct ipr_ioasa_gpdd gpdd;
 729                 struct ipr_ioasa_gata gata;
 730         } u;
 731
 732         struct ipr_auto_sense auto_sense;
 733 }__attribute__((packed, aligned (4)));
 734
 735 struct ipr_ioasa64 {
 736         struct ipr_ioasa_hdr hdr;
 737         u8 fd_res_path[8];
 738
 739         union {
 740                 struct ipr_ioasa_vset vset;
 741                 struct ipr_ioasa_af_dasd dasd;
 742                 struct ipr_ioasa_gpdd gpdd;
 743                 struct ipr_ioasa_gata gata;
 744         } u;
 745
 746         struct ipr_auto_sense auto_sense;
 747 }__attribute__((packed, aligned (4)));
 748
 749 struct ipr_mode_parm_hdr {
 750         u8 length;
 751         u8 medium_type;
 752         u8 device_spec_parms;
 753         u8 block_desc_len;
 754 }__attribute__((packed));
 755
 756 struct ipr_mode_pages {
 757         struct ipr_mode_parm_hdr hdr;
 758         u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
 759 }__attribute__((packed));
 760
 761 struct ipr_mode_page_hdr {
 762         u8 ps_page_code;
 763 #define IPR_MODE_PAGE_PS        0x80
 764 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
 765         u8 page_length;
 766 }__attribute__ ((packed));
 767
 768 struct ipr_dev_bus_entry {
 769         struct ipr_res_addr res_addr;
 770         u8 flags;
 771 #define IPR_SCSI_ATTR_ENABLE_QAS                        0x80
 772 #define IPR_SCSI_ATTR_DISABLE_QAS                       0x40
 773 #define IPR_SCSI_ATTR_QAS_MASK                          0xC0
 774 #define IPR_SCSI_ATTR_ENABLE_TM                         0x20
 775 #define IPR_SCSI_ATTR_NO_TERM_PWR                       0x10
 776 #define IPR_SCSI_ATTR_TM_SUPPORTED                      0x08
 777 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED     0x04
 778
 779         u8 scsi_id;
 780         u8 bus_width;
 781         u8 extended_reset_delay;
 782 #define IPR_EXTENDED_RESET_DELAY        7
 783
 784         __be32 max_xfer_rate;
 785
 786         u8 spinup_delay;
 787         u8 reserved3;
 788         __be16 reserved4;
 789 }__attribute__((packed, aligned (4)));
 790
 791 struct ipr_mode_page28 {
 792         struct ipr_mode_page_hdr hdr;
 793         u8 num_entries;
 794         u8 entry_length;
 795         struct ipr_dev_bus_entry bus[];
 796 }__attribute__((packed));
 797
 798 struct ipr_mode_page24 {
 799         struct ipr_mode_page_hdr hdr;
 800         u8 flags;
 801 #define IPR_ENABLE_DUAL_IOA_AF 0x80
 802 }__attribute__((packed));
 803
 804 struct ipr_ioa_vpd {
 805         struct ipr_std_inq_data std_inq_data;
 806         u8 ascii_part_num[12];
 807         u8 reserved[40];
 808         u8 ascii_plant_code[4];
 809 }__attribute__((packed));
 810
 811 struct ipr_inquiry_page3 {
 812         u8 peri_qual_dev_type;
 813         u8 page_code;
 814         u8 reserved1;
 815         u8 page_length;
 816         u8 ascii_len;
 817         u8 reserved2[3];
 818         u8 load_id[4];
 819         u8 major_release;
 820         u8 card_type;
 821         u8 minor_release[2];
 822         u8 ptf_number[4];
 823         u8 patch_number[4];
 824 }__attribute__((packed));
 825
 826 struct ipr_inquiry_cap {
 827         u8 peri_qual_dev_type;
 828         u8 page_code;
 829         u8 reserved1;
 830         u8 page_length;
 831         u8 ascii_len;
 832         u8 reserved2;
 833         u8 sis_version[2];
 834         u8 cap;
 835 #define IPR_CAP_DUAL_IOA_RAID           0x80
 836         u8 reserved3[15];
 837 }__attribute__((packed));
 838
 839 #define IPR_INQUIRY_PAGE0_ENTRIES 20
 840 struct ipr_inquiry_page0 {
 841         u8 peri_qual_dev_type;
 842         u8 page_code;
 843         u8 reserved1;
 844         u8 len;
 845         u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
 846 }__attribute__((packed));
 847
 848 struct ipr_inquiry_pageC4 {
 849         u8 peri_qual_dev_type;
 850         u8 page_code;
 851         u8 reserved1;
 852         u8 len;
 853         u8 cache_cap[4];
 854 #define IPR_CAP_SYNC_CACHE              0x08
 855         u8 reserved2[20];
 856 } __packed;
 857
 858 struct ipr_hostrcb_device_data_entry {
 859         struct ipr_vpd vpd;
 860         struct ipr_res_addr dev_res_addr;
 861         struct ipr_vpd new_vpd;
 862         struct ipr_vpd ioa_last_with_dev_vpd;
 863         struct ipr_vpd cfc_last_with_dev_vpd;
 864         __be32 ioa_data[5];
 865 }__attribute__((packed, aligned (4)));
 866
 867 struct ipr_hostrcb_device_data_entry_enhanced {
 868         struct ipr_ext_vpd vpd;
 869         u8 ccin[4];
 870         struct ipr_res_addr dev_res_addr;
 871         struct ipr_ext_vpd new_vpd;
 872         u8 new_ccin[4];
 873         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 874         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 875 }__attribute__((packed, aligned (4)));
 876
 877 struct ipr_hostrcb64_device_data_entry_enhanced {
 878         struct ipr_ext_vpd vpd;
 879         u8 ccin[4];
 880         u8 res_path[8];
 881         struct ipr_ext_vpd new_vpd;
 882         u8 new_ccin[4];
 883         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 884         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 885 }__attribute__((packed, aligned (4)));
 886
 887 struct ipr_hostrcb_array_data_entry {
 888         struct ipr_vpd vpd;
 889         struct ipr_res_addr expected_dev_res_addr;
 890         struct ipr_res_addr dev_res_addr;
 891 }__attribute__((packed, aligned (4)));
 892
 893 struct ipr_hostrcb64_array_data_entry {
 894         struct ipr_ext_vpd vpd;
 895         u8 ccin[4];
 896         u8 expected_res_path[8];
 897         u8 res_path[8];
 898 }__attribute__((packed, aligned (4)));
 899
 900 struct ipr_hostrcb_array_data_entry_enhanced {
 901         struct ipr_ext_vpd vpd;
 902         u8 ccin[4];
 903         struct ipr_res_addr expected_dev_res_addr;
 904         struct ipr_res_addr dev_res_addr;
 905 }__attribute__((packed, aligned (4)));
 906
 907 struct ipr_hostrcb_type_ff_error {
 908         __be32 ioa_data[758];
 909 }__attribute__((packed, aligned (4)));
 910
 911 struct ipr_hostrcb_type_01_error {
 912         __be32 seek_counter;
 913         __be32 read_counter;
 914         u8 sense_data[32];
 915         __be32 ioa_data[236];
 916 }__attribute__((packed, aligned (4)));
 917
 918 struct ipr_hostrcb_type_21_error {
 919         __be32 wwn[4];
 920         u8 res_path[8];
 921         u8 primary_problem_desc[32];
 922         u8 second_problem_desc[32];
 923         __be32 sense_data[8];
 924         __be32 cdb[4];
 925         __be32 residual_trans_length;
 926         __be32 length_of_error;
 927         __be32 ioa_data[236];
 928 }__attribute__((packed, aligned (4)));
 929
 930 struct ipr_hostrcb_type_02_error {
 931         struct ipr_vpd ioa_vpd;
 932         struct ipr_vpd cfc_vpd;
 933         struct ipr_vpd ioa_last_attached_to_cfc_vpd;
 934         struct ipr_vpd cfc_last_attached_to_ioa_vpd;
 935         __be32 ioa_data[3];
 936 }__attribute__((packed, aligned (4)));
 937
 938 struct ipr_hostrcb_type_12_error {
 939         struct ipr_ext_vpd ioa_vpd;
 940         struct ipr_ext_vpd cfc_vpd;
 941         struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
 942         struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
 943         __be32 ioa_data[3];
 944 }__attribute__((packed, aligned (4)));
 945
 946 struct ipr_hostrcb_type_03_error {
 947         struct ipr_vpd ioa_vpd;
 948         struct ipr_vpd cfc_vpd;
 949         __be32 errors_detected;
 950         __be32 errors_logged;
 951         u8 ioa_data[12];
 952         struct ipr_hostrcb_device_data_entry dev[3];
 953 }__attribute__((packed, aligned (4)));
 954
 955 struct ipr_hostrcb_type_13_error {
 956         struct ipr_ext_vpd ioa_vpd;
 957         struct ipr_ext_vpd cfc_vpd;
 958         __be32 errors_detected;
 959         __be32 errors_logged;
 960         struct ipr_hostrcb_device_data_entry_enhanced dev[3];
 961 }__attribute__((packed, aligned (4)));
 962
 963 struct ipr_hostrcb_type_23_error {
 964         struct ipr_ext_vpd ioa_vpd;
 965         struct ipr_ext_vpd cfc_vpd;
 966         __be32 errors_detected;
 967         __be32 errors_logged;
 968         struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
 969 }__attribute__((packed, aligned (4)));
 970
 971 struct ipr_hostrcb_type_04_error {
 972         struct ipr_vpd ioa_vpd;
 973         struct ipr_vpd cfc_vpd;
 974         u8 ioa_data[12];
 975         struct ipr_hostrcb_array_data_entry array_member[10];
 976         __be32 exposed_mode_adn;
 977         __be32 array_id;
 978         struct ipr_vpd incomp_dev_vpd;
 979         __be32 ioa_data2;
 980         struct ipr_hostrcb_array_data_entry array_member2[8];
 981         struct ipr_res_addr last_func_vset_res_addr;
 982         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 983         u8 protection_level[8];
 984 }__attribute__((packed, aligned (4)));
 985
 986 struct ipr_hostrcb_type_14_error {
 987         struct ipr_ext_vpd ioa_vpd;
 988         struct ipr_ext_vpd cfc_vpd;
 989         __be32 exposed_mode_adn;
 990         __be32 array_id;
 991         struct ipr_res_addr last_func_vset_res_addr;
 992         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 993         u8 protection_level[8];
 994         __be32 num_entries;
 995         struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
 996 }__attribute__((packed, aligned (4)));
 997
 998 struct ipr_hostrcb_type_24_error {
 999         struct ipr_ext_vpd ioa_vpd;
1000         struct ipr_ext_vpd cfc_vpd;
1001         u8 reserved[2];
1002         u8 exposed_mode_adn;
1003 #define IPR_INVALID_ARRAY_DEV_NUM               0xff
1004         u8 array_id;
1005         u8 last_res_path[8];
1006         u8 protection_level[8];
1007         struct ipr_ext_vpd64 array_vpd;
1008         u8 description[16];
1009         u8 reserved2[3];
1010         u8 num_entries;
1011         struct ipr_hostrcb64_array_data_entry array_member[32];
1012 }__attribute__((packed, aligned (4)));
1013
1014 struct ipr_hostrcb_type_07_error {
1015         u8 failure_reason[64];
1016         struct ipr_vpd vpd;
1017         __be32 data[222];
1018 }__attribute__((packed, aligned (4)));
1019
1020 struct ipr_hostrcb_type_17_error {
1021         u8 failure_reason[64];
1022         struct ipr_ext_vpd vpd;
1023         __be32 data[476];
1024 }__attribute__((packed, aligned (4)));
1025
1026 struct ipr_hostrcb_config_element {
1027         u8 type_status;
1028 #define IPR_PATH_CFG_TYPE_MASK  0xF0
1029 #define IPR_PATH_CFG_NOT_EXIST  0x00
1030 #define IPR_PATH_CFG_IOA_PORT           0x10
1031 #define IPR_PATH_CFG_EXP_PORT           0x20
1032 #define IPR_PATH_CFG_DEVICE_PORT        0x30
1033 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1034
1035 #define IPR_PATH_CFG_STATUS_MASK        0x0F
1036 #define IPR_PATH_CFG_NO_PROB            0x00
1037 #define IPR_PATH_CFG_DEGRADED           0x01
1038 #define IPR_PATH_CFG_FAILED             0x02
1039 #define IPR_PATH_CFG_SUSPECT            0x03
1040 #define IPR_PATH_NOT_DETECTED           0x04
1041 #define IPR_PATH_INCORRECT_CONN 0x05
1042
1043         u8 cascaded_expander;
1044         u8 phy;
1045         u8 link_rate;
1046 #define IPR_PHY_LINK_RATE_MASK  0x0F
1047
1048         __be32 wwid[2];
1049 }__attribute__((packed, aligned (4)));
1050
1051 struct ipr_hostrcb64_config_element {
1052         __be16 length;
1053         u8 descriptor_id;
1054 #define IPR_DESCRIPTOR_MASK             0xC0
1055 #define IPR_DESCRIPTOR_SIS64            0x00
1056
1057         u8 reserved;
1058         u8 type_status;
1059
1060         u8 reserved2[2];
1061         u8 link_rate;
1062
1063         u8 res_path[8];
1064         __be32 wwid[2];
1065 }__attribute__((packed, aligned (8)));
1066
1067 struct ipr_hostrcb_fabric_desc {
1068         __be16 length;
1069         u8 ioa_port;
1070         u8 cascaded_expander;
1071         u8 phy;
1072         u8 path_state;
1073 #define IPR_PATH_ACTIVE_MASK            0xC0
1074 #define IPR_PATH_NO_INFO                0x00
1075 #define IPR_PATH_ACTIVE                 0x40
1076 #define IPR_PATH_NOT_ACTIVE             0x80
1077
1078 #define IPR_PATH_STATE_MASK             0x0F
1079 #define IPR_PATH_STATE_NO_INFO  0x00
1080 #define IPR_PATH_HEALTHY                0x01
1081 #define IPR_PATH_DEGRADED               0x02
1082 #define IPR_PATH_FAILED                 0x03
1083
1084         __be16 num_entries;
1085         struct ipr_hostrcb_config_element elem[1];
1086 }__attribute__((packed, aligned (4)));
1087
1088 struct ipr_hostrcb64_fabric_desc {
1089         __be16 length;
1090         u8 descriptor_id;
1091
1092         u8 reserved[2];
1093         u8 path_state;
1094
1095         u8 reserved2[2];
1096         u8 res_path[8];
1097         u8 reserved3[6];
1098         __be16 num_entries;
1099         struct ipr_hostrcb64_config_element elem[1];
1100 }__attribute__((packed, aligned (8)));
1101
1102 #define for_each_hrrq(hrrq, ioa_cfg) \
1103                 for (hrrq = (ioa_cfg)->hrrq; \
1104                         hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1105
1106 #define for_each_fabric_cfg(fabric, cfg) \
1107                 for (cfg = (fabric)->elem; \
1108                         cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1109                         cfg++)
1110
1111 struct ipr_hostrcb_type_20_error {
1112         u8 failure_reason[64];
1113         u8 reserved[3];
1114         u8 num_entries;
1115         struct ipr_hostrcb_fabric_desc desc[1];
1116 }__attribute__((packed, aligned (4)));
1117
1118 struct ipr_hostrcb_type_30_error {
1119         u8 failure_reason[64];
1120         u8 reserved[3];
1121         u8 num_entries;
1122         struct ipr_hostrcb64_fabric_desc desc[1];
1123 }__attribute__((packed, aligned (4)));
1124
1125 struct ipr_hostrcb_type_41_error {
1126         u8 failure_reason[64];
1127          __be32 data[200];
1128 }__attribute__((packed, aligned (4)));
1129
1130 struct ipr_hostrcb_error {
1131         __be32 fd_ioasc;
1132         struct ipr_res_addr fd_res_addr;
1133         __be32 fd_res_handle;
1134         __be32 prc;
1135         union {
1136                 struct ipr_hostrcb_type_ff_error type_ff_error;
1137                 struct ipr_hostrcb_type_01_error type_01_error;
1138                 struct ipr_hostrcb_type_02_error type_02_error;
1139                 struct ipr_hostrcb_type_03_error type_03_error;
1140                 struct ipr_hostrcb_type_04_error type_04_error;
1141                 struct ipr_hostrcb_type_07_error type_07_error;
1142                 struct ipr_hostrcb_type_12_error type_12_error;
1143                 struct ipr_hostrcb_type_13_error type_13_error;
1144                 struct ipr_hostrcb_type_14_error type_14_error;
1145                 struct ipr_hostrcb_type_17_error type_17_error;
1146                 struct ipr_hostrcb_type_20_error type_20_error;
1147         } u;
1148 }__attribute__((packed, aligned (4)));
1149
1150 struct ipr_hostrcb64_error {
1151         __be32 fd_ioasc;
1152         __be32 ioa_fw_level;
1153         __be32 fd_res_handle;
1154         __be32 prc;
1155         __be64 fd_dev_id;
1156         __be64 fd_lun;
1157         u8 fd_res_path[8];
1158         __be64 time_stamp;
1159         u8 reserved[16];
1160         union {
1161                 struct ipr_hostrcb_type_ff_error type_ff_error;
1162                 struct ipr_hostrcb_type_12_error type_12_error;
1163                 struct ipr_hostrcb_type_17_error type_17_error;
1164                 struct ipr_hostrcb_type_21_error type_21_error;
1165                 struct ipr_hostrcb_type_23_error type_23_error;
1166                 struct ipr_hostrcb_type_24_error type_24_error;
1167                 struct ipr_hostrcb_type_30_error type_30_error;
1168                 struct ipr_hostrcb_type_41_error type_41_error;
1169         } u;
1170 }__attribute__((packed, aligned (8)));
1171
1172 struct ipr_hostrcb_raw {
1173         __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1174 }__attribute__((packed, aligned (4)));
1175
1176 struct ipr_hcam {
1177         u8 op_code;
1178 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE                      0xE1
1179 #define IPR_HOST_RCB_OP_CODE_LOG_DATA                           0xE2
1180
1181         u8 notify_type;
1182 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED        0x00
1183 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY                       0x01
1184 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY                       0x02
1185 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY         0x10
1186 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY       0x11
1187
1188         u8 notifications_lost;
1189 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST                      0
1190 #define IPR_HOST_RCB_NOTIFICATIONS_LOST                         0x80
1191
1192         u8 flags;
1193 #define IPR_HOSTRCB_INTERNAL_OPER       0x80
1194 #define IPR_HOSTRCB_ERR_RESP_SENT       0x40
1195
1196         u8 overlay_id;
1197 #define IPR_HOST_RCB_OVERLAY_ID_1                               0x01
1198 #define IPR_HOST_RCB_OVERLAY_ID_2                               0x02
1199 #define IPR_HOST_RCB_OVERLAY_ID_3                               0x03
1200 #define IPR_HOST_RCB_OVERLAY_ID_4                               0x04
1201 #define IPR_HOST_RCB_OVERLAY_ID_6                               0x06
1202 #define IPR_HOST_RCB_OVERLAY_ID_7                               0x07
1203 #define IPR_HOST_RCB_OVERLAY_ID_12                              0x12
1204 #define IPR_HOST_RCB_OVERLAY_ID_13                              0x13
1205 #define IPR_HOST_RCB_OVERLAY_ID_14                              0x14
1206 #define IPR_HOST_RCB_OVERLAY_ID_16                              0x16
1207 #define IPR_HOST_RCB_OVERLAY_ID_17                              0x17
1208 #define IPR_HOST_RCB_OVERLAY_ID_20                              0x20
1209 #define IPR_HOST_RCB_OVERLAY_ID_21                              0x21
1210 #define IPR_HOST_RCB_OVERLAY_ID_23                              0x23
1211 #define IPR_HOST_RCB_OVERLAY_ID_24                              0x24
1212 #define IPR_HOST_RCB_OVERLAY_ID_26                              0x26
1213 #define IPR_HOST_RCB_OVERLAY_ID_30                              0x30
1214 #define IPR_HOST_RCB_OVERLAY_ID_41                              0x41
1215 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT                         0xFF
1216
1217         u8 reserved1[3];
1218         __be32 ilid;
1219         __be32 time_since_last_ioa_reset;
1220         __be32 reserved2;
1221         __be32 length;
1222
1223         union {
1224                 struct ipr_hostrcb_error error;
1225                 struct ipr_hostrcb64_error error64;
1226                 struct ipr_hostrcb_cfg_ch_not ccn;
1227                 struct ipr_hostrcb_raw raw;
1228         } u;
1229 }__attribute__((packed, aligned (4)));
1230
1231 struct ipr_hostrcb {
1232         struct ipr_hcam hcam;
1233         dma_addr_t hostrcb_dma;
1234         struct list_head queue;
1235         struct ipr_ioa_cfg *ioa_cfg;
1236         char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1237 };
1238
1239 /* IPR smart dump table structures */
1240 struct ipr_sdt_entry {
1241         __be32 start_token;
1242         __be32 end_token;
1243         u8 reserved[4];
1244
1245         u8 flags;
1246 #define IPR_SDT_ENDIAN          0x80
1247 #define IPR_SDT_VALID_ENTRY     0x20
1248
1249         u8 resv;
1250         __be16 priority;
1251 }__attribute__((packed, aligned (4)));
1252
1253 struct ipr_sdt_header {
1254         __be32 state;
1255         __be32 num_entries;
1256         __be32 num_entries_used;
1257         __be32 dump_size;
1258 }__attribute__((packed, aligned (4)));
1259
1260 struct ipr_sdt {
1261         struct ipr_sdt_header hdr;
1262         struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1263 }__attribute__((packed, aligned (4)));
1264
1265 struct ipr_uc_sdt {
1266         struct ipr_sdt_header hdr;
1267         struct ipr_sdt_entry entry[1];
1268 }__attribute__((packed, aligned (4)));
1269
1270 /*
1271  * Driver types
1272  */
1273 struct ipr_bus_attributes {
1274         u8 bus;
1275         u8 qas_enabled;
1276         u8 bus_width;
1277         u8 reserved;
1278         u32 max_xfer_rate;
1279 };
1280
1281 struct ipr_sata_port {
1282         struct ipr_ioa_cfg *ioa_cfg;
1283         struct ata_port *ap;
1284         struct ipr_resource_entry *res;
1285         struct ipr_ioasa_gata ioasa;
1286 };
1287
1288 struct ipr_resource_entry {
1289         u8 needs_sync_complete:1;
1290         u8 in_erp:1;
1291         u8 add_to_ml:1;
1292         u8 del_from_ml:1;
1293         u8 resetting_device:1;
1294         u8 reset_occurred:1;
1295         u8 raw_mode:1;
1296
1297         u32 bus;                /* AKA channel */
1298         u32 target;             /* AKA id */
1299         u32 lun;
1300 #define IPR_ARRAY_VIRTUAL_BUS                   0x1
1301 #define IPR_VSET_VIRTUAL_BUS                    0x2
1302 #define IPR_IOAFP_VIRTUAL_BUS                   0x3
1303 #define IPR_MAX_SIS64_BUSES                     0x4
1304
1305 #define IPR_GET_RES_PHYS_LOC(res) \
1306         (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1307
1308         u8 ata_class;
1309         u8 type;
1310
1311         u16 flags;
1312         u16 res_flags;
1313
1314         u8 qmodel;
1315         struct ipr_std_inq_data std_inq_data;
1316
1317         __be32 res_handle;
1318         __be64 dev_id;
1319         u64 lun_wwn;
1320         struct scsi_lun dev_lun;
1321         u8 res_path[8];
1322
1323         struct ipr_ioa_cfg *ioa_cfg;
1324         struct scsi_device *sdev;
1325         struct ipr_sata_port *sata_port;
1326         struct list_head queue;
1327 }; /* struct ipr_resource_entry */
1328
1329 struct ipr_resource_hdr {
1330         u16 num_entries;
1331         u16 reserved;
1332 };
1333
1334 struct ipr_misc_cbs {
1335         struct ipr_ioa_vpd ioa_vpd;
1336         struct ipr_inquiry_page0 page0_data;
1337         struct ipr_inquiry_page3 page3_data;
1338         struct ipr_inquiry_cap cap;
1339         struct ipr_inquiry_pageC4 pageC4_data;
1340         struct ipr_mode_pages mode_pages;
1341         struct ipr_supported_device supp_dev;
1342 };
1343
1344 struct ipr_interrupt_offsets {
1345         unsigned long set_interrupt_mask_reg;
1346         unsigned long clr_interrupt_mask_reg;
1347         unsigned long clr_interrupt_mask_reg32;
1348         unsigned long sense_interrupt_mask_reg;
1349         unsigned long sense_interrupt_mask_reg32;
1350         unsigned long clr_interrupt_reg;
1351         unsigned long clr_interrupt_reg32;
1352
1353         unsigned long sense_interrupt_reg;
1354         unsigned long sense_interrupt_reg32;
1355         unsigned long ioarrin_reg;
1356         unsigned long sense_uproc_interrupt_reg;
1357         unsigned long sense_uproc_interrupt_reg32;
1358         unsigned long set_uproc_interrupt_reg;
1359         unsigned long set_uproc_interrupt_reg32;
1360         unsigned long clr_uproc_interrupt_reg;
1361         unsigned long clr_uproc_interrupt_reg32;
1362
1363         unsigned long init_feedback_reg;
1364
1365         unsigned long dump_addr_reg;
1366         unsigned long dump_data_reg;
1367
1368 #define IPR_ENDIAN_SWAP_KEY             0x00080800
1369         unsigned long endian_swap_reg;
1370 };
1371
1372 struct ipr_interrupts {
1373         void __iomem *set_interrupt_mask_reg;
1374         void __iomem *clr_interrupt_mask_reg;
1375         void __iomem *clr_interrupt_mask_reg32;
1376         void __iomem *sense_interrupt_mask_reg;
1377         void __iomem *sense_interrupt_mask_reg32;
1378         void __iomem *clr_interrupt_reg;
1379         void __iomem *clr_interrupt_reg32;
1380
1381         void __iomem *sense_interrupt_reg;
1382         void __iomem *sense_interrupt_reg32;
1383         void __iomem *ioarrin_reg;
1384         void __iomem *sense_uproc_interrupt_reg;
1385         void __iomem *sense_uproc_interrupt_reg32;
1386         void __iomem *set_uproc_interrupt_reg;
1387         void __iomem *set_uproc_interrupt_reg32;
1388         void __iomem *clr_uproc_interrupt_reg;
1389         void __iomem *clr_uproc_interrupt_reg32;
1390
1391         void __iomem *init_feedback_reg;
1392
1393         void __iomem *dump_addr_reg;
1394         void __iomem *dump_data_reg;
1395
1396         void __iomem *endian_swap_reg;
1397 };
1398
1399 struct ipr_chip_cfg_t {
1400         u32 mailbox;
1401         u16 max_cmds;
1402         u8 cache_line_size;
1403         u8 clear_isr;
1404         u32 iopoll_weight;
1405         struct ipr_interrupt_offsets regs;
1406 };
1407
1408 struct ipr_chip_t {
1409         u16 vendor;
1410         u16 device;
1411         bool has_msi;
1412         u16 sis_type;
1413 #define IPR_SIS32                       0x00
1414 #define IPR_SIS64                       0x01
1415         u16 bist_method;
1416 #define IPR_PCI_CFG                     0x00
1417 #define IPR_MMIO                        0x01
1418         const struct ipr_chip_cfg_t *cfg;
1419 };
1420
1421 enum ipr_shutdown_type {
1422         IPR_SHUTDOWN_NORMAL = 0x00,
1423         IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1424         IPR_SHUTDOWN_ABBREV = 0x80,
1425         IPR_SHUTDOWN_NONE = 0x100,
1426         IPR_SHUTDOWN_QUIESCE = 0x101,
1427 };
1428
1429 struct ipr_trace_entry {
1430         u32 time;
1431
1432         u8 op_code;
1433         u8 ata_op_code;
1434         u8 type;
1435 #define IPR_TRACE_START                 0x00
1436 #define IPR_TRACE_FINISH                0xff
1437         u8 cmd_index;
1438
1439         __be32 res_handle;
1440         union {
1441                 u32 ioasc;
1442                 u32 add_data;
1443                 u32 res_addr;
1444         } u;
1445 };
1446
1447 struct ipr_sglist {
1448         u32 order;
1449         u32 num_sg;
1450         u32 num_dma_sg;
1451         u32 buffer_len;
1452         struct scatterlist *scatterlist;
1453 };
1454
1455 enum ipr_sdt_state {
1456         INACTIVE,
1457         WAIT_FOR_DUMP,
1458         GET_DUMP,
1459         READ_DUMP,
1460         ABORT_DUMP,
1461         DUMP_OBTAINED
1462 };
1463
1464 /* Per-controller data */
1465 struct ipr_ioa_cfg {
1466         char eye_catcher[8];
1467 #define IPR_EYECATCHER                  "iprcfg"
1468
1469         struct list_head queue;
1470
1471         u8 in_reset_reload:1;
1472         u8 in_ioa_bringdown:1;
1473         u8 ioa_unit_checked:1;
1474         u8 dump_taken:1;
1475         u8 scan_enabled:1;
1476         u8 scan_done:1;
1477         u8 needs_hard_reset:1;
1478         u8 dual_raid:1;
1479         u8 needs_warm_reset:1;
1480         u8 msi_received:1;
1481         u8 sis64:1;
1482         u8 dump_timeout:1;
1483         u8 cfg_locked:1;
1484         u8 clear_isr:1;
1485         u8 probe_done:1;
1486         u8 scsi_unblock:1;
1487         u8 scsi_blocked:1;
1488
1489         u8 revid;
1490
1491         /*
1492          * Bitmaps for SIS64 generated target values
1493          */
1494         unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1495         unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1496         unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1497
1498         u16 type; /* CCIN of the card */
1499
1500         u8 log_level;
1501 #define IPR_MAX_LOG_LEVEL                       4
1502 #define IPR_DEFAULT_LOG_LEVEL           2
1503 #define IPR_DEBUG_LOG_LEVEL             3
1504
1505 #define IPR_NUM_TRACE_INDEX_BITS        8
1506 #define IPR_NUM_TRACE_ENTRIES           (1 << IPR_NUM_TRACE_INDEX_BITS)
1507 #define IPR_TRACE_INDEX_MASK            (IPR_NUM_TRACE_ENTRIES - 1)
1508 #define IPR_TRACE_SIZE  (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1509         char trace_start[8];
1510 #define IPR_TRACE_START_LABEL                   "trace"
1511         struct ipr_trace_entry *trace;
1512         atomic_t trace_index;
1513
1514         char cfg_table_start[8];
1515 #define IPR_CFG_TBL_START               "cfg"
1516         union {
1517                 struct ipr_config_table *cfg_table;
1518                 struct ipr_config_table64 *cfg_table64;
1519         } u;
1520         dma_addr_t cfg_table_dma;
1521         u32 cfg_table_size;
1522         u32 max_devs_supported;
1523
1524         char resource_table_label[8];
1525 #define IPR_RES_TABLE_LABEL             "res_tbl"
1526         struct ipr_resource_entry *res_entries;
1527         struct list_head free_res_q;
1528         struct list_head used_res_q;
1529
1530         char ipr_hcam_label[8];
1531 #define IPR_HCAM_LABEL                  "hcams"
1532         struct ipr_hostrcb *hostrcb[IPR_MAX_HCAMS];
1533         dma_addr_t hostrcb_dma[IPR_MAX_HCAMS];
1534         struct list_head hostrcb_free_q;
1535         struct list_head hostrcb_pending_q;
1536         struct list_head hostrcb_report_q;
1537
1538         struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1539         u32 hrrq_num;
1540         atomic_t  hrrq_index;
1541         u16 identify_hrrq_index;
1542
1543         struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1544
1545         unsigned int transop_timeout;
1546         const struct ipr_chip_cfg_t *chip_cfg;
1547         const struct ipr_chip_t *ipr_chip;
1548
1549         void __iomem *hdw_dma_regs;     /* iomapped PCI memory space */
1550         unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1551         void __iomem *ioa_mailbox;
1552         struct ipr_interrupts regs;
1553
1554         u16 saved_pcix_cmd_reg;
1555         u16 reset_retries;
1556
1557         u32 errors_logged;
1558         u32 doorbell;
1559
1560         struct Scsi_Host *host;
1561         struct pci_dev *pdev;
1562         struct ipr_sglist *ucode_sglist;
1563         u8 saved_mode_page_len;
1564
1565         struct work_struct work_q;
1566         struct work_struct scsi_add_work_q;
1567         struct workqueue_struct *reset_work_q;
1568
1569         wait_queue_head_t reset_wait_q;
1570         wait_queue_head_t msi_wait_q;
1571         wait_queue_head_t eeh_wait_q;
1572
1573         struct ipr_dump *dump;
1574         enum ipr_sdt_state sdt_state;
1575
1576         struct ipr_misc_cbs *vpd_cbs;
1577         dma_addr_t vpd_cbs_dma;
1578
1579         struct dma_pool *ipr_cmd_pool;
1580
1581         struct ipr_cmnd *reset_cmd;
1582         int (*reset) (struct ipr_cmnd *);
1583
1584         struct ata_host ata_host;
1585         char ipr_cmd_label[8];
1586 #define IPR_CMD_LABEL           "ipr_cmd"
1587         u32 max_cmds;
1588         struct ipr_cmnd **ipr_cmnd_list;
1589         dma_addr_t *ipr_cmnd_list_dma;
1590
1591         unsigned int nvectors;
1592
1593         struct {
1594                 char desc[22];
1595         } vectors_info[IPR_MAX_MSIX_VECTORS];
1596
1597         u32 iopoll_weight;
1598
1599 }; /* struct ipr_ioa_cfg */
1600
1601 struct ipr_cmnd {
1602         struct ipr_ioarcb ioarcb;
1603         union {
1604                 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1605                 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1606                 struct ipr_ata64_ioadl ata_ioadl;
1607         } i;
1608         union {
1609                 struct ipr_ioasa ioasa;
1610                 struct ipr_ioasa64 ioasa64;
1611         } s;
1612         struct list_head queue;
1613         struct scsi_cmnd *scsi_cmd;
1614         struct ata_queued_cmd *qc;
1615         struct completion completion;
1616         struct timer_list timer;
1617         struct work_struct work;
1618         void (*fast_done) (struct ipr_cmnd *);
1619         void (*done) (struct ipr_cmnd *);
1620         int (*job_step) (struct ipr_cmnd *);
1621         int (*job_step_failed) (struct ipr_cmnd *);
1622         u16 cmd_index;
1623         u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1624         dma_addr_t sense_buffer_dma;
1625         unsigned short dma_use_sg;
1626         dma_addr_t dma_addr;
1627         struct ipr_cmnd *sibling;
1628         union {
1629                 enum ipr_shutdown_type shutdown_type;
1630                 struct ipr_hostrcb *hostrcb;
1631                 unsigned long time_left;
1632                 unsigned long scratch;
1633                 struct ipr_resource_entry *res;
1634                 struct scsi_device *sdev;
1635         } u;
1636
1637         struct completion *eh_comp;
1638         struct ipr_hrr_queue *hrrq;
1639         struct ipr_ioa_cfg *ioa_cfg;
1640 };
1641
1642 struct ipr_ses_table_entry {
1643         char product_id[17];
1644         char compare_product_id_byte[17];
1645         u32 max_bus_speed_limit;        /* MB/sec limit for this backplane */
1646 };
1647
1648 struct ipr_dump_header {
1649         u32 eye_catcher;
1650 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1651         u32 len;
1652         u32 num_entries;
1653         u32 first_entry_offset;
1654         u32 status;
1655 #define IPR_DUMP_STATUS_SUCCESS                 0
1656 #define IPR_DUMP_STATUS_QUAL_SUCCESS            2
1657 #define IPR_DUMP_STATUS_FAILED                  0xffffffff
1658         u32 os;
1659 #define IPR_DUMP_OS_LINUX       0x4C4E5558
1660         u32 driver_name;
1661 #define IPR_DUMP_DRIVER_NAME    0x49505232
1662 }__attribute__((packed, aligned (4)));
1663
1664 struct ipr_dump_entry_header {
1665         u32 eye_catcher;
1666 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1667         u32 len;
1668         u32 num_elems;
1669         u32 offset;
1670         u32 data_type;
1671 #define IPR_DUMP_DATA_TYPE_ASCII        0x41534349
1672 #define IPR_DUMP_DATA_TYPE_BINARY       0x42494E41
1673         u32 id;
1674 #define IPR_DUMP_IOA_DUMP_ID            0x494F4131
1675 #define IPR_DUMP_LOCATION_ID            0x4C4F4341
1676 #define IPR_DUMP_TRACE_ID               0x54524143
1677 #define IPR_DUMP_DRIVER_VERSION_ID      0x44525652
1678 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1679 #define IPR_DUMP_IOA_CTRL_BLK           0x494F4342
1680 #define IPR_DUMP_PEND_OPS               0x414F5053
1681         u32 status;
1682 }__attribute__((packed, aligned (4)));
1683
1684 struct ipr_dump_location_entry {
1685         struct ipr_dump_entry_header hdr;
1686         u8 location[20];
1687 }__attribute__((packed, aligned (4)));
1688
1689 struct ipr_dump_trace_entry {
1690         struct ipr_dump_entry_header hdr;
1691         u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1692 }__attribute__((packed, aligned (4)));
1693
1694 struct ipr_dump_version_entry {
1695         struct ipr_dump_entry_header hdr;
1696         u8 version[sizeof(IPR_DRIVER_VERSION)];
1697 };
1698
1699 struct ipr_dump_ioa_type_entry {
1700         struct ipr_dump_entry_header hdr;
1701         u32 type;
1702         u32 fw_version;
1703 };
1704
1705 struct ipr_driver_dump {
1706         struct ipr_dump_header hdr;
1707         struct ipr_dump_version_entry version_entry;
1708         struct ipr_dump_location_entry location_entry;
1709         struct ipr_dump_ioa_type_entry ioa_type_entry;
1710         struct ipr_dump_trace_entry trace_entry;
1711 }__attribute__((packed, aligned (4)));
1712
1713 struct ipr_ioa_dump {
1714         struct ipr_dump_entry_header hdr;
1715         struct ipr_sdt sdt;
1716         __be32 **ioa_data;
1717         u32 reserved;
1718         u32 next_page_index;
1719         u32 page_offset;
1720         u32 format;
1721 }__attribute__((packed, aligned (4)));
1722
1723 struct ipr_dump {
1724         struct kref kref;
1725         struct ipr_ioa_cfg *ioa_cfg;
1726         struct ipr_driver_dump driver_dump;
1727         struct ipr_ioa_dump ioa_dump;
1728 };
1729
1730 struct ipr_error_table_t {
1731         u32 ioasc;
1732         int log_ioasa;
1733         int log_hcam;
1734         char *error;
1735 };
1736
1737 struct ipr_software_inq_lid_info {
1738         __be32 load_id;
1739         __be32 timestamp[3];
1740 }__attribute__((packed, aligned (4)));
1741
1742 struct ipr_ucode_image_header {
1743         __be32 header_length;
1744         __be32 lid_table_offset;
1745         u8 major_release;
1746         u8 card_type;
1747         u8 minor_release[2];
1748         u8 reserved[20];
1749         char eyecatcher[16];
1750         __be32 num_lids;
1751         struct ipr_software_inq_lid_info lid[1];
1752 }__attribute__((packed, aligned (4)));
1753
1754 /*
1755  * Macros
1756  */
1757 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1758
1759 #ifdef CONFIG_SCSI_IPR_TRACE
1760 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1761 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1762 #else
1763 #define ipr_create_trace_file(kobj, attr) 0
1764 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1765 #endif
1766
1767 #ifdef CONFIG_SCSI_IPR_DUMP
1768 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1769 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1770 #else
1771 #define ipr_create_dump_file(kobj, attr) 0
1772 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1773 #endif
1774
1775 /*
1776  * Error logging macros
1777  */
1778 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1779 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1780 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1781
1782 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1783         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1784                 bus, target, lun, ##__VA_ARGS__)
1785
1786 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1787         ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1788
1789 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1790         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1791                 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1792
1793 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1794         ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1795
1796 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)                        \
1797 {                                                                       \
1798         if ((res).bus >= IPR_MAX_NUM_BUSES) {                           \
1799                 ipr_err(fmt": unknown\n", ##__VA_ARGS__);               \
1800         } else {                                                        \
1801                 ipr_err(fmt": %d:%d:%d:%d\n",                           \
1802                         ##__VA_ARGS__, (ioa_cfg)->host->host_no,        \
1803                         (res).bus, (res).target, (res).lun);            \
1804         }                                                               \
1805 }
1806
1807 #define ipr_hcam_err(hostrcb, fmt, ...)                                 \
1808 {                                                                       \
1809         if (ipr_is_device(hostrcb)) {                                   \
1810                 if ((hostrcb)->ioa_cfg->sis64) {                        \
1811                         printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
1812                                 ipr_format_res_path(hostrcb->ioa_cfg,   \
1813                                         hostrcb->hcam.u.error64.fd_res_path, \
1814                                         hostrcb->rp_buffer,             \
1815                                         sizeof(hostrcb->rp_buffer)),    \
1816                                 __VA_ARGS__);                           \
1817                 } else {                                                \
1818                         ipr_ra_err((hostrcb)->ioa_cfg,                  \
1819                                 (hostrcb)->hcam.u.error.fd_res_addr,    \
1820                                 fmt, __VA_ARGS__);                      \
1821                 }                                                       \
1822         } else {                                                        \
1823                 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1824         }                                                               \
1825 }
1826
1827 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1828         __FILE__, __func__, __LINE__)
1829
1830 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1831 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1832
1833 #define ipr_err_separator \
1834 ipr_err("----------------------------------------------------------\n")
1835
1836
1837 /*
1838  * Inlines
1839  */
1840
1841 /**
1842  * ipr_is_ioa_resource - Determine if a resource is the IOA
1843  * @res:        resource entry struct
1844  *
1845  * Return value:
1846  *      1 if IOA / 0 if not IOA
1847  **/
1848 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1849 {
1850         return res->type == IPR_RES_TYPE_IOAFP;
1851 }
1852
1853 /**
1854  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1855  * @res:        resource entry struct
1856  *
1857  * Return value:
1858  *      1 if AF DASD / 0 if not AF DASD
1859  **/
1860 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1861 {
1862         return res->type == IPR_RES_TYPE_AF_DASD ||
1863                 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1864 }
1865
1866 /**
1867  * ipr_is_vset_device - Determine if a resource is a VSET
1868  * @res:        resource entry struct
1869  *
1870  * Return value:
1871  *      1 if VSET / 0 if not VSET
1872  **/
1873 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1874 {
1875         return res->type == IPR_RES_TYPE_VOLUME_SET;
1876 }
1877
1878 /**
1879  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1880  * @res:        resource entry struct
1881  *
1882  * Return value:
1883  *      1 if GSCSI / 0 if not GSCSI
1884  **/
1885 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1886 {
1887         return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1888 }
1889
1890 /**
1891  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1892  * @res:        resource entry struct
1893  *
1894  * Return value:
1895  *      1 if SCSI disk / 0 if not SCSI disk
1896  **/
1897 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1898 {
1899         if (ipr_is_af_dasd_device(res) ||
1900             (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1901                 return 1;
1902         else
1903                 return 0;
1904 }
1905
1906 /**
1907  * ipr_is_gata - Determine if a resource is a generic ATA resource
1908  * @res:        resource entry struct
1909  *
1910  * Return value:
1911  *      1 if GATA / 0 if not GATA
1912  **/
1913 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1914 {
1915         return res->type == IPR_RES_TYPE_GENERIC_ATA;
1916 }
1917
1918 /**
1919  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1920  * @res:        resource entry struct
1921  *
1922  * Return value:
1923  *      1 if NACA queueing model / 0 if not NACA queueing model
1924  **/
1925 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1926 {
1927         if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1928                 return 1;
1929         return 0;
1930 }
1931
1932 /**
1933  * ipr_is_device - Determine if the hostrcb structure is related to a device
1934  * @hostrcb:    host resource control blocks struct
1935  *
1936  * Return value:
1937  *      1 if AF / 0 if not AF
1938  **/
1939 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1940 {
1941         struct ipr_res_addr *res_addr;
1942         u8 *res_path;
1943
1944         if (hostrcb->ioa_cfg->sis64) {
1945                 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1946                 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1947                     res_path[0] == 0x81) && res_path[2] != 0xFF)
1948                         return 1;
1949         } else {
1950                 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1951
1952                 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1953                     (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1954                         return 1;
1955         }
1956         return 0;
1957 }
1958
1959 /**
1960  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1961  * @sdt_word:   SDT address
1962  *
1963  * Return value:
1964  *      1 if format 2 / 0 if not
1965  **/
1966 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1967 {
1968         u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1969
1970         switch (bar_sel) {
1971         case IPR_SDT_FMT2_BAR0_SEL:
1972         case IPR_SDT_FMT2_BAR1_SEL:
1973         case IPR_SDT_FMT2_BAR2_SEL:
1974         case IPR_SDT_FMT2_BAR3_SEL:
1975         case IPR_SDT_FMT2_BAR4_SEL:
1976         case IPR_SDT_FMT2_BAR5_SEL:
1977         case IPR_SDT_FMT2_EXP_ROM_SEL:
1978                 return 1;
1979         };
1980
1981         return 0;
1982 }
1983
1984 #ifndef writeq
1985 static inline void writeq(u64 val, void __iomem *addr)
1986 {
1987         writel(((u32) (val >> 32)), addr);
1988         writel(((u32) (val)), (addr + 4));
1989 }
1990 #endif
1991
1992 #endif /* _IPR_H */