1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microsemi PQI-based storage controllers
4 * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
8 * Questions/Comments/Bugfixes to storagedev@microchip.com
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/pci.h>
16 #include <scsi/scsi_device.h>
17 #include <asm/unaligned.h>
19 #include "smartpqi_sis.h"
21 /* legacy SIS interface commands */
22 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
23 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
24 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
26 /* for submission of legacy SIS commands */
27 #define SIS_REENABLE_SIS_MODE 0x1
28 #define SIS_ENABLE_MSIX 0x40
29 #define SIS_ENABLE_INTX 0x80
30 #define SIS_SOFT_RESET 0x100
31 #define SIS_CMD_READY 0x200
32 #define SIS_TRIGGER_SHUTDOWN 0x800000
33 #define SIS_PQI_RESET_QUIESCE 0x1000000
35 #define SIS_CMD_COMPLETE 0x1000
36 #define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
38 #define SIS_CMD_STATUS_SUCCESS 0x1
39 #define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
40 #define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
42 /* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
43 #define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
44 #define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
45 #define SIS_PQI_MODE_SUPPORTED 0x4
46 #define SIS_PQI_RESET_QUIESCE_SUPPORTED 0x8
47 #define SIS_REQUIRED_EXTENDED_PROPERTIES \
48 (SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
50 /* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
51 #define SIS_BASE_STRUCT_REVISION 9
52 #define SIS_BASE_STRUCT_ALIGNMENT 16
54 #define SIS_CTRL_KERNEL_UP 0x80
55 #define SIS_CTRL_KERNEL_PANIC 0x100
56 #define SIS_CTRL_READY_TIMEOUT_SECS 180
57 #define SIS_CTRL_READY_RESUME_TIMEOUT_SECS 90
58 #define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10
62 /* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
63 struct sis_base_struct
{
64 __le32 revision
; /* revision of this structure */
65 __le32 flags
; /* reserved */
66 __le32 error_buffer_paddr_low
; /* lower 32 bits of physical memory */
67 /* buffer for PQI error response */
69 __le32 error_buffer_paddr_high
; /* upper 32 bits of physical */
70 /* memory buffer for PQI */
71 /* error response data */
72 __le32 error_buffer_element_length
; /* length of each PQI error */
73 /* response buffer element */
75 __le32 error_buffer_num_elements
; /* total number of PQI error */
76 /* response buffers available */
81 static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info
*ctrl_info
,
82 unsigned int timeout_secs
)
84 unsigned long timeout
;
87 timeout
= (timeout_secs
* PQI_HZ
) + jiffies
;
90 status
= readl(&ctrl_info
->registers
->sis_firmware_status
);
92 if (status
& SIS_CTRL_KERNEL_PANIC
) {
93 dev_err(&ctrl_info
->pci_dev
->dev
,
94 "controller is offline: status code 0x%x\n",
96 &ctrl_info
->registers
->sis_mailbox
[7]));
99 if (status
& SIS_CTRL_KERNEL_UP
)
102 if (time_after(jiffies
, timeout
)) {
103 dev_err(&ctrl_info
->pci_dev
->dev
,
104 "controller not ready after %u seconds\n",
108 msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS
);
114 int sis_wait_for_ctrl_ready(struct pqi_ctrl_info
*ctrl_info
)
116 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info
,
117 SIS_CTRL_READY_TIMEOUT_SECS
);
120 int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info
*ctrl_info
)
122 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info
,
123 SIS_CTRL_READY_RESUME_TIMEOUT_SECS
);
126 bool sis_is_firmware_running(struct pqi_ctrl_info
*ctrl_info
)
131 status
= readl(&ctrl_info
->registers
->sis_firmware_status
);
133 if (status
& SIS_CTRL_KERNEL_PANIC
)
139 dev_err(&ctrl_info
->pci_dev
->dev
,
140 "controller is offline: status code 0x%x\n",
141 readl(&ctrl_info
->registers
->sis_mailbox
[7]));
146 bool sis_is_kernel_up(struct pqi_ctrl_info
*ctrl_info
)
148 return readl(&ctrl_info
->registers
->sis_firmware_status
) &
152 /* used for passing command parameters/results when issuing SIS commands */
153 struct sis_sync_cmd_params
{
154 u32 mailbox
[6]; /* mailboxes 0-5 */
157 static int sis_send_sync_cmd(struct pqi_ctrl_info
*ctrl_info
,
158 u32 cmd
, struct sis_sync_cmd_params
*params
)
160 struct pqi_ctrl_registers __iomem
*registers
;
162 unsigned long timeout
;
166 registers
= ctrl_info
->registers
;
168 /* Write the command to mailbox 0. */
169 writel(cmd
, ®isters
->sis_mailbox
[0]);
172 * Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
173 * when sending a command to the controller).
175 for (i
= 1; i
<= 4; i
++)
176 writel(params
->mailbox
[i
], ®isters
->sis_mailbox
[i
]);
178 /* Clear the command doorbell. */
179 writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL
,
180 ®isters
->sis_ctrl_to_host_doorbell_clear
);
182 /* Disable doorbell interrupts by masking all interrupts. */
183 writel(~0, ®isters
->sis_interrupt_mask
);
186 * Force the completion of the interrupt mask register write before
187 * submitting the command.
189 readl(®isters
->sis_interrupt_mask
);
191 /* Submit the command to the controller. */
192 writel(SIS_CMD_READY
, ®isters
->sis_host_to_ctrl_doorbell
);
195 * Poll for command completion. Note that the call to msleep() is at
196 * the top of the loop in order to give the controller time to start
197 * processing the command before we start polling.
199 timeout
= (SIS_CMD_COMPLETE_TIMEOUT_SECS
* PQI_HZ
) + jiffies
;
201 msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS
);
202 doorbell
= readl(®isters
->sis_ctrl_to_host_doorbell
);
203 if (doorbell
& SIS_CMD_COMPLETE
)
205 if (time_after(jiffies
, timeout
))
209 /* Read the command status from mailbox 0. */
210 cmd_status
= readl(®isters
->sis_mailbox
[0]);
211 if (cmd_status
!= SIS_CMD_STATUS_SUCCESS
) {
212 dev_err(&ctrl_info
->pci_dev
->dev
,
213 "SIS command failed for command 0x%x: status = 0x%x\n",
219 * The command completed successfully, so save the command status and
220 * read the values returned in mailboxes 1-5.
222 params
->mailbox
[0] = cmd_status
;
223 for (i
= 1; i
< ARRAY_SIZE(params
->mailbox
); i
++)
224 params
->mailbox
[i
] = readl(®isters
->sis_mailbox
[i
]);
230 * This function verifies that we are talking to a controller that speaks PQI.
233 int sis_get_ctrl_properties(struct pqi_ctrl_info
*ctrl_info
)
237 u32 extended_properties
;
238 struct sis_sync_cmd_params params
;
240 memset(¶ms
, 0, sizeof(params
));
242 rc
= sis_send_sync_cmd(ctrl_info
, SIS_CMD_GET_ADAPTER_PROPERTIES
,
247 properties
= params
.mailbox
[1];
249 if (!(properties
& SIS_EXTENDED_PROPERTIES_SUPPORTED
))
252 extended_properties
= params
.mailbox
[4];
254 if ((extended_properties
& SIS_REQUIRED_EXTENDED_PROPERTIES
) !=
255 SIS_REQUIRED_EXTENDED_PROPERTIES
)
258 if (extended_properties
& SIS_PQI_RESET_QUIESCE_SUPPORTED
)
259 ctrl_info
->pqi_reset_quiesce_supported
= true;
264 int sis_get_pqi_capabilities(struct pqi_ctrl_info
*ctrl_info
)
267 struct sis_sync_cmd_params params
;
269 memset(¶ms
, 0, sizeof(params
));
271 rc
= sis_send_sync_cmd(ctrl_info
, SIS_CMD_GET_PQI_CAPABILITIES
,
276 ctrl_info
->max_sg_entries
= params
.mailbox
[1];
277 ctrl_info
->max_transfer_size
= params
.mailbox
[2];
278 ctrl_info
->max_outstanding_requests
= params
.mailbox
[3];
279 ctrl_info
->config_table_offset
= params
.mailbox
[4];
280 ctrl_info
->config_table_length
= params
.mailbox
[5];
285 int sis_init_base_struct_addr(struct pqi_ctrl_info
*ctrl_info
)
288 void *base_struct_unaligned
;
289 struct sis_base_struct
*base_struct
;
290 struct sis_sync_cmd_params params
;
291 unsigned long error_buffer_paddr
;
292 dma_addr_t bus_address
;
294 base_struct_unaligned
= kzalloc(sizeof(*base_struct
)
295 + SIS_BASE_STRUCT_ALIGNMENT
- 1, GFP_KERNEL
);
296 if (!base_struct_unaligned
)
299 base_struct
= PTR_ALIGN(base_struct_unaligned
,
300 SIS_BASE_STRUCT_ALIGNMENT
);
301 error_buffer_paddr
= (unsigned long)ctrl_info
->error_buffer_dma_handle
;
303 put_unaligned_le32(SIS_BASE_STRUCT_REVISION
, &base_struct
->revision
);
304 put_unaligned_le32(lower_32_bits(error_buffer_paddr
),
305 &base_struct
->error_buffer_paddr_low
);
306 put_unaligned_le32(upper_32_bits(error_buffer_paddr
),
307 &base_struct
->error_buffer_paddr_high
);
308 put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH
,
309 &base_struct
->error_buffer_element_length
);
310 put_unaligned_le32(ctrl_info
->max_io_slots
,
311 &base_struct
->error_buffer_num_elements
);
313 bus_address
= dma_map_single(&ctrl_info
->pci_dev
->dev
, base_struct
,
314 sizeof(*base_struct
), DMA_TO_DEVICE
);
315 if (dma_mapping_error(&ctrl_info
->pci_dev
->dev
, bus_address
)) {
320 memset(¶ms
, 0, sizeof(params
));
321 params
.mailbox
[1] = lower_32_bits((u64
)bus_address
);
322 params
.mailbox
[2] = upper_32_bits((u64
)bus_address
);
323 params
.mailbox
[3] = sizeof(*base_struct
);
325 rc
= sis_send_sync_cmd(ctrl_info
, SIS_CMD_INIT_BASE_STRUCT_ADDRESS
,
328 dma_unmap_single(&ctrl_info
->pci_dev
->dev
, bus_address
,
329 sizeof(*base_struct
), DMA_TO_DEVICE
);
331 kfree(base_struct_unaligned
);
336 #define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS 30
338 static int sis_wait_for_doorbell_bit_to_clear(
339 struct pqi_ctrl_info
*ctrl_info
, u32 bit
)
342 u32 doorbell_register
;
343 unsigned long timeout
;
345 timeout
= (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS
* PQI_HZ
) + jiffies
;
349 readl(&ctrl_info
->registers
->sis_host_to_ctrl_doorbell
);
350 if ((doorbell_register
& bit
) == 0)
352 if (readl(&ctrl_info
->registers
->sis_firmware_status
) &
353 SIS_CTRL_KERNEL_PANIC
) {
357 if (time_after(jiffies
, timeout
)) {
358 dev_err(&ctrl_info
->pci_dev
->dev
,
359 "doorbell register bit 0x%x not cleared\n",
364 usleep_range(1000, 2000);
370 static inline int sis_set_doorbell_bit(struct pqi_ctrl_info
*ctrl_info
, u32 bit
)
372 writel(bit
, &ctrl_info
->registers
->sis_host_to_ctrl_doorbell
);
374 return sis_wait_for_doorbell_bit_to_clear(ctrl_info
, bit
);
377 void sis_enable_msix(struct pqi_ctrl_info
*ctrl_info
)
379 sis_set_doorbell_bit(ctrl_info
, SIS_ENABLE_MSIX
);
382 void sis_enable_intx(struct pqi_ctrl_info
*ctrl_info
)
384 sis_set_doorbell_bit(ctrl_info
, SIS_ENABLE_INTX
);
387 void sis_shutdown_ctrl(struct pqi_ctrl_info
*ctrl_info
)
389 if (readl(&ctrl_info
->registers
->sis_firmware_status
) &
390 SIS_CTRL_KERNEL_PANIC
)
393 writel(SIS_TRIGGER_SHUTDOWN
,
394 &ctrl_info
->registers
->sis_host_to_ctrl_doorbell
);
397 int sis_pqi_reset_quiesce(struct pqi_ctrl_info
*ctrl_info
)
399 return sis_set_doorbell_bit(ctrl_info
, SIS_PQI_RESET_QUIESCE
);
402 int sis_reenable_sis_mode(struct pqi_ctrl_info
*ctrl_info
)
404 return sis_set_doorbell_bit(ctrl_info
, SIS_REENABLE_SIS_MODE
);
407 void sis_write_driver_scratch(struct pqi_ctrl_info
*ctrl_info
, u32 value
)
409 writel(value
, &ctrl_info
->registers
->sis_driver_scratch
);
412 u32
sis_read_driver_scratch(struct pqi_ctrl_info
*ctrl_info
)
414 return readl(&ctrl_info
->registers
->sis_driver_scratch
);
417 void sis_soft_reset(struct pqi_ctrl_info
*ctrl_info
)
419 writel(SIS_SOFT_RESET
,
420 &ctrl_info
->registers
->sis_host_to_ctrl_doorbell
);
423 static void __attribute__((unused
)) verify_structures(void)
425 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
427 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
429 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
430 error_buffer_paddr_low
) != 0x8);
431 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
432 error_buffer_paddr_high
) != 0xc);
433 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
434 error_buffer_element_length
) != 0x10);
435 BUILD_BUG_ON(offsetof(struct sis_base_struct
,
436 error_buffer_num_elements
) != 0x14);
437 BUILD_BUG_ON(sizeof(struct sis_base_struct
) != 0x18);