1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys G210 Test Chip driver
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
7 * Authors: Joao Pinto <jpinto@synopsys.com>
13 #include "ufshcd-dwc.h"
14 #include "ufshci-dwc.h"
15 #include "tc-dwc-g210.h"
18 * tc_dwc_g210_setup_40bit_rmmi()
19 * This function configures Synopsys TC specific atributes (40-bit RMMI)
20 * @hba: Pointer to drivers structure
22 * Returns 0 on success or non-zero value on failure
24 static int tc_dwc_g210_setup_40bit_rmmi(struct ufs_hba
*hba
)
26 static const struct ufshcd_dme_attr_val setup_attrs
[] = {
27 { UIC_ARG_MIB(TX_GLOBALHIBERNATE
), 0x00, DME_LOCAL
},
28 { UIC_ARG_MIB(REFCLKMODE
), 0x01, DME_LOCAL
},
29 { UIC_ARG_MIB(CDIRECTCTRL6
), 0x80, DME_LOCAL
},
30 { UIC_ARG_MIB(CBDIVFACTOR
), 0x08, DME_LOCAL
},
31 { UIC_ARG_MIB(CBDCOCTRL5
), 0x64, DME_LOCAL
},
32 { UIC_ARG_MIB(CBPRGTUNING
), 0x09, DME_LOCAL
},
33 { UIC_ARG_MIB(RTOBSERVESELECT
), 0x00, DME_LOCAL
},
34 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ
, SELIND_LN0_TX
), 0x01,
36 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL
, SELIND_LN0_TX
), 0x19,
38 { UIC_ARG_MIB_SEL(CFGEXTRATTR
, SELIND_LN0_TX
), 0x14,
40 { UIC_ARG_MIB_SEL(DITHERCTRL2
, SELIND_LN0_TX
), 0xd6,
42 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ
, SELIND_LN0_RX
), 0x01,
44 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL
, SELIND_LN0_RX
), 0x19,
46 { UIC_ARG_MIB_SEL(CFGWIDEINLN
, SELIND_LN0_RX
), 4,
48 { UIC_ARG_MIB_SEL(CFGRXCDR8
, SELIND_LN0_RX
), 0x80,
50 { UIC_ARG_MIB(DIRECTCTRL10
), 0x04, DME_LOCAL
},
51 { UIC_ARG_MIB(DIRECTCTRL19
), 0x02, DME_LOCAL
},
52 { UIC_ARG_MIB_SEL(CFGRXCDR8
, SELIND_LN0_RX
), 0x80,
54 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4
, SELIND_LN0_RX
), 0x03,
56 { UIC_ARG_MIB_SEL(CFGRXOVR8
, SELIND_LN0_RX
), 0x16,
58 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2
, SELIND_LN0_RX
), 0x42,
60 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3
, SELIND_LN0_RX
), 0xa4,
62 { UIC_ARG_MIB_SEL(RXCALCTRL
, SELIND_LN0_RX
), 0x01,
64 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2
, SELIND_LN0_RX
), 0x01,
66 { UIC_ARG_MIB_SEL(CFGRXOVR4
, SELIND_LN0_RX
), 0x28,
68 { UIC_ARG_MIB_SEL(RXSQCTRL
, SELIND_LN0_RX
), 0x1E,
70 { UIC_ARG_MIB_SEL(CFGRXOVR6
, SELIND_LN0_RX
), 0x2f,
72 { UIC_ARG_MIB_SEL(CFGRXOVR6
, SELIND_LN0_RX
), 0x2f,
74 { UIC_ARG_MIB(CBPRGPLL2
), 0x00, DME_LOCAL
},
77 return ufshcd_dwc_dme_set_attrs(hba
, setup_attrs
,
78 ARRAY_SIZE(setup_attrs
));
82 * tc_dwc_g210_setup_20bit_rmmi_lane0()
83 * This function configures Synopsys TC 20-bit RMMI Lane 0
84 * @hba: Pointer to drivers structure
86 * Returns 0 on success or non-zero value on failure
88 static int tc_dwc_g210_setup_20bit_rmmi_lane0(struct ufs_hba
*hba
)
90 static const struct ufshcd_dme_attr_val setup_attrs
[] = {
91 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ
, SELIND_LN0_TX
), 0x01,
93 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL
, SELIND_LN0_TX
), 0x19,
95 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL
, SELIND_LN0_RX
), 0x19,
97 { UIC_ARG_MIB_SEL(CFGEXTRATTR
, SELIND_LN0_TX
), 0x12,
99 { UIC_ARG_MIB_SEL(DITHERCTRL2
, SELIND_LN0_TX
), 0xd6,
101 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ
, SELIND_LN0_RX
), 0x01,
103 { UIC_ARG_MIB_SEL(CFGWIDEINLN
, SELIND_LN0_RX
), 2,
105 { UIC_ARG_MIB_SEL(CFGRXCDR8
, SELIND_LN0_RX
), 0x80,
107 { UIC_ARG_MIB(DIRECTCTRL10
), 0x04, DME_LOCAL
},
108 { UIC_ARG_MIB(DIRECTCTRL19
), 0x02, DME_LOCAL
},
109 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4
, SELIND_LN0_RX
), 0x03,
111 { UIC_ARG_MIB_SEL(CFGRXOVR8
, SELIND_LN0_RX
), 0x16,
113 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2
, SELIND_LN0_RX
), 0x42,
115 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3
, SELIND_LN0_RX
), 0xa4,
117 { UIC_ARG_MIB_SEL(RXCALCTRL
, SELIND_LN0_RX
), 0x01,
119 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2
, SELIND_LN0_RX
), 0x01,
121 { UIC_ARG_MIB_SEL(CFGRXOVR4
, SELIND_LN0_RX
), 0x28,
123 { UIC_ARG_MIB_SEL(RXSQCTRL
, SELIND_LN0_RX
), 0x1E,
125 { UIC_ARG_MIB_SEL(CFGRXOVR6
, SELIND_LN0_RX
), 0x2f,
127 { UIC_ARG_MIB(CBPRGPLL2
), 0x00, DME_LOCAL
},
130 return ufshcd_dwc_dme_set_attrs(hba
, setup_attrs
,
131 ARRAY_SIZE(setup_attrs
));
135 * tc_dwc_g210_setup_20bit_rmmi_lane1()
136 * This function configures Synopsys TC 20-bit RMMI Lane 1
137 * @hba: Pointer to drivers structure
139 * Returns 0 on success or non-zero value on failure
141 static int tc_dwc_g210_setup_20bit_rmmi_lane1(struct ufs_hba
*hba
)
143 int connected_rx_lanes
= 0;
144 int connected_tx_lanes
= 0;
147 static const struct ufshcd_dme_attr_val setup_tx_attrs
[] = {
148 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ
, SELIND_LN1_TX
), 0x0d,
150 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL
, SELIND_LN1_TX
), 0x19,
152 { UIC_ARG_MIB_SEL(CFGEXTRATTR
, SELIND_LN1_TX
), 0x12,
154 { UIC_ARG_MIB_SEL(DITHERCTRL2
, SELIND_LN0_TX
), 0xd6,
158 static const struct ufshcd_dme_attr_val setup_rx_attrs
[] = {
159 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ
, SELIND_LN1_RX
), 0x01,
161 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL
, SELIND_LN1_RX
), 0x19,
163 { UIC_ARG_MIB_SEL(CFGWIDEINLN
, SELIND_LN1_RX
), 2,
165 { UIC_ARG_MIB_SEL(CFGRXCDR8
, SELIND_LN1_RX
), 0x80,
167 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4
, SELIND_LN1_RX
), 0x03,
169 { UIC_ARG_MIB_SEL(CFGRXOVR8
, SELIND_LN1_RX
), 0x16,
171 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2
, SELIND_LN1_RX
), 0x42,
173 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3
, SELIND_LN1_RX
), 0xa4,
175 { UIC_ARG_MIB_SEL(RXCALCTRL
, SELIND_LN1_RX
), 0x01,
177 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2
, SELIND_LN1_RX
), 0x01,
179 { UIC_ARG_MIB_SEL(CFGRXOVR4
, SELIND_LN1_RX
), 0x28,
181 { UIC_ARG_MIB_SEL(RXSQCTRL
, SELIND_LN1_RX
), 0x1E,
183 { UIC_ARG_MIB_SEL(CFGRXOVR6
, SELIND_LN1_RX
), 0x2f,
187 /* Get the available lane count */
188 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_AVAILRXDATALANES
),
189 &connected_rx_lanes
);
190 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_AVAILTXDATALANES
),
191 &connected_tx_lanes
);
193 if (connected_tx_lanes
== 2) {
195 ret
= ufshcd_dwc_dme_set_attrs(hba
, setup_tx_attrs
,
196 ARRAY_SIZE(setup_tx_attrs
));
202 if (connected_rx_lanes
== 2) {
203 ret
= ufshcd_dwc_dme_set_attrs(hba
, setup_rx_attrs
,
204 ARRAY_SIZE(setup_rx_attrs
));
212 * tc_dwc_g210_setup_20bit_rmmi()
213 * This function configures Synopsys TC specific atributes (20-bit RMMI)
214 * @hba: Pointer to drivers structure
216 * Returns 0 on success or non-zero value on failure
218 static int tc_dwc_g210_setup_20bit_rmmi(struct ufs_hba
*hba
)
222 static const struct ufshcd_dme_attr_val setup_attrs
[] = {
223 { UIC_ARG_MIB(TX_GLOBALHIBERNATE
), 0x00, DME_LOCAL
},
224 { UIC_ARG_MIB(REFCLKMODE
), 0x01, DME_LOCAL
},
225 { UIC_ARG_MIB(CDIRECTCTRL6
), 0xc0, DME_LOCAL
},
226 { UIC_ARG_MIB(CBDIVFACTOR
), 0x44, DME_LOCAL
},
227 { UIC_ARG_MIB(CBDCOCTRL5
), 0x64, DME_LOCAL
},
228 { UIC_ARG_MIB(CBPRGTUNING
), 0x09, DME_LOCAL
},
229 { UIC_ARG_MIB(RTOBSERVESELECT
), 0x00, DME_LOCAL
},
232 ret
= ufshcd_dwc_dme_set_attrs(hba
, setup_attrs
,
233 ARRAY_SIZE(setup_attrs
));
237 /* Lane 0 configuration*/
238 ret
= tc_dwc_g210_setup_20bit_rmmi_lane0(hba
);
242 /* Lane 1 configuration*/
243 ret
= tc_dwc_g210_setup_20bit_rmmi_lane1(hba
);
252 * tc_dwc_g210_config_40_bit()
253 * This function configures Local (host) Synopsys 40-bit TC specific attributes
255 * @hba: Pointer to drivers structure
257 * Returns 0 on success non-zero value on failure
259 int tc_dwc_g210_config_40_bit(struct ufs_hba
*hba
)
263 dev_info(hba
->dev
, "Configuring Test Chip 40-bit RMMI\n");
264 ret
= tc_dwc_g210_setup_40bit_rmmi(hba
);
266 dev_err(hba
->dev
, "Configuration failed\n");
270 /* To write Shadow register bank to effective configuration block */
271 ret
= ufshcd_dme_set(hba
, UIC_ARG_MIB(VS_MPHYCFGUPDT
), 0x01);
275 /* To configure Debug OMC */
276 ret
= ufshcd_dme_set(hba
, UIC_ARG_MIB(VS_DEBUGOMC
), 0x01);
281 EXPORT_SYMBOL(tc_dwc_g210_config_40_bit
);
284 * tc_dwc_g210_config_20_bit()
285 * This function configures Local (host) Synopsys 20-bit TC specific attributes
287 * @hba: Pointer to drivers structure
289 * Returns 0 on success non-zero value on failure
291 int tc_dwc_g210_config_20_bit(struct ufs_hba
*hba
)
295 dev_info(hba
->dev
, "Configuring Test Chip 20-bit RMMI\n");
296 ret
= tc_dwc_g210_setup_20bit_rmmi(hba
);
298 dev_err(hba
->dev
, "Configuration failed\n");
302 /* To write Shadow register bank to effective configuration block */
303 ret
= ufshcd_dme_set(hba
, UIC_ARG_MIB(VS_MPHYCFGUPDT
), 0x01);
307 /* To configure Debug OMC */
308 ret
= ufshcd_dme_set(hba
, UIC_ARG_MIB(VS_DEBUGOMC
), 0x01);
313 EXPORT_SYMBOL(tc_dwc_g210_config_20_bit
);
315 MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
316 MODULE_DESCRIPTION("Synopsys G210 Test Chip driver");
317 MODULE_LICENSE("Dual BSD/GPL");