drivers/soc/litex/litex_soc_ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * LiteX SoC Controller Driver
   4  *
   5  * Copyright (C) 2020 Antmicro <www.antmicro.com>
   6  *
   7  */
   8
   9 #include <linux/litex.h>
  10 #include <linux/device.h>
  11 #include <linux/errno.h>
  12 #include <linux/of.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/printk.h>
  15 #include <linux/module.h>
  16 #include <linux/errno.h>
  17 #include <linux/io.h>
  18
  19 /*
  20  * LiteX SoC Generator, depending on the configuration, can split a single
  21  * logical CSR (Control&Status Register) into a series of consecutive physical
  22  * registers.
  23  *
  24  * For example, in the configuration with 8-bit CSR Bus, 32-bit aligned (the
  25  * default one for 32-bit CPUs) a 32-bit logical CSR will be generated as four
  26  * 32-bit physical registers, each one containing one byte of meaningful data.
  27  *
  28  * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
  29  *
  30  * The purpose of `litex_set_reg`/`litex_get_reg` is to implement the logic
  31  * of writing to/reading from the LiteX CSR in a single place that can be
  32  * then reused by all LiteX drivers.
  33  */
  34
  35 /**
  36  * litex_set_reg() - Writes the value to the LiteX CSR (Control&Status Register)
  37  * @reg: Address of the CSR
  38  * @reg_size: The width of the CSR expressed in the number of bytes
  39  * @val: Value to be written to the CSR
  40  *
  41  * In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
  42  * a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
  43  * each one containing one byte of meaningful data.
  44  *
  45  * This function splits a single possibly multi-byte write into a series of
  46  * single-byte writes with a proper offset.
  47  */
  48 void litex_set_reg(void __iomem *reg, unsigned long reg_size,
  49                     unsigned long val)
  50 {
  51         unsigned long shifted_data, shift, i;
  52
  53         for (i = 0; i < reg_size; ++i) {
  54                 shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
  55                 shifted_data = val >> shift;
  56
  57                 WRITE_LITEX_SUBREGISTER(shifted_data, reg, i);
  58         }
  59 }
  60 EXPORT_SYMBOL_GPL(litex_set_reg);
  61
  62 /**
  63  * litex_get_reg() - Reads the value of the LiteX CSR (Control&Status Register)
  64  * @reg: Address of the CSR
  65  * @reg_size: The width of the CSR expressed in the number of bytes
  66  *
  67  * Return: Value read from the CSR
  68  *
  69  * In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
  70  * a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
  71  * each one containing one byte of meaningful data.
  72  *
  73  * This function generates a series of single-byte reads with a proper offset
  74  * and joins their results into a single multi-byte value.
  75  */
  76 unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size)
  77 {
  78         unsigned long shifted_data, shift, i;
  79         unsigned long result = 0;
  80
  81         for (i = 0; i < reg_size; ++i) {
  82                 shifted_data = READ_LITEX_SUBREGISTER(reg, i);
  83
  84                 shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
  85                 result |= (shifted_data << shift);
  86         }
  87
  88         return result;
  89 }
  90 EXPORT_SYMBOL_GPL(litex_get_reg);
  91
  92 #define SCRATCH_REG_OFF         0x04
  93 #define SCRATCH_REG_VALUE       0x12345678
  94 #define SCRATCH_TEST_VALUE      0xdeadbeef
  95
  96 /*
  97  * Check LiteX CSR read/write access
  98  *
  99  * This function reads and writes a scratch register in order to verify if CSR
 100  * access works.
 101  *
 102  * In case any problems are detected, the driver should panic.
 103  *
 104  * Access to the LiteX CSR is, by design, done in CPU native endianness.
 105  * The driver should not dynamically configure access functions when
 106  * the endianness mismatch is detected. Such situation indicates problems in
 107  * the soft SoC design and should be solved at the LiteX generator level,
 108  * not in the software.
 109  */
 110 static int litex_check_csr_access(void __iomem *reg_addr)
 111 {
 112         unsigned long reg;
 113
 114         reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
 115
 116         if (reg != SCRATCH_REG_VALUE) {
 117                 panic("Scratch register read error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
 118                         SCRATCH_REG_VALUE, reg);
 119                 return -EINVAL;
 120         }
 121
 122         litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE);
 123         reg = litex_read32(reg_addr + SCRATCH_REG_OFF);
 124
 125         if (reg != SCRATCH_TEST_VALUE) {
 126                 panic("Scratch register write error - the system is probably broken! Expected: 0x%x but got: 0x%lx",
 127                         SCRATCH_TEST_VALUE, reg);
 128                 return -EINVAL;
 129         }
 130
 131         /* restore original value of the SCRATCH register */
 132         litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE);
 133
 134         pr_info("LiteX SoC Controller driver initialized");
 135
 136         return 0;
 137 }
 138
 139 struct litex_soc_ctrl_device {
 140         void __iomem *base;
 141 };
 142
 143 static const struct of_device_id litex_soc_ctrl_of_match[] = {
 144         {.compatible = "litex,soc-controller"},
 145         {},
 146 };
 147
 148 MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match);
 149
 150 static int litex_soc_ctrl_probe(struct platform_device *pdev)
 151 {
 152         struct litex_soc_ctrl_device *soc_ctrl_dev;
 153
 154         soc_ctrl_dev = devm_kzalloc(&pdev->dev, sizeof(*soc_ctrl_dev), GFP_KERNEL);
 155         if (!soc_ctrl_dev)
 156                 return -ENOMEM;
 157
 158         soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0);
 159         if (IS_ERR(soc_ctrl_dev->base))
 160                 return PTR_ERR(soc_ctrl_dev->base);
 161
 162         return litex_check_csr_access(soc_ctrl_dev->base);
 163 }
 164
 165 static struct platform_driver litex_soc_ctrl_driver = {
 166         .driver = {
 167                 .name = "litex-soc-controller",
 168                 .of_match_table = of_match_ptr(litex_soc_ctrl_of_match)
 169         },
 170         .probe = litex_soc_ctrl_probe,
 171 };
 172
 173 module_platform_driver(litex_soc_ctrl_driver);
 174 MODULE_DESCRIPTION("LiteX SoC Controller driver");
 175 MODULE_AUTHOR("Antmicro <www.antmicro.com>");
 176 MODULE_LICENSE("GPL v2");