drivers/soc/mediatek/mt8173-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8173-power.h>
   8
   9 /*
  10  * MT8173 power domain support
  11  */
  12
  13 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
  14         [MT8173_POWER_DOMAIN_VDEC] = {
  15                 .sta_mask = PWR_STATUS_VDEC,
  16                 .ctl_offs = SPM_VDE_PWR_CON,
  17                 .sram_pdn_bits = GENMASK(11, 8),
  18                 .sram_pdn_ack_bits = GENMASK(12, 12),
  19         },
  20         [MT8173_POWER_DOMAIN_VENC] = {
  21                 .sta_mask = PWR_STATUS_VENC,
  22                 .ctl_offs = SPM_VEN_PWR_CON,
  23                 .sram_pdn_bits = GENMASK(11, 8),
  24                 .sram_pdn_ack_bits = GENMASK(15, 12),
  25         },
  26         [MT8173_POWER_DOMAIN_ISP] = {
  27                 .sta_mask = PWR_STATUS_ISP,
  28                 .ctl_offs = SPM_ISP_PWR_CON,
  29                 .sram_pdn_bits = GENMASK(11, 8),
  30                 .sram_pdn_ack_bits = GENMASK(13, 12),
  31         },
  32         [MT8173_POWER_DOMAIN_MM] = {
  33                 .sta_mask = PWR_STATUS_DISP,
  34                 .ctl_offs = SPM_DIS_PWR_CON,
  35                 .sram_pdn_bits = GENMASK(11, 8),
  36                 .sram_pdn_ack_bits = GENMASK(12, 12),
  37                 .bp_infracfg = {
  38                         BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
  39                                                MT8173_TOP_AXI_PROT_EN_MM_M1),
  40                 },
  41         },
  42         [MT8173_POWER_DOMAIN_VENC_LT] = {
  43                 .sta_mask = PWR_STATUS_VENC_LT,
  44                 .ctl_offs = SPM_VEN2_PWR_CON,
  45                 .sram_pdn_bits = GENMASK(11, 8),
  46                 .sram_pdn_ack_bits = GENMASK(15, 12),
  47         },
  48         [MT8173_POWER_DOMAIN_AUDIO] = {
  49                 .sta_mask = PWR_STATUS_AUDIO,
  50                 .ctl_offs = SPM_AUDIO_PWR_CON,
  51                 .sram_pdn_bits = GENMASK(11, 8),
  52                 .sram_pdn_ack_bits = GENMASK(15, 12),
  53         },
  54         [MT8173_POWER_DOMAIN_USB] = {
  55                 .sta_mask = PWR_STATUS_USB,
  56                 .ctl_offs = SPM_USB_PWR_CON,
  57                 .sram_pdn_bits = GENMASK(11, 8),
  58                 .sram_pdn_ack_bits = GENMASK(15, 12),
  59                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  60         },
  61         [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
  62                 .sta_mask = PWR_STATUS_MFG_ASYNC,
  63                 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
  64                 .sram_pdn_bits = GENMASK(11, 8),
  65                 .sram_pdn_ack_bits = 0,
  66         },
  67         [MT8173_POWER_DOMAIN_MFG_2D] = {
  68                 .sta_mask = PWR_STATUS_MFG_2D,
  69                 .ctl_offs = SPM_MFG_2D_PWR_CON,
  70                 .sram_pdn_bits = GENMASK(11, 8),
  71                 .sram_pdn_ack_bits = GENMASK(13, 12),
  72         },
  73         [MT8173_POWER_DOMAIN_MFG] = {
  74                 .sta_mask = PWR_STATUS_MFG,
  75                 .ctl_offs = SPM_MFG_PWR_CON,
  76                 .sram_pdn_bits = GENMASK(13, 8),
  77                 .sram_pdn_ack_bits = GENMASK(21, 16),
  78                 .bp_infracfg = {
  79                         BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
  80                                                MT8173_TOP_AXI_PROT_EN_MFG_M0 |
  81                                                MT8173_TOP_AXI_PROT_EN_MFG_M1 |
  82                                                MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
  83                 },
  84         },
  85 };
  86
  87 static const struct scpsys_soc_data mt8173_scpsys_data = {
  88         .domains_data = scpsys_domain_data_mt8173,
  89         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
  90         .pwr_sta_offs = SPM_PWR_STATUS,
  91         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  92 };
  93
  94 #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */