Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / soc / mediatek / mtk-pm-domains.h
bloba2f4d8f97e058e424171417fd2e897515ed354fd
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
7 #define MTK_SCPD_FWAIT_SRAM BIT(1)
8 #define MTK_SCPD_SRAM_ISO BIT(2)
9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
10 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
12 #define SPM_VDE_PWR_CON 0x0210
13 #define SPM_MFG_PWR_CON 0x0214
14 #define SPM_VEN_PWR_CON 0x0230
15 #define SPM_ISP_PWR_CON 0x0238
16 #define SPM_DIS_PWR_CON 0x023c
17 #define SPM_VEN2_PWR_CON 0x0298
18 #define SPM_AUDIO_PWR_CON 0x029c
19 #define SPM_MFG_2D_PWR_CON 0x02c0
20 #define SPM_MFG_ASYNC_PWR_CON 0x02c4
21 #define SPM_USB_PWR_CON 0x02cc
23 #define SPM_PWR_STATUS 0x060c
24 #define SPM_PWR_STATUS_2ND 0x0610
26 #define PWR_STATUS_CONN BIT(1)
27 #define PWR_STATUS_DISP BIT(3)
28 #define PWR_STATUS_MFG BIT(4)
29 #define PWR_STATUS_ISP BIT(5)
30 #define PWR_STATUS_VDEC BIT(7)
31 #define PWR_STATUS_VENC_LT BIT(20)
32 #define PWR_STATUS_VENC BIT(21)
33 #define PWR_STATUS_MFG_2D BIT(22)
34 #define PWR_STATUS_MFG_ASYNC BIT(23)
35 #define PWR_STATUS_AUDIO BIT(24)
36 #define PWR_STATUS_USB BIT(25)
38 #define SPM_MAX_BUS_PROT_DATA 5
40 #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
41 .bus_prot_mask = (_mask), \
42 .bus_prot_set = _set, \
43 .bus_prot_clr = _clr, \
44 .bus_prot_sta = _sta, \
45 .bus_prot_reg_update = _update, \
46 .ignore_clr_ack = _ignore, \
49 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
50 _BUS_PROT(_mask, _set, _clr, _sta, false, false)
52 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
53 _BUS_PROT(_mask, _set, _clr, _sta, false, true)
55 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
56 _BUS_PROT(_mask, _set, _clr, _sta, true, false)
58 #define BUS_PROT_UPDATE_TOPAXI(_mask) \
59 BUS_PROT_UPDATE(_mask, \
60 INFRA_TOPAXI_PROTECTEN, \
61 INFRA_TOPAXI_PROTECTEN_CLR, \
62 INFRA_TOPAXI_PROTECTSTA1)
64 struct scpsys_bus_prot_data {
65 u32 bus_prot_mask;
66 u32 bus_prot_set;
67 u32 bus_prot_clr;
68 u32 bus_prot_sta;
69 bool bus_prot_reg_update;
70 bool ignore_clr_ack;
73 #define MAX_SUBSYS_CLKS 10
75 /**
76 * struct scpsys_domain_data - scp domain data for power on/off flow
77 * @sta_mask: The mask for power on/off status bit.
78 * @ctl_offs: The offset for main power control register.
79 * @sram_pdn_bits: The mask for sram power control bits.
80 * @sram_pdn_ack_bits: The mask for sram power control acked bits.
81 * @caps: The flag for active wake-up action.
82 * @bp_infracfg: bus protection for infracfg subsystem
83 * @bp_smi: bus protection for smi subsystem
85 struct scpsys_domain_data {
86 u32 sta_mask;
87 int ctl_offs;
88 u32 sram_pdn_bits;
89 u32 sram_pdn_ack_bits;
90 u8 caps;
91 const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
92 const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
95 struct scpsys_soc_data {
96 const struct scpsys_domain_data *domains_data;
97 int num_domains;
98 int pwr_sta_offs;
99 int pwr_sta2nd_offs;
102 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */