1 // SPDX-License-Identifier: GPL-2.0
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 2008 Cavium Networks
9 * Some parts of the code were originally released under BSD license:
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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15 * modification, are permitted provided that the following conditions are
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22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials provided
24 * with the distribution.
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48 #include <linux/usb.h>
49 #include <linux/slab.h>
50 #include <linux/module.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/prefetch.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
56 #include <asm/octeon/octeon.h>
58 #include "octeon-hcd.h"
61 * enum cvmx_usb_speed - the possible USB device speeds
63 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
64 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
65 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
68 CVMX_USB_SPEED_HIGH
= 0,
69 CVMX_USB_SPEED_FULL
= 1,
70 CVMX_USB_SPEED_LOW
= 2,
74 * enum cvmx_usb_transfer - the possible USB transfer types
76 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
78 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
79 * priority periodic transfers
80 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
82 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
85 enum cvmx_usb_transfer
{
86 CVMX_USB_TRANSFER_CONTROL
= 0,
87 CVMX_USB_TRANSFER_ISOCHRONOUS
= 1,
88 CVMX_USB_TRANSFER_BULK
= 2,
89 CVMX_USB_TRANSFER_INTERRUPT
= 3,
93 * enum cvmx_usb_direction - the transfer directions
95 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
96 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
98 enum cvmx_usb_direction
{
99 CVMX_USB_DIRECTION_OUT
,
100 CVMX_USB_DIRECTION_IN
,
104 * enum cvmx_usb_status - possible callback function status codes
106 * @CVMX_USB_STATUS_OK: The transaction / operation finished without
108 * @CVMX_USB_STATUS_SHORT: FIXME: This is currently not implemented
109 * @CVMX_USB_STATUS_CANCEL: The transaction was canceled while in flight
110 * by a user call to cvmx_usb_cancel
111 * @CVMX_USB_STATUS_ERROR: The transaction aborted with an unexpected
113 * @CVMX_USB_STATUS_STALL: The transaction received a USB STALL response
115 * @CVMX_USB_STATUS_XACTERR: The transaction failed with an error from the
116 * device even after a number of retries
117 * @CVMX_USB_STATUS_DATATGLERR: The transaction failed with a data toggle
118 * error even after a number of retries
119 * @CVMX_USB_STATUS_BABBLEERR: The transaction failed with a babble error
120 * @CVMX_USB_STATUS_FRAMEERR: The transaction failed with a frame error
121 * even after a number of retries
123 enum cvmx_usb_status
{
125 CVMX_USB_STATUS_SHORT
,
126 CVMX_USB_STATUS_CANCEL
,
127 CVMX_USB_STATUS_ERROR
,
128 CVMX_USB_STATUS_STALL
,
129 CVMX_USB_STATUS_XACTERR
,
130 CVMX_USB_STATUS_DATATGLERR
,
131 CVMX_USB_STATUS_BABBLEERR
,
132 CVMX_USB_STATUS_FRAMEERR
,
136 * struct cvmx_usb_port_status - the USB port status information
138 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
139 * @port_over_current: 1 = Over current detected, 0 = Over current not
140 * detected. Octeon doesn't support over current detection.
141 * @port_powered: 1 = Port power is being supplied to the device, 0 =
142 * power is off. Octeon doesn't support turning port power
144 * @port_speed: Current port speed.
145 * @connected: 1 = A device is connected to the port, 0 = No device is
147 * @connect_change: 1 = Device connected state changed since the last set
150 struct cvmx_usb_port_status
{
152 u32 port_enabled
: 1;
153 u32 port_over_current
: 1;
154 u32 port_powered
: 1;
155 enum cvmx_usb_speed port_speed
: 2;
157 u32 connect_change
: 1;
161 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
163 * @offset: This is the offset in bytes into the main buffer where this data
165 * @length: This is the length in bytes of the data.
166 * @status: This is the status of this individual packet transfer.
168 struct cvmx_usb_iso_packet
{
171 enum cvmx_usb_status status
;
175 * enum cvmx_usb_initialize_flags - flags used by the initialization function
177 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
178 * as clock source at USB_XO and
180 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
181 * board clock source at USB_XO.
182 * USB_XI should be tied to GND.
183 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
184 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
186 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
187 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
188 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
189 * data transfer use for the USB
191 enum cvmx_usb_initialize_flags
{
192 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
= 1 << 0,
193 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
= 1 << 1,
194 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
= 3 << 3,
195 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
= 1 << 3,
196 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
= 2 << 3,
197 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
= 3 << 3,
198 /* Bits 3-4 used to encode the clock frequency */
199 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
= 1 << 5,
203 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
205 * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
206 * actively using hardware.
207 * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed
208 * pipe is in the ping state.
210 enum cvmx_usb_pipe_flags
{
211 CVMX_USB_PIPE_FLAGS_SCHEDULED
= 1 << 17,
212 CVMX_USB_PIPE_FLAGS_NEED_PING
= 1 << 18,
215 /* Maximum number of times to retry failed transactions */
216 #define MAX_RETRIES 3
218 /* Maximum number of hardware channels supported by the USB block */
219 #define MAX_CHANNELS 8
222 * The low level hardware can transfer a maximum of this number of bytes in each
223 * transfer. The field is 19 bits wide
225 #define MAX_TRANSFER_BYTES ((1 << 19) - 1)
228 * The low level hardware can transfer a maximum of this number of packets in
229 * each transfer. The field is 10 bits wide
231 #define MAX_TRANSFER_PACKETS ((1 << 10) - 1)
234 * Logical transactions may take numerous low level
235 * transactions, especially when splits are concerned. This
236 * enum represents all of the possible stages a transaction can
237 * be in. Note that split completes are always even. This is so
238 * the NAK handler can backup to the previous low level
239 * transaction with a simple clearing of bit 0.
241 enum cvmx_usb_stage
{
242 CVMX_USB_STAGE_NON_CONTROL
,
243 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
,
244 CVMX_USB_STAGE_SETUP
,
245 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
,
247 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
,
248 CVMX_USB_STAGE_STATUS
,
249 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
,
253 * struct cvmx_usb_transaction - describes each pending USB transaction
254 * regardless of type. These are linked together
255 * to form a list of pending requests for a pipe.
257 * @node: List node for transactions in the pipe.
258 * @type: Type of transaction, duplicated of the pipe.
259 * @flags: State flags for this transaction.
260 * @buffer: User's physical buffer address to read/write.
261 * @buffer_length: Size of the user's buffer in bytes.
262 * @control_header: For control transactions, physical address of the 8
263 * byte standard header.
264 * @iso_start_frame: For ISO transactions, the starting frame number.
265 * @iso_number_packets: For ISO transactions, the number of packets in the
267 * @iso_packets: For ISO transactions, the sub packets in the request.
268 * @actual_bytes: Actual bytes transfer for this transaction.
269 * @stage: For control transactions, the current stage.
272 struct cvmx_usb_transaction
{
273 struct list_head node
;
274 enum cvmx_usb_transfer type
;
279 int iso_number_packets
;
280 struct cvmx_usb_iso_packet
*iso_packets
;
285 enum cvmx_usb_stage stage
;
290 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
291 * and some USB device. It contains a list of pending
292 * request to the device.
294 * @node: List node for pipe list
295 * @next: Pipe after this one in the list
296 * @transactions: List of pending transactions
297 * @interval: For periodic pipes, the interval between packets in
299 * @next_tx_frame: The next frame this pipe is allowed to transmit on
300 * @flags: State flags for this pipe
301 * @device_speed: Speed of device connected to this pipe
302 * @transfer_type: Type of transaction supported by this pipe
303 * @transfer_dir: IN or OUT. Ignored for Control
304 * @multi_count: Max packet in a row for the device
305 * @max_packet: The device's maximum packet size in bytes
306 * @device_addr: USB device address at other end of pipe
307 * @endpoint_num: USB endpoint number at other end of pipe
308 * @hub_device_addr: Hub address this device is connected to
309 * @hub_port: Hub port this device is connected to
310 * @pid_toggle: This toggles between 0/1 on every packet send to track
311 * the data pid needed
312 * @channel: Hardware DMA channel for this pipe
313 * @split_sc_frame: The low order bits of the frame number the split
314 * complete should be sent on
316 struct cvmx_usb_pipe
{
317 struct list_head node
;
318 struct list_head transactions
;
321 enum cvmx_usb_pipe_flags flags
;
322 enum cvmx_usb_speed device_speed
;
323 enum cvmx_usb_transfer transfer_type
;
324 enum cvmx_usb_direction transfer_dir
;
336 struct cvmx_usb_tx_fifo
{
341 } entry
[MAX_CHANNELS
+ 1];
347 * struct octeon_hcd - the state of the USB block
349 * lock: Serialization lock.
350 * init_flags: Flags passed to initialize.
351 * index: Which USB block this is for.
352 * idle_hardware_channels: Bit set for every idle hardware channel.
353 * usbcx_hprt: Stored port status so we don't need to read a CSR to
355 * pipe_for_channel: Map channels to pipes.
356 * pipe: Storage for pipes.
357 * indent: Used by debug output to indent functions.
358 * port_status: Last port status used for change notification.
359 * idle_pipes: List of open pipes that have no transactions.
360 * active_pipes: Active pipes indexed by transfer type.
361 * frame_number: Increments every SOF interrupt for time keeping.
362 * active_split: Points to the current active split, or NULL.
365 spinlock_t lock
; /* serialization lock */
368 int idle_hardware_channels
;
369 union cvmx_usbcx_hprt usbcx_hprt
;
370 struct cvmx_usb_pipe
*pipe_for_channel
[MAX_CHANNELS
];
372 struct cvmx_usb_port_status port_status
;
373 struct list_head idle_pipes
;
374 struct list_head active_pipes
[4];
376 struct cvmx_usb_transaction
*active_split
;
377 struct cvmx_usb_tx_fifo periodic
;
378 struct cvmx_usb_tx_fifo nonperiodic
;
382 * This macro logically sets a single field in a CSR. It does the sequence
383 * read, modify, and write
385 #define USB_SET_FIELD32(address, _union, field, value) \
389 c.u32 = cvmx_usb_read_csr32(usb, address); \
391 cvmx_usb_write_csr32(usb, address, c.u32); \
394 /* Returns the IO address to push/pop stuff data from the FIFOs */
395 #define USB_FIFO_ADDRESS(channel, usb_index) \
396 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel) + 1) * 0x1000)
399 * struct octeon_temp_buffer - a bounce buffer for USB transfers
400 * @orig_buffer: the original buffer passed by the USB stack
401 * @data: the newly allocated temporary buffer (excluding meta-data)
403 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
404 * the buffer is too short, we need to allocate a temporary one, and this struct
407 struct octeon_temp_buffer
{
412 static inline struct usb_hcd
*octeon_to_hcd(struct octeon_hcd
*p
)
414 return container_of((void *)p
, struct usb_hcd
, hcd_priv
);
418 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
421 * @mem_flags: Memory allocation flags.
423 * This function allocates a temporary bounce buffer whenever it's needed
424 * due to HW limitations.
426 static int octeon_alloc_temp_buffer(struct urb
*urb
, gfp_t mem_flags
)
428 struct octeon_temp_buffer
*temp
;
430 if (urb
->num_sgs
|| urb
->sg
||
431 (urb
->transfer_flags
& URB_NO_TRANSFER_DMA_MAP
) ||
432 !(urb
->transfer_buffer_length
% sizeof(u32
)))
435 temp
= kmalloc(ALIGN(urb
->transfer_buffer_length
, sizeof(u32
)) +
436 sizeof(*temp
), mem_flags
);
440 temp
->orig_buffer
= urb
->transfer_buffer
;
441 if (usb_urb_dir_out(urb
))
442 memcpy(temp
->data
, urb
->transfer_buffer
,
443 urb
->transfer_buffer_length
);
444 urb
->transfer_buffer
= temp
->data
;
445 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
451 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
454 * Frees a buffer allocated by octeon_alloc_temp_buffer().
456 static void octeon_free_temp_buffer(struct urb
*urb
)
458 struct octeon_temp_buffer
*temp
;
461 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
464 temp
= container_of(urb
->transfer_buffer
, struct octeon_temp_buffer
,
466 if (usb_urb_dir_in(urb
)) {
467 if (usb_pipeisoc(urb
->pipe
))
468 length
= urb
->transfer_buffer_length
;
470 length
= urb
->actual_length
;
472 memcpy(temp
->orig_buffer
, urb
->transfer_buffer
, length
);
474 urb
->transfer_buffer
= temp
->orig_buffer
;
475 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
480 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
481 * @hcd: USB HCD structure.
483 * @mem_flags: Memory allocation flags.
485 static int octeon_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
490 ret
= octeon_alloc_temp_buffer(urb
, mem_flags
);
494 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
496 octeon_free_temp_buffer(urb
);
502 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
503 * @hcd: USB HCD structure.
506 static void octeon_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
508 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
509 octeon_free_temp_buffer(urb
);
513 * Read a USB 32bit CSR. It performs the necessary address swizzle
514 * for 32bit CSRs and logs the value in a readable format if
517 * @usb: USB block this access is for
518 * @address: 64bit address to read
520 * Returns: Result of the read
522 static inline u32
cvmx_usb_read_csr32(struct octeon_hcd
*usb
, u64 address
)
524 return cvmx_read64_uint32(address
^ 4);
528 * Write a USB 32bit CSR. It performs the necessary address
529 * swizzle for 32bit CSRs and logs the value in a readable format
530 * if debugging is on.
532 * @usb: USB block this access is for
533 * @address: 64bit address to write
534 * @value: Value to write
536 static inline void cvmx_usb_write_csr32(struct octeon_hcd
*usb
,
537 u64 address
, u32 value
)
539 cvmx_write64_uint32(address
^ 4, value
);
540 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
544 * Return non zero if this pipe connects to a non HIGH speed
545 * device through a high speed hub.
547 * @usb: USB block this access is for
548 * @pipe: Pipe to check
550 * Returns: Non zero if we need to do split transactions
552 static inline int cvmx_usb_pipe_needs_split(struct octeon_hcd
*usb
,
553 struct cvmx_usb_pipe
*pipe
)
555 return pipe
->device_speed
!= CVMX_USB_SPEED_HIGH
&&
556 usb
->usbcx_hprt
.s
.prtspd
== CVMX_USB_SPEED_HIGH
;
560 * Trivial utility function to return the correct PID for a pipe
562 * @pipe: pipe to check
564 * Returns: PID for pipe
566 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe
*pipe
)
568 if (pipe
->pid_toggle
)
569 return 2; /* Data1 */
570 return 0; /* Data0 */
573 /* Loops through register until txfflsh or rxfflsh become zero.*/
574 static int cvmx_wait_tx_rx(struct octeon_hcd
*usb
, int fflsh_type
)
577 u64 address
= CVMX_USBCX_GRSTCTL(usb
->index
);
578 u64 done
= cvmx_get_cycle() + 100 *
579 (u64
)octeon_get_clock_rate
/ 1000000;
580 union cvmx_usbcx_grstctl c
;
583 c
.u32
= cvmx_usb_read_csr32(usb
, address
);
584 if (fflsh_type
== 0 && c
.s
.txfflsh
== 0) {
587 } else if (fflsh_type
== 1 && c
.s
.rxfflsh
== 0) {
590 } else if (cvmx_get_cycle() > done
) {
600 static void cvmx_fifo_setup(struct octeon_hcd
*usb
)
602 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3
;
603 union cvmx_usbcx_gnptxfsiz npsiz
;
604 union cvmx_usbcx_hptxfsiz psiz
;
606 usbcx_ghwcfg3
.u32
= cvmx_usb_read_csr32(usb
,
607 CVMX_USBCX_GHWCFG3(usb
->index
));
610 * Program the USBC_GRXFSIZ register to select the size of the receive
613 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb
->index
), cvmx_usbcx_grxfsiz
,
614 rxfdep
, usbcx_ghwcfg3
.s
.dfifodepth
/ 4);
617 * Program the USBC_GNPTXFSIZ register to select the size and the start
618 * address of the non-periodic transmit FIFO for nonperiodic
619 * transactions (50%).
621 npsiz
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
));
622 npsiz
.s
.nptxfdep
= usbcx_ghwcfg3
.s
.dfifodepth
/ 2;
623 npsiz
.s
.nptxfstaddr
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
624 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
), npsiz
.u32
);
627 * Program the USBC_HPTXFSIZ register to select the size and start
628 * address of the periodic transmit FIFO for periodic transactions
631 psiz
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
));
632 psiz
.s
.ptxfsize
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
633 psiz
.s
.ptxfstaddr
= 3 * usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
634 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
), psiz
.u32
);
636 /* Flush all FIFOs */
637 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
638 cvmx_usbcx_grstctl
, txfnum
, 0x10);
639 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
640 cvmx_usbcx_grstctl
, txfflsh
, 1);
641 cvmx_wait_tx_rx(usb
, 0);
642 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
643 cvmx_usbcx_grstctl
, rxfflsh
, 1);
644 cvmx_wait_tx_rx(usb
, 1);
648 * Shutdown a USB port after a call to cvmx_usb_initialize().
649 * The port should be disabled with all pipes closed when this
650 * function is called.
652 * @usb: USB device state populated by cvmx_usb_initialize().
654 * Returns: 0 or a negative error code.
656 static int cvmx_usb_shutdown(struct octeon_hcd
*usb
)
658 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
660 /* Make sure all pipes are closed */
661 if (!list_empty(&usb
->idle_pipes
) ||
662 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_ISOCHRONOUS
]) ||
663 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_INTERRUPT
]) ||
664 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_CONTROL
]) ||
665 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_BULK
]))
668 /* Disable the clocks and put them in power on reset */
669 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
670 usbn_clk_ctl
.s
.enable
= 1;
671 usbn_clk_ctl
.s
.por
= 1;
672 usbn_clk_ctl
.s
.hclk_rst
= 1;
673 usbn_clk_ctl
.s
.prst
= 0;
674 usbn_clk_ctl
.s
.hrst
= 0;
675 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
680 * Initialize a USB port for use. This must be called before any
681 * other access to the Octeon USB port is made. The port starts
682 * off in the disabled state.
684 * @dev: Pointer to struct device for logging purposes.
685 * @usb: Pointer to struct octeon_hcd.
687 * Returns: 0 or a negative error code.
689 static int cvmx_usb_initialize(struct device
*dev
,
690 struct octeon_hcd
*usb
)
695 union cvmx_usbcx_hcfg usbcx_hcfg
;
696 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
697 union cvmx_usbcx_gintsts usbc_gintsts
;
698 union cvmx_usbcx_gahbcfg usbcx_gahbcfg
;
699 union cvmx_usbcx_gintmsk usbcx_gintmsk
;
700 union cvmx_usbcx_gusbcfg usbcx_gusbcfg
;
701 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status
;
705 * Power On Reset and PHY Initialization
707 * 1. Wait for DCOK to assert (nothing to do)
709 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
710 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
712 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
713 usbn_clk_ctl
.s
.por
= 1;
714 usbn_clk_ctl
.s
.hrst
= 0;
715 usbn_clk_ctl
.s
.prst
= 0;
716 usbn_clk_ctl
.s
.hclk_rst
= 0;
717 usbn_clk_ctl
.s
.enable
= 0;
719 * 2b. Select the USB reference clock/crystal parameters by writing
720 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
722 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
) {
724 * The USB port uses 12/24/48MHz 2.5V board clock
725 * source at USB_XO. USB_XI should be tied to GND.
726 * Most Octeon evaluation boards require this setting
728 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
) ||
729 OCTEON_IS_MODEL(OCTEON_CN56XX
) ||
730 OCTEON_IS_MODEL(OCTEON_CN50XX
))
731 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
732 usbn_clk_ctl
.s
.p_rtype
= 2; /* p_rclk=1 & p_xenbn=0 */
734 /* From CN52XX manual */
735 usbn_clk_ctl
.s
.p_rtype
= 1;
737 switch (usb
->init_flags
&
738 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
) {
739 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
:
740 usbn_clk_ctl
.s
.p_c_sel
= 0;
742 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
:
743 usbn_clk_ctl
.s
.p_c_sel
= 1;
745 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
:
746 usbn_clk_ctl
.s
.p_c_sel
= 2;
751 * The USB port uses a 12MHz crystal as clock source
752 * at USB_XO and USB_XI
754 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
))
755 /* From CN31XX,CN30XX manual */
756 usbn_clk_ctl
.s
.p_rtype
= 3; /* p_rclk=1 & p_xenbn=1 */
758 /* From CN56XX,CN52XX,CN50XX manuals. */
759 usbn_clk_ctl
.s
.p_rtype
= 0;
761 usbn_clk_ctl
.s
.p_c_sel
= 0;
764 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
765 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
766 * such that USB is as close as possible to 125Mhz
768 divisor
= DIV_ROUND_UP(octeon_get_clock_rate(), 125000000);
769 /* Lower than 4 doesn't seem to work properly */
772 usbn_clk_ctl
.s
.divide
= divisor
;
773 usbn_clk_ctl
.s
.divide2
= 0;
774 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
776 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
777 usbn_clk_ctl
.s
.hclk_rst
= 1;
778 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
779 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
782 * 3. Program the power-on reset field in the USBN clock-control
784 * USBN_CLK_CTL[POR] = 0
786 usbn_clk_ctl
.s
.por
= 0;
787 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
788 /* 4. Wait 1 ms for PHY clock to start */
791 * 5. Program the Reset input from automatic test equipment field in the
792 * USBP control and status register:
793 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
795 usbn_usbp_ctl_status
.u64
=
796 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
));
797 usbn_usbp_ctl_status
.s
.ate_reset
= 1;
798 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
799 usbn_usbp_ctl_status
.u64
);
800 /* 6. Wait 10 cycles */
803 * 7. Clear ATE_RESET field in the USBN clock-control register:
804 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
806 usbn_usbp_ctl_status
.s
.ate_reset
= 0;
807 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
808 usbn_usbp_ctl_status
.u64
);
810 * 8. Program the PHY reset field in the USBN clock-control register:
811 * USBN_CLK_CTL[PRST] = 1
813 usbn_clk_ctl
.s
.prst
= 1;
814 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
816 * 9. Program the USBP control and status register to select host or
817 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
820 usbn_usbp_ctl_status
.s
.hst_mode
= 0;
821 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
822 usbn_usbp_ctl_status
.u64
);
826 * 11. Program the hreset_n field in the USBN clock-control register:
827 * USBN_CLK_CTL[HRST] = 1
829 usbn_clk_ctl
.s
.hrst
= 1;
830 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
831 /* 12. Proceed to USB core initialization */
832 usbn_clk_ctl
.s
.enable
= 1;
833 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
837 * USB Core Initialization
839 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
840 * determine USB core configuration parameters.
844 * 2. Program the following fields in the global AHB configuration
845 * register (USBC_GAHBCFG)
846 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
847 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
848 * Nonperiodic TxFIFO empty level (slave mode only),
849 * USBC_GAHBCFG[NPTXFEMPLVL]
850 * Periodic TxFIFO empty level (slave mode only),
851 * USBC_GAHBCFG[PTXFEMPLVL]
852 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
854 usbcx_gahbcfg
.u32
= 0;
855 usbcx_gahbcfg
.s
.dmaen
= !(usb
->init_flags
&
856 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
);
857 usbcx_gahbcfg
.s
.hbstlen
= 0;
858 usbcx_gahbcfg
.s
.nptxfemplvl
= 1;
859 usbcx_gahbcfg
.s
.ptxfemplvl
= 1;
860 usbcx_gahbcfg
.s
.glblintrmsk
= 1;
861 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GAHBCFG(usb
->index
),
865 * 3. Program the following fields in USBC_GUSBCFG register.
866 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
867 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
868 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
869 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
871 usbcx_gusbcfg
.u32
= cvmx_usb_read_csr32(usb
,
872 CVMX_USBCX_GUSBCFG(usb
->index
));
873 usbcx_gusbcfg
.s
.toutcal
= 0;
874 usbcx_gusbcfg
.s
.ddrsel
= 0;
875 usbcx_gusbcfg
.s
.usbtrdtim
= 0x5;
876 usbcx_gusbcfg
.s
.phylpwrclksel
= 0;
877 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
),
881 * 4. The software must unmask the following bits in the USBC_GINTMSK
883 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
884 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
886 usbcx_gintmsk
.u32
= cvmx_usb_read_csr32(usb
,
887 CVMX_USBCX_GINTMSK(usb
->index
));
888 usbcx_gintmsk
.s
.otgintmsk
= 1;
889 usbcx_gintmsk
.s
.modemismsk
= 1;
890 usbcx_gintmsk
.s
.hchintmsk
= 1;
891 usbcx_gintmsk
.s
.sofmsk
= 0;
892 /* We need RX FIFO interrupts if we don't have DMA */
893 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
894 usbcx_gintmsk
.s
.rxflvlmsk
= 1;
895 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
),
899 * Disable all channel interrupts. We'll enable them per channel later.
901 for (channel
= 0; channel
< 8; channel
++)
902 cvmx_usb_write_csr32(usb
,
903 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
907 * Host Port Initialization
909 * 1. Program the host-port interrupt-mask field to unmask,
910 * USBC_GINTMSK[PRTINT] = 1
912 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
913 cvmx_usbcx_gintmsk
, prtintmsk
, 1);
914 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
915 cvmx_usbcx_gintmsk
, disconnintmsk
, 1);
918 * 2. Program the USBC_HCFG register to select full-speed host
919 * or high-speed host.
921 usbcx_hcfg
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
));
922 usbcx_hcfg
.s
.fslssupp
= 0;
923 usbcx_hcfg
.s
.fslspclksel
= 0;
924 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
), usbcx_hcfg
.u32
);
926 cvmx_fifo_setup(usb
);
929 * If the controller is getting port events right after the reset, it
930 * means the initialization failed. Try resetting the controller again
931 * in such case. This is seen to happen after cold boot on DSR-1000N.
933 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
934 CVMX_USBCX_GINTSTS(usb
->index
));
935 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
937 dev_dbg(dev
, "gintsts after reset: 0x%x\n", (int)usbc_gintsts
.u32
);
938 if (!usbc_gintsts
.s
.disconnint
&& !usbc_gintsts
.s
.prtint
)
942 dev_info(dev
, "controller reset failed (gintsts=0x%x) - retrying\n",
943 (int)usbc_gintsts
.u32
);
945 cvmx_usb_shutdown(usb
);
951 * Reset a USB port. After this call succeeds, the USB port is
952 * online and servicing requests.
954 * @usb: USB device state populated by cvmx_usb_initialize().
956 static void cvmx_usb_reset_port(struct octeon_hcd
*usb
)
958 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
959 CVMX_USBCX_HPRT(usb
->index
));
961 /* Program the port reset bit to start the reset process */
962 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
966 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
967 * process to complete.
971 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
972 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
976 * Read the port speed field to get the enumerated speed,
979 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
980 CVMX_USBCX_HPRT(usb
->index
));
984 * Disable a USB port. After this call the USB port will not
985 * generate data transfers and will not generate events.
986 * Transactions in process will fail and call their
987 * associated callbacks.
989 * @usb: USB device state populated by cvmx_usb_initialize().
991 * Returns: 0 or a negative error code.
993 static int cvmx_usb_disable(struct octeon_hcd
*usb
)
995 /* Disable the port */
996 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), cvmx_usbcx_hprt
,
1002 * Get the current state of the USB port. Use this call to
1003 * determine if the usb port has anything connected, is enabled,
1004 * or has some sort of error condition. The return value of this
1005 * call has "changed" bits to signal of the value of some fields
1006 * have changed between calls.
1008 * @usb: USB device state populated by cvmx_usb_initialize().
1010 * Returns: Port status information
1012 static struct cvmx_usb_port_status
cvmx_usb_get_status(struct octeon_hcd
*usb
)
1014 union cvmx_usbcx_hprt usbc_hprt
;
1015 struct cvmx_usb_port_status result
;
1017 memset(&result
, 0, sizeof(result
));
1019 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1020 result
.port_enabled
= usbc_hprt
.s
.prtena
;
1021 result
.port_over_current
= usbc_hprt
.s
.prtovrcurract
;
1022 result
.port_powered
= usbc_hprt
.s
.prtpwr
;
1023 result
.port_speed
= usbc_hprt
.s
.prtspd
;
1024 result
.connected
= usbc_hprt
.s
.prtconnsts
;
1025 result
.connect_change
=
1026 result
.connected
!= usb
->port_status
.connected
;
1032 * Open a virtual pipe between the host and a USB device. A pipe
1033 * must be opened before data can be transferred between a device
1036 * @usb: USB device state populated by cvmx_usb_initialize().
1038 * USB device address to open the pipe to
1041 * USB endpoint number to open the pipe to
1044 * The speed of the device the pipe is going
1045 * to. This must match the device's speed,
1046 * which may be different than the port speed.
1047 * @max_packet: The maximum packet length the device can
1048 * transmit/receive (low speed=0-8, full
1049 * speed=0-1023, high speed=0-1024). This value
1050 * comes from the standard endpoint descriptor
1051 * field wMaxPacketSize bits <10:0>.
1053 * The type of transfer this pipe is for.
1055 * The direction the pipe is in. This is not
1056 * used for control pipes.
1057 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1058 * this is how often the transfer is scheduled
1059 * for. All other transfers should specify
1060 * zero. The units are in frames (8000/sec at
1061 * high speed, 1000/sec for full speed).
1063 * For high speed devices, this is the maximum
1064 * allowed number of packet per microframe.
1065 * Specify zero for non high speed devices. This
1066 * value comes from the standard endpoint descriptor
1067 * field wMaxPacketSize bits <12:11>.
1069 * Hub device address this device is connected
1070 * to. Devices connected directly to Octeon
1071 * use zero. This is only used when the device
1072 * is full/low speed behind a high speed hub.
1073 * The address will be of the high speed hub,
1074 * not and full speed hubs after it.
1075 * @hub_port: Which port on the hub the device is
1076 * connected. Use zero for devices connected
1077 * directly to Octeon. Like hub_device_addr,
1078 * this is only used for full/low speed
1079 * devices behind a high speed hub.
1081 * Returns: A non-NULL value is a pipe. NULL means an error.
1083 static struct cvmx_usb_pipe
*cvmx_usb_open_pipe(struct octeon_hcd
*usb
,
1089 enum cvmx_usb_transfer
1091 enum cvmx_usb_direction
1093 int interval
, int multi_count
,
1094 int hub_device_addr
,
1097 struct cvmx_usb_pipe
*pipe
;
1099 pipe
= kzalloc(sizeof(*pipe
), GFP_ATOMIC
);
1102 if ((device_speed
== CVMX_USB_SPEED_HIGH
) &&
1103 (transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1104 (transfer_type
== CVMX_USB_TRANSFER_BULK
))
1105 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
1106 pipe
->device_addr
= device_addr
;
1107 pipe
->endpoint_num
= endpoint_num
;
1108 pipe
->device_speed
= device_speed
;
1109 pipe
->max_packet
= max_packet
;
1110 pipe
->transfer_type
= transfer_type
;
1111 pipe
->transfer_dir
= transfer_dir
;
1112 INIT_LIST_HEAD(&pipe
->transactions
);
1115 * All pipes use interval to rate limit NAK processing. Force an
1116 * interval if one wasn't supplied
1120 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1121 pipe
->interval
= interval
* 8;
1122 /* Force start splits to be schedule on uFrame 0 */
1123 pipe
->next_tx_frame
= ((usb
->frame_number
+ 7) & ~7) +
1126 pipe
->interval
= interval
;
1127 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
;
1129 pipe
->multi_count
= multi_count
;
1130 pipe
->hub_device_addr
= hub_device_addr
;
1131 pipe
->hub_port
= hub_port
;
1132 pipe
->pid_toggle
= 0;
1133 pipe
->split_sc_frame
= -1;
1134 list_add_tail(&pipe
->node
, &usb
->idle_pipes
);
1137 * We don't need to tell the hardware about this pipe yet since
1138 * it doesn't have any submitted requests
1145 * Poll the RX FIFOs and remove data as needed. This function is only used
1146 * in non DMA mode. It is very important that this function be called quickly
1147 * enough to prevent FIFO overflow.
1149 * @usb: USB device state populated by cvmx_usb_initialize().
1151 static void cvmx_usb_poll_rx_fifo(struct octeon_hcd
*usb
)
1153 union cvmx_usbcx_grxstsph rx_status
;
1159 rx_status
.u32
= cvmx_usb_read_csr32(usb
,
1160 CVMX_USBCX_GRXSTSPH(usb
->index
));
1161 /* Only read data if IN data is there */
1162 if (rx_status
.s
.pktsts
!= 2)
1164 /* Check if no data is available */
1165 if (!rx_status
.s
.bcnt
)
1168 channel
= rx_status
.s
.chnum
;
1169 bytes
= rx_status
.s
.bcnt
;
1173 /* Get where the DMA engine would have written this data */
1174 address
= cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) +
1177 ptr
= cvmx_phys_to_ptr(address
);
1178 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
* 8,
1181 /* Loop writing the FIFO data for this packet into memory */
1183 *ptr
++ = cvmx_usb_read_csr32(usb
,
1184 USB_FIFO_ADDRESS(channel
, usb
->index
));
1191 * Fill the TX hardware fifo with data out of the software
1194 * @usb: USB device state populated by cvmx_usb_initialize().
1195 * @fifo: Software fifo to use
1196 * @available: Amount of space in the hardware fifo
1198 * Returns: Non zero if the hardware fifo was too small and needs
1199 * to be serviced again.
1201 static int cvmx_usb_fill_tx_hw(struct octeon_hcd
*usb
,
1202 struct cvmx_usb_tx_fifo
*fifo
, int available
)
1205 * We're done either when there isn't anymore space or the software FIFO
1208 while (available
&& (fifo
->head
!= fifo
->tail
)) {
1210 const u32
*ptr
= cvmx_phys_to_ptr(fifo
->entry
[i
].address
);
1211 u64 csr_address
= USB_FIFO_ADDRESS(fifo
->entry
[i
].channel
,
1213 int words
= available
;
1215 /* Limit the amount of data to what the SW fifo has */
1216 if (fifo
->entry
[i
].size
<= available
) {
1217 words
= fifo
->entry
[i
].size
;
1219 if (fifo
->tail
> MAX_CHANNELS
)
1223 /* Update the next locations and counts */
1225 fifo
->entry
[i
].address
+= words
* 4;
1226 fifo
->entry
[i
].size
-= words
;
1229 * Write the HW fifo data. The read every three writes is due
1230 * to an errata on CN3XXX chips
1233 cvmx_write64_uint32(csr_address
, *ptr
++);
1234 cvmx_write64_uint32(csr_address
, *ptr
++);
1235 cvmx_write64_uint32(csr_address
, *ptr
++);
1236 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1239 cvmx_write64_uint32(csr_address
, *ptr
++);
1241 cvmx_write64_uint32(csr_address
, *ptr
++);
1243 cvmx_write64_uint32(csr_address
, *ptr
++);
1245 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1247 return fifo
->head
!= fifo
->tail
;
1251 * Check the hardware FIFOs and fill them as needed
1253 * @usb: USB device state populated by cvmx_usb_initialize().
1255 static void cvmx_usb_poll_tx_fifo(struct octeon_hcd
*usb
)
1257 if (usb
->periodic
.head
!= usb
->periodic
.tail
) {
1258 union cvmx_usbcx_hptxsts tx_status
;
1260 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1261 CVMX_USBCX_HPTXSTS(usb
->index
));
1262 if (cvmx_usb_fill_tx_hw(usb
, &usb
->periodic
,
1263 tx_status
.s
.ptxfspcavail
))
1264 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1265 cvmx_usbcx_gintmsk
, ptxfempmsk
, 1);
1267 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1268 cvmx_usbcx_gintmsk
, ptxfempmsk
, 0);
1271 if (usb
->nonperiodic
.head
!= usb
->nonperiodic
.tail
) {
1272 union cvmx_usbcx_gnptxsts tx_status
;
1274 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1275 CVMX_USBCX_GNPTXSTS(usb
->index
));
1276 if (cvmx_usb_fill_tx_hw(usb
, &usb
->nonperiodic
,
1277 tx_status
.s
.nptxfspcavail
))
1278 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1279 cvmx_usbcx_gintmsk
, nptxfempmsk
, 1);
1281 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1282 cvmx_usbcx_gintmsk
, nptxfempmsk
, 0);
1287 * Fill the TX FIFO with an outgoing packet
1289 * @usb: USB device state populated by cvmx_usb_initialize().
1290 * @channel: Channel number to get packet from
1292 static void cvmx_usb_fill_tx_fifo(struct octeon_hcd
*usb
, int channel
)
1294 union cvmx_usbcx_hccharx hcchar
;
1295 union cvmx_usbcx_hcspltx usbc_hcsplt
;
1296 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1297 struct cvmx_usb_tx_fifo
*fifo
;
1299 /* We only need to fill data on outbound channels */
1300 hcchar
.u32
= cvmx_usb_read_csr32(usb
,
1301 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
1302 if (hcchar
.s
.epdir
!= CVMX_USB_DIRECTION_OUT
)
1305 /* OUT Splits only have data on the start and not the complete */
1306 usbc_hcsplt
.u32
= cvmx_usb_read_csr32(usb
,
1307 CVMX_USBCX_HCSPLTX(channel
, usb
->index
));
1308 if (usbc_hcsplt
.s
.spltena
&& usbc_hcsplt
.s
.compsplt
)
1312 * Find out how many bytes we need to fill and convert it into 32bit
1315 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1316 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1317 if (!usbc_hctsiz
.s
.xfersize
)
1320 if ((hcchar
.s
.eptype
== CVMX_USB_TRANSFER_INTERRUPT
) ||
1321 (hcchar
.s
.eptype
== CVMX_USB_TRANSFER_ISOCHRONOUS
))
1322 fifo
= &usb
->periodic
;
1324 fifo
= &usb
->nonperiodic
;
1326 fifo
->entry
[fifo
->head
].channel
= channel
;
1327 fifo
->entry
[fifo
->head
].address
=
1328 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1330 fifo
->entry
[fifo
->head
].size
= (usbc_hctsiz
.s
.xfersize
+ 3) >> 2;
1332 if (fifo
->head
> MAX_CHANNELS
)
1335 cvmx_usb_poll_tx_fifo(usb
);
1339 * Perform channel specific setup for Control transactions. All
1340 * the generic stuff will already have been done in cvmx_usb_start_channel().
1342 * @usb: USB device state populated by cvmx_usb_initialize().
1343 * @channel: Channel to setup
1344 * @pipe: Pipe for control transaction
1346 static void cvmx_usb_start_channel_control(struct octeon_hcd
*usb
,
1348 struct cvmx_usb_pipe
*pipe
)
1350 struct usb_hcd
*hcd
= octeon_to_hcd(usb
);
1351 struct device
*dev
= hcd
->self
.controller
;
1352 struct cvmx_usb_transaction
*transaction
=
1353 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1355 struct usb_ctrlrequest
*header
=
1356 cvmx_phys_to_ptr(transaction
->control_header
);
1357 int bytes_to_transfer
= transaction
->buffer_length
-
1358 transaction
->actual_bytes
;
1359 int packets_to_transfer
;
1360 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1362 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1363 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1365 switch (transaction
->stage
) {
1366 case CVMX_USB_STAGE_NON_CONTROL
:
1367 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
1368 dev_err(dev
, "%s: ERROR - Non control stage\n", __func__
);
1370 case CVMX_USB_STAGE_SETUP
:
1371 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1372 bytes_to_transfer
= sizeof(*header
);
1373 /* All Control operations start with a setup going OUT */
1374 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1375 cvmx_usbcx_hccharx
, epdir
,
1376 CVMX_USB_DIRECTION_OUT
);
1378 * Setup send the control header instead of the buffer data. The
1379 * buffer data will be used in the next stage
1381 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1383 transaction
->control_header
);
1385 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
1386 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1387 bytes_to_transfer
= 0;
1388 /* All Control operations start with a setup going OUT */
1389 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1390 cvmx_usbcx_hccharx
, epdir
,
1391 CVMX_USB_DIRECTION_OUT
);
1393 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1394 cvmx_usbcx_hcspltx
, compsplt
, 1);
1396 case CVMX_USB_STAGE_DATA
:
1397 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1398 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1399 if (header
->bRequestType
& USB_DIR_IN
)
1400 bytes_to_transfer
= 0;
1401 else if (bytes_to_transfer
> pipe
->max_packet
)
1402 bytes_to_transfer
= pipe
->max_packet
;
1404 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1405 cvmx_usbcx_hccharx
, epdir
,
1406 ((header
->bRequestType
& USB_DIR_IN
) ?
1407 CVMX_USB_DIRECTION_IN
:
1408 CVMX_USB_DIRECTION_OUT
));
1410 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
1411 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1412 if (!(header
->bRequestType
& USB_DIR_IN
))
1413 bytes_to_transfer
= 0;
1414 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1415 cvmx_usbcx_hccharx
, epdir
,
1416 ((header
->bRequestType
& USB_DIR_IN
) ?
1417 CVMX_USB_DIRECTION_IN
:
1418 CVMX_USB_DIRECTION_OUT
));
1419 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1420 cvmx_usbcx_hcspltx
, compsplt
, 1);
1422 case CVMX_USB_STAGE_STATUS
:
1423 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1424 bytes_to_transfer
= 0;
1425 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1426 cvmx_usbcx_hccharx
, epdir
,
1427 ((header
->bRequestType
& USB_DIR_IN
) ?
1428 CVMX_USB_DIRECTION_OUT
:
1429 CVMX_USB_DIRECTION_IN
));
1431 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
1432 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1433 bytes_to_transfer
= 0;
1434 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1435 cvmx_usbcx_hccharx
, epdir
,
1436 ((header
->bRequestType
& USB_DIR_IN
) ?
1437 CVMX_USB_DIRECTION_OUT
:
1438 CVMX_USB_DIRECTION_IN
));
1439 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1440 cvmx_usbcx_hcspltx
, compsplt
, 1);
1445 * Make sure the transfer never exceeds the byte limit of the hardware.
1446 * Further bytes will be sent as continued transactions
1448 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1449 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1450 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1451 bytes_to_transfer
*= pipe
->max_packet
;
1455 * Calculate the number of packets to transfer. If the length is zero
1456 * we still need to transfer one packet
1458 packets_to_transfer
= DIV_ROUND_UP(bytes_to_transfer
,
1460 if (packets_to_transfer
== 0) {
1461 packets_to_transfer
= 1;
1462 } else if ((packets_to_transfer
> 1) &&
1463 (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1465 * Limit to one packet when not using DMA. Channels must be
1466 * restarted between every packet for IN transactions, so there
1467 * is no reason to do multiple packets in a row
1469 packets_to_transfer
= 1;
1470 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1471 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1473 * Limit the number of packet and data transferred to what the
1474 * hardware can handle
1476 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1477 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1480 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1481 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1483 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1488 * Start a channel to perform the pipe's head transaction
1490 * @usb: USB device state populated by cvmx_usb_initialize().
1491 * @channel: Channel to setup
1492 * @pipe: Pipe to start
1494 static void cvmx_usb_start_channel(struct octeon_hcd
*usb
, int channel
,
1495 struct cvmx_usb_pipe
*pipe
)
1497 struct cvmx_usb_transaction
*transaction
=
1498 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1501 /* Make sure all writes to the DMA region get flushed */
1504 /* Attach the channel to the pipe */
1505 usb
->pipe_for_channel
[channel
] = pipe
;
1506 pipe
->channel
= channel
;
1507 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_SCHEDULED
;
1509 /* Mark this channel as in use */
1510 usb
->idle_hardware_channels
&= ~(1 << channel
);
1512 /* Enable the channel interrupt bits */
1514 union cvmx_usbcx_hcintx usbc_hcint
;
1515 union cvmx_usbcx_hcintmskx usbc_hcintmsk
;
1516 union cvmx_usbcx_haintmsk usbc_haintmsk
;
1518 /* Clear all channel status bits */
1519 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
1520 CVMX_USBCX_HCINTX(channel
, usb
->index
));
1522 cvmx_usb_write_csr32(usb
,
1523 CVMX_USBCX_HCINTX(channel
, usb
->index
),
1526 usbc_hcintmsk
.u32
= 0;
1527 usbc_hcintmsk
.s
.chhltdmsk
= 1;
1528 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1530 * Channels need these extra interrupts when we aren't
1533 usbc_hcintmsk
.s
.datatglerrmsk
= 1;
1534 usbc_hcintmsk
.s
.frmovrunmsk
= 1;
1535 usbc_hcintmsk
.s
.bblerrmsk
= 1;
1536 usbc_hcintmsk
.s
.xacterrmsk
= 1;
1537 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1539 * Splits don't generate xfercompl, so we need
1542 usbc_hcintmsk
.s
.nyetmsk
= 1;
1543 usbc_hcintmsk
.s
.ackmsk
= 1;
1545 usbc_hcintmsk
.s
.nakmsk
= 1;
1546 usbc_hcintmsk
.s
.stallmsk
= 1;
1547 usbc_hcintmsk
.s
.xfercomplmsk
= 1;
1549 cvmx_usb_write_csr32(usb
,
1550 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
1553 /* Enable the channel interrupt to propagate */
1554 usbc_haintmsk
.u32
= cvmx_usb_read_csr32(usb
,
1555 CVMX_USBCX_HAINTMSK(usb
->index
));
1556 usbc_haintmsk
.s
.haintmsk
|= 1 << channel
;
1557 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
),
1561 /* Setup the location the DMA engine uses. */
1564 u64 dma_address
= transaction
->buffer
+
1565 transaction
->actual_bytes
;
1567 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1568 dma_address
= transaction
->buffer
+
1569 transaction
->iso_packets
[0].offset
+
1570 transaction
->actual_bytes
;
1572 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
)
1573 reg
= CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
);
1575 reg
= CVMX_USBNX_DMA0_INB_CHN0(usb
->index
);
1576 cvmx_write64_uint64(reg
+ channel
* 8, dma_address
);
1579 /* Setup both the size of the transfer and the SPLIT characteristics */
1581 union cvmx_usbcx_hcspltx usbc_hcsplt
= {.u32
= 0};
1582 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= 0};
1583 int packets_to_transfer
;
1584 int bytes_to_transfer
= transaction
->buffer_length
-
1585 transaction
->actual_bytes
;
1588 * ISOCHRONOUS transactions store each individual transfer size
1589 * in the packet structure, not the global buffer_length
1591 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1593 transaction
->iso_packets
[0].length
-
1594 transaction
->actual_bytes
;
1597 * We need to do split transactions when we are talking to non
1598 * high speed devices that are behind a high speed hub
1600 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1602 * On the start split phase (stage is even) record the
1603 * frame number we will need to send the split complete.
1604 * We only store the lower two bits since the time ahead
1605 * can only be two frames
1607 if ((transaction
->stage
& 1) == 0) {
1608 if (transaction
->type
== CVMX_USB_TRANSFER_BULK
)
1609 pipe
->split_sc_frame
=
1610 (usb
->frame_number
+ 1) & 0x7f;
1612 pipe
->split_sc_frame
=
1613 (usb
->frame_number
+ 2) & 0x7f;
1615 pipe
->split_sc_frame
= -1;
1618 usbc_hcsplt
.s
.spltena
= 1;
1619 usbc_hcsplt
.s
.hubaddr
= pipe
->hub_device_addr
;
1620 usbc_hcsplt
.s
.prtaddr
= pipe
->hub_port
;
1621 usbc_hcsplt
.s
.compsplt
= (transaction
->stage
==
1622 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
);
1625 * SPLIT transactions can only ever transmit one data
1626 * packet so limit the transfer size to the max packet
1629 if (bytes_to_transfer
> pipe
->max_packet
)
1630 bytes_to_transfer
= pipe
->max_packet
;
1633 * ISOCHRONOUS OUT splits are unique in that they limit
1634 * data transfers to 188 byte chunks representing the
1635 * begin/middle/end of the data or all
1637 if (!usbc_hcsplt
.s
.compsplt
&&
1638 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1639 (pipe
->transfer_type
==
1640 CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
1642 * Clear the split complete frame number as
1643 * there isn't going to be a split complete
1645 pipe
->split_sc_frame
= -1;
1647 * See if we've started this transfer and sent
1650 if (transaction
->actual_bytes
== 0) {
1652 * Nothing sent yet, this is either a
1653 * begin or the entire payload
1655 if (bytes_to_transfer
<= 188)
1656 /* Entire payload in one go */
1657 usbc_hcsplt
.s
.xactpos
= 3;
1659 /* First part of payload */
1660 usbc_hcsplt
.s
.xactpos
= 2;
1663 * Continuing the previous data, we must
1664 * either be in the middle or at the end
1666 if (bytes_to_transfer
<= 188)
1667 /* End of payload */
1668 usbc_hcsplt
.s
.xactpos
= 1;
1670 /* Middle of payload */
1671 usbc_hcsplt
.s
.xactpos
= 0;
1674 * Again, the transfer size is limited to 188
1677 if (bytes_to_transfer
> 188)
1678 bytes_to_transfer
= 188;
1683 * Make sure the transfer never exceeds the byte limit of the
1684 * hardware. Further bytes will be sent as continued
1687 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1689 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1692 bytes_to_transfer
= MAX_TRANSFER_BYTES
/
1694 bytes_to_transfer
*= pipe
->max_packet
;
1698 * Calculate the number of packets to transfer. If the length is
1699 * zero we still need to transfer one packet
1701 packets_to_transfer
=
1702 DIV_ROUND_UP(bytes_to_transfer
, pipe
->max_packet
);
1703 if (packets_to_transfer
== 0) {
1704 packets_to_transfer
= 1;
1705 } else if ((packets_to_transfer
> 1) &&
1707 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1709 * Limit to one packet when not using DMA. Channels must
1710 * be restarted between every packet for IN
1711 * transactions, so there is no reason to do multiple
1714 packets_to_transfer
= 1;
1715 bytes_to_transfer
= packets_to_transfer
*
1717 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1719 * Limit the number of packet and data transferred to
1720 * what the hardware can handle
1722 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1723 bytes_to_transfer
= packets_to_transfer
*
1727 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1728 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1730 /* Update the DATA0/DATA1 toggle */
1731 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1733 * High speed pipes may need a hardware ping before they start
1735 if (pipe
->flags
& CVMX_USB_PIPE_FLAGS_NEED_PING
)
1736 usbc_hctsiz
.s
.dopng
= 1;
1738 cvmx_usb_write_csr32(usb
,
1739 CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1741 cvmx_usb_write_csr32(usb
,
1742 CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1746 /* Setup the Host Channel Characteristics Register */
1748 union cvmx_usbcx_hccharx usbc_hcchar
= {.u32
= 0};
1751 * Set the startframe odd/even properly. This is only used for
1754 usbc_hcchar
.s
.oddfrm
= usb
->frame_number
& 1;
1757 * Set the number of back to back packets allowed by this
1758 * endpoint. Split transactions interpret "ec" as the number of
1759 * immediate retries of failure. These retries happen too
1760 * quickly, so we disable these entirely for splits
1762 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1763 usbc_hcchar
.s
.ec
= 1;
1764 else if (pipe
->multi_count
< 1)
1765 usbc_hcchar
.s
.ec
= 1;
1766 else if (pipe
->multi_count
> 3)
1767 usbc_hcchar
.s
.ec
= 3;
1769 usbc_hcchar
.s
.ec
= pipe
->multi_count
;
1771 /* Set the rest of the endpoint specific settings */
1772 usbc_hcchar
.s
.devaddr
= pipe
->device_addr
;
1773 usbc_hcchar
.s
.eptype
= transaction
->type
;
1774 usbc_hcchar
.s
.lspddev
=
1775 (pipe
->device_speed
== CVMX_USB_SPEED_LOW
);
1776 usbc_hcchar
.s
.epdir
= pipe
->transfer_dir
;
1777 usbc_hcchar
.s
.epnum
= pipe
->endpoint_num
;
1778 usbc_hcchar
.s
.mps
= pipe
->max_packet
;
1779 cvmx_usb_write_csr32(usb
,
1780 CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1784 /* Do transaction type specific fixups as needed */
1785 switch (transaction
->type
) {
1786 case CVMX_USB_TRANSFER_CONTROL
:
1787 cvmx_usb_start_channel_control(usb
, channel
, pipe
);
1789 case CVMX_USB_TRANSFER_BULK
:
1790 case CVMX_USB_TRANSFER_INTERRUPT
:
1792 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
1793 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1795 * ISO transactions require different PIDs depending on
1796 * direction and how many packets are needed
1798 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
1799 if (pipe
->multi_count
< 2) /* Need DATA0 */
1801 CVMX_USBCX_HCTSIZX(channel
,
1803 cvmx_usbcx_hctsizx
, pid
, 0);
1804 else /* Need MDATA */
1806 CVMX_USBCX_HCTSIZX(channel
,
1808 cvmx_usbcx_hctsizx
, pid
, 3);
1814 union cvmx_usbcx_hctsizx usbc_hctsiz
= { .u32
=
1815 cvmx_usb_read_csr32(usb
,
1816 CVMX_USBCX_HCTSIZX(channel
,
1819 transaction
->xfersize
= usbc_hctsiz
.s
.xfersize
;
1820 transaction
->pktcnt
= usbc_hctsiz
.s
.pktcnt
;
1822 /* Remember when we start a split transaction */
1823 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1824 usb
->active_split
= transaction
;
1825 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1826 cvmx_usbcx_hccharx
, chena
, 1);
1827 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
1828 cvmx_usb_fill_tx_fifo(usb
, channel
);
1832 * Find a pipe that is ready to be scheduled to hardware.
1833 * @usb: USB device state populated by cvmx_usb_initialize().
1834 * @xfer_type: Transfer type
1836 * Returns: Pipe or NULL if none are ready
1838 static struct cvmx_usb_pipe
*cvmx_usb_find_ready_pipe(struct octeon_hcd
*usb
,
1839 enum cvmx_usb_transfer xfer_type
)
1841 struct list_head
*list
= usb
->active_pipes
+ xfer_type
;
1842 u64 current_frame
= usb
->frame_number
;
1843 struct cvmx_usb_pipe
*pipe
;
1845 list_for_each_entry(pipe
, list
, node
) {
1846 struct cvmx_usb_transaction
*t
=
1847 list_first_entry(&pipe
->transactions
, typeof(*t
),
1849 if (!(pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
) && t
&&
1850 (pipe
->next_tx_frame
<= current_frame
) &&
1851 ((pipe
->split_sc_frame
== -1) ||
1852 ((((int)current_frame
- pipe
->split_sc_frame
) & 0x7f) <
1854 (!usb
->active_split
|| (usb
->active_split
== t
))) {
1862 static struct cvmx_usb_pipe
*cvmx_usb_next_pipe(struct octeon_hcd
*usb
,
1865 struct cvmx_usb_pipe
*pipe
;
1867 /* Find a pipe needing service. */
1870 * Only process periodic pipes on SOF interrupts. This way we
1871 * are sure that the periodic data is sent in the beginning of
1874 pipe
= cvmx_usb_find_ready_pipe(usb
,
1875 CVMX_USB_TRANSFER_ISOCHRONOUS
);
1878 pipe
= cvmx_usb_find_ready_pipe(usb
,
1879 CVMX_USB_TRANSFER_INTERRUPT
);
1883 pipe
= cvmx_usb_find_ready_pipe(usb
, CVMX_USB_TRANSFER_CONTROL
);
1886 return cvmx_usb_find_ready_pipe(usb
, CVMX_USB_TRANSFER_BULK
);
1890 * Called whenever a pipe might need to be scheduled to the
1893 * @usb: USB device state populated by cvmx_usb_initialize().
1894 * @is_sof: True if this schedule was called on a SOF interrupt.
1896 static void cvmx_usb_schedule(struct octeon_hcd
*usb
, int is_sof
)
1899 struct cvmx_usb_pipe
*pipe
;
1901 enum cvmx_usb_transfer ttype
;
1903 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1905 * Without DMA we need to be careful to not schedule something
1906 * at the end of a frame and cause an overrun.
1908 union cvmx_usbcx_hfnum hfnum
= {
1909 .u32
= cvmx_usb_read_csr32(usb
,
1910 CVMX_USBCX_HFNUM(usb
->index
))
1913 union cvmx_usbcx_hfir hfir
= {
1914 .u32
= cvmx_usb_read_csr32(usb
,
1915 CVMX_USBCX_HFIR(usb
->index
))
1918 if (hfnum
.s
.frrem
< hfir
.s
.frint
/ 4)
1922 while (usb
->idle_hardware_channels
) {
1923 /* Find an idle channel */
1924 channel
= __fls(usb
->idle_hardware_channels
);
1925 if (unlikely(channel
> 7))
1928 pipe
= cvmx_usb_next_pipe(usb
, is_sof
);
1932 cvmx_usb_start_channel(usb
, channel
, pipe
);
1937 * Only enable SOF interrupts when we have transactions pending in the
1938 * future that might need to be scheduled
1941 for (ttype
= CVMX_USB_TRANSFER_CONTROL
;
1942 ttype
<= CVMX_USB_TRANSFER_INTERRUPT
; ttype
++) {
1943 list_for_each_entry(pipe
, &usb
->active_pipes
[ttype
], node
) {
1944 if (pipe
->next_tx_frame
> usb
->frame_number
) {
1950 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1951 cvmx_usbcx_gintmsk
, sofmsk
, need_sof
);
1954 static void octeon_usb_urb_complete_callback(struct octeon_hcd
*usb
,
1955 enum cvmx_usb_status status
,
1956 struct cvmx_usb_pipe
*pipe
,
1957 struct cvmx_usb_transaction
1959 int bytes_transferred
,
1962 struct usb_hcd
*hcd
= octeon_to_hcd(usb
);
1963 struct device
*dev
= hcd
->self
.controller
;
1965 if (likely(status
== CVMX_USB_STATUS_OK
))
1966 urb
->actual_length
= bytes_transferred
;
1968 urb
->actual_length
= 0;
1972 /* For Isochronous transactions we need to update the URB packet status
1973 * list from data in our private copy
1975 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1978 * The pointer to the private list is stored in the setup_packet
1981 struct cvmx_usb_iso_packet
*iso_packet
=
1982 (struct cvmx_usb_iso_packet
*)urb
->setup_packet
;
1983 /* Recalculate the transfer size by adding up each packet */
1984 urb
->actual_length
= 0;
1985 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1986 if (iso_packet
[i
].status
== CVMX_USB_STATUS_OK
) {
1987 urb
->iso_frame_desc
[i
].status
= 0;
1988 urb
->iso_frame_desc
[i
].actual_length
=
1989 iso_packet
[i
].length
;
1990 urb
->actual_length
+=
1991 urb
->iso_frame_desc
[i
].actual_length
;
1993 dev_dbg(dev
, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
1994 i
, urb
->number_of_packets
,
1995 iso_packet
[i
].status
, pipe
,
1996 transaction
, iso_packet
[i
].length
);
1997 urb
->iso_frame_desc
[i
].status
= -EREMOTEIO
;
2000 /* Free the private list now that we don't need it anymore */
2002 urb
->setup_packet
= NULL
;
2006 case CVMX_USB_STATUS_OK
:
2009 case CVMX_USB_STATUS_CANCEL
:
2010 if (urb
->status
== 0)
2011 urb
->status
= -ENOENT
;
2013 case CVMX_USB_STATUS_STALL
:
2014 dev_dbg(dev
, "status=stall pipe=%p transaction=%p size=%d\n",
2015 pipe
, transaction
, bytes_transferred
);
2016 urb
->status
= -EPIPE
;
2018 case CVMX_USB_STATUS_BABBLEERR
:
2019 dev_dbg(dev
, "status=babble pipe=%p transaction=%p size=%d\n",
2020 pipe
, transaction
, bytes_transferred
);
2021 urb
->status
= -EPIPE
;
2023 case CVMX_USB_STATUS_SHORT
:
2024 dev_dbg(dev
, "status=short pipe=%p transaction=%p size=%d\n",
2025 pipe
, transaction
, bytes_transferred
);
2026 urb
->status
= -EREMOTEIO
;
2028 case CVMX_USB_STATUS_ERROR
:
2029 case CVMX_USB_STATUS_XACTERR
:
2030 case CVMX_USB_STATUS_DATATGLERR
:
2031 case CVMX_USB_STATUS_FRAMEERR
:
2032 dev_dbg(dev
, "status=%d pipe=%p transaction=%p size=%d\n",
2033 status
, pipe
, transaction
, bytes_transferred
);
2034 urb
->status
= -EPROTO
;
2037 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(usb
), urb
);
2038 spin_unlock(&usb
->lock
);
2039 usb_hcd_giveback_urb(octeon_to_hcd(usb
), urb
, urb
->status
);
2040 spin_lock(&usb
->lock
);
2044 * Signal the completion of a transaction and free it. The
2045 * transaction will be removed from the pipe transaction list.
2047 * @usb: USB device state populated by cvmx_usb_initialize().
2048 * @pipe: Pipe the transaction is on
2050 * Transaction that completed
2054 static void cvmx_usb_complete(struct octeon_hcd
*usb
,
2055 struct cvmx_usb_pipe
*pipe
,
2056 struct cvmx_usb_transaction
*transaction
,
2057 enum cvmx_usb_status complete_code
)
2059 /* If this was a split then clear our split in progress marker */
2060 if (usb
->active_split
== transaction
)
2061 usb
->active_split
= NULL
;
2064 * Isochronous transactions need extra processing as they might not be
2065 * done after a single data transfer
2067 if (unlikely(transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
2068 /* Update the number of bytes transferred in this ISO packet */
2069 transaction
->iso_packets
[0].length
= transaction
->actual_bytes
;
2070 transaction
->iso_packets
[0].status
= complete_code
;
2073 * If there are more ISOs pending and we succeeded, schedule the
2076 if ((transaction
->iso_number_packets
> 1) &&
2077 (complete_code
== CVMX_USB_STATUS_OK
)) {
2078 /* No bytes transferred for this packet as of yet */
2079 transaction
->actual_bytes
= 0;
2080 /* One less ISO waiting to transfer */
2081 transaction
->iso_number_packets
--;
2082 /* Increment to the next location in our packet array */
2083 transaction
->iso_packets
++;
2084 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2089 /* Remove the transaction from the pipe list */
2090 list_del(&transaction
->node
);
2091 if (list_empty(&pipe
->transactions
))
2092 list_move_tail(&pipe
->node
, &usb
->idle_pipes
);
2093 octeon_usb_urb_complete_callback(usb
, complete_code
, pipe
,
2095 transaction
->actual_bytes
,
2101 * Submit a usb transaction to a pipe. Called for all types
2105 * @pipe: Which pipe to submit to.
2106 * @type: Transaction type
2107 * @buffer: User buffer for the transaction
2109 * User buffer's length in bytes
2111 * For control transactions, the 8 byte standard header
2113 * For ISO transactions, the start frame
2114 * @iso_number_packets:
2115 * For ISO, the number of packet in the transaction.
2117 * A description of each ISO packet
2118 * @urb: URB for the callback
2120 * Returns: Transaction or NULL on failure.
2122 static struct cvmx_usb_transaction
*cvmx_usb_submit_transaction(
2123 struct octeon_hcd
*usb
,
2124 struct cvmx_usb_pipe
*pipe
,
2125 enum cvmx_usb_transfer type
,
2129 int iso_start_frame
,
2130 int iso_number_packets
,
2131 struct cvmx_usb_iso_packet
*iso_packets
,
2134 struct cvmx_usb_transaction
*transaction
;
2136 if (unlikely(pipe
->transfer_type
!= type
))
2139 transaction
= kzalloc(sizeof(*transaction
), GFP_ATOMIC
);
2140 if (unlikely(!transaction
))
2143 transaction
->type
= type
;
2144 transaction
->buffer
= buffer
;
2145 transaction
->buffer_length
= buffer_length
;
2146 transaction
->control_header
= control_header
;
2147 /* FIXME: This is not used, implement it. */
2148 transaction
->iso_start_frame
= iso_start_frame
;
2149 transaction
->iso_number_packets
= iso_number_packets
;
2150 transaction
->iso_packets
= iso_packets
;
2151 transaction
->urb
= urb
;
2152 if (transaction
->type
== CVMX_USB_TRANSFER_CONTROL
)
2153 transaction
->stage
= CVMX_USB_STAGE_SETUP
;
2155 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2157 if (!list_empty(&pipe
->transactions
)) {
2158 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2160 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2161 list_move_tail(&pipe
->node
,
2162 &usb
->active_pipes
[pipe
->transfer_type
]);
2165 * We may need to schedule the pipe if this was the head of the
2168 cvmx_usb_schedule(usb
, 0);
2175 * Call to submit a USB Bulk transfer to a pipe.
2177 * @usb: USB device state populated by cvmx_usb_initialize().
2178 * @pipe: Handle to the pipe for the transfer.
2181 * Returns: A submitted transaction or NULL on failure.
2183 static struct cvmx_usb_transaction
*cvmx_usb_submit_bulk(
2184 struct octeon_hcd
*usb
,
2185 struct cvmx_usb_pipe
*pipe
,
2188 return cvmx_usb_submit_transaction(usb
, pipe
, CVMX_USB_TRANSFER_BULK
,
2190 urb
->transfer_buffer_length
,
2191 0, /* control_header */
2192 0, /* iso_start_frame */
2193 0, /* iso_number_packets */
2194 NULL
, /* iso_packets */
2199 * Call to submit a USB Interrupt transfer to a pipe.
2201 * @usb: USB device state populated by cvmx_usb_initialize().
2202 * @pipe: Handle to the pipe for the transfer.
2203 * @urb: URB returned when the callback is called.
2205 * Returns: A submitted transaction or NULL on failure.
2207 static struct cvmx_usb_transaction
*cvmx_usb_submit_interrupt(
2208 struct octeon_hcd
*usb
,
2209 struct cvmx_usb_pipe
*pipe
,
2212 return cvmx_usb_submit_transaction(usb
, pipe
,
2213 CVMX_USB_TRANSFER_INTERRUPT
,
2215 urb
->transfer_buffer_length
,
2216 0, /* control_header */
2217 0, /* iso_start_frame */
2218 0, /* iso_number_packets */
2219 NULL
, /* iso_packets */
2224 * Call to submit a USB Control transfer to a pipe.
2226 * @usb: USB device state populated by cvmx_usb_initialize().
2227 * @pipe: Handle to the pipe for the transfer.
2230 * Returns: A submitted transaction or NULL on failure.
2232 static struct cvmx_usb_transaction
*cvmx_usb_submit_control(
2233 struct octeon_hcd
*usb
,
2234 struct cvmx_usb_pipe
*pipe
,
2237 int buffer_length
= urb
->transfer_buffer_length
;
2238 u64 control_header
= urb
->setup_dma
;
2239 struct usb_ctrlrequest
*header
= cvmx_phys_to_ptr(control_header
);
2241 if ((header
->bRequestType
& USB_DIR_IN
) == 0)
2242 buffer_length
= le16_to_cpu(header
->wLength
);
2244 return cvmx_usb_submit_transaction(usb
, pipe
,
2245 CVMX_USB_TRANSFER_CONTROL
,
2246 urb
->transfer_dma
, buffer_length
,
2248 0, /* iso_start_frame */
2249 0, /* iso_number_packets */
2250 NULL
, /* iso_packets */
2255 * Call to submit a USB Isochronous transfer to a pipe.
2257 * @usb: USB device state populated by cvmx_usb_initialize().
2258 * @pipe: Handle to the pipe for the transfer.
2259 * @urb: URB returned when the callback is called.
2261 * Returns: A submitted transaction or NULL on failure.
2263 static struct cvmx_usb_transaction
*cvmx_usb_submit_isochronous(
2264 struct octeon_hcd
*usb
,
2265 struct cvmx_usb_pipe
*pipe
,
2268 struct cvmx_usb_iso_packet
*packets
;
2270 packets
= (struct cvmx_usb_iso_packet
*)urb
->setup_packet
;
2271 return cvmx_usb_submit_transaction(usb
, pipe
,
2272 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2274 urb
->transfer_buffer_length
,
2275 0, /* control_header */
2277 urb
->number_of_packets
,
2282 * Cancel one outstanding request in a pipe. Canceling a request
2283 * can fail if the transaction has already completed before cancel
2284 * is called. Even after a successful cancel call, it may take
2285 * a frame or two for the cvmx_usb_poll() function to call the
2286 * associated callback.
2288 * @usb: USB device state populated by cvmx_usb_initialize().
2289 * @pipe: Pipe to cancel requests in.
2290 * @transaction: Transaction to cancel, returned by the submit function.
2292 * Returns: 0 or a negative error code.
2294 static int cvmx_usb_cancel(struct octeon_hcd
*usb
,
2295 struct cvmx_usb_pipe
*pipe
,
2296 struct cvmx_usb_transaction
*transaction
)
2299 * If the transaction is the HEAD of the queue and scheduled. We need to
2302 if (list_first_entry(&pipe
->transactions
, typeof(*transaction
), node
) ==
2303 transaction
&& (pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
)) {
2304 union cvmx_usbcx_hccharx usbc_hcchar
;
2306 usb
->pipe_for_channel
[pipe
->channel
] = NULL
;
2307 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2311 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2312 CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
));
2314 * If the channel isn't enabled then the transaction already
2317 if (usbc_hcchar
.s
.chena
) {
2318 usbc_hcchar
.s
.chdis
= 1;
2319 cvmx_usb_write_csr32(usb
,
2320 CVMX_USBCX_HCCHARX(pipe
->channel
,
2325 cvmx_usb_complete(usb
, pipe
, transaction
, CVMX_USB_STATUS_CANCEL
);
2330 * Cancel all outstanding requests in a pipe. Logically all this
2331 * does is call cvmx_usb_cancel() in a loop.
2333 * @usb: USB device state populated by cvmx_usb_initialize().
2334 * @pipe: Pipe to cancel requests in.
2336 * Returns: 0 or a negative error code.
2338 static int cvmx_usb_cancel_all(struct octeon_hcd
*usb
,
2339 struct cvmx_usb_pipe
*pipe
)
2341 struct cvmx_usb_transaction
*transaction
, *next
;
2343 /* Simply loop through and attempt to cancel each transaction */
2344 list_for_each_entry_safe(transaction
, next
, &pipe
->transactions
, node
) {
2345 int result
= cvmx_usb_cancel(usb
, pipe
, transaction
);
2347 if (unlikely(result
!= 0))
2354 * Close a pipe created with cvmx_usb_open_pipe().
2356 * @usb: USB device state populated by cvmx_usb_initialize().
2357 * @pipe: Pipe to close.
2359 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2360 * outstanding transfers.
2362 static int cvmx_usb_close_pipe(struct octeon_hcd
*usb
,
2363 struct cvmx_usb_pipe
*pipe
)
2365 /* Fail if the pipe has pending transactions */
2366 if (!list_empty(&pipe
->transactions
))
2369 list_del(&pipe
->node
);
2376 * Get the current USB protocol level frame number. The frame
2377 * number is always in the range of 0-0x7ff.
2379 * @usb: USB device state populated by cvmx_usb_initialize().
2381 * Returns: USB frame number
2383 static int cvmx_usb_get_frame_number(struct octeon_hcd
*usb
)
2385 union cvmx_usbcx_hfnum usbc_hfnum
;
2387 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2389 return usbc_hfnum
.s
.frnum
;
2392 static void cvmx_usb_transfer_control(struct octeon_hcd
*usb
,
2393 struct cvmx_usb_pipe
*pipe
,
2394 struct cvmx_usb_transaction
*transaction
,
2395 union cvmx_usbcx_hccharx usbc_hcchar
,
2396 int buffer_space_left
,
2397 int bytes_in_last_packet
)
2399 switch (transaction
->stage
) {
2400 case CVMX_USB_STAGE_NON_CONTROL
:
2401 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
2402 /* This should be impossible */
2403 cvmx_usb_complete(usb
, pipe
, transaction
,
2404 CVMX_USB_STATUS_ERROR
);
2406 case CVMX_USB_STAGE_SETUP
:
2407 pipe
->pid_toggle
= 1;
2408 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2409 transaction
->stage
=
2410 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
;
2412 struct usb_ctrlrequest
*header
=
2413 cvmx_phys_to_ptr(transaction
->control_header
);
2414 if (header
->wLength
)
2415 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2417 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2420 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
2422 struct usb_ctrlrequest
*header
=
2423 cvmx_phys_to_ptr(transaction
->control_header
);
2424 if (header
->wLength
)
2425 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2427 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2430 case CVMX_USB_STAGE_DATA
:
2431 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2432 transaction
->stage
= CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
;
2434 * For setup OUT data that are splits,
2435 * the hardware doesn't appear to count
2436 * transferred data. Here we manually
2437 * update the data transferred
2439 if (!usbc_hcchar
.s
.epdir
) {
2440 if (buffer_space_left
< pipe
->max_packet
)
2441 transaction
->actual_bytes
+=
2444 transaction
->actual_bytes
+=
2447 } else if ((buffer_space_left
== 0) ||
2448 (bytes_in_last_packet
< pipe
->max_packet
)) {
2449 pipe
->pid_toggle
= 1;
2450 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2453 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
2454 if ((buffer_space_left
== 0) ||
2455 (bytes_in_last_packet
< pipe
->max_packet
)) {
2456 pipe
->pid_toggle
= 1;
2457 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2459 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2462 case CVMX_USB_STAGE_STATUS
:
2463 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2464 transaction
->stage
=
2465 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
;
2467 cvmx_usb_complete(usb
, pipe
, transaction
,
2468 CVMX_USB_STATUS_OK
);
2470 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
2471 cvmx_usb_complete(usb
, pipe
, transaction
, CVMX_USB_STATUS_OK
);
2476 static void cvmx_usb_transfer_bulk(struct octeon_hcd
*usb
,
2477 struct cvmx_usb_pipe
*pipe
,
2478 struct cvmx_usb_transaction
*transaction
,
2479 union cvmx_usbcx_hcintx usbc_hcint
,
2480 int buffer_space_left
,
2481 int bytes_in_last_packet
)
2484 * The only time a bulk transfer isn't complete when it finishes with
2485 * an ACK is during a split transaction. For splits we need to continue
2486 * the transfer if more data is needed.
2488 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2489 if (transaction
->stage
== CVMX_USB_STAGE_NON_CONTROL
)
2490 transaction
->stage
=
2491 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2492 else if (buffer_space_left
&&
2493 (bytes_in_last_packet
== pipe
->max_packet
))
2494 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2496 cvmx_usb_complete(usb
, pipe
, transaction
,
2497 CVMX_USB_STATUS_OK
);
2499 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2500 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
2502 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
2503 if (!buffer_space_left
||
2504 (bytes_in_last_packet
< pipe
->max_packet
))
2505 cvmx_usb_complete(usb
, pipe
, transaction
,
2506 CVMX_USB_STATUS_OK
);
2510 static void cvmx_usb_transfer_intr(struct octeon_hcd
*usb
,
2511 struct cvmx_usb_pipe
*pipe
,
2512 struct cvmx_usb_transaction
*transaction
,
2513 int buffer_space_left
,
2514 int bytes_in_last_packet
)
2516 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2517 if (transaction
->stage
== CVMX_USB_STAGE_NON_CONTROL
) {
2518 transaction
->stage
=
2519 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2520 } else if (buffer_space_left
&&
2521 (bytes_in_last_packet
== pipe
->max_packet
)) {
2522 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2524 pipe
->next_tx_frame
+= pipe
->interval
;
2525 cvmx_usb_complete(usb
, pipe
, transaction
,
2526 CVMX_USB_STATUS_OK
);
2528 } else if (!buffer_space_left
||
2529 (bytes_in_last_packet
< pipe
->max_packet
)) {
2530 pipe
->next_tx_frame
+= pipe
->interval
;
2531 cvmx_usb_complete(usb
, pipe
, transaction
, CVMX_USB_STATUS_OK
);
2535 static void cvmx_usb_transfer_isoc(struct octeon_hcd
*usb
,
2536 struct cvmx_usb_pipe
*pipe
,
2537 struct cvmx_usb_transaction
*transaction
,
2538 int buffer_space_left
,
2539 int bytes_in_last_packet
,
2540 int bytes_this_transfer
)
2542 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2544 * ISOCHRONOUS OUT splits don't require a complete split stage.
2545 * Instead they use a sequence of begin OUT splits to transfer
2546 * the data 188 bytes at a time. Once the transfer is complete,
2547 * the pipe sleeps until the next schedule interval.
2549 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
2551 * If no space left or this wasn't a max size packet
2552 * then this transfer is complete. Otherwise start it
2553 * again to send the next 188 bytes
2555 if (!buffer_space_left
|| (bytes_this_transfer
< 188)) {
2556 pipe
->next_tx_frame
+= pipe
->interval
;
2557 cvmx_usb_complete(usb
, pipe
, transaction
,
2558 CVMX_USB_STATUS_OK
);
2562 if (transaction
->stage
==
2563 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
) {
2565 * We are in the incoming data phase. Keep getting data
2566 * until we run out of space or get a small packet
2568 if ((buffer_space_left
== 0) ||
2569 (bytes_in_last_packet
< pipe
->max_packet
)) {
2570 pipe
->next_tx_frame
+= pipe
->interval
;
2571 cvmx_usb_complete(usb
, pipe
, transaction
,
2572 CVMX_USB_STATUS_OK
);
2575 transaction
->stage
=
2576 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2579 pipe
->next_tx_frame
+= pipe
->interval
;
2580 cvmx_usb_complete(usb
, pipe
, transaction
, CVMX_USB_STATUS_OK
);
2585 * Poll a channel for status
2588 * @channel: Channel to poll
2590 * Returns: Zero on success
2592 static int cvmx_usb_poll_channel(struct octeon_hcd
*usb
, int channel
)
2594 struct usb_hcd
*hcd
= octeon_to_hcd(usb
);
2595 struct device
*dev
= hcd
->self
.controller
;
2596 union cvmx_usbcx_hcintx usbc_hcint
;
2597 union cvmx_usbcx_hctsizx usbc_hctsiz
;
2598 union cvmx_usbcx_hccharx usbc_hcchar
;
2599 struct cvmx_usb_pipe
*pipe
;
2600 struct cvmx_usb_transaction
*transaction
;
2601 int bytes_this_transfer
;
2602 int bytes_in_last_packet
;
2603 int packets_processed
;
2604 int buffer_space_left
;
2606 /* Read the interrupt status bits for the channel */
2607 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
2608 CVMX_USBCX_HCINTX(channel
, usb
->index
));
2610 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
2611 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2612 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2614 if (usbc_hcchar
.s
.chena
&& usbc_hcchar
.s
.chdis
) {
2616 * There seems to be a bug in CN31XX which can cause
2617 * interrupt IN transfers to get stuck until we do a
2618 * write of HCCHARX without changing things
2620 cvmx_usb_write_csr32(usb
,
2621 CVMX_USBCX_HCCHARX(channel
,
2628 * In non DMA mode the channels don't halt themselves. We need
2629 * to manually disable channels that are left running
2631 if (!usbc_hcint
.s
.chhltd
) {
2632 if (usbc_hcchar
.s
.chena
) {
2633 union cvmx_usbcx_hcintmskx hcintmsk
;
2634 /* Disable all interrupts except CHHLTD */
2636 hcintmsk
.s
.chhltdmsk
= 1;
2637 cvmx_usb_write_csr32(usb
,
2638 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
2640 usbc_hcchar
.s
.chdis
= 1;
2641 cvmx_usb_write_csr32(usb
,
2642 CVMX_USBCX_HCCHARX(channel
, usb
->index
),
2645 } else if (usbc_hcint
.s
.xfercompl
) {
2647 * Successful IN/OUT with transfer complete.
2648 * Channel halt isn't needed.
2651 dev_err(dev
, "USB%d: Channel %d interrupt without halt\n",
2652 usb
->index
, channel
);
2658 * There is are no interrupts that we need to process when the
2659 * channel is still running
2661 if (!usbc_hcint
.s
.chhltd
)
2665 /* Disable the channel interrupts now that it is done */
2666 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
2667 usb
->idle_hardware_channels
|= (1 << channel
);
2669 /* Make sure this channel is tied to a valid pipe */
2670 pipe
= usb
->pipe_for_channel
[channel
];
2674 transaction
= list_first_entry(&pipe
->transactions
,
2675 typeof(*transaction
),
2677 prefetch(transaction
);
2680 * Disconnect this pipe from the HW channel. Later the schedule
2681 * function will figure out which pipe needs to go
2683 usb
->pipe_for_channel
[channel
] = NULL
;
2684 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2687 * Read the channel config info so we can figure out how much data
2690 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2691 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2692 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
2693 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
2696 * Calculating the number of bytes successfully transferred is dependent
2697 * on the transfer direction
2699 packets_processed
= transaction
->pktcnt
- usbc_hctsiz
.s
.pktcnt
;
2700 if (usbc_hcchar
.s
.epdir
) {
2702 * IN transactions are easy. For every byte received the
2703 * hardware decrements xfersize. All we need to do is subtract
2704 * the current value of xfersize from its starting value and we
2705 * know how many bytes were written to the buffer
2707 bytes_this_transfer
= transaction
->xfersize
-
2708 usbc_hctsiz
.s
.xfersize
;
2711 * OUT transaction don't decrement xfersize. Instead pktcnt is
2712 * decremented on every successful packet send. The hardware
2713 * does this when it receives an ACK, or NYET. If it doesn't
2714 * receive one of these responses pktcnt doesn't change
2716 bytes_this_transfer
= packets_processed
* usbc_hcchar
.s
.mps
;
2718 * The last packet may not be a full transfer if we didn't have
2721 if (bytes_this_transfer
> transaction
->xfersize
)
2722 bytes_this_transfer
= transaction
->xfersize
;
2724 /* Figure out how many bytes were in the last packet of the transfer */
2725 if (packets_processed
)
2726 bytes_in_last_packet
= bytes_this_transfer
-
2727 (packets_processed
- 1) * usbc_hcchar
.s
.mps
;
2729 bytes_in_last_packet
= bytes_this_transfer
;
2732 * As a special case, setup transactions output the setup header, not
2733 * the user's data. For this reason we don't count setup data as bytes
2736 if ((transaction
->stage
== CVMX_USB_STAGE_SETUP
) ||
2737 (transaction
->stage
== CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
))
2738 bytes_this_transfer
= 0;
2741 * Add the bytes transferred to the running total. It is important that
2742 * bytes_this_transfer doesn't count any data that needs to be
2745 transaction
->actual_bytes
+= bytes_this_transfer
;
2746 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
2747 buffer_space_left
= transaction
->iso_packets
[0].length
-
2748 transaction
->actual_bytes
;
2750 buffer_space_left
= transaction
->buffer_length
-
2751 transaction
->actual_bytes
;
2754 * We need to remember the PID toggle state for the next transaction.
2755 * The hardware already updated it for the next transaction
2757 pipe
->pid_toggle
= !(usbc_hctsiz
.s
.pid
== 0);
2760 * For high speed bulk out, assume the next transaction will need to do
2761 * a ping before proceeding. If this isn't true the ACK processing below
2762 * will clear this flag
2764 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2765 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2766 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
))
2767 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
2769 if (WARN_ON_ONCE(bytes_this_transfer
< 0)) {
2771 * In some rare cases the DMA engine seems to get stuck and
2772 * keeps substracting same byte count over and over again. In
2773 * such case we just need to fail every transaction.
2775 cvmx_usb_complete(usb
, pipe
, transaction
,
2776 CVMX_USB_STATUS_ERROR
);
2780 if (usbc_hcint
.s
.stall
) {
2782 * STALL as a response means this transaction cannot be
2783 * completed because the device can't process transactions. Tell
2784 * the user. Any data that was transferred will be counted on
2785 * the actual bytes transferred
2787 pipe
->pid_toggle
= 0;
2788 cvmx_usb_complete(usb
, pipe
, transaction
,
2789 CVMX_USB_STATUS_STALL
);
2790 } else if (usbc_hcint
.s
.xacterr
) {
2792 * XactErr as a response means the device signaled
2793 * something wrong with the transfer. For example, PID
2794 * toggle errors cause these.
2796 cvmx_usb_complete(usb
, pipe
, transaction
,
2797 CVMX_USB_STATUS_XACTERR
);
2798 } else if (usbc_hcint
.s
.bblerr
) {
2799 /* Babble Error (BblErr) */
2800 cvmx_usb_complete(usb
, pipe
, transaction
,
2801 CVMX_USB_STATUS_BABBLEERR
);
2802 } else if (usbc_hcint
.s
.datatglerr
) {
2803 /* Data toggle error */
2804 cvmx_usb_complete(usb
, pipe
, transaction
,
2805 CVMX_USB_STATUS_DATATGLERR
);
2806 } else if (usbc_hcint
.s
.nyet
) {
2808 * NYET as a response is only allowed in three cases: as a
2809 * response to a ping, as a response to a split transaction, and
2810 * as a response to a bulk out. The ping case is handled by
2811 * hardware, so we only have splits and bulk out
2813 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2814 transaction
->retries
= 0;
2816 * If there is more data to go then we need to try
2817 * again. Otherwise this transaction is complete
2819 if ((buffer_space_left
== 0) ||
2820 (bytes_in_last_packet
< pipe
->max_packet
))
2821 cvmx_usb_complete(usb
, pipe
,
2823 CVMX_USB_STATUS_OK
);
2826 * Split transactions retry the split complete 4 times
2827 * then rewind to the start split and do the entire
2828 * transactions again
2830 transaction
->retries
++;
2831 if ((transaction
->retries
& 0x3) == 0) {
2833 * Rewind to the beginning of the transaction by
2834 * anding off the split complete bit
2836 transaction
->stage
&= ~1;
2837 pipe
->split_sc_frame
= -1;
2840 } else if (usbc_hcint
.s
.ack
) {
2841 transaction
->retries
= 0;
2843 * The ACK bit can only be checked after the other error bits.
2844 * This is because a multi packet transfer may succeed in a
2845 * number of packets and then get a different response on the
2846 * last packet. In this case both ACK and the last response bit
2847 * will be set. If none of the other response bits is set, then
2848 * the last packet must have been an ACK
2850 * Since we got an ACK, we know we don't need to do a ping on
2853 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_NEED_PING
;
2855 switch (transaction
->type
) {
2856 case CVMX_USB_TRANSFER_CONTROL
:
2857 cvmx_usb_transfer_control(usb
, pipe
, transaction
,
2860 bytes_in_last_packet
);
2862 case CVMX_USB_TRANSFER_BULK
:
2863 cvmx_usb_transfer_bulk(usb
, pipe
, transaction
,
2864 usbc_hcint
, buffer_space_left
,
2865 bytes_in_last_packet
);
2867 case CVMX_USB_TRANSFER_INTERRUPT
:
2868 cvmx_usb_transfer_intr(usb
, pipe
, transaction
,
2870 bytes_in_last_packet
);
2872 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
2873 cvmx_usb_transfer_isoc(usb
, pipe
, transaction
,
2875 bytes_in_last_packet
,
2876 bytes_this_transfer
);
2879 } else if (usbc_hcint
.s
.nak
) {
2881 * If this was a split then clear our split in progress marker.
2883 if (usb
->active_split
== transaction
)
2884 usb
->active_split
= NULL
;
2886 * NAK as a response means the device couldn't accept the
2887 * transaction, but it should be retried in the future. Rewind
2888 * to the beginning of the transaction by anding off the split
2889 * complete bit. Retry in the next interval
2891 transaction
->retries
= 0;
2892 transaction
->stage
&= ~1;
2893 pipe
->next_tx_frame
+= pipe
->interval
;
2894 if (pipe
->next_tx_frame
< usb
->frame_number
)
2895 pipe
->next_tx_frame
= usb
->frame_number
+
2897 (usb
->frame_number
- pipe
->next_tx_frame
) %
2900 struct cvmx_usb_port_status port
;
2902 port
= cvmx_usb_get_status(usb
);
2903 if (port
.port_enabled
) {
2904 /* We'll retry the exact same transaction again */
2905 transaction
->retries
++;
2908 * We get channel halted interrupts with no result bits
2909 * sets when the cable is unplugged
2911 cvmx_usb_complete(usb
, pipe
, transaction
,
2912 CVMX_USB_STATUS_ERROR
);
2918 static void octeon_usb_port_callback(struct octeon_hcd
*usb
)
2920 spin_unlock(&usb
->lock
);
2921 usb_hcd_poll_rh_status(octeon_to_hcd(usb
));
2922 spin_lock(&usb
->lock
);
2926 * Poll the USB block for status and call all needed callback
2927 * handlers. This function is meant to be called in the interrupt
2928 * handler for the USB controller. It can also be called
2929 * periodically in a loop for non-interrupt based operation.
2931 * @usb: USB device state populated by cvmx_usb_initialize().
2933 * Returns: 0 or a negative error code.
2935 static int cvmx_usb_poll(struct octeon_hcd
*usb
)
2937 union cvmx_usbcx_hfnum usbc_hfnum
;
2938 union cvmx_usbcx_gintsts usbc_gintsts
;
2940 prefetch_range(usb
, sizeof(*usb
));
2942 /* Update the frame counter */
2943 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2944 if ((usb
->frame_number
& 0x3fff) > usbc_hfnum
.s
.frnum
)
2945 usb
->frame_number
+= 0x4000;
2946 usb
->frame_number
&= ~0x3fffull
;
2947 usb
->frame_number
|= usbc_hfnum
.s
.frnum
;
2949 /* Read the pending interrupts */
2950 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
2951 CVMX_USBCX_GINTSTS(usb
->index
));
2953 /* Clear the interrupts now that we know about them */
2954 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
2957 if (usbc_gintsts
.s
.rxflvl
) {
2959 * RxFIFO Non-Empty (RxFLvl)
2960 * Indicates that there is at least one packet pending to be
2961 * read from the RxFIFO.
2963 * In DMA mode this is handled by hardware
2965 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
2966 cvmx_usb_poll_rx_fifo(usb
);
2968 if (usbc_gintsts
.s
.ptxfemp
|| usbc_gintsts
.s
.nptxfemp
) {
2969 /* Fill the Tx FIFOs when not in DMA mode */
2970 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
2971 cvmx_usb_poll_tx_fifo(usb
);
2973 if (usbc_gintsts
.s
.disconnint
|| usbc_gintsts
.s
.prtint
) {
2974 union cvmx_usbcx_hprt usbc_hprt
;
2976 * Disconnect Detected Interrupt (DisconnInt)
2977 * Asserted when a device disconnect is detected.
2979 * Host Port Interrupt (PrtInt)
2980 * The core sets this bit to indicate a change in port status of
2981 * one of the O2P USB core ports in Host mode. The application
2982 * must read the Host Port Control and Status (HPRT) register to
2983 * determine the exact event that caused this interrupt. The
2984 * application must clear the appropriate status bit in the Host
2985 * Port Control and Status register to clear this bit.
2987 * Call the user's port callback
2989 octeon_usb_port_callback(usb
);
2990 /* Clear the port change bits */
2992 cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
2993 usbc_hprt
.s
.prtena
= 0;
2994 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
),
2997 if (usbc_gintsts
.s
.hchint
) {
2999 * Host Channels Interrupt (HChInt)
3000 * The core sets this bit to indicate that an interrupt is
3001 * pending on one of the channels of the core (in Host mode).
3002 * The application must read the Host All Channels Interrupt
3003 * (HAINT) register to determine the exact number of the channel
3004 * on which the interrupt occurred, and then read the
3005 * corresponding Host Channel-n Interrupt (HCINTn) register to
3006 * determine the exact cause of the interrupt. The application
3007 * must clear the appropriate status bit in the HCINTn register
3008 * to clear this bit.
3010 union cvmx_usbcx_haint usbc_haint
;
3012 usbc_haint
.u32
= cvmx_usb_read_csr32(usb
,
3013 CVMX_USBCX_HAINT(usb
->index
));
3014 while (usbc_haint
.u32
) {
3017 channel
= __fls(usbc_haint
.u32
);
3018 cvmx_usb_poll_channel(usb
, channel
);
3019 usbc_haint
.u32
^= 1 << channel
;
3023 cvmx_usb_schedule(usb
, usbc_gintsts
.s
.sof
);
3028 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3029 static inline struct octeon_hcd
*hcd_to_octeon(struct usb_hcd
*hcd
)
3031 return (struct octeon_hcd
*)(hcd
->hcd_priv
);
3034 static irqreturn_t
octeon_usb_irq(struct usb_hcd
*hcd
)
3036 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3037 unsigned long flags
;
3039 spin_lock_irqsave(&usb
->lock
, flags
);
3041 spin_unlock_irqrestore(&usb
->lock
, flags
);
3045 static int octeon_usb_start(struct usb_hcd
*hcd
)
3047 hcd
->state
= HC_STATE_RUNNING
;
3051 static void octeon_usb_stop(struct usb_hcd
*hcd
)
3053 hcd
->state
= HC_STATE_HALT
;
3056 static int octeon_usb_get_frame_number(struct usb_hcd
*hcd
)
3058 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3060 return cvmx_usb_get_frame_number(usb
);
3063 static int octeon_usb_urb_enqueue(struct usb_hcd
*hcd
,
3067 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3068 struct device
*dev
= hcd
->self
.controller
;
3069 struct cvmx_usb_transaction
*transaction
= NULL
;
3070 struct cvmx_usb_pipe
*pipe
;
3071 unsigned long flags
;
3072 struct cvmx_usb_iso_packet
*iso_packet
;
3073 struct usb_host_endpoint
*ep
= urb
->ep
;
3077 spin_lock_irqsave(&usb
->lock
, flags
);
3079 rc
= usb_hcd_link_urb_to_ep(hcd
, urb
);
3081 spin_unlock_irqrestore(&usb
->lock
, flags
);
3086 enum cvmx_usb_transfer transfer_type
;
3087 enum cvmx_usb_speed speed
;
3088 int split_device
= 0;
3091 switch (usb_pipetype(urb
->pipe
)) {
3092 case PIPE_ISOCHRONOUS
:
3093 transfer_type
= CVMX_USB_TRANSFER_ISOCHRONOUS
;
3095 case PIPE_INTERRUPT
:
3096 transfer_type
= CVMX_USB_TRANSFER_INTERRUPT
;
3099 transfer_type
= CVMX_USB_TRANSFER_CONTROL
;
3102 transfer_type
= CVMX_USB_TRANSFER_BULK
;
3105 switch (urb
->dev
->speed
) {
3107 speed
= CVMX_USB_SPEED_LOW
;
3109 case USB_SPEED_FULL
:
3110 speed
= CVMX_USB_SPEED_FULL
;
3113 speed
= CVMX_USB_SPEED_HIGH
;
3117 * For slow devices on high speed ports we need to find the hub
3118 * that does the speed translation so we know where to send the
3119 * split transactions.
3121 if (speed
!= CVMX_USB_SPEED_HIGH
) {
3123 * Start at this device and work our way up the usb
3126 struct usb_device
*dev
= urb
->dev
;
3128 while (dev
->parent
) {
3130 * If our parent is high speed then he'll
3131 * receive the splits.
3133 if (dev
->parent
->speed
== USB_SPEED_HIGH
) {
3134 split_device
= dev
->parent
->devnum
;
3135 split_port
= dev
->portnum
;
3139 * Move up the tree one level. If we make it all
3140 * the way up the tree, then the port must not
3141 * be in high speed mode and we don't need a
3147 pipe
= cvmx_usb_open_pipe(usb
, usb_pipedevice(urb
->pipe
),
3148 usb_pipeendpoint(urb
->pipe
), speed
,
3149 le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3152 usb_pipein(urb
->pipe
) ?
3153 CVMX_USB_DIRECTION_IN
:
3154 CVMX_USB_DIRECTION_OUT
,
3156 (le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3158 split_device
, split_port
);
3160 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3161 spin_unlock_irqrestore(&usb
->lock
, flags
);
3162 dev_dbg(dev
, "Failed to create pipe\n");
3170 switch (usb_pipetype(urb
->pipe
)) {
3171 case PIPE_ISOCHRONOUS
:
3172 dev_dbg(dev
, "Submit isochronous to %d.%d\n",
3173 usb_pipedevice(urb
->pipe
),
3174 usb_pipeendpoint(urb
->pipe
));
3176 * Allocate a structure to use for our private list of
3177 * isochronous packets.
3179 iso_packet
= kmalloc_array(urb
->number_of_packets
,
3180 sizeof(struct cvmx_usb_iso_packet
),
3184 /* Fill the list with the data from the URB */
3185 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
3186 iso_packet
[i
].offset
=
3187 urb
->iso_frame_desc
[i
].offset
;
3188 iso_packet
[i
].length
=
3189 urb
->iso_frame_desc
[i
].length
;
3190 iso_packet
[i
].status
= CVMX_USB_STATUS_ERROR
;
3193 * Store a pointer to the list in the URB setup_packet
3194 * field. We know this currently isn't being used and
3195 * this saves us a bunch of logic.
3197 urb
->setup_packet
= (char *)iso_packet
;
3198 transaction
= cvmx_usb_submit_isochronous(usb
,
3201 * If submit failed we need to free our private packet
3205 urb
->setup_packet
= NULL
;
3210 case PIPE_INTERRUPT
:
3211 dev_dbg(dev
, "Submit interrupt to %d.%d\n",
3212 usb_pipedevice(urb
->pipe
),
3213 usb_pipeendpoint(urb
->pipe
));
3214 transaction
= cvmx_usb_submit_interrupt(usb
, pipe
, urb
);
3217 dev_dbg(dev
, "Submit control to %d.%d\n",
3218 usb_pipedevice(urb
->pipe
),
3219 usb_pipeendpoint(urb
->pipe
));
3220 transaction
= cvmx_usb_submit_control(usb
, pipe
, urb
);
3223 dev_dbg(dev
, "Submit bulk to %d.%d\n",
3224 usb_pipedevice(urb
->pipe
),
3225 usb_pipeendpoint(urb
->pipe
));
3226 transaction
= cvmx_usb_submit_bulk(usb
, pipe
, urb
);
3230 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3231 spin_unlock_irqrestore(&usb
->lock
, flags
);
3232 dev_dbg(dev
, "Failed to submit\n");
3235 urb
->hcpriv
= transaction
;
3236 spin_unlock_irqrestore(&usb
->lock
, flags
);
3240 static int octeon_usb_urb_dequeue(struct usb_hcd
*hcd
,
3244 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3245 unsigned long flags
;
3251 spin_lock_irqsave(&usb
->lock
, flags
);
3253 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
3257 urb
->status
= status
;
3258 cvmx_usb_cancel(usb
, urb
->ep
->hcpriv
, urb
->hcpriv
);
3261 spin_unlock_irqrestore(&usb
->lock
, flags
);
3266 static void octeon_usb_endpoint_disable(struct usb_hcd
*hcd
,
3267 struct usb_host_endpoint
*ep
)
3269 struct device
*dev
= hcd
->self
.controller
;
3272 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3273 struct cvmx_usb_pipe
*pipe
= ep
->hcpriv
;
3274 unsigned long flags
;
3276 spin_lock_irqsave(&usb
->lock
, flags
);
3277 cvmx_usb_cancel_all(usb
, pipe
);
3278 if (cvmx_usb_close_pipe(usb
, pipe
))
3279 dev_dbg(dev
, "Closing pipe %p failed\n", pipe
);
3280 spin_unlock_irqrestore(&usb
->lock
, flags
);
3285 static int octeon_usb_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3287 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3288 struct cvmx_usb_port_status port_status
;
3289 unsigned long flags
;
3291 spin_lock_irqsave(&usb
->lock
, flags
);
3292 port_status
= cvmx_usb_get_status(usb
);
3293 spin_unlock_irqrestore(&usb
->lock
, flags
);
3294 buf
[0] = port_status
.connect_change
<< 1;
3299 static int octeon_usb_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
3300 u16 wIndex
, char *buf
, u16 wLength
)
3302 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3303 struct device
*dev
= hcd
->self
.controller
;
3304 struct cvmx_usb_port_status usb_port_status
;
3306 struct usb_hub_descriptor
*desc
;
3307 unsigned long flags
;
3310 case ClearHubFeature
:
3311 dev_dbg(dev
, "ClearHubFeature\n");
3313 case C_HUB_LOCAL_POWER
:
3314 case C_HUB_OVER_CURRENT
:
3315 /* Nothing required here */
3321 case ClearPortFeature
:
3322 dev_dbg(dev
, "ClearPortFeature\n");
3324 dev_dbg(dev
, " INVALID\n");
3329 case USB_PORT_FEAT_ENABLE
:
3330 dev_dbg(dev
, " ENABLE\n");
3331 spin_lock_irqsave(&usb
->lock
, flags
);
3332 cvmx_usb_disable(usb
);
3333 spin_unlock_irqrestore(&usb
->lock
, flags
);
3335 case USB_PORT_FEAT_SUSPEND
:
3336 dev_dbg(dev
, " SUSPEND\n");
3337 /* Not supported on Octeon */
3339 case USB_PORT_FEAT_POWER
:
3340 dev_dbg(dev
, " POWER\n");
3341 /* Not supported on Octeon */
3343 case USB_PORT_FEAT_INDICATOR
:
3344 dev_dbg(dev
, " INDICATOR\n");
3345 /* Port inidicator not supported */
3347 case USB_PORT_FEAT_C_CONNECTION
:
3348 dev_dbg(dev
, " C_CONNECTION\n");
3349 /* Clears drivers internal connect status change flag */
3350 spin_lock_irqsave(&usb
->lock
, flags
);
3351 usb
->port_status
= cvmx_usb_get_status(usb
);
3352 spin_unlock_irqrestore(&usb
->lock
, flags
);
3354 case USB_PORT_FEAT_C_RESET
:
3355 dev_dbg(dev
, " C_RESET\n");
3357 * Clears the driver's internal Port Reset Change flag.
3359 spin_lock_irqsave(&usb
->lock
, flags
);
3360 usb
->port_status
= cvmx_usb_get_status(usb
);
3361 spin_unlock_irqrestore(&usb
->lock
, flags
);
3363 case USB_PORT_FEAT_C_ENABLE
:
3364 dev_dbg(dev
, " C_ENABLE\n");
3366 * Clears the driver's internal Port Enable/Disable
3369 spin_lock_irqsave(&usb
->lock
, flags
);
3370 usb
->port_status
= cvmx_usb_get_status(usb
);
3371 spin_unlock_irqrestore(&usb
->lock
, flags
);
3373 case USB_PORT_FEAT_C_SUSPEND
:
3374 dev_dbg(dev
, " C_SUSPEND\n");
3376 * Clears the driver's internal Port Suspend Change
3377 * flag, which is set when resume signaling on the host
3381 case USB_PORT_FEAT_C_OVER_CURRENT
:
3382 dev_dbg(dev
, " C_OVER_CURRENT\n");
3383 /* Clears the driver's overcurrent Change flag */
3384 spin_lock_irqsave(&usb
->lock
, flags
);
3385 usb
->port_status
= cvmx_usb_get_status(usb
);
3386 spin_unlock_irqrestore(&usb
->lock
, flags
);
3389 dev_dbg(dev
, " UNKNOWN\n");
3393 case GetHubDescriptor
:
3394 dev_dbg(dev
, "GetHubDescriptor\n");
3395 desc
= (struct usb_hub_descriptor
*)buf
;
3396 desc
->bDescLength
= 9;
3397 desc
->bDescriptorType
= 0x29;
3398 desc
->bNbrPorts
= 1;
3399 desc
->wHubCharacteristics
= cpu_to_le16(0x08);
3400 desc
->bPwrOn2PwrGood
= 1;
3401 desc
->bHubContrCurrent
= 0;
3402 desc
->u
.hs
.DeviceRemovable
[0] = 0;
3403 desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3406 dev_dbg(dev
, "GetHubStatus\n");
3410 dev_dbg(dev
, "GetPortStatus\n");
3412 dev_dbg(dev
, " INVALID\n");
3416 spin_lock_irqsave(&usb
->lock
, flags
);
3417 usb_port_status
= cvmx_usb_get_status(usb
);
3418 spin_unlock_irqrestore(&usb
->lock
, flags
);
3421 if (usb_port_status
.connect_change
) {
3422 port_status
|= (1 << USB_PORT_FEAT_C_CONNECTION
);
3423 dev_dbg(dev
, " C_CONNECTION\n");
3426 if (usb_port_status
.port_enabled
) {
3427 port_status
|= (1 << USB_PORT_FEAT_C_ENABLE
);
3428 dev_dbg(dev
, " C_ENABLE\n");
3431 if (usb_port_status
.connected
) {
3432 port_status
|= (1 << USB_PORT_FEAT_CONNECTION
);
3433 dev_dbg(dev
, " CONNECTION\n");
3436 if (usb_port_status
.port_enabled
) {
3437 port_status
|= (1 << USB_PORT_FEAT_ENABLE
);
3438 dev_dbg(dev
, " ENABLE\n");
3441 if (usb_port_status
.port_over_current
) {
3442 port_status
|= (1 << USB_PORT_FEAT_OVER_CURRENT
);
3443 dev_dbg(dev
, " OVER_CURRENT\n");
3446 if (usb_port_status
.port_powered
) {
3447 port_status
|= (1 << USB_PORT_FEAT_POWER
);
3448 dev_dbg(dev
, " POWER\n");
3451 if (usb_port_status
.port_speed
== CVMX_USB_SPEED_HIGH
) {
3452 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3453 dev_dbg(dev
, " HIGHSPEED\n");
3454 } else if (usb_port_status
.port_speed
== CVMX_USB_SPEED_LOW
) {
3455 port_status
|= (1 << USB_PORT_FEAT_LOWSPEED
);
3456 dev_dbg(dev
, " LOWSPEED\n");
3459 *((__le32
*)buf
) = cpu_to_le32(port_status
);
3462 dev_dbg(dev
, "SetHubFeature\n");
3463 /* No HUB features supported */
3465 case SetPortFeature
:
3466 dev_dbg(dev
, "SetPortFeature\n");
3468 dev_dbg(dev
, " INVALID\n");
3473 case USB_PORT_FEAT_SUSPEND
:
3474 dev_dbg(dev
, " SUSPEND\n");
3476 case USB_PORT_FEAT_POWER
:
3477 dev_dbg(dev
, " POWER\n");
3479 * Program the port power bit to drive VBUS on the USB.
3481 spin_lock_irqsave(&usb
->lock
, flags
);
3482 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
3483 cvmx_usbcx_hprt
, prtpwr
, 1);
3484 spin_unlock_irqrestore(&usb
->lock
, flags
);
3486 case USB_PORT_FEAT_RESET
:
3487 dev_dbg(dev
, " RESET\n");
3488 spin_lock_irqsave(&usb
->lock
, flags
);
3489 cvmx_usb_reset_port(usb
);
3490 spin_unlock_irqrestore(&usb
->lock
, flags
);
3492 case USB_PORT_FEAT_INDICATOR
:
3493 dev_dbg(dev
, " INDICATOR\n");
3497 dev_dbg(dev
, " UNKNOWN\n");
3502 dev_dbg(dev
, "Unknown root hub request\n");
3508 static const struct hc_driver octeon_hc_driver
= {
3509 .description
= "Octeon USB",
3510 .product_desc
= "Octeon Host Controller",
3511 .hcd_priv_size
= sizeof(struct octeon_hcd
),
3512 .irq
= octeon_usb_irq
,
3513 .flags
= HCD_MEMORY
| HCD_DMA
| HCD_USB2
,
3514 .start
= octeon_usb_start
,
3515 .stop
= octeon_usb_stop
,
3516 .urb_enqueue
= octeon_usb_urb_enqueue
,
3517 .urb_dequeue
= octeon_usb_urb_dequeue
,
3518 .endpoint_disable
= octeon_usb_endpoint_disable
,
3519 .get_frame_number
= octeon_usb_get_frame_number
,
3520 .hub_status_data
= octeon_usb_hub_status_data
,
3521 .hub_control
= octeon_usb_hub_control
,
3522 .map_urb_for_dma
= octeon_map_urb_for_dma
,
3523 .unmap_urb_for_dma
= octeon_unmap_urb_for_dma
,
3526 static int octeon_usb_probe(struct platform_device
*pdev
)
3529 int initialize_flags
;
3531 struct resource
*res_mem
;
3532 struct device_node
*usbn_node
;
3533 int irq
= platform_get_irq(pdev
, 0);
3534 struct device
*dev
= &pdev
->dev
;
3535 struct octeon_hcd
*usb
;
3536 struct usb_hcd
*hcd
;
3537 u32 clock_rate
= 48000000;
3538 bool is_crystal_clock
= false;
3539 const char *clock_type
;
3542 if (!dev
->of_node
) {
3543 dev_err(dev
, "Error: empty of_node\n");
3546 usbn_node
= dev
->of_node
->parent
;
3548 i
= of_property_read_u32(usbn_node
,
3549 "clock-frequency", &clock_rate
);
3551 i
= of_property_read_u32(usbn_node
,
3552 "refclk-frequency", &clock_rate
);
3554 dev_err(dev
, "No USBN \"clock-frequency\"\n");
3557 switch (clock_rate
) {
3559 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
;
3562 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
;
3565 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
;
3568 dev_err(dev
, "Illegal USBN \"clock-frequency\" %u\n",
3573 i
= of_property_read_string(usbn_node
,
3574 "cavium,refclk-type", &clock_type
);
3576 i
= of_property_read_string(usbn_node
,
3577 "refclk-type", &clock_type
);
3579 if (!i
&& strcmp("crystal", clock_type
) == 0)
3580 is_crystal_clock
= true;
3582 if (is_crystal_clock
)
3583 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
;
3585 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
;
3587 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3589 dev_err(dev
, "found no memory resource\n");
3592 usb_num
= (res_mem
->start
>> 44) & 1;
3595 /* Defective device tree, but we know how to fix it. */
3596 irq_hw_number_t hwirq
= usb_num
? (1 << 6) + 17 : 56;
3598 irq
= irq_create_mapping(NULL
, hwirq
);
3602 * Set the DMA mask to 64bits so we get buffers already translated for
3605 i
= dma_coerce_mask_and_coherent(dev
, DMA_BIT_MASK(64));
3610 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3611 * IOB priority registers. Under heavy network load USB
3612 * hardware can be starved by the IOB causing a crash. Give
3613 * it a priority boost if it has been waiting more than 400
3614 * cycles to avoid this situation.
3616 * Testing indicates that a cnt_val of 8192 is not sufficient,
3617 * but no failures are seen with 4096. We choose a value of
3618 * 400 to give a safety factor of 10.
3620 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) || OCTEON_IS_MODEL(OCTEON_CN56XX
)) {
3621 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt
;
3624 pri_cnt
.s
.cnt_enb
= 1;
3625 pri_cnt
.s
.cnt_val
= 400;
3626 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT
, pri_cnt
.u64
);
3629 hcd
= usb_create_hcd(&octeon_hc_driver
, dev
, dev_name(dev
));
3631 dev_dbg(dev
, "Failed to allocate memory for HCD\n");
3634 hcd
->uses_new_polling
= 1;
3635 usb
= (struct octeon_hcd
*)hcd
->hcd_priv
;
3637 spin_lock_init(&usb
->lock
);
3639 usb
->init_flags
= initialize_flags
;
3641 /* Initialize the USB state structure */
3642 usb
->index
= usb_num
;
3643 INIT_LIST_HEAD(&usb
->idle_pipes
);
3644 for (i
= 0; i
< ARRAY_SIZE(usb
->active_pipes
); i
++)
3645 INIT_LIST_HEAD(&usb
->active_pipes
[i
]);
3647 /* Due to an errata, CN31XX doesn't support DMA */
3648 if (OCTEON_IS_MODEL(OCTEON_CN31XX
)) {
3649 usb
->init_flags
|= CVMX_USB_INITIALIZE_FLAGS_NO_DMA
;
3650 /* Only use one channel with non DMA */
3651 usb
->idle_hardware_channels
= 0x1;
3652 } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX
)) {
3653 /* CN5XXX have an errata with channel 3 */
3654 usb
->idle_hardware_channels
= 0xf7;
3656 usb
->idle_hardware_channels
= 0xff;
3659 status
= cvmx_usb_initialize(dev
, usb
);
3661 dev_dbg(dev
, "USB initialization failed with %d\n", status
);
3666 status
= usb_add_hcd(hcd
, irq
, 0);
3668 dev_dbg(dev
, "USB add HCD failed with %d\n", status
);
3672 device_wakeup_enable(hcd
->self
.controller
);
3674 dev_info(dev
, "Registered HCD for port %d on irq %d\n", usb_num
, irq
);
3679 static int octeon_usb_remove(struct platform_device
*pdev
)
3682 struct device
*dev
= &pdev
->dev
;
3683 struct usb_hcd
*hcd
= dev_get_drvdata(dev
);
3684 struct octeon_hcd
*usb
= hcd_to_octeon(hcd
);
3685 unsigned long flags
;
3687 usb_remove_hcd(hcd
);
3688 spin_lock_irqsave(&usb
->lock
, flags
);
3689 status
= cvmx_usb_shutdown(usb
);
3690 spin_unlock_irqrestore(&usb
->lock
, flags
);
3692 dev_dbg(dev
, "USB shutdown failed with %d\n", status
);
3699 static const struct of_device_id octeon_usb_match
[] = {
3701 .compatible
= "cavium,octeon-5750-usbc",
3705 MODULE_DEVICE_TABLE(of
, octeon_usb_match
);
3707 static struct platform_driver octeon_usb_driver
= {
3709 .name
= "octeon-hcd",
3710 .of_match_table
= octeon_usb_match
,
3712 .probe
= octeon_usb_probe
,
3713 .remove
= octeon_usb_remove
,
3716 static int __init
octeon_usb_driver_init(void)
3721 return platform_driver_register(&octeon_usb_driver
);
3723 module_init(octeon_usb_driver_init
);
3725 static void __exit
octeon_usb_driver_exit(void)
3730 platform_driver_unregister(&octeon_usb_driver
);
3732 module_exit(octeon_usb_driver_exit
);
3734 MODULE_LICENSE("GPL");
3735 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3736 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");