1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Driver for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2001 Russell King.
10 #include <linux/serial_8250.h>
11 #include <linux/serial_reg.h>
12 #include <linux/dmaengine.h>
14 #include "../serial_mctrl_gpio.h"
16 struct uart_8250_dma
{
17 int (*tx_dma
)(struct uart_8250_port
*p
);
18 int (*rx_dma
)(struct uart_8250_port
*p
);
22 /* Parameter to the filter function */
26 struct dma_slave_config rxconf
;
27 struct dma_slave_config txconf
;
29 struct dma_chan
*rxchan
;
30 struct dma_chan
*txchan
;
32 /* Device address base for DMA operations */
33 phys_addr_t rx_dma_addr
;
34 phys_addr_t tx_dma_addr
;
36 /* DMA address of the buffer in memory */
40 dma_cookie_t rx_cookie
;
41 dma_cookie_t tx_cookie
;
48 unsigned char tx_running
;
50 unsigned char rx_running
;
53 struct old_serial_port
{
55 unsigned int baud_base
;
59 unsigned char io_type
;
60 unsigned char __iomem
*iomem_base
;
61 unsigned short iomem_reg_shift
;
64 struct serial8250_config
{
66 unsigned short fifo_size
;
67 unsigned short tx_loadsz
;
69 unsigned char rxtrig_bytes
[UART_FCR_R_TRIG_MAX_STATE
];
73 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
74 #define UART_CAP_EFR (1 << 9) /* UART has EFR */
75 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
76 #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
77 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
78 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
79 #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
80 #define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
81 #define UART_CAP_IRDA (1 << 16) /* UART supports IrDA line discipline */
82 #define UART_CAP_MINI (1 << 17) /* Mini UART on BCM283X family lacks:
83 * STOP PARITY EPAR SPAR WLEN5 WLEN6
86 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
87 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
88 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
89 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
90 #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
93 #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
94 #define SERIAL8250_SHARE_IRQS 1
96 #define SERIAL8250_SHARE_IRQS 0
99 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
103 .uartclk = 1843200, \
104 .iotype = UPIO_PORT, \
105 .flags = UPF_BOOT_AUTOCONF | (_flags), \
108 #define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
111 static inline int serial_in(struct uart_8250_port
*up
, int offset
)
113 return up
->port
.serial_in(&up
->port
, offset
);
116 static inline void serial_out(struct uart_8250_port
*up
, int offset
, int value
)
118 up
->port
.serial_out(&up
->port
, offset
, value
);
121 void serial8250_clear_and_reinit_fifos(struct uart_8250_port
*p
);
123 static inline int serial_dl_read(struct uart_8250_port
*up
)
125 return up
->dl_read(up
);
128 static inline void serial_dl_write(struct uart_8250_port
*up
, int value
)
130 up
->dl_write(up
, value
);
133 static inline bool serial8250_set_THRI(struct uart_8250_port
*up
)
135 if (up
->ier
& UART_IER_THRI
)
137 up
->ier
|= UART_IER_THRI
;
138 serial_out(up
, UART_IER
, up
->ier
);
142 static inline bool serial8250_clear_THRI(struct uart_8250_port
*up
)
144 if (!(up
->ier
& UART_IER_THRI
))
146 up
->ier
&= ~UART_IER_THRI
;
147 serial_out(up
, UART_IER
, up
->ier
);
151 struct uart_8250_port
*serial8250_get_port(int line
);
153 void serial8250_rpm_get(struct uart_8250_port
*p
);
154 void serial8250_rpm_put(struct uart_8250_port
*p
);
156 void serial8250_rpm_get_tx(struct uart_8250_port
*p
);
157 void serial8250_rpm_put_tx(struct uart_8250_port
*p
);
159 int serial8250_em485_config(struct uart_port
*port
, struct serial_rs485
*rs485
);
160 void serial8250_em485_start_tx(struct uart_8250_port
*p
);
161 void serial8250_em485_stop_tx(struct uart_8250_port
*p
);
162 void serial8250_em485_destroy(struct uart_8250_port
*p
);
164 /* MCR <-> TIOCM conversion */
165 static inline int serial8250_TIOCM_to_MCR(int tiocm
)
169 if (tiocm
& TIOCM_RTS
)
171 if (tiocm
& TIOCM_DTR
)
173 if (tiocm
& TIOCM_OUT1
)
174 mcr
|= UART_MCR_OUT1
;
175 if (tiocm
& TIOCM_OUT2
)
176 mcr
|= UART_MCR_OUT2
;
177 if (tiocm
& TIOCM_LOOP
)
178 mcr
|= UART_MCR_LOOP
;
183 static inline int serial8250_MCR_to_TIOCM(int mcr
)
187 if (mcr
& UART_MCR_RTS
)
189 if (mcr
& UART_MCR_DTR
)
191 if (mcr
& UART_MCR_OUT1
)
193 if (mcr
& UART_MCR_OUT2
)
195 if (mcr
& UART_MCR_LOOP
)
201 /* MSR <-> TIOCM conversion */
202 static inline int serial8250_MSR_to_TIOCM(int msr
)
206 if (msr
& UART_MSR_DCD
)
208 if (msr
& UART_MSR_RI
)
210 if (msr
& UART_MSR_DSR
)
212 if (msr
& UART_MSR_CTS
)
218 static inline void serial8250_out_MCR(struct uart_8250_port
*up
, int value
)
220 serial_out(up
, UART_MCR
, value
);
223 mctrl_gpio_set(up
->gpios
, serial8250_MCR_to_TIOCM(value
));
226 static inline int serial8250_in_MCR(struct uart_8250_port
*up
)
230 mctrl
= serial_in(up
, UART_MCR
);
233 unsigned int mctrl_gpio
= 0;
235 mctrl_gpio
= mctrl_gpio_get_outputs(up
->gpios
, &mctrl_gpio
);
236 mctrl
|= serial8250_TIOCM_to_MCR(mctrl_gpio
);
242 #if defined(__alpha__) && !defined(CONFIG_PCI)
244 * Digital did something really horribly wrong with the OUT1 and OUT2
245 * lines on at least some ALPHA's. The failure mode is that if either
246 * is cleared, the machine locks up with endless interrupts.
248 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
250 #define ALPHA_KLUDGE_MCR 0
253 #ifdef CONFIG_SERIAL_8250_PNP
254 int serial8250_pnp_init(void);
255 void serial8250_pnp_exit(void);
257 static inline int serial8250_pnp_init(void) { return 0; }
258 static inline void serial8250_pnp_exit(void) { }
261 #ifdef CONFIG_SERIAL_8250_FINTEK
262 int fintek_8250_probe(struct uart_8250_port
*uart
);
264 static inline int fintek_8250_probe(struct uart_8250_port
*uart
) { return 0; }
267 #ifdef CONFIG_ARCH_OMAP1
268 static inline int is_omap1_8250(struct uart_8250_port
*pt
)
272 switch (pt
->port
.mapbase
) {
273 case OMAP1_UART1_BASE
:
274 case OMAP1_UART2_BASE
:
275 case OMAP1_UART3_BASE
:
286 static inline int is_omap1510_8250(struct uart_8250_port
*pt
)
288 if (!cpu_is_omap1510())
291 return is_omap1_8250(pt
);
294 static inline int is_omap1_8250(struct uart_8250_port
*pt
)
298 static inline int is_omap1510_8250(struct uart_8250_port
*pt
)
304 #ifdef CONFIG_SERIAL_8250_DMA
305 extern int serial8250_tx_dma(struct uart_8250_port
*);
306 extern int serial8250_rx_dma(struct uart_8250_port
*);
307 extern void serial8250_rx_dma_flush(struct uart_8250_port
*);
308 extern int serial8250_request_dma(struct uart_8250_port
*);
309 extern void serial8250_release_dma(struct uart_8250_port
*);
311 static inline int serial8250_tx_dma(struct uart_8250_port
*p
)
315 static inline int serial8250_rx_dma(struct uart_8250_port
*p
)
319 static inline void serial8250_rx_dma_flush(struct uart_8250_port
*p
) { }
320 static inline int serial8250_request_dma(struct uart_8250_port
*p
)
324 static inline void serial8250_release_dma(struct uart_8250_port
*p
) { }
327 static inline int ns16550a_goto_highspeed(struct uart_8250_port
*up
)
329 unsigned char status
;
331 status
= serial_in(up
, 0x04); /* EXCR2 */
332 #define PRESL(x) ((x) & 0x30)
333 if (PRESL(status
) == 0x10) {
334 /* already in high speed mode */
337 status
&= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
338 status
|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
339 serial_out(up
, 0x04, status
);
344 static inline int serial_index(struct uart_port
*port
)
346 return port
->minor
- 64;