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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / tty / serial / fsl_lpuart.c
blobbd047e1f9bea71f982b4d743b3dc1cc7c60887f4
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/console.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dmapool.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/of_dma.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty_flip.h>
22
23 /* All registers are 8-bit width */
24 #define UARTBDH 0x00
25 #define UARTBDL 0x01
26 #define UARTCR1 0x02
27 #define UARTCR2 0x03
28 #define UARTSR1 0x04
29 #define UARTCR3 0x06
30 #define UARTDR 0x07
31 #define UARTCR4 0x0a
32 #define UARTCR5 0x0b
33 #define UARTMODEM 0x0d
34 #define UARTPFIFO 0x10
35 #define UARTCFIFO 0x11
36 #define UARTSFIFO 0x12
37 #define UARTTWFIFO 0x13
38 #define UARTTCFIFO 0x14
39 #define UARTRWFIFO 0x15
40
41 #define UARTBDH_LBKDIE 0x80
42 #define UARTBDH_RXEDGIE 0x40
43 #define UARTBDH_SBR_MASK 0x1f
44
45 #define UARTCR1_LOOPS 0x80
46 #define UARTCR1_RSRC 0x20
47 #define UARTCR1_M 0x10
48 #define UARTCR1_WAKE 0x08
49 #define UARTCR1_ILT 0x04
50 #define UARTCR1_PE 0x02
51 #define UARTCR1_PT 0x01
52
53 #define UARTCR2_TIE 0x80
54 #define UARTCR2_TCIE 0x40
55 #define UARTCR2_RIE 0x20
56 #define UARTCR2_ILIE 0x10
57 #define UARTCR2_TE 0x08
58 #define UARTCR2_RE 0x04
59 #define UARTCR2_RWU 0x02
60 #define UARTCR2_SBK 0x01
61
62 #define UARTSR1_TDRE 0x80
63 #define UARTSR1_TC 0x40
64 #define UARTSR1_RDRF 0x20
65 #define UARTSR1_IDLE 0x10
66 #define UARTSR1_OR 0x08
67 #define UARTSR1_NF 0x04
68 #define UARTSR1_FE 0x02
69 #define UARTSR1_PE 0x01
70
71 #define UARTCR3_R8 0x80
72 #define UARTCR3_T8 0x40
73 #define UARTCR3_TXDIR 0x20
74 #define UARTCR3_TXINV 0x10
75 #define UARTCR3_ORIE 0x08
76 #define UARTCR3_NEIE 0x04
77 #define UARTCR3_FEIE 0x02
78 #define UARTCR3_PEIE 0x01
79
80 #define UARTCR4_MAEN1 0x80
81 #define UARTCR4_MAEN2 0x40
82 #define UARTCR4_M10 0x20
83 #define UARTCR4_BRFA_MASK 0x1f
84 #define UARTCR4_BRFA_OFF 0
85
86 #define UARTCR5_TDMAS 0x80
87 #define UARTCR5_RDMAS 0x20
88
89 #define UARTMODEM_RXRTSE 0x08
90 #define UARTMODEM_TXRTSPOL 0x04
91 #define UARTMODEM_TXRTSE 0x02
92 #define UARTMODEM_TXCTSE 0x01
93
94 #define UARTPFIFO_TXFE 0x80
95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
96 #define UARTPFIFO_TXSIZE_OFF 4
97 #define UARTPFIFO_RXFE 0x08
98 #define UARTPFIFO_RXSIZE_OFF 0
99
100 #define UARTCFIFO_TXFLUSH 0x80
101 #define UARTCFIFO_RXFLUSH 0x40
102 #define UARTCFIFO_RXOFE 0x04
103 #define UARTCFIFO_TXOFE 0x02
104 #define UARTCFIFO_RXUFE 0x01
105
106 #define UARTSFIFO_TXEMPT 0x80
107 #define UARTSFIFO_RXEMPT 0x40
108 #define UARTSFIFO_RXOF 0x04
109 #define UARTSFIFO_TXOF 0x02
110 #define UARTSFIFO_RXUF 0x01
111
112 /* 32-bit register definition */
113 #define UARTBAUD 0x00
114 #define UARTSTAT 0x04
115 #define UARTCTRL 0x08
116 #define UARTDATA 0x0C
117 #define UARTMATCH 0x10
118 #define UARTMODIR 0x14
119 #define UARTFIFO 0x18
120 #define UARTWATER 0x1c
121
122 #define UARTBAUD_MAEN1 0x80000000
123 #define UARTBAUD_MAEN2 0x40000000
124 #define UARTBAUD_M10 0x20000000
125 #define UARTBAUD_TDMAE 0x00800000
126 #define UARTBAUD_RDMAE 0x00200000
127 #define UARTBAUD_MATCFG 0x00400000
128 #define UARTBAUD_BOTHEDGE 0x00020000
129 #define UARTBAUD_RESYNCDIS 0x00010000
130 #define UARTBAUD_LBKDIE 0x00008000
131 #define UARTBAUD_RXEDGIE 0x00004000
132 #define UARTBAUD_SBNS 0x00002000
133 #define UARTBAUD_SBR 0x00000000
134 #define UARTBAUD_SBR_MASK 0x1fff
135 #define UARTBAUD_OSR_MASK 0x1f
136 #define UARTBAUD_OSR_SHIFT 24
137
138 #define UARTSTAT_LBKDIF 0x80000000
139 #define UARTSTAT_RXEDGIF 0x40000000
140 #define UARTSTAT_MSBF 0x20000000
141 #define UARTSTAT_RXINV 0x10000000
142 #define UARTSTAT_RWUID 0x08000000
143 #define UARTSTAT_BRK13 0x04000000
144 #define UARTSTAT_LBKDE 0x02000000
145 #define UARTSTAT_RAF 0x01000000
146 #define UARTSTAT_TDRE 0x00800000
147 #define UARTSTAT_TC 0x00400000
148 #define UARTSTAT_RDRF 0x00200000
149 #define UARTSTAT_IDLE 0x00100000
150 #define UARTSTAT_OR 0x00080000
151 #define UARTSTAT_NF 0x00040000
152 #define UARTSTAT_FE 0x00020000
153 #define UARTSTAT_PE 0x00010000
154 #define UARTSTAT_MA1F 0x00008000
155 #define UARTSTAT_M21F 0x00004000
156
157 #define UARTCTRL_R8T9 0x80000000
158 #define UARTCTRL_R9T8 0x40000000
159 #define UARTCTRL_TXDIR 0x20000000
160 #define UARTCTRL_TXINV 0x10000000
161 #define UARTCTRL_ORIE 0x08000000
162 #define UARTCTRL_NEIE 0x04000000
163 #define UARTCTRL_FEIE 0x02000000
164 #define UARTCTRL_PEIE 0x01000000
165 #define UARTCTRL_TIE 0x00800000
166 #define UARTCTRL_TCIE 0x00400000
167 #define UARTCTRL_RIE 0x00200000
168 #define UARTCTRL_ILIE 0x00100000
169 #define UARTCTRL_TE 0x00080000
170 #define UARTCTRL_RE 0x00040000
171 #define UARTCTRL_RWU 0x00020000
172 #define UARTCTRL_SBK 0x00010000
173 #define UARTCTRL_MA1IE 0x00008000
174 #define UARTCTRL_MA2IE 0x00004000
175 #define UARTCTRL_IDLECFG 0x00000100
176 #define UARTCTRL_LOOPS 0x00000080
177 #define UARTCTRL_DOZEEN 0x00000040
178 #define UARTCTRL_RSRC 0x00000020
179 #define UARTCTRL_M 0x00000010
180 #define UARTCTRL_WAKE 0x00000008
181 #define UARTCTRL_ILT 0x00000004
182 #define UARTCTRL_PE 0x00000002
183 #define UARTCTRL_PT 0x00000001
184
185 #define UARTDATA_NOISY 0x00008000
186 #define UARTDATA_PARITYE 0x00004000
187 #define UARTDATA_FRETSC 0x00002000
188 #define UARTDATA_RXEMPT 0x00001000
189 #define UARTDATA_IDLINE 0x00000800
190 #define UARTDATA_MASK 0x3ff
191
192 #define UARTMODIR_IREN 0x00020000
193 #define UARTMODIR_TXCTSSRC 0x00000020
194 #define UARTMODIR_TXCTSC 0x00000010
195 #define UARTMODIR_RXRTSE 0x00000008
196 #define UARTMODIR_TXRTSPOL 0x00000004
197 #define UARTMODIR_TXRTSE 0x00000002
198 #define UARTMODIR_TXCTSE 0x00000001
199
200 #define UARTFIFO_TXEMPT 0x00800000
201 #define UARTFIFO_RXEMPT 0x00400000
202 #define UARTFIFO_TXOF 0x00020000
203 #define UARTFIFO_RXUF 0x00010000
204 #define UARTFIFO_TXFLUSH 0x00008000
205 #define UARTFIFO_RXFLUSH 0x00004000
206 #define UARTFIFO_TXOFE 0x00000200
207 #define UARTFIFO_RXUFE 0x00000100
208 #define UARTFIFO_TXFE 0x00000080
209 #define UARTFIFO_FIFOSIZE_MASK 0x7
210 #define UARTFIFO_TXSIZE_OFF 4
211 #define UARTFIFO_RXFE 0x00000008
212 #define UARTFIFO_RXSIZE_OFF 0
213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
214
215 #define UARTWATER_COUNT_MASK 0xff
216 #define UARTWATER_TXCNT_OFF 8
217 #define UARTWATER_RXCNT_OFF 24
218 #define UARTWATER_WATER_MASK 0xff
219 #define UARTWATER_TXWATER_OFF 0
220 #define UARTWATER_RXWATER_OFF 16
221
222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
223 #define DMA_RX_TIMEOUT (10)
224
225 #define DRIVER_NAME "fsl-lpuart"
226 #define DEV_NAME "ttyLP"
227 #define UART_NR 6
228
229 /* IMX lpuart has four extra unused regs located at the beginning */
230 #define IMX_REG_OFF 0x10
231
232 static DEFINE_IDA(fsl_lpuart_ida);
233
234 enum lpuart_type {
235 VF610_LPUART,
236 LS1021A_LPUART,
237 LS1028A_LPUART,
238 IMX7ULP_LPUART,
239 IMX8QXP_LPUART,
240 };
241
242 struct lpuart_port {
243 struct uart_port port;
244 enum lpuart_type devtype;
245 struct clk *ipg_clk;
246 struct clk *baud_clk;
247 unsigned int txfifo_size;
248 unsigned int rxfifo_size;
249
250 bool lpuart_dma_tx_use;
251 bool lpuart_dma_rx_use;
252 struct dma_chan *dma_tx_chan;
253 struct dma_chan *dma_rx_chan;
254 struct dma_async_tx_descriptor *dma_tx_desc;
255 struct dma_async_tx_descriptor *dma_rx_desc;
256 dma_cookie_t dma_tx_cookie;
257 dma_cookie_t dma_rx_cookie;
258 unsigned int dma_tx_bytes;
259 unsigned int dma_rx_bytes;
260 bool dma_tx_in_progress;
261 unsigned int dma_rx_timeout;
262 struct timer_list lpuart_timer;
263 struct scatterlist rx_sgl, tx_sgl[2];
264 struct circ_buf rx_ring;
265 int rx_dma_rng_buf_len;
266 unsigned int dma_tx_nents;
267 wait_queue_head_t dma_wait;
268 bool id_allocated;
269 };
270
271 struct lpuart_soc_data {
272 enum lpuart_type devtype;
273 char iotype;
274 u8 reg_off;
275 };
276
277 static const struct lpuart_soc_data vf_data = {
278 .devtype = VF610_LPUART,
279 .iotype = UPIO_MEM,
280 };
281
282 static const struct lpuart_soc_data ls1021a_data = {
283 .devtype = LS1021A_LPUART,
284 .iotype = UPIO_MEM32BE,
285 };
286
287 static const struct lpuart_soc_data ls1028a_data = {
288 .devtype = LS1028A_LPUART,
289 .iotype = UPIO_MEM32,
290 };
291
292 static struct lpuart_soc_data imx7ulp_data = {
293 .devtype = IMX7ULP_LPUART,
294 .iotype = UPIO_MEM32,
295 .reg_off = IMX_REG_OFF,
296 };
297
298 static struct lpuart_soc_data imx8qxp_data = {
299 .devtype = IMX8QXP_LPUART,
300 .iotype = UPIO_MEM32,
301 .reg_off = IMX_REG_OFF,
302 };
303
304 static const struct of_device_id lpuart_dt_ids[] = {
305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
310 { /* sentinel */ }
311 };
312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
313
314 /* Forward declare this for the dma callbacks*/
315 static void lpuart_dma_tx_complete(void *arg);
316
317 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
318 {
319 return (sport->devtype == LS1021A_LPUART ||
320 sport->devtype == LS1028A_LPUART);
321 }
322
323 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
324 {
325 return sport->devtype == IMX8QXP_LPUART;
326 }
327
328 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
329 {
330 switch (port->iotype) {
331 case UPIO_MEM32:
332 return readl(port->membase + off);
333 case UPIO_MEM32BE:
334 return ioread32be(port->membase + off);
335 default:
336 return 0;
337 }
338 }
339
340 static inline void lpuart32_write(struct uart_port *port, u32 val,
341 u32 off)
342 {
343 switch (port->iotype) {
344 case UPIO_MEM32:
345 writel(val, port->membase + off);
346 break;
347 case UPIO_MEM32BE:
348 iowrite32be(val, port->membase + off);
349 break;
350 }
351 }
352
353 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
354 {
355 int ret = 0;
356
357 if (is_en) {
358 ret = clk_prepare_enable(sport->ipg_clk);
359 if (ret)
360 return ret;
361
362 ret = clk_prepare_enable(sport->baud_clk);
363 if (ret) {
364 clk_disable_unprepare(sport->ipg_clk);
365 return ret;
366 }
367 } else {
368 clk_disable_unprepare(sport->baud_clk);
369 clk_disable_unprepare(sport->ipg_clk);
370 }
371
372 return 0;
373 }
374
375 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
376 {
377 if (is_imx8qxp_lpuart(sport))
378 return clk_get_rate(sport->baud_clk);
379
380 return clk_get_rate(sport->ipg_clk);
381 }
382
383 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
384 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
385
386 static void lpuart_stop_tx(struct uart_port *port)
387 {
388 unsigned char temp;
389
390 temp = readb(port->membase + UARTCR2);
391 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
392 writeb(temp, port->membase + UARTCR2);
393 }
394
395 static void lpuart32_stop_tx(struct uart_port *port)
396 {
397 unsigned long temp;
398
399 temp = lpuart32_read(port, UARTCTRL);
400 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
401 lpuart32_write(port, temp, UARTCTRL);
402 }
403
404 static void lpuart_stop_rx(struct uart_port *port)
405 {
406 unsigned char temp;
407
408 temp = readb(port->membase + UARTCR2);
409 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
410 }
411
412 static void lpuart32_stop_rx(struct uart_port *port)
413 {
414 unsigned long temp;
415
416 temp = lpuart32_read(port, UARTCTRL);
417 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
418 }
419
420 static void lpuart_dma_tx(struct lpuart_port *sport)
421 {
422 struct circ_buf *xmit = &sport->port.state->xmit;
423 struct scatterlist *sgl = sport->tx_sgl;
424 struct device *dev = sport->port.dev;
425 struct dma_chan *chan = sport->dma_tx_chan;
426 int ret;
427
428 if (sport->dma_tx_in_progress)
429 return;
430
431 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
432
433 if (xmit->tail < xmit->head || xmit->head == 0) {
434 sport->dma_tx_nents = 1;
435 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
436 } else {
437 sport->dma_tx_nents = 2;
438 sg_init_table(sgl, 2);
439 sg_set_buf(sgl, xmit->buf + xmit->tail,
440 UART_XMIT_SIZE - xmit->tail);
441 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
442 }
443
444 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
445 DMA_TO_DEVICE);
446 if (!ret) {
447 dev_err(dev, "DMA mapping error for TX.\n");
448 return;
449 }
450
451 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
452 ret, DMA_MEM_TO_DEV,
453 DMA_PREP_INTERRUPT);
454 if (!sport->dma_tx_desc) {
455 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
456 DMA_TO_DEVICE);
457 dev_err(dev, "Cannot prepare TX slave DMA!\n");
458 return;
459 }
460
461 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
462 sport->dma_tx_desc->callback_param = sport;
463 sport->dma_tx_in_progress = true;
464 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
465 dma_async_issue_pending(chan);
466 }
467
468 static bool lpuart_stopped_or_empty(struct uart_port *port)
469 {
470 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
471 }
472
473 static void lpuart_dma_tx_complete(void *arg)
474 {
475 struct lpuart_port *sport = arg;
476 struct scatterlist *sgl = &sport->tx_sgl[0];
477 struct circ_buf *xmit = &sport->port.state->xmit;
478 struct dma_chan *chan = sport->dma_tx_chan;
479 unsigned long flags;
480
481 spin_lock_irqsave(&sport->port.lock, flags);
482
483 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
484 DMA_TO_DEVICE);
485
486 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
487
488 sport->port.icount.tx += sport->dma_tx_bytes;
489 sport->dma_tx_in_progress = false;
490 spin_unlock_irqrestore(&sport->port.lock, flags);
491
492 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
493 uart_write_wakeup(&sport->port);
494
495 if (waitqueue_active(&sport->dma_wait)) {
496 wake_up(&sport->dma_wait);
497 return;
498 }
499
500 spin_lock_irqsave(&sport->port.lock, flags);
501
502 if (!lpuart_stopped_or_empty(&sport->port))
503 lpuart_dma_tx(sport);
504
505 spin_unlock_irqrestore(&sport->port.lock, flags);
506 }
507
508 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
509 {
510 switch (sport->port.iotype) {
511 case UPIO_MEM32:
512 return sport->port.mapbase + UARTDATA;
513 case UPIO_MEM32BE:
514 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
515 }
516 return sport->port.mapbase + UARTDR;
517 }
518
519 static int lpuart_dma_tx_request(struct uart_port *port)
520 {
521 struct lpuart_port *sport = container_of(port,
522 struct lpuart_port, port);
523 struct dma_slave_config dma_tx_sconfig = {};
524 int ret;
525
526 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
527 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
528 dma_tx_sconfig.dst_maxburst = 1;
529 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
530 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
531
532 if (ret) {
533 dev_err(sport->port.dev,
534 "DMA slave config failed, err = %d\n", ret);
535 return ret;
536 }
537
538 return 0;
539 }
540
541 static bool lpuart_is_32(struct lpuart_port *sport)
542 {
543 return sport->port.iotype == UPIO_MEM32 ||
544 sport->port.iotype == UPIO_MEM32BE;
545 }
546
547 static void lpuart_flush_buffer(struct uart_port *port)
548 {
549 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
550 struct dma_chan *chan = sport->dma_tx_chan;
551 u32 val;
552
553 if (sport->lpuart_dma_tx_use) {
554 if (sport->dma_tx_in_progress) {
555 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
556 sport->dma_tx_nents, DMA_TO_DEVICE);
557 sport->dma_tx_in_progress = false;
558 }
559 dmaengine_terminate_all(chan);
560 }
561
562 if (lpuart_is_32(sport)) {
563 val = lpuart32_read(&sport->port, UARTFIFO);
564 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
565 lpuart32_write(&sport->port, val, UARTFIFO);
566 } else {
567 val = readb(sport->port.membase + UARTCFIFO);
568 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
569 writeb(val, sport->port.membase + UARTCFIFO);
570 }
571 }
572
573 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
574 u8 bit)
575 {
576 while (!(readb(port->membase + offset) & bit))
577 cpu_relax();
578 }
579
580 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
581 u32 bit)
582 {
583 while (!(lpuart32_read(port, offset) & bit))
584 cpu_relax();
585 }
586
587 #if defined(CONFIG_CONSOLE_POLL)
588
589 static int lpuart_poll_init(struct uart_port *port)
590 {
591 struct lpuart_port *sport = container_of(port,
592 struct lpuart_port, port);
593 unsigned long flags;
594 unsigned char temp;
595
596 sport->port.fifosize = 0;
597
598 spin_lock_irqsave(&sport->port.lock, flags);
599 /* Disable Rx & Tx */
600 writeb(0, sport->port.membase + UARTCR2);
601
602 temp = readb(sport->port.membase + UARTPFIFO);
603 /* Enable Rx and Tx FIFO */
604 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
605 sport->port.membase + UARTPFIFO);
606
607 /* flush Tx and Rx FIFO */
608 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
609 sport->port.membase + UARTCFIFO);
610
611 /* explicitly clear RDRF */
612 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
613 readb(sport->port.membase + UARTDR);
614 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
615 }
616
617 writeb(0, sport->port.membase + UARTTWFIFO);
618 writeb(1, sport->port.membase + UARTRWFIFO);
619
620 /* Enable Rx and Tx */
621 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
622 spin_unlock_irqrestore(&sport->port.lock, flags);
623
624 return 0;
625 }
626
627 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
628 {
629 /* drain */
630 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
631 writeb(c, port->membase + UARTDR);
632 }
633
634 static int lpuart_poll_get_char(struct uart_port *port)
635 {
636 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
637 return NO_POLL_CHAR;
638
639 return readb(port->membase + UARTDR);
640 }
641
642 static int lpuart32_poll_init(struct uart_port *port)
643 {
644 unsigned long flags;
645 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
646 u32 temp;
647
648 sport->port.fifosize = 0;
649
650 spin_lock_irqsave(&sport->port.lock, flags);
651
652 /* Disable Rx & Tx */
653 lpuart32_write(&sport->port, 0, UARTCTRL);
654
655 temp = lpuart32_read(&sport->port, UARTFIFO);
656
657 /* Enable Rx and Tx FIFO */
658 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
659
660 /* flush Tx and Rx FIFO */
661 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
662
663 /* explicitly clear RDRF */
664 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
665 lpuart32_read(&sport->port, UARTDATA);
666 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
667 }
668
669 /* Enable Rx and Tx */
670 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
671 spin_unlock_irqrestore(&sport->port.lock, flags);
672
673 return 0;
674 }
675
676 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
677 {
678 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
679 lpuart32_write(port, c, UARTDATA);
680 }
681
682 static int lpuart32_poll_get_char(struct uart_port *port)
683 {
684 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
685 return NO_POLL_CHAR;
686
687 return lpuart32_read(port, UARTDATA);
688 }
689 #endif
690
691 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
692 {
693 struct circ_buf *xmit = &sport->port.state->xmit;
694
695 if (sport->port.x_char) {
696 writeb(sport->port.x_char, sport->port.membase + UARTDR);
697 sport->port.icount.tx++;
698 sport->port.x_char = 0;
699 return;
700 }
701
702 if (lpuart_stopped_or_empty(&sport->port)) {
703 lpuart_stop_tx(&sport->port);
704 return;
705 }
706
707 while (!uart_circ_empty(xmit) &&
708 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
709 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
710 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
711 sport->port.icount.tx++;
712 }
713
714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
715 uart_write_wakeup(&sport->port);
716
717 if (uart_circ_empty(xmit))
718 lpuart_stop_tx(&sport->port);
719 }
720
721 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
722 {
723 struct circ_buf *xmit = &sport->port.state->xmit;
724 unsigned long txcnt;
725
726 if (sport->port.x_char) {
727 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
728 sport->port.icount.tx++;
729 sport->port.x_char = 0;
730 return;
731 }
732
733 if (lpuart_stopped_or_empty(&sport->port)) {
734 lpuart32_stop_tx(&sport->port);
735 return;
736 }
737
738 txcnt = lpuart32_read(&sport->port, UARTWATER);
739 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
740 txcnt &= UARTWATER_COUNT_MASK;
741 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
742 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
743 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
744 sport->port.icount.tx++;
745 txcnt = lpuart32_read(&sport->port, UARTWATER);
746 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
747 txcnt &= UARTWATER_COUNT_MASK;
748 }
749
750 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
751 uart_write_wakeup(&sport->port);
752
753 if (uart_circ_empty(xmit))
754 lpuart32_stop_tx(&sport->port);
755 }
756
757 static void lpuart_start_tx(struct uart_port *port)
758 {
759 struct lpuart_port *sport = container_of(port,
760 struct lpuart_port, port);
761 unsigned char temp;
762
763 temp = readb(port->membase + UARTCR2);
764 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
765
766 if (sport->lpuart_dma_tx_use) {
767 if (!lpuart_stopped_or_empty(port))
768 lpuart_dma_tx(sport);
769 } else {
770 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
771 lpuart_transmit_buffer(sport);
772 }
773 }
774
775 static void lpuart32_start_tx(struct uart_port *port)
776 {
777 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
778 unsigned long temp;
779
780 if (sport->lpuart_dma_tx_use) {
781 if (!lpuart_stopped_or_empty(port))
782 lpuart_dma_tx(sport);
783 } else {
784 temp = lpuart32_read(port, UARTCTRL);
785 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
786
787 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
788 lpuart32_transmit_buffer(sport);
789 }
790 }
791
792 /* return TIOCSER_TEMT when transmitter is not busy */
793 static unsigned int lpuart_tx_empty(struct uart_port *port)
794 {
795 struct lpuart_port *sport = container_of(port,
796 struct lpuart_port, port);
797 unsigned char sr1 = readb(port->membase + UARTSR1);
798 unsigned char sfifo = readb(port->membase + UARTSFIFO);
799
800 if (sport->dma_tx_in_progress)
801 return 0;
802
803 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
804 return TIOCSER_TEMT;
805
806 return 0;
807 }
808
809 static unsigned int lpuart32_tx_empty(struct uart_port *port)
810 {
811 struct lpuart_port *sport = container_of(port,
812 struct lpuart_port, port);
813 unsigned long stat = lpuart32_read(port, UARTSTAT);
814 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
815
816 if (sport->dma_tx_in_progress)
817 return 0;
818
819 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
820 return TIOCSER_TEMT;
821
822 return 0;
823 }
824
825 static void lpuart_txint(struct lpuart_port *sport)
826 {
827 unsigned long flags;
828
829 spin_lock_irqsave(&sport->port.lock, flags);
830 lpuart_transmit_buffer(sport);
831 spin_unlock_irqrestore(&sport->port.lock, flags);
832 }
833
834 static void lpuart_rxint(struct lpuart_port *sport)
835 {
836 unsigned int flg, ignored = 0, overrun = 0;
837 struct tty_port *port = &sport->port.state->port;
838 unsigned long flags;
839 unsigned char rx, sr;
840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
843 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
844 flg = TTY_NORMAL;
845 sport->port.icount.rx++;
846 /*
847 * to clear the FE, OR, NF, FE, PE flags,
848 * read SR1 then read DR
849 */
850 sr = readb(sport->port.membase + UARTSR1);
851 rx = readb(sport->port.membase + UARTDR);
852
853 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
854 continue;
855
856 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
857 if (sr & UARTSR1_PE)
858 sport->port.icount.parity++;
859 else if (sr & UARTSR1_FE)
860 sport->port.icount.frame++;
861
862 if (sr & UARTSR1_OR)
863 overrun++;
864
865 if (sr & sport->port.ignore_status_mask) {
866 if (++ignored > 100)
867 goto out;
868 continue;
869 }
870
871 sr &= sport->port.read_status_mask;
872
873 if (sr & UARTSR1_PE)
874 flg = TTY_PARITY;
875 else if (sr & UARTSR1_FE)
876 flg = TTY_FRAME;
877
878 if (sr & UARTSR1_OR)
879 flg = TTY_OVERRUN;
880
881 sport->port.sysrq = 0;
882 }
883
884 tty_insert_flip_char(port, rx, flg);
885 }
886
887 out:
888 if (overrun) {
889 sport->port.icount.overrun += overrun;
890
891 /*
892 * Overruns cause FIFO pointers to become missaligned.
893 * Flushing the receive FIFO reinitializes the pointers.
894 */
895 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
896 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
897 }
898
899 spin_unlock_irqrestore(&sport->port.lock, flags);
900
901 tty_flip_buffer_push(port);
902 }
903
904 static void lpuart32_txint(struct lpuart_port *sport)
905 {
906 unsigned long flags;
907
908 spin_lock_irqsave(&sport->port.lock, flags);
909 lpuart32_transmit_buffer(sport);
910 spin_unlock_irqrestore(&sport->port.lock, flags);
911 }
912
913 static void lpuart32_rxint(struct lpuart_port *sport)
914 {
915 unsigned int flg, ignored = 0;
916 struct tty_port *port = &sport->port.state->port;
917 unsigned long flags;
918 unsigned long rx, sr;
919
920 spin_lock_irqsave(&sport->port.lock, flags);
921
922 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
923 flg = TTY_NORMAL;
924 sport->port.icount.rx++;
925 /*
926 * to clear the FE, OR, NF, FE, PE flags,
927 * read STAT then read DATA reg
928 */
929 sr = lpuart32_read(&sport->port, UARTSTAT);
930 rx = lpuart32_read(&sport->port, UARTDATA);
931 rx &= 0x3ff;
932
933 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
934 continue;
935
936 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
937 if (sr & UARTSTAT_PE)
938 sport->port.icount.parity++;
939 else if (sr & UARTSTAT_FE)
940 sport->port.icount.frame++;
941
942 if (sr & UARTSTAT_OR)
943 sport->port.icount.overrun++;
944
945 if (sr & sport->port.ignore_status_mask) {
946 if (++ignored > 100)
947 goto out;
948 continue;
949 }
950
951 sr &= sport->port.read_status_mask;
952
953 if (sr & UARTSTAT_PE)
954 flg = TTY_PARITY;
955 else if (sr & UARTSTAT_FE)
956 flg = TTY_FRAME;
957
958 if (sr & UARTSTAT_OR)
959 flg = TTY_OVERRUN;
960
961 sport->port.sysrq = 0;
962 }
963
964 tty_insert_flip_char(port, rx, flg);
965 }
966
967 out:
968 spin_unlock_irqrestore(&sport->port.lock, flags);
969
970 tty_flip_buffer_push(port);
971 }
972
973 static irqreturn_t lpuart_int(int irq, void *dev_id)
974 {
975 struct lpuart_port *sport = dev_id;
976 unsigned char sts;
977
978 sts = readb(sport->port.membase + UARTSR1);
979
980 /* SysRq, using dma, check for linebreak by framing err. */
981 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
982 readb(sport->port.membase + UARTDR);
983 uart_handle_break(&sport->port);
984 /* linebreak produces some garbage, removing it */
985 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
986 return IRQ_HANDLED;
987 }
988
989 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
990 lpuart_rxint(sport);
991
992 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
993 lpuart_txint(sport);
994
995 return IRQ_HANDLED;
996 }
997
998 static irqreturn_t lpuart32_int(int irq, void *dev_id)
999 {
1000 struct lpuart_port *sport = dev_id;
1001 unsigned long sts, rxcount;
1002
1003 sts = lpuart32_read(&sport->port, UARTSTAT);
1004 rxcount = lpuart32_read(&sport->port, UARTWATER);
1005 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1006
1007 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1008 lpuart32_rxint(sport);
1009
1010 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1011 lpuart32_txint(sport);
1012
1013 lpuart32_write(&sport->port, sts, UARTSTAT);
1014 return IRQ_HANDLED;
1015 }
1016
1017
1018 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1019 unsigned char *p, int count)
1020 {
1021 while (count--) {
1022 if (*p && uart_handle_sysrq_char(port, *p))
1023 return;
1024 p++;
1025 }
1026 }
1027
1028 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1029 {
1030 struct circ_buf *ring = &sport->rx_ring;
1031 int count;
1032
1033 if (ring->head < ring->tail) {
1034 count = sport->rx_sgl.length - ring->tail;
1035 lpuart_handle_sysrq_chars(&sport->port,
1036 ring->buf + ring->tail, count);
1037 ring->tail = 0;
1038 }
1039
1040 if (ring->head > ring->tail) {
1041 count = ring->head - ring->tail;
1042 lpuart_handle_sysrq_chars(&sport->port,
1043 ring->buf + ring->tail, count);
1044 ring->tail = ring->head;
1045 }
1046 }
1047
1048 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1049 {
1050 struct tty_port *port = &sport->port.state->port;
1051 struct dma_tx_state state;
1052 enum dma_status dmastat;
1053 struct dma_chan *chan = sport->dma_rx_chan;
1054 struct circ_buf *ring = &sport->rx_ring;
1055 unsigned long flags;
1056 int count = 0;
1057
1058 if (lpuart_is_32(sport)) {
1059 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1060
1061 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1062 /* Read DR to clear the error flags */
1063 lpuart32_read(&sport->port, UARTDATA);
1064
1065 if (sr & UARTSTAT_PE)
1066 sport->port.icount.parity++;
1067 else if (sr & UARTSTAT_FE)
1068 sport->port.icount.frame++;
1069 }
1070 } else {
1071 unsigned char sr = readb(sport->port.membase + UARTSR1);
1072
1073 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1074 unsigned char cr2;
1075
1076 /* Disable receiver during this operation... */
1077 cr2 = readb(sport->port.membase + UARTCR2);
1078 cr2 &= ~UARTCR2_RE;
1079 writeb(cr2, sport->port.membase + UARTCR2);
1080
1081 /* Read DR to clear the error flags */
1082 readb(sport->port.membase + UARTDR);
1083
1084 if (sr & UARTSR1_PE)
1085 sport->port.icount.parity++;
1086 else if (sr & UARTSR1_FE)
1087 sport->port.icount.frame++;
1088 /*
1089 * At this point parity/framing error is
1090 * cleared However, since the DMA already read
1091 * the data register and we had to read it
1092 * again after reading the status register to
1093 * properly clear the flags, the FIFO actually
1094 * underflowed... This requires a clearing of
1095 * the FIFO...
1096 */
1097 if (readb(sport->port.membase + UARTSFIFO) &
1098 UARTSFIFO_RXUF) {
1099 writeb(UARTSFIFO_RXUF,
1100 sport->port.membase + UARTSFIFO);
1101 writeb(UARTCFIFO_RXFLUSH,
1102 sport->port.membase + UARTCFIFO);
1103 }
1104
1105 cr2 |= UARTCR2_RE;
1106 writeb(cr2, sport->port.membase + UARTCR2);
1107 }
1108 }
1109
1110 async_tx_ack(sport->dma_rx_desc);
1111
1112 spin_lock_irqsave(&sport->port.lock, flags);
1113
1114 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1115 if (dmastat == DMA_ERROR) {
1116 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1117 spin_unlock_irqrestore(&sport->port.lock, flags);
1118 return;
1119 }
1120
1121 /* CPU claims ownership of RX DMA buffer */
1122 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1123 DMA_FROM_DEVICE);
1124
1125 /*
1126 * ring->head points to the end of data already written by the DMA.
1127 * ring->tail points to the beginning of data to be read by the
1128 * framework.
1129 * The current transfer size should not be larger than the dma buffer
1130 * length.
1131 */
1132 ring->head = sport->rx_sgl.length - state.residue;
1133 BUG_ON(ring->head > sport->rx_sgl.length);
1134
1135 /*
1136 * Silent handling of keys pressed in the sysrq timeframe
1137 */
1138 if (sport->port.sysrq) {
1139 lpuart_handle_sysrq(sport);
1140 goto exit;
1141 }
1142
1143 /*
1144 * At this point ring->head may point to the first byte right after the
1145 * last byte of the dma buffer:
1146 * 0 <= ring->head <= sport->rx_sgl.length
1147 *
1148 * However ring->tail must always points inside the dma buffer:
1149 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1150 *
1151 * Since we use a ring buffer, we have to handle the case
1152 * where head is lower than tail. In such a case, we first read from
1153 * tail to the end of the buffer then reset tail.
1154 */
1155 if (ring->head < ring->tail) {
1156 count = sport->rx_sgl.length - ring->tail;
1157
1158 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1159 ring->tail = 0;
1160 sport->port.icount.rx += count;
1161 }
1162
1163 /* Finally we read data from tail to head */
1164 if (ring->tail < ring->head) {
1165 count = ring->head - ring->tail;
1166 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1167 /* Wrap ring->head if needed */
1168 if (ring->head >= sport->rx_sgl.length)
1169 ring->head = 0;
1170 ring->tail = ring->head;
1171 sport->port.icount.rx += count;
1172 }
1173
1174 exit:
1175 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1176 DMA_FROM_DEVICE);
1177
1178 spin_unlock_irqrestore(&sport->port.lock, flags);
1179
1180 tty_flip_buffer_push(port);
1181 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1182 }
1183
1184 static void lpuart_dma_rx_complete(void *arg)
1185 {
1186 struct lpuart_port *sport = arg;
1187
1188 lpuart_copy_rx_to_tty(sport);
1189 }
1190
1191 static void lpuart_timer_func(struct timer_list *t)
1192 {
1193 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1194
1195 lpuart_copy_rx_to_tty(sport);
1196 }
1197
1198 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1199 {
1200 struct dma_slave_config dma_rx_sconfig = {};
1201 struct circ_buf *ring = &sport->rx_ring;
1202 int ret, nent;
1203 int bits, baud;
1204 struct tty_port *port = &sport->port.state->port;
1205 struct tty_struct *tty = port->tty;
1206 struct ktermios *termios = &tty->termios;
1207 struct dma_chan *chan = sport->dma_rx_chan;
1208
1209 baud = tty_get_baud_rate(tty);
1210
1211 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1212 if (termios->c_cflag & PARENB)
1213 bits++;
1214
1215 /*
1216 * Calculate length of one DMA buffer size to keep latency below
1217 * 10ms at any baud rate.
1218 */
1219 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1220 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1221 if (sport->rx_dma_rng_buf_len < 16)
1222 sport->rx_dma_rng_buf_len = 16;
1223
1224 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1225 if (!ring->buf)
1226 return -ENOMEM;
1227
1228 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1229 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1230 DMA_FROM_DEVICE);
1231
1232 if (!nent) {
1233 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1234 return -EINVAL;
1235 }
1236
1237 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1238 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1239 dma_rx_sconfig.src_maxburst = 1;
1240 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1241 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1242
1243 if (ret < 0) {
1244 dev_err(sport->port.dev,
1245 "DMA Rx slave config failed, err = %d\n", ret);
1246 return ret;
1247 }
1248
1249 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1250 sg_dma_address(&sport->rx_sgl),
1251 sport->rx_sgl.length,
1252 sport->rx_sgl.length / 2,
1253 DMA_DEV_TO_MEM,
1254 DMA_PREP_INTERRUPT);
1255 if (!sport->dma_rx_desc) {
1256 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1257 return -EFAULT;
1258 }
1259
1260 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1261 sport->dma_rx_desc->callback_param = sport;
1262 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1263 dma_async_issue_pending(chan);
1264
1265 if (lpuart_is_32(sport)) {
1266 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1267
1268 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1269 } else {
1270 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1271 sport->port.membase + UARTCR5);
1272 }
1273
1274 return 0;
1275 }
1276
1277 static void lpuart_dma_rx_free(struct uart_port *port)
1278 {
1279 struct lpuart_port *sport = container_of(port,
1280 struct lpuart_port, port);
1281 struct dma_chan *chan = sport->dma_rx_chan;
1282
1283 dmaengine_terminate_all(chan);
1284 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1285 kfree(sport->rx_ring.buf);
1286 sport->rx_ring.tail = 0;
1287 sport->rx_ring.head = 0;
1288 sport->dma_rx_desc = NULL;
1289 sport->dma_rx_cookie = -EINVAL;
1290 }
1291
1292 static int lpuart_config_rs485(struct uart_port *port,
1293 struct serial_rs485 *rs485)
1294 {
1295 struct lpuart_port *sport = container_of(port,
1296 struct lpuart_port, port);
1297
1298 u8 modem = readb(sport->port.membase + UARTMODEM) &
1299 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1300 writeb(modem, sport->port.membase + UARTMODEM);
1301
1302 /* clear unsupported configurations */
1303 rs485->delay_rts_before_send = 0;
1304 rs485->delay_rts_after_send = 0;
1305 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1306
1307 if (rs485->flags & SER_RS485_ENABLED) {
1308 /* Enable auto RS-485 RTS mode */
1309 modem |= UARTMODEM_TXRTSE;
1310
1311 /*
1312 * RTS needs to be logic HIGH either during transfer _or_ after
1313 * transfer, other variants are not supported by the hardware.
1314 */
1315
1316 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1317 SER_RS485_RTS_AFTER_SEND)))
1318 rs485->flags |= SER_RS485_RTS_ON_SEND;
1319
1320 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1321 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1322 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1323
1324 /*
1325 * The hardware defaults to RTS logic HIGH while transfer.
1326 * Switch polarity in case RTS shall be logic HIGH
1327 * after transfer.
1328 * Note: UART is assumed to be active high.
1329 */
1330 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1331 modem &= ~UARTMODEM_TXRTSPOL;
1332 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1333 modem |= UARTMODEM_TXRTSPOL;
1334 }
1335
1336 /* Store the new configuration */
1337 sport->port.rs485 = *rs485;
1338
1339 writeb(modem, sport->port.membase + UARTMODEM);
1340 return 0;
1341 }
1342
1343 static int lpuart32_config_rs485(struct uart_port *port,
1344 struct serial_rs485 *rs485)
1345 {
1346 struct lpuart_port *sport = container_of(port,
1347 struct lpuart_port, port);
1348
1349 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1350 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1351 lpuart32_write(&sport->port, modem, UARTMODIR);
1352
1353 /* clear unsupported configurations */
1354 rs485->delay_rts_before_send = 0;
1355 rs485->delay_rts_after_send = 0;
1356 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1357
1358 if (rs485->flags & SER_RS485_ENABLED) {
1359 /* Enable auto RS-485 RTS mode */
1360 modem |= UARTMODEM_TXRTSE;
1361
1362 /*
1363 * RTS needs to be logic HIGH either during transfer _or_ after
1364 * transfer, other variants are not supported by the hardware.
1365 */
1366
1367 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1368 SER_RS485_RTS_AFTER_SEND)))
1369 rs485->flags |= SER_RS485_RTS_ON_SEND;
1370
1371 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1372 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1373 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1374
1375 /*
1376 * The hardware defaults to RTS logic HIGH while transfer.
1377 * Switch polarity in case RTS shall be logic HIGH
1378 * after transfer.
1379 * Note: UART is assumed to be active high.
1380 */
1381 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1382 modem &= ~UARTMODEM_TXRTSPOL;
1383 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1384 modem |= UARTMODEM_TXRTSPOL;
1385 }
1386
1387 /* Store the new configuration */
1388 sport->port.rs485 = *rs485;
1389
1390 lpuart32_write(&sport->port, modem, UARTMODIR);
1391 return 0;
1392 }
1393
1394 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1395 {
1396 unsigned int temp = 0;
1397 unsigned char reg;
1398
1399 reg = readb(port->membase + UARTMODEM);
1400 if (reg & UARTMODEM_TXCTSE)
1401 temp |= TIOCM_CTS;
1402
1403 if (reg & UARTMODEM_RXRTSE)
1404 temp |= TIOCM_RTS;
1405
1406 return temp;
1407 }
1408
1409 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1410 {
1411 unsigned int temp = 0;
1412 unsigned long reg;
1413
1414 reg = lpuart32_read(port, UARTMODIR);
1415 if (reg & UARTMODIR_TXCTSE)
1416 temp |= TIOCM_CTS;
1417
1418 if (reg & UARTMODIR_RXRTSE)
1419 temp |= TIOCM_RTS;
1420
1421 return temp;
1422 }
1423
1424 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1425 {
1426 unsigned char temp;
1427 struct lpuart_port *sport = container_of(port,
1428 struct lpuart_port, port);
1429
1430 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1431 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1432 temp = readb(sport->port.membase + UARTMODEM) &
1433 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1434
1435 if (mctrl & TIOCM_RTS)
1436 temp |= UARTMODEM_RXRTSE;
1437
1438 if (mctrl & TIOCM_CTS)
1439 temp |= UARTMODEM_TXCTSE;
1440
1441 writeb(temp, port->membase + UARTMODEM);
1442 }
1443 }
1444
1445 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1446 {
1447
1448 }
1449
1450 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1451 {
1452 unsigned char temp;
1453
1454 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1455
1456 if (break_state != 0)
1457 temp |= UARTCR2_SBK;
1458
1459 writeb(temp, port->membase + UARTCR2);
1460 }
1461
1462 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1463 {
1464 unsigned long temp;
1465
1466 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1467
1468 if (break_state != 0)
1469 temp |= UARTCTRL_SBK;
1470
1471 lpuart32_write(port, temp, UARTCTRL);
1472 }
1473
1474 static void lpuart_setup_watermark(struct lpuart_port *sport)
1475 {
1476 unsigned char val, cr2;
1477 unsigned char cr2_saved;
1478
1479 cr2 = readb(sport->port.membase + UARTCR2);
1480 cr2_saved = cr2;
1481 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1482 UARTCR2_RIE | UARTCR2_RE);
1483 writeb(cr2, sport->port.membase + UARTCR2);
1484
1485 val = readb(sport->port.membase + UARTPFIFO);
1486 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1487 sport->port.membase + UARTPFIFO);
1488
1489 /* flush Tx and Rx FIFO */
1490 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1491 sport->port.membase + UARTCFIFO);
1492
1493 /* explicitly clear RDRF */
1494 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1495 readb(sport->port.membase + UARTDR);
1496 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1497 }
1498
1499 writeb(0, sport->port.membase + UARTTWFIFO);
1500 writeb(1, sport->port.membase + UARTRWFIFO);
1501
1502 /* Restore cr2 */
1503 writeb(cr2_saved, sport->port.membase + UARTCR2);
1504 }
1505
1506 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1507 {
1508 unsigned char cr2;
1509
1510 lpuart_setup_watermark(sport);
1511
1512 cr2 = readb(sport->port.membase + UARTCR2);
1513 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1514 writeb(cr2, sport->port.membase + UARTCR2);
1515 }
1516
1517 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1518 {
1519 unsigned long val, ctrl;
1520 unsigned long ctrl_saved;
1521
1522 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1523 ctrl_saved = ctrl;
1524 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1525 UARTCTRL_RIE | UARTCTRL_RE);
1526 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1527
1528 /* enable FIFO mode */
1529 val = lpuart32_read(&sport->port, UARTFIFO);
1530 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1531 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1532 lpuart32_write(&sport->port, val, UARTFIFO);
1533
1534 /* set the watermark */
1535 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1536 lpuart32_write(&sport->port, val, UARTWATER);
1537
1538 /* Restore cr2 */
1539 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1540 }
1541
1542 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1543 {
1544 u32 temp;
1545
1546 lpuart32_setup_watermark(sport);
1547
1548 temp = lpuart32_read(&sport->port, UARTCTRL);
1549 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1550 lpuart32_write(&sport->port, temp, UARTCTRL);
1551 }
1552
1553 static void rx_dma_timer_init(struct lpuart_port *sport)
1554 {
1555 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1556 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1557 add_timer(&sport->lpuart_timer);
1558 }
1559
1560 static void lpuart_request_dma(struct lpuart_port *sport)
1561 {
1562 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1563 if (IS_ERR(sport->dma_tx_chan)) {
1564 dev_dbg_once(sport->port.dev,
1565 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1566 PTR_ERR(sport->dma_tx_chan));
1567 sport->dma_tx_chan = NULL;
1568 }
1569
1570 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1571 if (IS_ERR(sport->dma_rx_chan)) {
1572 dev_dbg_once(sport->port.dev,
1573 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1574 PTR_ERR(sport->dma_rx_chan));
1575 sport->dma_rx_chan = NULL;
1576 }
1577 }
1578
1579 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1580 {
1581 u32 uartbaud;
1582 int ret;
1583
1584 if (!sport->dma_tx_chan)
1585 goto err;
1586
1587 ret = lpuart_dma_tx_request(&sport->port);
1588 if (ret)
1589 goto err;
1590
1591 init_waitqueue_head(&sport->dma_wait);
1592 sport->lpuart_dma_tx_use = true;
1593 if (lpuart_is_32(sport)) {
1594 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1595 lpuart32_write(&sport->port,
1596 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1597 } else {
1598 writeb(readb(sport->port.membase + UARTCR5) |
1599 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1600 }
1601
1602 return;
1603
1604 err:
1605 sport->lpuart_dma_tx_use = false;
1606 }
1607
1608 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1609 {
1610 int ret;
1611 unsigned char cr3;
1612
1613 if (!sport->dma_rx_chan)
1614 goto err;
1615
1616 ret = lpuart_start_rx_dma(sport);
1617 if (ret)
1618 goto err;
1619
1620 /* set Rx DMA timeout */
1621 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1622 if (!sport->dma_rx_timeout)
1623 sport->dma_rx_timeout = 1;
1624
1625 sport->lpuart_dma_rx_use = true;
1626 rx_dma_timer_init(sport);
1627
1628 if (sport->port.has_sysrq) {
1629 cr3 = readb(sport->port.membase + UARTCR3);
1630 cr3 |= UARTCR3_FEIE;
1631 writeb(cr3, sport->port.membase + UARTCR3);
1632 }
1633
1634 return;
1635
1636 err:
1637 sport->lpuart_dma_rx_use = false;
1638 }
1639
1640 static int lpuart_startup(struct uart_port *port)
1641 {
1642 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1643 unsigned long flags;
1644 unsigned char temp;
1645
1646 /* determine FIFO size and enable FIFO mode */
1647 temp = readb(sport->port.membase + UARTPFIFO);
1648
1649 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1650 UARTPFIFO_FIFOSIZE_MASK);
1651 sport->port.fifosize = sport->txfifo_size;
1652
1653 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1654 UARTPFIFO_FIFOSIZE_MASK);
1655
1656 lpuart_request_dma(sport);
1657
1658 spin_lock_irqsave(&sport->port.lock, flags);
1659
1660 lpuart_setup_watermark_enable(sport);
1661
1662 lpuart_rx_dma_startup(sport);
1663 lpuart_tx_dma_startup(sport);
1664
1665 spin_unlock_irqrestore(&sport->port.lock, flags);
1666
1667 return 0;
1668 }
1669
1670 static void lpuart32_configure(struct lpuart_port *sport)
1671 {
1672 unsigned long temp;
1673
1674 if (sport->lpuart_dma_rx_use) {
1675 /* RXWATER must be 0 */
1676 temp = lpuart32_read(&sport->port, UARTWATER);
1677 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1678 lpuart32_write(&sport->port, temp, UARTWATER);
1679 }
1680 temp = lpuart32_read(&sport->port, UARTCTRL);
1681 if (!sport->lpuart_dma_rx_use)
1682 temp |= UARTCTRL_RIE;
1683 if (!sport->lpuart_dma_tx_use)
1684 temp |= UARTCTRL_TIE;
1685 lpuart32_write(&sport->port, temp, UARTCTRL);
1686 }
1687
1688 static int lpuart32_startup(struct uart_port *port)
1689 {
1690 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1691 unsigned long flags;
1692 unsigned long temp;
1693
1694 /* determine FIFO size */
1695 temp = lpuart32_read(&sport->port, UARTFIFO);
1696
1697 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1698 UARTFIFO_FIFOSIZE_MASK);
1699 sport->port.fifosize = sport->txfifo_size;
1700
1701 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1702 UARTFIFO_FIFOSIZE_MASK);
1703
1704 /*
1705 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1706 * Although they support the RX/TXSIZE fields, their encoding is
1707 * different. Eg the reference manual states 0b101 is 16 words.
1708 */
1709 if (is_layerscape_lpuart(sport)) {
1710 sport->rxfifo_size = 16;
1711 sport->txfifo_size = 16;
1712 sport->port.fifosize = sport->txfifo_size;
1713 }
1714
1715 lpuart_request_dma(sport);
1716
1717 spin_lock_irqsave(&sport->port.lock, flags);
1718
1719 lpuart32_setup_watermark_enable(sport);
1720
1721 lpuart_rx_dma_startup(sport);
1722 lpuart_tx_dma_startup(sport);
1723
1724 lpuart32_configure(sport);
1725
1726 spin_unlock_irqrestore(&sport->port.lock, flags);
1727 return 0;
1728 }
1729
1730 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1731 {
1732 if (sport->lpuart_dma_rx_use) {
1733 del_timer_sync(&sport->lpuart_timer);
1734 lpuart_dma_rx_free(&sport->port);
1735 }
1736
1737 if (sport->lpuart_dma_tx_use) {
1738 if (wait_event_interruptible(sport->dma_wait,
1739 !sport->dma_tx_in_progress) != false) {
1740 sport->dma_tx_in_progress = false;
1741 dmaengine_terminate_all(sport->dma_tx_chan);
1742 }
1743 }
1744
1745 if (sport->dma_tx_chan)
1746 dma_release_channel(sport->dma_tx_chan);
1747 if (sport->dma_rx_chan)
1748 dma_release_channel(sport->dma_rx_chan);
1749 }
1750
1751 static void lpuart_shutdown(struct uart_port *port)
1752 {
1753 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1754 unsigned char temp;
1755 unsigned long flags;
1756
1757 spin_lock_irqsave(&port->lock, flags);
1758
1759 /* disable Rx/Tx and interrupts */
1760 temp = readb(port->membase + UARTCR2);
1761 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1762 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1763 writeb(temp, port->membase + UARTCR2);
1764
1765 spin_unlock_irqrestore(&port->lock, flags);
1766
1767 lpuart_dma_shutdown(sport);
1768 }
1769
1770 static void lpuart32_shutdown(struct uart_port *port)
1771 {
1772 struct lpuart_port *sport =
1773 container_of(port, struct lpuart_port, port);
1774 unsigned long temp;
1775 unsigned long flags;
1776
1777 spin_lock_irqsave(&port->lock, flags);
1778
1779 /* disable Rx/Tx and interrupts */
1780 temp = lpuart32_read(port, UARTCTRL);
1781 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1782 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1783 lpuart32_write(port, temp, UARTCTRL);
1784
1785 spin_unlock_irqrestore(&port->lock, flags);
1786
1787 lpuart_dma_shutdown(sport);
1788 }
1789
1790 static void
1791 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1792 struct ktermios *old)
1793 {
1794 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1795 unsigned long flags;
1796 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1797 unsigned int baud;
1798 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1799 unsigned int sbr, brfa;
1800
1801 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1802 old_cr2 = readb(sport->port.membase + UARTCR2);
1803 cr3 = readb(sport->port.membase + UARTCR3);
1804 cr4 = readb(sport->port.membase + UARTCR4);
1805 bdh = readb(sport->port.membase + UARTBDH);
1806 modem = readb(sport->port.membase + UARTMODEM);
1807 /*
1808 * only support CS8 and CS7, and for CS7 must enable PE.
1809 * supported mode:
1810 * - (7,e/o,1)
1811 * - (8,n,1)
1812 * - (8,m/s,1)
1813 * - (8,e/o,1)
1814 */
1815 while ((termios->c_cflag & CSIZE) != CS8 &&
1816 (termios->c_cflag & CSIZE) != CS7) {
1817 termios->c_cflag &= ~CSIZE;
1818 termios->c_cflag |= old_csize;
1819 old_csize = CS8;
1820 }
1821
1822 if ((termios->c_cflag & CSIZE) == CS8 ||
1823 (termios->c_cflag & CSIZE) == CS7)
1824 cr1 = old_cr1 & ~UARTCR1_M;
1825
1826 if (termios->c_cflag & CMSPAR) {
1827 if ((termios->c_cflag & CSIZE) != CS8) {
1828 termios->c_cflag &= ~CSIZE;
1829 termios->c_cflag |= CS8;
1830 }
1831 cr1 |= UARTCR1_M;
1832 }
1833
1834 /*
1835 * When auto RS-485 RTS mode is enabled,
1836 * hardware flow control need to be disabled.
1837 */
1838 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1839 termios->c_cflag &= ~CRTSCTS;
1840
1841 if (termios->c_cflag & CRTSCTS)
1842 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1843 else
1844 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1845
1846 termios->c_cflag &= ~CSTOPB;
1847
1848 /* parity must be enabled when CS7 to match 8-bits format */
1849 if ((termios->c_cflag & CSIZE) == CS7)
1850 termios->c_cflag |= PARENB;
1851
1852 if (termios->c_cflag & PARENB) {
1853 if (termios->c_cflag & CMSPAR) {
1854 cr1 &= ~UARTCR1_PE;
1855 if (termios->c_cflag & PARODD)
1856 cr3 |= UARTCR3_T8;
1857 else
1858 cr3 &= ~UARTCR3_T8;
1859 } else {
1860 cr1 |= UARTCR1_PE;
1861 if ((termios->c_cflag & CSIZE) == CS8)
1862 cr1 |= UARTCR1_M;
1863 if (termios->c_cflag & PARODD)
1864 cr1 |= UARTCR1_PT;
1865 else
1866 cr1 &= ~UARTCR1_PT;
1867 }
1868 } else {
1869 cr1 &= ~UARTCR1_PE;
1870 }
1871
1872 /* ask the core to calculate the divisor */
1873 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1874
1875 /*
1876 * Need to update the Ring buffer length according to the selected
1877 * baud rate and restart Rx DMA path.
1878 *
1879 * Since timer function acqures sport->port.lock, need to stop before
1880 * acquring same lock because otherwise del_timer_sync() can deadlock.
1881 */
1882 if (old && sport->lpuart_dma_rx_use) {
1883 del_timer_sync(&sport->lpuart_timer);
1884 lpuart_dma_rx_free(&sport->port);
1885 }
1886
1887 spin_lock_irqsave(&sport->port.lock, flags);
1888
1889 sport->port.read_status_mask = 0;
1890 if (termios->c_iflag & INPCK)
1891 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1892 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1893 sport->port.read_status_mask |= UARTSR1_FE;
1894
1895 /* characters to ignore */
1896 sport->port.ignore_status_mask = 0;
1897 if (termios->c_iflag & IGNPAR)
1898 sport->port.ignore_status_mask |= UARTSR1_PE;
1899 if (termios->c_iflag & IGNBRK) {
1900 sport->port.ignore_status_mask |= UARTSR1_FE;
1901 /*
1902 * if we're ignoring parity and break indicators,
1903 * ignore overruns too (for real raw support).
1904 */
1905 if (termios->c_iflag & IGNPAR)
1906 sport->port.ignore_status_mask |= UARTSR1_OR;
1907 }
1908
1909 /* update the per-port timeout */
1910 uart_update_timeout(port, termios->c_cflag, baud);
1911
1912 /* wait transmit engin complete */
1913 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1914
1915 /* disable transmit and receive */
1916 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1917 sport->port.membase + UARTCR2);
1918
1919 sbr = sport->port.uartclk / (16 * baud);
1920 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1921 bdh &= ~UARTBDH_SBR_MASK;
1922 bdh |= (sbr >> 8) & 0x1F;
1923 cr4 &= ~UARTCR4_BRFA_MASK;
1924 brfa &= UARTCR4_BRFA_MASK;
1925 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1926 writeb(bdh, sport->port.membase + UARTBDH);
1927 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1928 writeb(cr3, sport->port.membase + UARTCR3);
1929 writeb(cr1, sport->port.membase + UARTCR1);
1930 writeb(modem, sport->port.membase + UARTMODEM);
1931
1932 /* restore control register */
1933 writeb(old_cr2, sport->port.membase + UARTCR2);
1934
1935 if (old && sport->lpuart_dma_rx_use) {
1936 if (!lpuart_start_rx_dma(sport))
1937 rx_dma_timer_init(sport);
1938 else
1939 sport->lpuart_dma_rx_use = false;
1940 }
1941
1942 spin_unlock_irqrestore(&sport->port.lock, flags);
1943 }
1944
1945 static void __lpuart32_serial_setbrg(struct uart_port *port,
1946 unsigned int baudrate, bool use_rx_dma,
1947 bool use_tx_dma)
1948 {
1949 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1950 u32 clk = port->uartclk;
1951
1952 /*
1953 * The idea is to use the best OSR (over-sampling rate) possible.
1954 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1955 * Loop to find the best OSR value possible, one that generates minimum
1956 * baud_diff iterate through the rest of the supported values of OSR.
1957 *
1958 * Calculation Formula:
1959 * Baud Rate = baud clock / ((OSR+1) × SBR)
1960 */
1961 baud_diff = baudrate;
1962 osr = 0;
1963 sbr = 0;
1964
1965 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1966 /* calculate the temporary sbr value */
1967 tmp_sbr = (clk / (baudrate * tmp_osr));
1968 if (tmp_sbr == 0)
1969 tmp_sbr = 1;
1970
1971 /*
1972 * calculate the baud rate difference based on the temporary
1973 * osr and sbr values
1974 */
1975 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1976
1977 /* select best values between sbr and sbr+1 */
1978 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1979 if (tmp_diff > (baudrate - tmp)) {
1980 tmp_diff = baudrate - tmp;
1981 tmp_sbr++;
1982 }
1983
1984 if (tmp_sbr > UARTBAUD_SBR_MASK)
1985 continue;
1986
1987 if (tmp_diff <= baud_diff) {
1988 baud_diff = tmp_diff;
1989 osr = tmp_osr;
1990 sbr = tmp_sbr;
1991
1992 if (!baud_diff)
1993 break;
1994 }
1995 }
1996
1997 /* handle buadrate outside acceptable rate */
1998 if (baud_diff > ((baudrate / 100) * 3))
1999 dev_warn(port->dev,
2000 "unacceptable baud rate difference of more than 3%%\n");
2001
2002 tmp = lpuart32_read(port, UARTBAUD);
2003
2004 if ((osr > 3) && (osr < 8))
2005 tmp |= UARTBAUD_BOTHEDGE;
2006
2007 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2008 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2009
2010 tmp &= ~UARTBAUD_SBR_MASK;
2011 tmp |= sbr & UARTBAUD_SBR_MASK;
2012
2013 if (!use_rx_dma)
2014 tmp &= ~UARTBAUD_RDMAE;
2015 if (!use_tx_dma)
2016 tmp &= ~UARTBAUD_TDMAE;
2017
2018 lpuart32_write(port, tmp, UARTBAUD);
2019 }
2020
2021 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2022 unsigned int baudrate)
2023 {
2024 __lpuart32_serial_setbrg(&sport->port, baudrate,
2025 sport->lpuart_dma_rx_use,
2026 sport->lpuart_dma_tx_use);
2027 }
2028
2029
2030 static void
2031 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2032 struct ktermios *old)
2033 {
2034 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2035 unsigned long flags;
2036 unsigned long ctrl, old_ctrl, modem;
2037 unsigned int baud;
2038 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2039
2040 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2041 modem = lpuart32_read(&sport->port, UARTMODIR);
2042 /*
2043 * only support CS8 and CS7, and for CS7 must enable PE.
2044 * supported mode:
2045 * - (7,e/o,1)
2046 * - (8,n,1)
2047 * - (8,m/s,1)
2048 * - (8,e/o,1)
2049 */
2050 while ((termios->c_cflag & CSIZE) != CS8 &&
2051 (termios->c_cflag & CSIZE) != CS7) {
2052 termios->c_cflag &= ~CSIZE;
2053 termios->c_cflag |= old_csize;
2054 old_csize = CS8;
2055 }
2056
2057 if ((termios->c_cflag & CSIZE) == CS8 ||
2058 (termios->c_cflag & CSIZE) == CS7)
2059 ctrl = old_ctrl & ~UARTCTRL_M;
2060
2061 if (termios->c_cflag & CMSPAR) {
2062 if ((termios->c_cflag & CSIZE) != CS8) {
2063 termios->c_cflag &= ~CSIZE;
2064 termios->c_cflag |= CS8;
2065 }
2066 ctrl |= UARTCTRL_M;
2067 }
2068
2069 /*
2070 * When auto RS-485 RTS mode is enabled,
2071 * hardware flow control need to be disabled.
2072 */
2073 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2074 termios->c_cflag &= ~CRTSCTS;
2075
2076 if (termios->c_cflag & CRTSCTS) {
2077 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2078 } else {
2079 termios->c_cflag &= ~CRTSCTS;
2080 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2081 }
2082
2083 if (termios->c_cflag & CSTOPB)
2084 termios->c_cflag &= ~CSTOPB;
2085
2086 /* parity must be enabled when CS7 to match 8-bits format */
2087 if ((termios->c_cflag & CSIZE) == CS7)
2088 termios->c_cflag |= PARENB;
2089
2090 if ((termios->c_cflag & PARENB)) {
2091 if (termios->c_cflag & CMSPAR) {
2092 ctrl &= ~UARTCTRL_PE;
2093 ctrl |= UARTCTRL_M;
2094 } else {
2095 ctrl |= UARTCTRL_PE;
2096 if ((termios->c_cflag & CSIZE) == CS8)
2097 ctrl |= UARTCTRL_M;
2098 if (termios->c_cflag & PARODD)
2099 ctrl |= UARTCTRL_PT;
2100 else
2101 ctrl &= ~UARTCTRL_PT;
2102 }
2103 } else {
2104 ctrl &= ~UARTCTRL_PE;
2105 }
2106
2107 /* ask the core to calculate the divisor */
2108 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2109
2110 /*
2111 * Need to update the Ring buffer length according to the selected
2112 * baud rate and restart Rx DMA path.
2113 *
2114 * Since timer function acqures sport->port.lock, need to stop before
2115 * acquring same lock because otherwise del_timer_sync() can deadlock.
2116 */
2117 if (old && sport->lpuart_dma_rx_use) {
2118 del_timer_sync(&sport->lpuart_timer);
2119 lpuart_dma_rx_free(&sport->port);
2120 }
2121
2122 spin_lock_irqsave(&sport->port.lock, flags);
2123
2124 sport->port.read_status_mask = 0;
2125 if (termios->c_iflag & INPCK)
2126 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2127 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2128 sport->port.read_status_mask |= UARTSTAT_FE;
2129
2130 /* characters to ignore */
2131 sport->port.ignore_status_mask = 0;
2132 if (termios->c_iflag & IGNPAR)
2133 sport->port.ignore_status_mask |= UARTSTAT_PE;
2134 if (termios->c_iflag & IGNBRK) {
2135 sport->port.ignore_status_mask |= UARTSTAT_FE;
2136 /*
2137 * if we're ignoring parity and break indicators,
2138 * ignore overruns too (for real raw support).
2139 */
2140 if (termios->c_iflag & IGNPAR)
2141 sport->port.ignore_status_mask |= UARTSTAT_OR;
2142 }
2143
2144 /* update the per-port timeout */
2145 uart_update_timeout(port, termios->c_cflag, baud);
2146
2147 /* wait transmit engin complete */
2148 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2149
2150 /* disable transmit and receive */
2151 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2152 UARTCTRL);
2153
2154 lpuart32_serial_setbrg(sport, baud);
2155 lpuart32_write(&sport->port, modem, UARTMODIR);
2156 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2157 /* restore control register */
2158
2159 if (old && sport->lpuart_dma_rx_use) {
2160 if (!lpuart_start_rx_dma(sport))
2161 rx_dma_timer_init(sport);
2162 else
2163 sport->lpuart_dma_rx_use = false;
2164 }
2165
2166 spin_unlock_irqrestore(&sport->port.lock, flags);
2167 }
2168
2169 static const char *lpuart_type(struct uart_port *port)
2170 {
2171 return "FSL_LPUART";
2172 }
2173
2174 static void lpuart_release_port(struct uart_port *port)
2175 {
2176 /* nothing to do */
2177 }
2178
2179 static int lpuart_request_port(struct uart_port *port)
2180 {
2181 return 0;
2182 }
2183
2184 /* configure/autoconfigure the port */
2185 static void lpuart_config_port(struct uart_port *port, int flags)
2186 {
2187 if (flags & UART_CONFIG_TYPE)
2188 port->type = PORT_LPUART;
2189 }
2190
2191 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2192 {
2193 int ret = 0;
2194
2195 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2196 ret = -EINVAL;
2197 if (port->irq != ser->irq)
2198 ret = -EINVAL;
2199 if (ser->io_type != UPIO_MEM)
2200 ret = -EINVAL;
2201 if (port->uartclk / 16 != ser->baud_base)
2202 ret = -EINVAL;
2203 if (port->iobase != ser->port)
2204 ret = -EINVAL;
2205 if (ser->hub6 != 0)
2206 ret = -EINVAL;
2207 return ret;
2208 }
2209
2210 static const struct uart_ops lpuart_pops = {
2211 .tx_empty = lpuart_tx_empty,
2212 .set_mctrl = lpuart_set_mctrl,
2213 .get_mctrl = lpuart_get_mctrl,
2214 .stop_tx = lpuart_stop_tx,
2215 .start_tx = lpuart_start_tx,
2216 .stop_rx = lpuart_stop_rx,
2217 .break_ctl = lpuart_break_ctl,
2218 .startup = lpuart_startup,
2219 .shutdown = lpuart_shutdown,
2220 .set_termios = lpuart_set_termios,
2221 .type = lpuart_type,
2222 .request_port = lpuart_request_port,
2223 .release_port = lpuart_release_port,
2224 .config_port = lpuart_config_port,
2225 .verify_port = lpuart_verify_port,
2226 .flush_buffer = lpuart_flush_buffer,
2227 #if defined(CONFIG_CONSOLE_POLL)
2228 .poll_init = lpuart_poll_init,
2229 .poll_get_char = lpuart_poll_get_char,
2230 .poll_put_char = lpuart_poll_put_char,
2231 #endif
2232 };
2233
2234 static const struct uart_ops lpuart32_pops = {
2235 .tx_empty = lpuart32_tx_empty,
2236 .set_mctrl = lpuart32_set_mctrl,
2237 .get_mctrl = lpuart32_get_mctrl,
2238 .stop_tx = lpuart32_stop_tx,
2239 .start_tx = lpuart32_start_tx,
2240 .stop_rx = lpuart32_stop_rx,
2241 .break_ctl = lpuart32_break_ctl,
2242 .startup = lpuart32_startup,
2243 .shutdown = lpuart32_shutdown,
2244 .set_termios = lpuart32_set_termios,
2245 .type = lpuart_type,
2246 .request_port = lpuart_request_port,
2247 .release_port = lpuart_release_port,
2248 .config_port = lpuart_config_port,
2249 .verify_port = lpuart_verify_port,
2250 .flush_buffer = lpuart_flush_buffer,
2251 #if defined(CONFIG_CONSOLE_POLL)
2252 .poll_init = lpuart32_poll_init,
2253 .poll_get_char = lpuart32_poll_get_char,
2254 .poll_put_char = lpuart32_poll_put_char,
2255 #endif
2256 };
2257
2258 static struct lpuart_port *lpuart_ports[UART_NR];
2259
2260 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2261 static void lpuart_console_putchar(struct uart_port *port, int ch)
2262 {
2263 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2264 writeb(ch, port->membase + UARTDR);
2265 }
2266
2267 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2268 {
2269 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2270 lpuart32_write(port, ch, UARTDATA);
2271 }
2272
2273 static void
2274 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2275 {
2276 struct lpuart_port *sport = lpuart_ports[co->index];
2277 unsigned char old_cr2, cr2;
2278 unsigned long flags;
2279 int locked = 1;
2280
2281 if (sport->port.sysrq || oops_in_progress)
2282 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2283 else
2284 spin_lock_irqsave(&sport->port.lock, flags);
2285
2286 /* first save CR2 and then disable interrupts */
2287 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2288 cr2 |= UARTCR2_TE | UARTCR2_RE;
2289 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2290 writeb(cr2, sport->port.membase + UARTCR2);
2291
2292 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2293
2294 /* wait for transmitter finish complete and restore CR2 */
2295 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2296
2297 writeb(old_cr2, sport->port.membase + UARTCR2);
2298
2299 if (locked)
2300 spin_unlock_irqrestore(&sport->port.lock, flags);
2301 }
2302
2303 static void
2304 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2305 {
2306 struct lpuart_port *sport = lpuart_ports[co->index];
2307 unsigned long old_cr, cr;
2308 unsigned long flags;
2309 int locked = 1;
2310
2311 if (sport->port.sysrq || oops_in_progress)
2312 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2313 else
2314 spin_lock_irqsave(&sport->port.lock, flags);
2315
2316 /* first save CR2 and then disable interrupts */
2317 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2318 cr |= UARTCTRL_TE | UARTCTRL_RE;
2319 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2320 lpuart32_write(&sport->port, cr, UARTCTRL);
2321
2322 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2323
2324 /* wait for transmitter finish complete and restore CR2 */
2325 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2326
2327 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2328
2329 if (locked)
2330 spin_unlock_irqrestore(&sport->port.lock, flags);
2331 }
2332
2333 /*
2334 * if the port was already initialised (eg, by a boot loader),
2335 * try to determine the current setup.
2336 */
2337 static void __init
2338 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2339 int *parity, int *bits)
2340 {
2341 unsigned char cr, bdh, bdl, brfa;
2342 unsigned int sbr, uartclk, baud_raw;
2343
2344 cr = readb(sport->port.membase + UARTCR2);
2345 cr &= UARTCR2_TE | UARTCR2_RE;
2346 if (!cr)
2347 return;
2348
2349 /* ok, the port was enabled */
2350
2351 cr = readb(sport->port.membase + UARTCR1);
2352
2353 *parity = 'n';
2354 if (cr & UARTCR1_PE) {
2355 if (cr & UARTCR1_PT)
2356 *parity = 'o';
2357 else
2358 *parity = 'e';
2359 }
2360
2361 if (cr & UARTCR1_M)
2362 *bits = 9;
2363 else
2364 *bits = 8;
2365
2366 bdh = readb(sport->port.membase + UARTBDH);
2367 bdh &= UARTBDH_SBR_MASK;
2368 bdl = readb(sport->port.membase + UARTBDL);
2369 sbr = bdh;
2370 sbr <<= 8;
2371 sbr |= bdl;
2372 brfa = readb(sport->port.membase + UARTCR4);
2373 brfa &= UARTCR4_BRFA_MASK;
2374
2375 uartclk = lpuart_get_baud_clk_rate(sport);
2376 /*
2377 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2378 */
2379 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2380
2381 if (*baud != baud_raw)
2382 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2383 "from %d to %d\n", baud_raw, *baud);
2384 }
2385
2386 static void __init
2387 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2388 int *parity, int *bits)
2389 {
2390 unsigned long cr, bd;
2391 unsigned int sbr, uartclk, baud_raw;
2392
2393 cr = lpuart32_read(&sport->port, UARTCTRL);
2394 cr &= UARTCTRL_TE | UARTCTRL_RE;
2395 if (!cr)
2396 return;
2397
2398 /* ok, the port was enabled */
2399
2400 cr = lpuart32_read(&sport->port, UARTCTRL);
2401
2402 *parity = 'n';
2403 if (cr & UARTCTRL_PE) {
2404 if (cr & UARTCTRL_PT)
2405 *parity = 'o';
2406 else
2407 *parity = 'e';
2408 }
2409
2410 if (cr & UARTCTRL_M)
2411 *bits = 9;
2412 else
2413 *bits = 8;
2414
2415 bd = lpuart32_read(&sport->port, UARTBAUD);
2416 bd &= UARTBAUD_SBR_MASK;
2417 sbr = bd;
2418 uartclk = lpuart_get_baud_clk_rate(sport);
2419 /*
2420 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2421 */
2422 baud_raw = uartclk / (16 * sbr);
2423
2424 if (*baud != baud_raw)
2425 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2426 "from %d to %d\n", baud_raw, *baud);
2427 }
2428
2429 static int __init lpuart_console_setup(struct console *co, char *options)
2430 {
2431 struct lpuart_port *sport;
2432 int baud = 115200;
2433 int bits = 8;
2434 int parity = 'n';
2435 int flow = 'n';
2436
2437 /*
2438 * check whether an invalid uart number has been specified, and
2439 * if so, search for the first available port that does have
2440 * console support.
2441 */
2442 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2443 co->index = 0;
2444
2445 sport = lpuart_ports[co->index];
2446 if (sport == NULL)
2447 return -ENODEV;
2448
2449 if (options)
2450 uart_parse_options(options, &baud, &parity, &bits, &flow);
2451 else
2452 if (lpuart_is_32(sport))
2453 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2454 else
2455 lpuart_console_get_options(sport, &baud, &parity, &bits);
2456
2457 if (lpuart_is_32(sport))
2458 lpuart32_setup_watermark(sport);
2459 else
2460 lpuart_setup_watermark(sport);
2461
2462 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2463 }
2464
2465 static struct uart_driver lpuart_reg;
2466 static struct console lpuart_console = {
2467 .name = DEV_NAME,
2468 .write = lpuart_console_write,
2469 .device = uart_console_device,
2470 .setup = lpuart_console_setup,
2471 .flags = CON_PRINTBUFFER,
2472 .index = -1,
2473 .data = &lpuart_reg,
2474 };
2475
2476 static struct console lpuart32_console = {
2477 .name = DEV_NAME,
2478 .write = lpuart32_console_write,
2479 .device = uart_console_device,
2480 .setup = lpuart_console_setup,
2481 .flags = CON_PRINTBUFFER,
2482 .index = -1,
2483 .data = &lpuart_reg,
2484 };
2485
2486 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2487 {
2488 struct earlycon_device *dev = con->data;
2489
2490 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2491 }
2492
2493 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2494 {
2495 struct earlycon_device *dev = con->data;
2496
2497 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2498 }
2499
2500 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2501 const char *opt)
2502 {
2503 if (!device->port.membase)
2504 return -ENODEV;
2505
2506 device->con->write = lpuart_early_write;
2507 return 0;
2508 }
2509
2510 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2511 const char *opt)
2512 {
2513 if (!device->port.membase)
2514 return -ENODEV;
2515
2516 if (device->port.iotype != UPIO_MEM32)
2517 device->port.iotype = UPIO_MEM32BE;
2518
2519 device->con->write = lpuart32_early_write;
2520 return 0;
2521 }
2522
2523 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2524 const char *opt)
2525 {
2526 u32 cr;
2527
2528 if (!device->port.membase)
2529 return -ENODEV;
2530
2531 device->port.iotype = UPIO_MEM32;
2532 device->con->write = lpuart32_early_write;
2533
2534 /* set the baudrate */
2535 if (device->port.uartclk && device->baud)
2536 __lpuart32_serial_setbrg(&device->port, device->baud,
2537 false, false);
2538
2539 /* enable transmitter */
2540 cr = lpuart32_read(&device->port, UARTCTRL);
2541 cr |= UARTCTRL_TE;
2542 lpuart32_write(&device->port, cr, UARTCTRL);
2543
2544 return 0;
2545 }
2546
2547 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2548 const char *opt)
2549 {
2550 if (!device->port.membase)
2551 return -ENODEV;
2552
2553 device->port.iotype = UPIO_MEM32;
2554 device->port.membase += IMX_REG_OFF;
2555 device->con->write = lpuart32_early_write;
2556
2557 return 0;
2558 }
2559 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2560 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2561 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2562 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2563 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2564 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2565
2566 #define LPUART_CONSOLE (&lpuart_console)
2567 #define LPUART32_CONSOLE (&lpuart32_console)
2568 #else
2569 #define LPUART_CONSOLE NULL
2570 #define LPUART32_CONSOLE NULL
2571 #endif
2572
2573 static struct uart_driver lpuart_reg = {
2574 .owner = THIS_MODULE,
2575 .driver_name = DRIVER_NAME,
2576 .dev_name = DEV_NAME,
2577 .nr = ARRAY_SIZE(lpuart_ports),
2578 .cons = LPUART_CONSOLE,
2579 };
2580
2581 static int lpuart_probe(struct platform_device *pdev)
2582 {
2583 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2584 &pdev->dev);
2585 const struct lpuart_soc_data *sdata = of_id->data;
2586 struct device_node *np = pdev->dev.of_node;
2587 struct lpuart_port *sport;
2588 struct resource *res;
2589 int ret;
2590
2591 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2592 if (!sport)
2593 return -ENOMEM;
2594
2595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2596 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2597 if (IS_ERR(sport->port.membase))
2598 return PTR_ERR(sport->port.membase);
2599
2600 sport->port.membase += sdata->reg_off;
2601 sport->port.mapbase = res->start;
2602 sport->port.dev = &pdev->dev;
2603 sport->port.type = PORT_LPUART;
2604 sport->devtype = sdata->devtype;
2605 ret = platform_get_irq(pdev, 0);
2606 if (ret < 0)
2607 return ret;
2608 sport->port.irq = ret;
2609 sport->port.iotype = sdata->iotype;
2610 if (lpuart_is_32(sport))
2611 sport->port.ops = &lpuart32_pops;
2612 else
2613 sport->port.ops = &lpuart_pops;
2614 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2615 sport->port.flags = UPF_BOOT_AUTOCONF;
2616
2617 if (lpuart_is_32(sport))
2618 sport->port.rs485_config = lpuart32_config_rs485;
2619 else
2620 sport->port.rs485_config = lpuart_config_rs485;
2621
2622 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2623 if (IS_ERR(sport->ipg_clk)) {
2624 ret = PTR_ERR(sport->ipg_clk);
2625 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2626 return ret;
2627 }
2628
2629 sport->baud_clk = NULL;
2630 if (is_imx8qxp_lpuart(sport)) {
2631 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2632 if (IS_ERR(sport->baud_clk)) {
2633 ret = PTR_ERR(sport->baud_clk);
2634 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2635 return ret;
2636 }
2637 }
2638
2639 ret = of_alias_get_id(np, "serial");
2640 if (ret < 0) {
2641 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2642 if (ret < 0) {
2643 dev_err(&pdev->dev, "port line is full, add device failed\n");
2644 return ret;
2645 }
2646 sport->id_allocated = true;
2647 }
2648 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2649 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2650 ret = -EINVAL;
2651 goto failed_out_of_range;
2652 }
2653 sport->port.line = ret;
2654
2655 ret = lpuart_enable_clks(sport);
2656 if (ret)
2657 goto failed_clock_enable;
2658 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2659
2660 lpuart_ports[sport->port.line] = sport;
2661
2662 platform_set_drvdata(pdev, &sport->port);
2663
2664 if (lpuart_is_32(sport)) {
2665 lpuart_reg.cons = LPUART32_CONSOLE;
2666 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2667 DRIVER_NAME, sport);
2668 } else {
2669 lpuart_reg.cons = LPUART_CONSOLE;
2670 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2671 DRIVER_NAME, sport);
2672 }
2673
2674 if (ret)
2675 goto failed_irq_request;
2676
2677 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2678 if (ret)
2679 goto failed_attach_port;
2680
2681 ret = uart_get_rs485_mode(&sport->port);
2682 if (ret)
2683 goto failed_get_rs485;
2684
2685 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2686 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2687
2688 if (sport->port.rs485.delay_rts_before_send ||
2689 sport->port.rs485.delay_rts_after_send)
2690 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2691
2692 sport->port.rs485_config(&sport->port, &sport->port.rs485);
2693
2694 return 0;
2695
2696 failed_get_rs485:
2697 failed_attach_port:
2698 failed_irq_request:
2699 lpuart_disable_clks(sport);
2700 failed_clock_enable:
2701 failed_out_of_range:
2702 if (sport->id_allocated)
2703 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2704 return ret;
2705 }
2706
2707 static int lpuart_remove(struct platform_device *pdev)
2708 {
2709 struct lpuart_port *sport = platform_get_drvdata(pdev);
2710
2711 uart_remove_one_port(&lpuart_reg, &sport->port);
2712
2713 if (sport->id_allocated)
2714 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2715
2716 lpuart_disable_clks(sport);
2717
2718 if (sport->dma_tx_chan)
2719 dma_release_channel(sport->dma_tx_chan);
2720
2721 if (sport->dma_rx_chan)
2722 dma_release_channel(sport->dma_rx_chan);
2723
2724 return 0;
2725 }
2726
2727 static int __maybe_unused lpuart_suspend(struct device *dev)
2728 {
2729 struct lpuart_port *sport = dev_get_drvdata(dev);
2730 unsigned long temp;
2731 bool irq_wake;
2732
2733 if (lpuart_is_32(sport)) {
2734 /* disable Rx/Tx and interrupts */
2735 temp = lpuart32_read(&sport->port, UARTCTRL);
2736 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2737 lpuart32_write(&sport->port, temp, UARTCTRL);
2738 } else {
2739 /* disable Rx/Tx and interrupts */
2740 temp = readb(sport->port.membase + UARTCR2);
2741 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2742 writeb(temp, sport->port.membase + UARTCR2);
2743 }
2744
2745 uart_suspend_port(&lpuart_reg, &sport->port);
2746
2747 /* uart_suspend_port() might set wakeup flag */
2748 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2749
2750 if (sport->lpuart_dma_rx_use) {
2751 /*
2752 * EDMA driver during suspend will forcefully release any
2753 * non-idle DMA channels. If port wakeup is enabled or if port
2754 * is console port or 'no_console_suspend' is set the Rx DMA
2755 * cannot resume as as expected, hence gracefully release the
2756 * Rx DMA path before suspend and start Rx DMA path on resume.
2757 */
2758 if (irq_wake) {
2759 del_timer_sync(&sport->lpuart_timer);
2760 lpuart_dma_rx_free(&sport->port);
2761 }
2762
2763 /* Disable Rx DMA to use UART port as wakeup source */
2764 if (lpuart_is_32(sport)) {
2765 temp = lpuart32_read(&sport->port, UARTBAUD);
2766 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2767 UARTBAUD);
2768 } else {
2769 writeb(readb(sport->port.membase + UARTCR5) &
2770 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2771 }
2772 }
2773
2774 if (sport->lpuart_dma_tx_use) {
2775 sport->dma_tx_in_progress = false;
2776 dmaengine_terminate_all(sport->dma_tx_chan);
2777 }
2778
2779 if (sport->port.suspended && !irq_wake)
2780 lpuart_disable_clks(sport);
2781
2782 return 0;
2783 }
2784
2785 static int __maybe_unused lpuart_resume(struct device *dev)
2786 {
2787 struct lpuart_port *sport = dev_get_drvdata(dev);
2788 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2789
2790 if (sport->port.suspended && !irq_wake)
2791 lpuart_enable_clks(sport);
2792
2793 if (lpuart_is_32(sport))
2794 lpuart32_setup_watermark_enable(sport);
2795 else
2796 lpuart_setup_watermark_enable(sport);
2797
2798 if (sport->lpuart_dma_rx_use) {
2799 if (irq_wake) {
2800 if (!lpuart_start_rx_dma(sport))
2801 rx_dma_timer_init(sport);
2802 else
2803 sport->lpuart_dma_rx_use = false;
2804 }
2805 }
2806
2807 lpuart_tx_dma_startup(sport);
2808
2809 if (lpuart_is_32(sport))
2810 lpuart32_configure(sport);
2811
2812 uart_resume_port(&lpuart_reg, &sport->port);
2813
2814 return 0;
2815 }
2816
2817 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2818
2819 static struct platform_driver lpuart_driver = {
2820 .probe = lpuart_probe,
2821 .remove = lpuart_remove,
2822 .driver = {
2823 .name = "fsl-lpuart",
2824 .of_match_table = lpuart_dt_ids,
2825 .pm = &lpuart_pm_ops,
2826 },
2827 };
2828
2829 static int __init lpuart_serial_init(void)
2830 {
2831 int ret = uart_register_driver(&lpuart_reg);
2832
2833 if (ret)
2834 return ret;
2835
2836 ret = platform_driver_register(&lpuart_driver);
2837 if (ret)
2838 uart_unregister_driver(&lpuart_reg);
2839
2840 return ret;
2841 }
2842
2843 static void __exit lpuart_serial_exit(void)
2844 {
2845 ida_destroy(&fsl_lpuart_ida);
2846 platform_driver_unregister(&lpuart_driver);
2847 uart_unregister_driver(&lpuart_reg);
2848 }
2849
2850 module_init(lpuart_serial_init);
2851 module_exit(lpuart_serial_exit);
2852
2853 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2854 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support