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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / tty / serial / serial-tegra.c
blobbbae072a125db880e87c19db1432017455e8fedf
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * serial_tegra.c
4 *
5 * High-speed serial driver for NVIDIA Tegra SoCs
6 *
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pagemap.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_reg.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <linux/termios.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36
37 #define TEGRA_UART_TYPE "TEGRA_UART"
38 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
39 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
40
41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
42 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
43 #define TEGRA_UART_IER_EORD 0x20
44 #define TEGRA_UART_MCR_RTS_EN 0x40
45 #define TEGRA_UART_MCR_CTS_EN 0x20
46 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
47 UART_LSR_PE | UART_LSR_FE)
48 #define TEGRA_UART_IRDA_CSR 0x08
49 #define TEGRA_UART_SIR_ENABLED 0x80
50
51 #define TEGRA_UART_TX_PIO 1
52 #define TEGRA_UART_TX_DMA 2
53 #define TEGRA_UART_MIN_DMA 16
54 #define TEGRA_UART_FIFO_SIZE 32
55
56 /*
57 * Tx fifo trigger level setting in tegra uart is in
58 * reverse way then conventional uart.
59 */
60 #define TEGRA_UART_TX_TRIG_16B 0x00
61 #define TEGRA_UART_TX_TRIG_8B 0x10
62 #define TEGRA_UART_TX_TRIG_4B 0x20
63 #define TEGRA_UART_TX_TRIG_1B 0x30
64
65 #define TEGRA_UART_MAXIMUM 8
66
67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68 #define TEGRA_UART_DEFAULT_BAUD 115200
69 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
70
71 /* Tx transfer mode */
72 #define TEGRA_TX_PIO 1
73 #define TEGRA_TX_DMA 2
74
75 #define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
76
77 /**
78 * struct tegra_uart_chip_data: SOC specific data.
79 *
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
82 * Tegra30 does not allow this.
83 * @support_clk_src_div: Clock source support the clock divider.
84 * @fifo_mode_enable_status: Is FIFO mode enabled?
85 * @uart_max_port: Maximum number of UART ports
86 * @max_dma_burst_bytes: Maximum size of DMA bursts
87 * @error_tolerance_low_range: Lowest number in the error tolerance range
88 * @error_tolerance_high_range: Highest number in the error tolerance range
89 */
90 struct tegra_uart_chip_data {
91 bool tx_fifo_full_status;
92 bool allow_txfifo_reset_fifo_mode;
93 bool support_clk_src_div;
94 bool fifo_mode_enable_status;
95 int uart_max_port;
96 int max_dma_burst_bytes;
97 int error_tolerance_low_range;
98 int error_tolerance_high_range;
99 };
100
101 struct tegra_baud_tolerance {
102 u32 lower_range_baud;
103 u32 upper_range_baud;
104 s32 tolerance;
105 };
106
107 struct tegra_uart_port {
108 struct uart_port uport;
109 const struct tegra_uart_chip_data *cdata;
110
111 struct clk *uart_clk;
112 struct reset_control *rst;
113 unsigned int current_baud;
114
115 /* Register shadow */
116 unsigned long fcr_shadow;
117 unsigned long mcr_shadow;
118 unsigned long lcr_shadow;
119 unsigned long ier_shadow;
120 bool rts_active;
121
122 int tx_in_progress;
123 unsigned int tx_bytes;
124
125 bool enable_modem_interrupt;
126
127 bool rx_timeout;
128 int rx_in_progress;
129 int symb_bit;
130
131 struct dma_chan *rx_dma_chan;
132 struct dma_chan *tx_dma_chan;
133 dma_addr_t rx_dma_buf_phys;
134 dma_addr_t tx_dma_buf_phys;
135 unsigned char *rx_dma_buf_virt;
136 unsigned char *tx_dma_buf_virt;
137 struct dma_async_tx_descriptor *tx_dma_desc;
138 struct dma_async_tx_descriptor *rx_dma_desc;
139 dma_cookie_t tx_cookie;
140 dma_cookie_t rx_cookie;
141 unsigned int tx_bytes_requested;
142 unsigned int rx_bytes_requested;
143 struct tegra_baud_tolerance *baud_tolerance;
144 int n_adjustable_baud_rates;
145 int required_rate;
146 int configured_rate;
147 bool use_rx_pio;
148 bool use_tx_pio;
149 bool rx_dma_active;
150 };
151
152 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
153 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
154 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
155 bool dma_to_memory);
156
157 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
158 unsigned long reg)
159 {
160 return readl(tup->uport.membase + (reg << tup->uport.regshift));
161 }
162
163 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
164 unsigned long reg)
165 {
166 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
167 }
168
169 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
170 {
171 return container_of(u, struct tegra_uart_port, uport);
172 }
173
174 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
175 {
176 struct tegra_uart_port *tup = to_tegra_uport(u);
177
178 /*
179 * RI - Ring detector is active
180 * CD/DCD/CAR - Carrier detect is always active. For some reason
181 * linux has different names for carrier detect.
182 * DSR - Data Set ready is active as the hardware doesn't support it.
183 * Don't know if the linux support this yet?
184 * CTS - Clear to send. Always set to active, as the hardware handles
185 * CTS automatically.
186 */
187 if (tup->enable_modem_interrupt)
188 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
189 return TIOCM_CTS;
190 }
191
192 static void set_rts(struct tegra_uart_port *tup, bool active)
193 {
194 unsigned long mcr;
195
196 mcr = tup->mcr_shadow;
197 if (active)
198 mcr |= TEGRA_UART_MCR_RTS_EN;
199 else
200 mcr &= ~TEGRA_UART_MCR_RTS_EN;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
204 }
205 }
206
207 static void set_dtr(struct tegra_uart_port *tup, bool active)
208 {
209 unsigned long mcr;
210
211 mcr = tup->mcr_shadow;
212 if (active)
213 mcr |= UART_MCR_DTR;
214 else
215 mcr &= ~UART_MCR_DTR;
216 if (mcr != tup->mcr_shadow) {
217 tegra_uart_write(tup, mcr, UART_MCR);
218 tup->mcr_shadow = mcr;
219 }
220 }
221
222 static void set_loopbk(struct tegra_uart_port *tup, bool active)
223 {
224 unsigned long mcr = tup->mcr_shadow;
225
226 if (active)
227 mcr |= UART_MCR_LOOP;
228 else
229 mcr &= ~UART_MCR_LOOP;
230
231 if (mcr != tup->mcr_shadow) {
232 tegra_uart_write(tup, mcr, UART_MCR);
233 tup->mcr_shadow = mcr;
234 }
235 }
236
237 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
238 {
239 struct tegra_uart_port *tup = to_tegra_uport(u);
240 int enable;
241
242 tup->rts_active = !!(mctrl & TIOCM_RTS);
243 set_rts(tup, tup->rts_active);
244
245 enable = !!(mctrl & TIOCM_DTR);
246 set_dtr(tup, enable);
247
248 enable = !!(mctrl & TIOCM_LOOP);
249 set_loopbk(tup, enable);
250 }
251
252 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
253 {
254 struct tegra_uart_port *tup = to_tegra_uport(u);
255 unsigned long lcr;
256
257 lcr = tup->lcr_shadow;
258 if (break_ctl)
259 lcr |= UART_LCR_SBC;
260 else
261 lcr &= ~UART_LCR_SBC;
262 tegra_uart_write(tup, lcr, UART_LCR);
263 tup->lcr_shadow = lcr;
264 }
265
266 /**
267 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
268 *
269 * @tup: Tegra serial port data structure.
270 * @cycles: Number of clock periods to wait.
271 *
272 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
273 * clock speed is 16X the current baud rate.
274 */
275 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
276 unsigned int cycles)
277 {
278 if (tup->current_baud)
279 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
280 }
281
282 /* Wait for a symbol-time. */
283 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
284 unsigned int syms)
285 {
286 if (tup->current_baud)
287 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
288 tup->current_baud));
289 }
290
291 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
292 {
293 unsigned long iir;
294 unsigned int tmout = 100;
295
296 do {
297 iir = tegra_uart_read(tup, UART_IIR);
298 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
299 return 0;
300 udelay(1);
301 } while (--tmout);
302
303 return -ETIMEDOUT;
304 }
305
306 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
307 {
308 unsigned long fcr = tup->fcr_shadow;
309 unsigned int lsr, tmout = 10000;
310
311 if (tup->rts_active)
312 set_rts(tup, false);
313
314 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
315 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
316 tegra_uart_write(tup, fcr, UART_FCR);
317 } else {
318 fcr &= ~UART_FCR_ENABLE_FIFO;
319 tegra_uart_write(tup, fcr, UART_FCR);
320 udelay(60);
321 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
322 tegra_uart_write(tup, fcr, UART_FCR);
323 fcr |= UART_FCR_ENABLE_FIFO;
324 tegra_uart_write(tup, fcr, UART_FCR);
325 if (tup->cdata->fifo_mode_enable_status)
326 tegra_uart_wait_fifo_mode_enabled(tup);
327 }
328
329 /* Dummy read to ensure the write is posted */
330 tegra_uart_read(tup, UART_SCR);
331
332 /*
333 * For all tegra devices (up to t210), there is a hardware issue that
334 * requires software to wait for 32 UART clock periods for the flush
335 * to propagate, otherwise data could be lost.
336 */
337 tegra_uart_wait_cycle_time(tup, 32);
338
339 do {
340 lsr = tegra_uart_read(tup, UART_LSR);
341 if ((lsr | UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
342 break;
343 udelay(1);
344 } while (--tmout);
345
346 if (tup->rts_active)
347 set_rts(tup, true);
348 }
349
350 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
351 unsigned int baud, long rate)
352 {
353 int i;
354
355 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
356 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
357 baud <= tup->baud_tolerance[i].upper_range_baud)
358 return (rate + (rate *
359 tup->baud_tolerance[i].tolerance) / 10000);
360 }
361
362 return rate;
363 }
364
365 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
366 {
367 long diff;
368
369 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
370 / tup->required_rate;
371 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
372 diff > (tup->cdata->error_tolerance_high_range * 100)) {
373 dev_err(tup->uport.dev,
374 "configured baud rate is out of range by %ld", diff);
375 return -EIO;
376 }
377
378 return 0;
379 }
380
381 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
382 {
383 unsigned long rate;
384 unsigned int divisor;
385 unsigned long lcr;
386 unsigned long flags;
387 int ret;
388
389 if (tup->current_baud == baud)
390 return 0;
391
392 if (tup->cdata->support_clk_src_div) {
393 rate = baud * 16;
394 tup->required_rate = rate;
395
396 if (tup->n_adjustable_baud_rates)
397 rate = tegra_get_tolerance_rate(tup, baud, rate);
398
399 ret = clk_set_rate(tup->uart_clk, rate);
400 if (ret < 0) {
401 dev_err(tup->uport.dev,
402 "clk_set_rate() failed for rate %lu\n", rate);
403 return ret;
404 }
405 tup->configured_rate = clk_get_rate(tup->uart_clk);
406 divisor = 1;
407 ret = tegra_check_rate_in_range(tup);
408 if (ret < 0)
409 return ret;
410 } else {
411 rate = clk_get_rate(tup->uart_clk);
412 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
413 }
414
415 spin_lock_irqsave(&tup->uport.lock, flags);
416 lcr = tup->lcr_shadow;
417 lcr |= UART_LCR_DLAB;
418 tegra_uart_write(tup, lcr, UART_LCR);
419
420 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
421 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
422
423 lcr &= ~UART_LCR_DLAB;
424 tegra_uart_write(tup, lcr, UART_LCR);
425
426 /* Dummy read to ensure the write is posted */
427 tegra_uart_read(tup, UART_SCR);
428 spin_unlock_irqrestore(&tup->uport.lock, flags);
429
430 tup->current_baud = baud;
431
432 /* wait two character intervals at new rate */
433 tegra_uart_wait_sym_time(tup, 2);
434 return 0;
435 }
436
437 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
438 unsigned long lsr)
439 {
440 char flag = TTY_NORMAL;
441
442 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
443 if (lsr & UART_LSR_OE) {
444 /* Overrrun error */
445 flag = TTY_OVERRUN;
446 tup->uport.icount.overrun++;
447 dev_dbg(tup->uport.dev, "Got overrun errors\n");
448 } else if (lsr & UART_LSR_PE) {
449 /* Parity error */
450 flag = TTY_PARITY;
451 tup->uport.icount.parity++;
452 dev_dbg(tup->uport.dev, "Got Parity errors\n");
453 } else if (lsr & UART_LSR_FE) {
454 flag = TTY_FRAME;
455 tup->uport.icount.frame++;
456 dev_dbg(tup->uport.dev, "Got frame errors\n");
457 } else if (lsr & UART_LSR_BI) {
458 /*
459 * Break error
460 * If FIFO read error without any data, reset Rx FIFO
461 */
462 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
463 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
464 if (tup->uport.ignore_status_mask & UART_LSR_BI)
465 return TTY_BREAK;
466 flag = TTY_BREAK;
467 tup->uport.icount.brk++;
468 dev_dbg(tup->uport.dev, "Got Break\n");
469 }
470 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
471 }
472
473 return flag;
474 }
475
476 static int tegra_uart_request_port(struct uart_port *u)
477 {
478 return 0;
479 }
480
481 static void tegra_uart_release_port(struct uart_port *u)
482 {
483 /* Nothing to do here */
484 }
485
486 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
487 {
488 struct circ_buf *xmit = &tup->uport.state->xmit;
489 int i;
490
491 for (i = 0; i < max_bytes; i++) {
492 BUG_ON(uart_circ_empty(xmit));
493 if (tup->cdata->tx_fifo_full_status) {
494 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
495 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
496 break;
497 }
498 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
499 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
500 tup->uport.icount.tx++;
501 }
502 }
503
504 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
505 unsigned int bytes)
506 {
507 if (bytes > TEGRA_UART_MIN_DMA)
508 bytes = TEGRA_UART_MIN_DMA;
509
510 tup->tx_in_progress = TEGRA_UART_TX_PIO;
511 tup->tx_bytes = bytes;
512 tup->ier_shadow |= UART_IER_THRI;
513 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
514 }
515
516 static void tegra_uart_tx_dma_complete(void *args)
517 {
518 struct tegra_uart_port *tup = args;
519 struct circ_buf *xmit = &tup->uport.state->xmit;
520 struct dma_tx_state state;
521 unsigned long flags;
522 unsigned int count;
523
524 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
525 count = tup->tx_bytes_requested - state.residue;
526 async_tx_ack(tup->tx_dma_desc);
527 spin_lock_irqsave(&tup->uport.lock, flags);
528 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
529 tup->tx_in_progress = 0;
530 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
531 uart_write_wakeup(&tup->uport);
532 tegra_uart_start_next_tx(tup);
533 spin_unlock_irqrestore(&tup->uport.lock, flags);
534 }
535
536 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
537 unsigned long count)
538 {
539 struct circ_buf *xmit = &tup->uport.state->xmit;
540 dma_addr_t tx_phys_addr;
541
542 tup->tx_bytes = count & ~(0xF);
543 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
544
545 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
546 tup->tx_bytes, DMA_TO_DEVICE);
547
548 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
549 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
550 DMA_PREP_INTERRUPT);
551 if (!tup->tx_dma_desc) {
552 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
553 return -EIO;
554 }
555
556 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
557 tup->tx_dma_desc->callback_param = tup;
558 tup->tx_in_progress = TEGRA_UART_TX_DMA;
559 tup->tx_bytes_requested = tup->tx_bytes;
560 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
561 dma_async_issue_pending(tup->tx_dma_chan);
562 return 0;
563 }
564
565 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
566 {
567 unsigned long tail;
568 unsigned long count;
569 struct circ_buf *xmit = &tup->uport.state->xmit;
570
571 if (!tup->current_baud)
572 return;
573
574 tail = (unsigned long)&xmit->buf[xmit->tail];
575 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
576 if (!count)
577 return;
578
579 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
580 tegra_uart_start_pio_tx(tup, count);
581 else if (BYTES_TO_ALIGN(tail) > 0)
582 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
583 else
584 tegra_uart_start_tx_dma(tup, count);
585 }
586
587 /* Called by serial core driver with u->lock taken. */
588 static void tegra_uart_start_tx(struct uart_port *u)
589 {
590 struct tegra_uart_port *tup = to_tegra_uport(u);
591 struct circ_buf *xmit = &u->state->xmit;
592
593 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
594 tegra_uart_start_next_tx(tup);
595 }
596
597 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
598 {
599 struct tegra_uart_port *tup = to_tegra_uport(u);
600 unsigned int ret = 0;
601 unsigned long flags;
602
603 spin_lock_irqsave(&u->lock, flags);
604 if (!tup->tx_in_progress) {
605 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
606 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
607 ret = TIOCSER_TEMT;
608 }
609 spin_unlock_irqrestore(&u->lock, flags);
610 return ret;
611 }
612
613 static void tegra_uart_stop_tx(struct uart_port *u)
614 {
615 struct tegra_uart_port *tup = to_tegra_uport(u);
616 struct circ_buf *xmit = &tup->uport.state->xmit;
617 struct dma_tx_state state;
618 unsigned int count;
619
620 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
621 return;
622
623 dmaengine_terminate_all(tup->tx_dma_chan);
624 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
625 count = tup->tx_bytes_requested - state.residue;
626 async_tx_ack(tup->tx_dma_desc);
627 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
628 tup->tx_in_progress = 0;
629 }
630
631 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
632 {
633 struct circ_buf *xmit = &tup->uport.state->xmit;
634
635 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
636 tup->tx_in_progress = 0;
637 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638 uart_write_wakeup(&tup->uport);
639 tegra_uart_start_next_tx(tup);
640 }
641
642 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
643 struct tty_port *port)
644 {
645 do {
646 char flag = TTY_NORMAL;
647 unsigned long lsr = 0;
648 unsigned char ch;
649
650 lsr = tegra_uart_read(tup, UART_LSR);
651 if (!(lsr & UART_LSR_DR))
652 break;
653
654 flag = tegra_uart_decode_rx_error(tup, lsr);
655 if (flag != TTY_NORMAL)
656 continue;
657
658 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
659 tup->uport.icount.rx++;
660
661 if (uart_handle_sysrq_char(&tup->uport, ch))
662 continue;
663
664 if (tup->uport.ignore_status_mask & UART_LSR_DR)
665 continue;
666
667 tty_insert_flip_char(port, ch, flag);
668 } while (1);
669 }
670
671 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
672 struct tty_port *port,
673 unsigned int count)
674 {
675 int copied;
676
677 /* If count is zero, then there is no data to be copied */
678 if (!count)
679 return;
680
681 tup->uport.icount.rx += count;
682
683 if (tup->uport.ignore_status_mask & UART_LSR_DR)
684 return;
685
686 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
687 count, DMA_FROM_DEVICE);
688 copied = tty_insert_flip_string(port,
689 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
690 if (copied != count) {
691 WARN_ON(1);
692 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
693 }
694 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
695 count, DMA_TO_DEVICE);
696 }
697
698 static void do_handle_rx_pio(struct tegra_uart_port *tup)
699 {
700 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
701 struct tty_port *port = &tup->uport.state->port;
702
703 tegra_uart_handle_rx_pio(tup, port);
704 if (tty) {
705 tty_flip_buffer_push(port);
706 tty_kref_put(tty);
707 }
708 }
709
710 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
711 unsigned int residue)
712 {
713 struct tty_port *port = &tup->uport.state->port;
714 unsigned int count;
715
716 async_tx_ack(tup->rx_dma_desc);
717 count = tup->rx_bytes_requested - residue;
718
719 /* If we are here, DMA is stopped */
720 tegra_uart_copy_rx_to_tty(tup, port, count);
721
722 do_handle_rx_pio(tup);
723 }
724
725 static void tegra_uart_rx_dma_complete(void *args)
726 {
727 struct tegra_uart_port *tup = args;
728 struct uart_port *u = &tup->uport;
729 unsigned long flags;
730 struct dma_tx_state state;
731 enum dma_status status;
732
733 spin_lock_irqsave(&u->lock, flags);
734
735 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
736
737 if (status == DMA_IN_PROGRESS) {
738 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
739 goto done;
740 }
741
742 /* Deactivate flow control to stop sender */
743 if (tup->rts_active)
744 set_rts(tup, false);
745
746 tup->rx_dma_active = false;
747 tegra_uart_rx_buffer_push(tup, 0);
748 tegra_uart_start_rx_dma(tup);
749
750 /* Activate flow control to start transfer */
751 if (tup->rts_active)
752 set_rts(tup, true);
753
754 done:
755 spin_unlock_irqrestore(&u->lock, flags);
756 }
757
758 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
759 {
760 struct dma_tx_state state;
761
762 if (!tup->rx_dma_active) {
763 do_handle_rx_pio(tup);
764 return;
765 }
766
767 dmaengine_terminate_all(tup->rx_dma_chan);
768 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
769
770 tegra_uart_rx_buffer_push(tup, state.residue);
771 tup->rx_dma_active = false;
772 }
773
774 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
775 {
776 /* Deactivate flow control to stop sender */
777 if (tup->rts_active)
778 set_rts(tup, false);
779
780 tegra_uart_terminate_rx_dma(tup);
781
782 if (tup->rts_active)
783 set_rts(tup, true);
784 }
785
786 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
787 {
788 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
789
790 if (tup->rx_dma_active)
791 return 0;
792
793 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
794 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
795 DMA_PREP_INTERRUPT);
796 if (!tup->rx_dma_desc) {
797 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
798 return -EIO;
799 }
800
801 tup->rx_dma_active = true;
802 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
803 tup->rx_dma_desc->callback_param = tup;
804 tup->rx_bytes_requested = count;
805 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
806 dma_async_issue_pending(tup->rx_dma_chan);
807 return 0;
808 }
809
810 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
811 {
812 struct tegra_uart_port *tup = to_tegra_uport(u);
813 unsigned long msr;
814
815 msr = tegra_uart_read(tup, UART_MSR);
816 if (!(msr & UART_MSR_ANY_DELTA))
817 return;
818
819 if (msr & UART_MSR_TERI)
820 tup->uport.icount.rng++;
821 if (msr & UART_MSR_DDSR)
822 tup->uport.icount.dsr++;
823 /* We may only get DDCD when HW init and reset */
824 if (msr & UART_MSR_DDCD)
825 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
826 /* Will start/stop_tx accordingly */
827 if (msr & UART_MSR_DCTS)
828 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
829 }
830
831 static irqreturn_t tegra_uart_isr(int irq, void *data)
832 {
833 struct tegra_uart_port *tup = data;
834 struct uart_port *u = &tup->uport;
835 unsigned long iir;
836 unsigned long ier;
837 bool is_rx_start = false;
838 bool is_rx_int = false;
839 unsigned long flags;
840
841 spin_lock_irqsave(&u->lock, flags);
842 while (1) {
843 iir = tegra_uart_read(tup, UART_IIR);
844 if (iir & UART_IIR_NO_INT) {
845 if (!tup->use_rx_pio && is_rx_int) {
846 tegra_uart_handle_rx_dma(tup);
847 if (tup->rx_in_progress) {
848 ier = tup->ier_shadow;
849 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
850 TEGRA_UART_IER_EORD | UART_IER_RDI);
851 tup->ier_shadow = ier;
852 tegra_uart_write(tup, ier, UART_IER);
853 }
854 } else if (is_rx_start) {
855 tegra_uart_start_rx_dma(tup);
856 }
857 spin_unlock_irqrestore(&u->lock, flags);
858 return IRQ_HANDLED;
859 }
860
861 switch ((iir >> 1) & 0x7) {
862 case 0: /* Modem signal change interrupt */
863 tegra_uart_handle_modem_signal_change(u);
864 break;
865
866 case 1: /* Transmit interrupt only triggered when using PIO */
867 tup->ier_shadow &= ~UART_IER_THRI;
868 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
869 tegra_uart_handle_tx_pio(tup);
870 break;
871
872 case 4: /* End of data */
873 case 6: /* Rx timeout */
874 if (!tup->use_rx_pio) {
875 is_rx_int = tup->rx_in_progress;
876 /* Disable Rx interrupts */
877 ier = tup->ier_shadow;
878 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
879 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
880 tup->ier_shadow = ier;
881 tegra_uart_write(tup, ier, UART_IER);
882 break;
883 }
884 fallthrough;
885 case 2: /* Receive */
886 if (!tup->use_rx_pio) {
887 is_rx_start = tup->rx_in_progress;
888 tup->ier_shadow &= ~UART_IER_RDI;
889 tegra_uart_write(tup, tup->ier_shadow,
890 UART_IER);
891 } else {
892 do_handle_rx_pio(tup);
893 }
894 break;
895
896 case 3: /* Receive error */
897 tegra_uart_decode_rx_error(tup,
898 tegra_uart_read(tup, UART_LSR));
899 break;
900
901 case 5: /* break nothing to handle */
902 case 7: /* break nothing to handle */
903 break;
904 }
905 }
906 }
907
908 static void tegra_uart_stop_rx(struct uart_port *u)
909 {
910 struct tegra_uart_port *tup = to_tegra_uport(u);
911 struct tty_port *port = &tup->uport.state->port;
912 unsigned long ier;
913
914 if (tup->rts_active)
915 set_rts(tup, false);
916
917 if (!tup->rx_in_progress)
918 return;
919
920 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
921
922 ier = tup->ier_shadow;
923 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
924 TEGRA_UART_IER_EORD);
925 tup->ier_shadow = ier;
926 tegra_uart_write(tup, ier, UART_IER);
927 tup->rx_in_progress = 0;
928
929 if (!tup->use_rx_pio)
930 tegra_uart_terminate_rx_dma(tup);
931 else
932 tegra_uart_handle_rx_pio(tup, port);
933 }
934
935 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
936 {
937 unsigned long flags;
938 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
939 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
940 unsigned long wait_time;
941 unsigned long lsr;
942 unsigned long msr;
943 unsigned long mcr;
944
945 /* Disable interrupts */
946 tegra_uart_write(tup, 0, UART_IER);
947
948 lsr = tegra_uart_read(tup, UART_LSR);
949 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
950 msr = tegra_uart_read(tup, UART_MSR);
951 mcr = tegra_uart_read(tup, UART_MCR);
952 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
953 dev_err(tup->uport.dev,
954 "Tx Fifo not empty, CTS disabled, waiting\n");
955
956 /* Wait for Tx fifo to be empty */
957 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
958 wait_time = min(fifo_empty_time, 100lu);
959 udelay(wait_time);
960 fifo_empty_time -= wait_time;
961 if (!fifo_empty_time) {
962 msr = tegra_uart_read(tup, UART_MSR);
963 mcr = tegra_uart_read(tup, UART_MCR);
964 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
965 (msr & UART_MSR_CTS))
966 dev_err(tup->uport.dev,
967 "Slave not ready\n");
968 break;
969 }
970 lsr = tegra_uart_read(tup, UART_LSR);
971 }
972 }
973
974 spin_lock_irqsave(&tup->uport.lock, flags);
975 /* Reset the Rx and Tx FIFOs */
976 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
977 tup->current_baud = 0;
978 spin_unlock_irqrestore(&tup->uport.lock, flags);
979
980 tup->rx_in_progress = 0;
981 tup->tx_in_progress = 0;
982
983 if (!tup->use_rx_pio)
984 tegra_uart_dma_channel_free(tup, true);
985 if (!tup->use_tx_pio)
986 tegra_uart_dma_channel_free(tup, false);
987
988 clk_disable_unprepare(tup->uart_clk);
989 }
990
991 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
992 {
993 int ret;
994
995 tup->fcr_shadow = 0;
996 tup->mcr_shadow = 0;
997 tup->lcr_shadow = 0;
998 tup->ier_shadow = 0;
999 tup->current_baud = 0;
1000
1001 clk_prepare_enable(tup->uart_clk);
1002
1003 /* Reset the UART controller to clear all previous status.*/
1004 reset_control_assert(tup->rst);
1005 udelay(10);
1006 reset_control_deassert(tup->rst);
1007
1008 tup->rx_in_progress = 0;
1009 tup->tx_in_progress = 0;
1010
1011 /*
1012 * Set the trigger level
1013 *
1014 * For PIO mode:
1015 *
1016 * For receive, this will interrupt the CPU after that many number of
1017 * bytes are received, for the remaining bytes the receive timeout
1018 * interrupt is received. Rx high watermark is set to 4.
1019 *
1020 * For transmit, if the trasnmit interrupt is enabled, this will
1021 * interrupt the CPU when the number of entries in the FIFO reaches the
1022 * low watermark. Tx low watermark is set to 16 bytes.
1023 *
1024 * For DMA mode:
1025 *
1026 * Set the Tx trigger to 16. This should match the DMA burst size that
1027 * programmed in the DMA registers.
1028 */
1029 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1030
1031 if (tup->use_rx_pio) {
1032 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1033 } else {
1034 if (tup->cdata->max_dma_burst_bytes == 8)
1035 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1036 else
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1038 }
1039
1040 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1041 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1042
1043 /* Dummy read to ensure the write is posted */
1044 tegra_uart_read(tup, UART_SCR);
1045
1046 if (tup->cdata->fifo_mode_enable_status) {
1047 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1048 dev_err(tup->uport.dev, "FIFO mode not enabled\n");
1049 if (ret < 0)
1050 return ret;
1051 } else {
1052 /*
1053 * For all tegra devices (up to t210), there is a hardware
1054 * issue that requires software to wait for 3 UART clock
1055 * periods after enabling the TX fifo, otherwise data could
1056 * be lost.
1057 */
1058 tegra_uart_wait_cycle_time(tup, 3);
1059 }
1060
1061 /*
1062 * Initialize the UART with default configuration
1063 * (115200, N, 8, 1) so that the receive DMA buffer may be
1064 * enqueued
1065 */
1066 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1067 if (ret < 0) {
1068 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1069 return ret;
1070 }
1071 if (!tup->use_rx_pio) {
1072 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1073 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1074 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1075 } else {
1076 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1077 }
1078 tup->rx_in_progress = 1;
1079
1080 /*
1081 * Enable IE_RXS for the receive status interrupts like line errros.
1082 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1083 *
1084 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1085 * the DATA is sitting in the FIFO and couldn't be transferred to the
1086 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1087 * triggered when there is a pause of the incomming data stream for 4
1088 * characters long.
1089 *
1090 * For pauses in the data which is not aligned to 4 bytes, we get
1091 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1092 * then the EORD.
1093 */
1094 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1095
1096 /*
1097 * If using DMA mode, enable EORD interrupt to notify about RX
1098 * completion.
1099 */
1100 if (!tup->use_rx_pio)
1101 tup->ier_shadow |= TEGRA_UART_IER_EORD;
1102
1103 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1104 return 0;
1105 }
1106
1107 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1108 bool dma_to_memory)
1109 {
1110 if (dma_to_memory) {
1111 dmaengine_terminate_all(tup->rx_dma_chan);
1112 dma_release_channel(tup->rx_dma_chan);
1113 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1114 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1115 tup->rx_dma_chan = NULL;
1116 tup->rx_dma_buf_phys = 0;
1117 tup->rx_dma_buf_virt = NULL;
1118 } else {
1119 dmaengine_terminate_all(tup->tx_dma_chan);
1120 dma_release_channel(tup->tx_dma_chan);
1121 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1122 UART_XMIT_SIZE, DMA_TO_DEVICE);
1123 tup->tx_dma_chan = NULL;
1124 tup->tx_dma_buf_phys = 0;
1125 tup->tx_dma_buf_virt = NULL;
1126 }
1127 }
1128
1129 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1130 bool dma_to_memory)
1131 {
1132 struct dma_chan *dma_chan;
1133 unsigned char *dma_buf;
1134 dma_addr_t dma_phys;
1135 int ret;
1136 struct dma_slave_config dma_sconfig;
1137
1138 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1139 if (IS_ERR(dma_chan)) {
1140 ret = PTR_ERR(dma_chan);
1141 dev_err(tup->uport.dev,
1142 "DMA channel alloc failed: %d\n", ret);
1143 return ret;
1144 }
1145
1146 if (dma_to_memory) {
1147 dma_buf = dma_alloc_coherent(tup->uport.dev,
1148 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1149 &dma_phys, GFP_KERNEL);
1150 if (!dma_buf) {
1151 dev_err(tup->uport.dev,
1152 "Not able to allocate the dma buffer\n");
1153 dma_release_channel(dma_chan);
1154 return -ENOMEM;
1155 }
1156 dma_sync_single_for_device(tup->uport.dev, dma_phys,
1157 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1158 DMA_TO_DEVICE);
1159 dma_sconfig.src_addr = tup->uport.mapbase;
1160 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1162 tup->rx_dma_chan = dma_chan;
1163 tup->rx_dma_buf_virt = dma_buf;
1164 tup->rx_dma_buf_phys = dma_phys;
1165 } else {
1166 dma_phys = dma_map_single(tup->uport.dev,
1167 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1168 DMA_TO_DEVICE);
1169 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1170 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1171 dma_release_channel(dma_chan);
1172 return -ENOMEM;
1173 }
1174 dma_buf = tup->uport.state->xmit.buf;
1175 dma_sconfig.dst_addr = tup->uport.mapbase;
1176 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1177 dma_sconfig.dst_maxburst = 16;
1178 tup->tx_dma_chan = dma_chan;
1179 tup->tx_dma_buf_virt = dma_buf;
1180 tup->tx_dma_buf_phys = dma_phys;
1181 }
1182
1183 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1184 if (ret < 0) {
1185 dev_err(tup->uport.dev,
1186 "Dma slave config failed, err = %d\n", ret);
1187 tegra_uart_dma_channel_free(tup, dma_to_memory);
1188 return ret;
1189 }
1190
1191 return 0;
1192 }
1193
1194 static int tegra_uart_startup(struct uart_port *u)
1195 {
1196 struct tegra_uart_port *tup = to_tegra_uport(u);
1197 int ret;
1198
1199 if (!tup->use_tx_pio) {
1200 ret = tegra_uart_dma_channel_allocate(tup, false);
1201 if (ret < 0) {
1202 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1203 ret);
1204 return ret;
1205 }
1206 }
1207
1208 if (!tup->use_rx_pio) {
1209 ret = tegra_uart_dma_channel_allocate(tup, true);
1210 if (ret < 0) {
1211 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1212 ret);
1213 goto fail_rx_dma;
1214 }
1215 }
1216
1217 ret = tegra_uart_hw_init(tup);
1218 if (ret < 0) {
1219 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1220 goto fail_hw_init;
1221 }
1222
1223 ret = request_irq(u->irq, tegra_uart_isr, 0,
1224 dev_name(u->dev), tup);
1225 if (ret < 0) {
1226 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1227 goto fail_hw_init;
1228 }
1229 return 0;
1230
1231 fail_hw_init:
1232 if (!tup->use_rx_pio)
1233 tegra_uart_dma_channel_free(tup, true);
1234 fail_rx_dma:
1235 if (!tup->use_tx_pio)
1236 tegra_uart_dma_channel_free(tup, false);
1237 return ret;
1238 }
1239
1240 /*
1241 * Flush any TX data submitted for DMA and PIO. Called when the
1242 * TX circular buffer is reset.
1243 */
1244 static void tegra_uart_flush_buffer(struct uart_port *u)
1245 {
1246 struct tegra_uart_port *tup = to_tegra_uport(u);
1247
1248 tup->tx_bytes = 0;
1249 if (tup->tx_dma_chan)
1250 dmaengine_terminate_all(tup->tx_dma_chan);
1251 }
1252
1253 static void tegra_uart_shutdown(struct uart_port *u)
1254 {
1255 struct tegra_uart_port *tup = to_tegra_uport(u);
1256
1257 tegra_uart_hw_deinit(tup);
1258 free_irq(u->irq, tup);
1259 }
1260
1261 static void tegra_uart_enable_ms(struct uart_port *u)
1262 {
1263 struct tegra_uart_port *tup = to_tegra_uport(u);
1264
1265 if (tup->enable_modem_interrupt) {
1266 tup->ier_shadow |= UART_IER_MSI;
1267 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1268 }
1269 }
1270
1271 static void tegra_uart_set_termios(struct uart_port *u,
1272 struct ktermios *termios, struct ktermios *oldtermios)
1273 {
1274 struct tegra_uart_port *tup = to_tegra_uport(u);
1275 unsigned int baud;
1276 unsigned long flags;
1277 unsigned int lcr;
1278 int symb_bit = 1;
1279 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1280 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1281 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1282 int ret;
1283
1284 max_divider *= 16;
1285 spin_lock_irqsave(&u->lock, flags);
1286
1287 /* Changing configuration, it is safe to stop any rx now */
1288 if (tup->rts_active)
1289 set_rts(tup, false);
1290
1291 /* Clear all interrupts as configuration is going to be changed */
1292 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1293 tegra_uart_read(tup, UART_IER);
1294 tegra_uart_write(tup, 0, UART_IER);
1295 tegra_uart_read(tup, UART_IER);
1296
1297 /* Parity */
1298 lcr = tup->lcr_shadow;
1299 lcr &= ~UART_LCR_PARITY;
1300
1301 /* CMSPAR isn't supported by this driver */
1302 termios->c_cflag &= ~CMSPAR;
1303
1304 if ((termios->c_cflag & PARENB) == PARENB) {
1305 symb_bit++;
1306 if (termios->c_cflag & PARODD) {
1307 lcr |= UART_LCR_PARITY;
1308 lcr &= ~UART_LCR_EPAR;
1309 lcr &= ~UART_LCR_SPAR;
1310 } else {
1311 lcr |= UART_LCR_PARITY;
1312 lcr |= UART_LCR_EPAR;
1313 lcr &= ~UART_LCR_SPAR;
1314 }
1315 }
1316
1317 lcr &= ~UART_LCR_WLEN8;
1318 switch (termios->c_cflag & CSIZE) {
1319 case CS5:
1320 lcr |= UART_LCR_WLEN5;
1321 symb_bit += 5;
1322 break;
1323 case CS6:
1324 lcr |= UART_LCR_WLEN6;
1325 symb_bit += 6;
1326 break;
1327 case CS7:
1328 lcr |= UART_LCR_WLEN7;
1329 symb_bit += 7;
1330 break;
1331 default:
1332 lcr |= UART_LCR_WLEN8;
1333 symb_bit += 8;
1334 break;
1335 }
1336
1337 /* Stop bits */
1338 if (termios->c_cflag & CSTOPB) {
1339 lcr |= UART_LCR_STOP;
1340 symb_bit += 2;
1341 } else {
1342 lcr &= ~UART_LCR_STOP;
1343 symb_bit++;
1344 }
1345
1346 tegra_uart_write(tup, lcr, UART_LCR);
1347 tup->lcr_shadow = lcr;
1348 tup->symb_bit = symb_bit;
1349
1350 /* Baud rate. */
1351 baud = uart_get_baud_rate(u, termios, oldtermios,
1352 parent_clk_rate/max_divider,
1353 parent_clk_rate/16);
1354 spin_unlock_irqrestore(&u->lock, flags);
1355 ret = tegra_set_baudrate(tup, baud);
1356 if (ret < 0) {
1357 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1358 return;
1359 }
1360 if (tty_termios_baud_rate(termios))
1361 tty_termios_encode_baud_rate(termios, baud, baud);
1362 spin_lock_irqsave(&u->lock, flags);
1363
1364 /* Flow control */
1365 if (termios->c_cflag & CRTSCTS) {
1366 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1367 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1368 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1369 /* if top layer has asked to set rts active then do so here */
1370 if (tup->rts_active)
1371 set_rts(tup, true);
1372 } else {
1373 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1374 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1375 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1376 }
1377
1378 /* update the port timeout based on new settings */
1379 uart_update_timeout(u, termios->c_cflag, baud);
1380
1381 /* Make sure all writes have completed */
1382 tegra_uart_read(tup, UART_IER);
1383
1384 /* Re-enable interrupt */
1385 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1386 tegra_uart_read(tup, UART_IER);
1387
1388 tup->uport.ignore_status_mask = 0;
1389 /* Ignore all characters if CREAD is not set */
1390 if ((termios->c_cflag & CREAD) == 0)
1391 tup->uport.ignore_status_mask |= UART_LSR_DR;
1392 if (termios->c_iflag & IGNBRK)
1393 tup->uport.ignore_status_mask |= UART_LSR_BI;
1394
1395 spin_unlock_irqrestore(&u->lock, flags);
1396 }
1397
1398 static const char *tegra_uart_type(struct uart_port *u)
1399 {
1400 return TEGRA_UART_TYPE;
1401 }
1402
1403 static const struct uart_ops tegra_uart_ops = {
1404 .tx_empty = tegra_uart_tx_empty,
1405 .set_mctrl = tegra_uart_set_mctrl,
1406 .get_mctrl = tegra_uart_get_mctrl,
1407 .stop_tx = tegra_uart_stop_tx,
1408 .start_tx = tegra_uart_start_tx,
1409 .stop_rx = tegra_uart_stop_rx,
1410 .flush_buffer = tegra_uart_flush_buffer,
1411 .enable_ms = tegra_uart_enable_ms,
1412 .break_ctl = tegra_uart_break_ctl,
1413 .startup = tegra_uart_startup,
1414 .shutdown = tegra_uart_shutdown,
1415 .set_termios = tegra_uart_set_termios,
1416 .type = tegra_uart_type,
1417 .request_port = tegra_uart_request_port,
1418 .release_port = tegra_uart_release_port,
1419 };
1420
1421 static struct uart_driver tegra_uart_driver = {
1422 .owner = THIS_MODULE,
1423 .driver_name = "tegra_hsuart",
1424 .dev_name = "ttyTHS",
1425 .cons = NULL,
1426 .nr = TEGRA_UART_MAXIMUM,
1427 };
1428
1429 static int tegra_uart_parse_dt(struct platform_device *pdev,
1430 struct tegra_uart_port *tup)
1431 {
1432 struct device_node *np = pdev->dev.of_node;
1433 int port;
1434 int ret;
1435 int index;
1436 u32 pval;
1437 int count;
1438 int n_entries;
1439
1440 port = of_alias_get_id(np, "serial");
1441 if (port < 0) {
1442 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1443 return port;
1444 }
1445 tup->uport.line = port;
1446
1447 tup->enable_modem_interrupt = of_property_read_bool(np,
1448 "nvidia,enable-modem-interrupt");
1449
1450 index = of_property_match_string(np, "dma-names", "rx");
1451 if (index < 0) {
1452 tup->use_rx_pio = true;
1453 dev_info(&pdev->dev, "RX in PIO mode\n");
1454 }
1455 index = of_property_match_string(np, "dma-names", "tx");
1456 if (index < 0) {
1457 tup->use_tx_pio = true;
1458 dev_info(&pdev->dev, "TX in PIO mode\n");
1459 }
1460
1461 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1462 if (n_entries > 0) {
1463 tup->n_adjustable_baud_rates = n_entries / 3;
1464 tup->baud_tolerance =
1465 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1466 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1467 if (!tup->baud_tolerance)
1468 return -ENOMEM;
1469 for (count = 0, index = 0; count < n_entries; count += 3,
1470 index++) {
1471 ret =
1472 of_property_read_u32_index(np,
1473 "nvidia,adjust-baud-rates",
1474 count, &pval);
1475 if (!ret)
1476 tup->baud_tolerance[index].lower_range_baud =
1477 pval;
1478 ret =
1479 of_property_read_u32_index(np,
1480 "nvidia,adjust-baud-rates",
1481 count + 1, &pval);
1482 if (!ret)
1483 tup->baud_tolerance[index].upper_range_baud =
1484 pval;
1485 ret =
1486 of_property_read_u32_index(np,
1487 "nvidia,adjust-baud-rates",
1488 count + 2, &pval);
1489 if (!ret)
1490 tup->baud_tolerance[index].tolerance =
1491 (s32)pval;
1492 }
1493 } else {
1494 tup->n_adjustable_baud_rates = 0;
1495 }
1496
1497 return 0;
1498 }
1499
1500 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1501 .tx_fifo_full_status = false,
1502 .allow_txfifo_reset_fifo_mode = true,
1503 .support_clk_src_div = false,
1504 .fifo_mode_enable_status = false,
1505 .uart_max_port = 5,
1506 .max_dma_burst_bytes = 4,
1507 .error_tolerance_low_range = 0,
1508 .error_tolerance_high_range = 4,
1509 };
1510
1511 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1512 .tx_fifo_full_status = true,
1513 .allow_txfifo_reset_fifo_mode = false,
1514 .support_clk_src_div = true,
1515 .fifo_mode_enable_status = false,
1516 .uart_max_port = 5,
1517 .max_dma_burst_bytes = 4,
1518 .error_tolerance_low_range = 0,
1519 .error_tolerance_high_range = 4,
1520 };
1521
1522 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1523 .tx_fifo_full_status = true,
1524 .allow_txfifo_reset_fifo_mode = false,
1525 .support_clk_src_div = true,
1526 .fifo_mode_enable_status = true,
1527 .uart_max_port = 8,
1528 .max_dma_burst_bytes = 8,
1529 .error_tolerance_low_range = 0,
1530 .error_tolerance_high_range = 4,
1531 };
1532
1533 static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1534 .tx_fifo_full_status = true,
1535 .allow_txfifo_reset_fifo_mode = false,
1536 .support_clk_src_div = true,
1537 .fifo_mode_enable_status = true,
1538 .uart_max_port = 8,
1539 .max_dma_burst_bytes = 8,
1540 .error_tolerance_low_range = -2,
1541 .error_tolerance_high_range = 2,
1542 };
1543
1544 static const struct of_device_id tegra_uart_of_match[] = {
1545 {
1546 .compatible = "nvidia,tegra30-hsuart",
1547 .data = &tegra30_uart_chip_data,
1548 }, {
1549 .compatible = "nvidia,tegra20-hsuart",
1550 .data = &tegra20_uart_chip_data,
1551 }, {
1552 .compatible = "nvidia,tegra186-hsuart",
1553 .data = &tegra186_uart_chip_data,
1554 }, {
1555 .compatible = "nvidia,tegra194-hsuart",
1556 .data = &tegra194_uart_chip_data,
1557 }, {
1558 },
1559 };
1560 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1561
1562 static int tegra_uart_probe(struct platform_device *pdev)
1563 {
1564 struct tegra_uart_port *tup;
1565 struct uart_port *u;
1566 struct resource *resource;
1567 int ret;
1568 const struct tegra_uart_chip_data *cdata;
1569 const struct of_device_id *match;
1570
1571 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1572 if (!match) {
1573 dev_err(&pdev->dev, "Error: No device match found\n");
1574 return -ENODEV;
1575 }
1576 cdata = match->data;
1577
1578 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1579 if (!tup) {
1580 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1581 return -ENOMEM;
1582 }
1583
1584 ret = tegra_uart_parse_dt(pdev, tup);
1585 if (ret < 0)
1586 return ret;
1587
1588 u = &tup->uport;
1589 u->dev = &pdev->dev;
1590 u->ops = &tegra_uart_ops;
1591 u->type = PORT_TEGRA;
1592 u->fifosize = 32;
1593 tup->cdata = cdata;
1594
1595 platform_set_drvdata(pdev, tup);
1596 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1597 if (!resource) {
1598 dev_err(&pdev->dev, "No IO memory resource\n");
1599 return -ENODEV;
1600 }
1601
1602 u->mapbase = resource->start;
1603 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1604 if (IS_ERR(u->membase))
1605 return PTR_ERR(u->membase);
1606
1607 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1608 if (IS_ERR(tup->uart_clk)) {
1609 dev_err(&pdev->dev, "Couldn't get the clock\n");
1610 return PTR_ERR(tup->uart_clk);
1611 }
1612
1613 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1614 if (IS_ERR(tup->rst)) {
1615 dev_err(&pdev->dev, "Couldn't get the reset\n");
1616 return PTR_ERR(tup->rst);
1617 }
1618
1619 u->iotype = UPIO_MEM32;
1620 ret = platform_get_irq(pdev, 0);
1621 if (ret < 0)
1622 return ret;
1623 u->irq = ret;
1624 u->regshift = 2;
1625 ret = uart_add_one_port(&tegra_uart_driver, u);
1626 if (ret < 0) {
1627 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1628 return ret;
1629 }
1630 return ret;
1631 }
1632
1633 static int tegra_uart_remove(struct platform_device *pdev)
1634 {
1635 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1636 struct uart_port *u = &tup->uport;
1637
1638 uart_remove_one_port(&tegra_uart_driver, u);
1639 return 0;
1640 }
1641
1642 #ifdef CONFIG_PM_SLEEP
1643 static int tegra_uart_suspend(struct device *dev)
1644 {
1645 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1646 struct uart_port *u = &tup->uport;
1647
1648 return uart_suspend_port(&tegra_uart_driver, u);
1649 }
1650
1651 static int tegra_uart_resume(struct device *dev)
1652 {
1653 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1654 struct uart_port *u = &tup->uport;
1655
1656 return uart_resume_port(&tegra_uart_driver, u);
1657 }
1658 #endif
1659
1660 static const struct dev_pm_ops tegra_uart_pm_ops = {
1661 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1662 };
1663
1664 static struct platform_driver tegra_uart_platform_driver = {
1665 .probe = tegra_uart_probe,
1666 .remove = tegra_uart_remove,
1667 .driver = {
1668 .name = "serial-tegra",
1669 .of_match_table = tegra_uart_of_match,
1670 .pm = &tegra_uart_pm_ops,
1671 },
1672 };
1673
1674 static int __init tegra_uart_init(void)
1675 {
1676 int ret;
1677 struct device_node *node;
1678 const struct of_device_id *match = NULL;
1679 const struct tegra_uart_chip_data *cdata = NULL;
1680
1681 node = of_find_matching_node(NULL, tegra_uart_of_match);
1682 if (node)
1683 match = of_match_node(tegra_uart_of_match, node);
1684 if (match)
1685 cdata = match->data;
1686 if (cdata)
1687 tegra_uart_driver.nr = cdata->uart_max_port;
1688
1689 ret = uart_register_driver(&tegra_uart_driver);
1690 if (ret < 0) {
1691 pr_err("Could not register %s driver\n",
1692 tegra_uart_driver.driver_name);
1693 return ret;
1694 }
1695
1696 ret = platform_driver_register(&tegra_uart_platform_driver);
1697 if (ret < 0) {
1698 pr_err("Uart platform driver register failed, e = %d\n", ret);
1699 uart_unregister_driver(&tegra_uart_driver);
1700 return ret;
1701 }
1702 return 0;
1703 }
1704
1705 static void __exit tegra_uart_exit(void)
1706 {
1707 pr_info("Unloading tegra uart driver\n");
1708 platform_driver_unregister(&tegra_uart_platform_driver);
1709 uart_unregister_driver(&tegra_uart_driver);
1710 }
1711
1712 module_init(tegra_uart_init);
1713 module_exit(tegra_uart_exit);
1714
1715 MODULE_ALIAS("platform:serial-tegra");
1716 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1717 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1718 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support