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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / vfio / pci / vfio_pci_config.c
bloba402adee8a215585bbbb4045b139d37350571b51
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * VFIO PCI config space virtualization
4 *
5 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
6 * Author: Alex Williamson <alex.williamson@redhat.com>
7 *
8 * Derived from original vfio:
9 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
10 * Author: Tom Lyon, pugs@cisco.com
11 */
12
13 /*
14 * This code handles reading and writing of PCI configuration registers.
15 * This is hairy because we want to allow a lot of flexibility to the
16 * user driver, but cannot trust it with all of the config fields.
17 * Tables determine which fields can be read and written, as well as
18 * which fields are 'virtualized' - special actions and translations to
19 * make it appear to the user that he has control, when in fact things
20 * must be negotiated with the underlying OS.
21 */
22
23 #include <linux/fs.h>
24 #include <linux/pci.h>
25 #include <linux/uaccess.h>
26 #include <linux/vfio.h>
27 #include <linux/slab.h>
28
29 #include "vfio_pci_private.h"
30
31 /* Fake capability ID for standard config space */
32 #define PCI_CAP_ID_BASIC 0
33
34 #define is_bar(offset) \
35 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
36 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
37
38 /*
39 * Lengths of PCI Config Capabilities
40 * 0: Removed from the user visible capability list
41 * FF: Variable length
42 */
43 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
44 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */
45 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF,
46 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF,
47 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF,
48 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */
49 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */
50 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */
51 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */
52 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */
53 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */
54 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */
55 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */
57 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */
58 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */
59 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */
60 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */
61 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF,
62 [PCI_CAP_ID_SATA] = 0xFF,
63 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF,
64 };
65
66 /*
67 * Lengths of PCIe/PCI-X Extended Config Capabilities
68 * 0: Removed or masked from the user visible capability list
69 * FF: Variable length
70 */
71 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
72 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND,
73 [PCI_EXT_CAP_ID_VC] = 0xFF,
74 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF,
75 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF,
76 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */
77 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */
78 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */
79 [PCI_EXT_CAP_ID_MFVC] = 0xFF,
80 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */
81 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_VNDR] = 0xFF,
83 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */
84 [PCI_EXT_CAP_ID_ACS] = 0xFF,
85 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF,
86 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF,
87 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF,
88 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */
89 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
90 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF,
91 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */
92 [PCI_EXT_CAP_ID_REBAR] = 0xFF,
93 [PCI_EXT_CAP_ID_DPA] = 0xFF,
94 [PCI_EXT_CAP_ID_TPH] = 0xFF,
95 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF,
96 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */
99 };
100
101 /*
102 * Read/Write Permission Bits - one bit for each bit in capability
103 * Any field can be read if it exists, but what is read depends on
104 * whether the field is 'virtualized', or just pass thru to the
105 * hardware. Any virtualized field is also virtualized for writes.
106 * Writes are only permitted if they have a 1 bit here.
107 */
108 struct perm_bits {
109 u8 *virt; /* read/write virtual data, not hw */
110 u8 *write; /* writeable bits */
111 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count,
112 struct perm_bits *perm, int offset, __le32 *val);
113 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count,
114 struct perm_bits *perm, int offset, __le32 val);
115 };
116
117 #define NO_VIRT 0
118 #define ALL_VIRT 0xFFFFFFFFU
119 #define NO_WRITE 0
120 #define ALL_WRITE 0xFFFFFFFFU
121
122 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
123 __le32 *val, int count)
124 {
125 int ret = -EINVAL;
126 u32 tmp_val = 0;
127
128 switch (count) {
129 case 1:
130 {
131 u8 tmp;
132 ret = pci_user_read_config_byte(pdev, offset, &tmp);
133 tmp_val = tmp;
134 break;
135 }
136 case 2:
137 {
138 u16 tmp;
139 ret = pci_user_read_config_word(pdev, offset, &tmp);
140 tmp_val = tmp;
141 break;
142 }
143 case 4:
144 ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
145 break;
146 }
147
148 *val = cpu_to_le32(tmp_val);
149
150 return ret;
151 }
152
153 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
154 __le32 val, int count)
155 {
156 int ret = -EINVAL;
157 u32 tmp_val = le32_to_cpu(val);
158
159 switch (count) {
160 case 1:
161 ret = pci_user_write_config_byte(pdev, offset, tmp_val);
162 break;
163 case 2:
164 ret = pci_user_write_config_word(pdev, offset, tmp_val);
165 break;
166 case 4:
167 ret = pci_user_write_config_dword(pdev, offset, tmp_val);
168 break;
169 }
170
171 return ret;
172 }
173
174 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
175 int count, struct perm_bits *perm,
176 int offset, __le32 *val)
177 {
178 __le32 virt = 0;
179
180 memcpy(val, vdev->vconfig + pos, count);
181
182 memcpy(&virt, perm->virt + offset, count);
183
184 /* Any non-virtualized bits? */
185 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
186 struct pci_dev *pdev = vdev->pdev;
187 __le32 phys_val = 0;
188 int ret;
189
190 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
191 if (ret)
192 return ret;
193
194 *val = (phys_val & ~virt) | (*val & virt);
195 }
196
197 return count;
198 }
199
200 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
201 int count, struct perm_bits *perm,
202 int offset, __le32 val)
203 {
204 __le32 virt = 0, write = 0;
205
206 memcpy(&write, perm->write + offset, count);
207
208 if (!write)
209 return count; /* drop, no writable bits */
210
211 memcpy(&virt, perm->virt + offset, count);
212
213 /* Virtualized and writable bits go to vconfig */
214 if (write & virt) {
215 __le32 virt_val = 0;
216
217 memcpy(&virt_val, vdev->vconfig + pos, count);
218
219 virt_val &= ~(write & virt);
220 virt_val |= (val & (write & virt));
221
222 memcpy(vdev->vconfig + pos, &virt_val, count);
223 }
224
225 /* Non-virtualzed and writable bits go to hardware */
226 if (write & ~virt) {
227 struct pci_dev *pdev = vdev->pdev;
228 __le32 phys_val = 0;
229 int ret;
230
231 ret = vfio_user_config_read(pdev, pos, &phys_val, count);
232 if (ret)
233 return ret;
234
235 phys_val &= ~(write & ~virt);
236 phys_val |= (val & (write & ~virt));
237
238 ret = vfio_user_config_write(pdev, pos, phys_val, count);
239 if (ret)
240 return ret;
241 }
242
243 return count;
244 }
245
246 /* Allow direct read from hardware, except for capability next pointer */
247 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
248 int count, struct perm_bits *perm,
249 int offset, __le32 *val)
250 {
251 int ret;
252
253 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
254 if (ret)
255 return ret;
256
257 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
258 if (offset < 4)
259 memcpy(val, vdev->vconfig + pos, count);
260 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
261 if (offset == PCI_CAP_LIST_ID && count > 1)
262 memcpy(val, vdev->vconfig + pos,
263 min(PCI_CAP_FLAGS, count));
264 else if (offset == PCI_CAP_LIST_NEXT)
265 memcpy(val, vdev->vconfig + pos, 1);
266 }
267
268 return count;
269 }
270
271 /* Raw access skips any kind of virtualization */
272 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
273 int count, struct perm_bits *perm,
274 int offset, __le32 val)
275 {
276 int ret;
277
278 ret = vfio_user_config_write(vdev->pdev, pos, val, count);
279 if (ret)
280 return ret;
281
282 return count;
283 }
284
285 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
286 int count, struct perm_bits *perm,
287 int offset, __le32 *val)
288 {
289 int ret;
290
291 ret = vfio_user_config_read(vdev->pdev, pos, val, count);
292 if (ret)
293 return ret;
294
295 return count;
296 }
297
298 /* Virt access uses only virtualization */
299 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
300 int count, struct perm_bits *perm,
301 int offset, __le32 val)
302 {
303 memcpy(vdev->vconfig + pos, &val, count);
304 return count;
305 }
306
307 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
308 int count, struct perm_bits *perm,
309 int offset, __le32 *val)
310 {
311 memcpy(val, vdev->vconfig + pos, count);
312 return count;
313 }
314
315 /* Default capability regions to read-only, no-virtualization */
316 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
317 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
318 };
319 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
320 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
321 };
322 /*
323 * Default unassigned regions to raw read-write access. Some devices
324 * require this to function as they hide registers between the gaps in
325 * config space (be2net). Like MMIO and I/O port registers, we have
326 * to trust the hardware isolation.
327 */
328 static struct perm_bits unassigned_perms = {
329 .readfn = vfio_raw_config_read,
330 .writefn = vfio_raw_config_write
331 };
332
333 static struct perm_bits virt_perms = {
334 .readfn = vfio_virt_config_read,
335 .writefn = vfio_virt_config_write
336 };
337
338 static void free_perm_bits(struct perm_bits *perm)
339 {
340 kfree(perm->virt);
341 kfree(perm->write);
342 perm->virt = NULL;
343 perm->write = NULL;
344 }
345
346 static int alloc_perm_bits(struct perm_bits *perm, int size)
347 {
348 /*
349 * Round up all permission bits to the next dword, this lets us
350 * ignore whether a read/write exceeds the defined capability
351 * structure. We can do this because:
352 * - Standard config space is already dword aligned
353 * - Capabilities are all dword aligned (bits 0:1 of next reserved)
354 * - Express capabilities defined as dword aligned
355 */
356 size = round_up(size, 4);
357
358 /*
359 * Zero state is
360 * - All Readable, None Writeable, None Virtualized
361 */
362 perm->virt = kzalloc(size, GFP_KERNEL);
363 perm->write = kzalloc(size, GFP_KERNEL);
364 if (!perm->virt || !perm->write) {
365 free_perm_bits(perm);
366 return -ENOMEM;
367 }
368
369 perm->readfn = vfio_default_config_read;
370 perm->writefn = vfio_default_config_write;
371
372 return 0;
373 }
374
375 /*
376 * Helper functions for filling in permission tables
377 */
378 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
379 {
380 p->virt[off] = virt;
381 p->write[off] = write;
382 }
383
384 /* Handle endian-ness - pci and tables are little-endian */
385 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
386 {
387 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
388 *(__le16 *)(&p->write[off]) = cpu_to_le16(write);
389 }
390
391 /* Handle endian-ness - pci and tables are little-endian */
392 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
393 {
394 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
395 *(__le32 *)(&p->write[off]) = cpu_to_le32(write);
396 }
397
398 /* Caller should hold memory_lock semaphore */
399 bool __vfio_pci_memory_enabled(struct vfio_pci_device *vdev)
400 {
401 struct pci_dev *pdev = vdev->pdev;
402 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
403
404 /*
405 * SR-IOV VF memory enable is handled by the MSE bit in the
406 * PF SR-IOV capability, there's therefore no need to trigger
407 * faults based on the virtual value.
408 */
409 return pdev->no_command_memory || (cmd & PCI_COMMAND_MEMORY);
410 }
411
412 /*
413 * Restore the *real* BARs after we detect a FLR or backdoor reset.
414 * (backdoor = some device specific technique that we didn't catch)
415 */
416 static void vfio_bar_restore(struct vfio_pci_device *vdev)
417 {
418 struct pci_dev *pdev = vdev->pdev;
419 u32 *rbar = vdev->rbar;
420 u16 cmd;
421 int i;
422
423 if (pdev->is_virtfn)
424 return;
425
426 pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__);
427
428 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
429 pci_user_write_config_dword(pdev, i, *rbar);
430
431 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
432
433 if (vdev->nointx) {
434 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
435 cmd |= PCI_COMMAND_INTX_DISABLE;
436 pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
437 }
438 }
439
440 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
441 {
442 unsigned long flags = pci_resource_flags(pdev, bar);
443 u32 val;
444
445 if (flags & IORESOURCE_IO)
446 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
447
448 val = PCI_BASE_ADDRESS_SPACE_MEMORY;
449
450 if (flags & IORESOURCE_PREFETCH)
451 val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
452
453 if (flags & IORESOURCE_MEM_64)
454 val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
455
456 return cpu_to_le32(val);
457 }
458
459 /*
460 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
461 * to reflect the hardware capabilities. This implements BAR sizing.
462 */
463 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
464 {
465 struct pci_dev *pdev = vdev->pdev;
466 int i;
467 __le32 *vbar;
468 u64 mask;
469
470 if (!vdev->bardirty)
471 return;
472
473 vbar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
474
475 for (i = 0; i < PCI_STD_NUM_BARS; i++, vbar++) {
476 int bar = i + PCI_STD_RESOURCES;
477
478 if (!pci_resource_start(pdev, bar)) {
479 *vbar = 0; /* Unmapped by host = unimplemented to user */
480 continue;
481 }
482
483 mask = ~(pci_resource_len(pdev, bar) - 1);
484
485 *vbar &= cpu_to_le32((u32)mask);
486 *vbar |= vfio_generate_bar_flags(pdev, bar);
487
488 if (*vbar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
489 vbar++;
490 *vbar &= cpu_to_le32((u32)(mask >> 32));
491 i++;
492 }
493 }
494
495 vbar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
496
497 /*
498 * NB. REGION_INFO will have reported zero size if we weren't able
499 * to read the ROM, but we still return the actual BAR size here if
500 * it exists (or the shadow ROM space).
501 */
502 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
503 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
504 mask |= PCI_ROM_ADDRESS_ENABLE;
505 *vbar &= cpu_to_le32((u32)mask);
506 } else if (pdev->resource[PCI_ROM_RESOURCE].flags &
507 IORESOURCE_ROM_SHADOW) {
508 mask = ~(0x20000 - 1);
509 mask |= PCI_ROM_ADDRESS_ENABLE;
510 *vbar &= cpu_to_le32((u32)mask);
511 } else
512 *vbar = 0;
513
514 vdev->bardirty = false;
515 }
516
517 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
518 int count, struct perm_bits *perm,
519 int offset, __le32 *val)
520 {
521 if (is_bar(offset)) /* pos == offset for basic config */
522 vfio_bar_fixup(vdev);
523
524 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
525
526 /* Mask in virtual memory enable */
527 if (offset == PCI_COMMAND && vdev->pdev->no_command_memory) {
528 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
529 u32 tmp_val = le32_to_cpu(*val);
530
531 tmp_val |= cmd & PCI_COMMAND_MEMORY;
532 *val = cpu_to_le32(tmp_val);
533 }
534
535 return count;
536 }
537
538 /* Test whether BARs match the value we think they should contain */
539 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
540 {
541 int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
542 u32 bar;
543
544 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
545 if (vdev->rbar[i]) {
546 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
547 if (ret || vdev->rbar[i] != bar)
548 return true;
549 }
550 }
551
552 return false;
553 }
554
555 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
556 int count, struct perm_bits *perm,
557 int offset, __le32 val)
558 {
559 struct pci_dev *pdev = vdev->pdev;
560 __le16 *virt_cmd;
561 u16 new_cmd = 0;
562 int ret;
563
564 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
565
566 if (offset == PCI_COMMAND) {
567 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
568 u16 phys_cmd;
569
570 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
571 if (ret)
572 return ret;
573
574 new_cmd = le32_to_cpu(val);
575
576 phys_io = !!(phys_cmd & PCI_COMMAND_IO);
577 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
578 new_io = !!(new_cmd & PCI_COMMAND_IO);
579
580 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
581 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
582 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
583
584 if (!new_mem)
585 vfio_pci_zap_and_down_write_memory_lock(vdev);
586 else
587 down_write(&vdev->memory_lock);
588
589 /*
590 * If the user is writing mem/io enable (new_mem/io) and we
591 * think it's already enabled (virt_mem/io), but the hardware
592 * shows it disabled (phys_mem/io, then the device has
593 * undergone some kind of backdoor reset and needs to be
594 * restored before we allow it to enable the bars.
595 * SR-IOV devices will trigger this - for mem enable let's
596 * catch this now and for io enable it will be caught later
597 */
598 if ((new_mem && virt_mem && !phys_mem &&
599 !pdev->no_command_memory) ||
600 (new_io && virt_io && !phys_io) ||
601 vfio_need_bar_restore(vdev))
602 vfio_bar_restore(vdev);
603 }
604
605 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
606 if (count < 0) {
607 if (offset == PCI_COMMAND)
608 up_write(&vdev->memory_lock);
609 return count;
610 }
611
612 /*
613 * Save current memory/io enable bits in vconfig to allow for
614 * the test above next time.
615 */
616 if (offset == PCI_COMMAND) {
617 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
618
619 *virt_cmd &= cpu_to_le16(~mask);
620 *virt_cmd |= cpu_to_le16(new_cmd & mask);
621
622 up_write(&vdev->memory_lock);
623 }
624
625 /* Emulate INTx disable */
626 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
627 bool virt_intx_disable;
628
629 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
630 PCI_COMMAND_INTX_DISABLE);
631
632 if (virt_intx_disable && !vdev->virq_disabled) {
633 vdev->virq_disabled = true;
634 vfio_pci_intx_mask(vdev);
635 } else if (!virt_intx_disable && vdev->virq_disabled) {
636 vdev->virq_disabled = false;
637 vfio_pci_intx_unmask(vdev);
638 }
639 }
640
641 if (is_bar(offset))
642 vdev->bardirty = true;
643
644 return count;
645 }
646
647 /* Permissions for the Basic PCI Header */
648 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
649 {
650 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
651 return -ENOMEM;
652
653 perm->readfn = vfio_basic_config_read;
654 perm->writefn = vfio_basic_config_write;
655
656 /* Virtualized for SR-IOV functions, which just have FFFF */
657 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
658 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
659
660 /*
661 * Virtualize INTx disable, we use it internally for interrupt
662 * control and can emulate it for non-PCI 2.3 devices.
663 */
664 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
665
666 /* Virtualize capability list, we might want to skip/disable */
667 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
668
669 /* No harm to write */
670 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
671 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
672 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
673
674 /* Virtualize all bars, can't touch the real ones */
675 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
676 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
677 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
678 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
679 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
680 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
681 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
682
683 /* Allow us to adjust capability chain */
684 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
685
686 /* Sometimes used by sw, just virtualize */
687 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
688
689 /* Virtualize interrupt pin to allow hiding INTx */
690 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
691
692 return 0;
693 }
694
695 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
696 int count, struct perm_bits *perm,
697 int offset, __le32 val)
698 {
699 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
700 if (count < 0)
701 return count;
702
703 if (offset == PCI_PM_CTRL) {
704 pci_power_t state;
705
706 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
707 case 0:
708 state = PCI_D0;
709 break;
710 case 1:
711 state = PCI_D1;
712 break;
713 case 2:
714 state = PCI_D2;
715 break;
716 case 3:
717 state = PCI_D3hot;
718 break;
719 }
720
721 vfio_pci_set_power_state(vdev, state);
722 }
723
724 return count;
725 }
726
727 /* Permissions for the Power Management capability */
728 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
729 {
730 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
731 return -ENOMEM;
732
733 perm->writefn = vfio_pm_config_write;
734
735 /*
736 * We always virtualize the next field so we can remove
737 * capabilities from the chain if we want to.
738 */
739 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
740
741 /*
742 * Power management is defined *per function*, so we can let
743 * the user change power state, but we trap and initiate the
744 * change ourselves, so the state bits are read-only.
745 */
746 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
747 return 0;
748 }
749
750 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
751 int count, struct perm_bits *perm,
752 int offset, __le32 val)
753 {
754 struct pci_dev *pdev = vdev->pdev;
755 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
756 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
757 u16 addr;
758 u32 data;
759
760 /*
761 * Write through to emulation. If the write includes the upper byte
762 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
763 * have work to do.
764 */
765 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
766 if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
767 offset + count <= PCI_VPD_ADDR + 1)
768 return count;
769
770 addr = le16_to_cpu(*paddr);
771
772 if (addr & PCI_VPD_ADDR_F) {
773 data = le32_to_cpu(*pdata);
774 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
775 return count;
776 } else {
777 data = 0;
778 if (pci_read_vpd(pdev, addr, 4, &data) < 0)
779 return count;
780 *pdata = cpu_to_le32(data);
781 }
782
783 /*
784 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
785 * signal completion. If an error occurs above, we assume that not
786 * toggling this bit will induce a driver timeout.
787 */
788 addr ^= PCI_VPD_ADDR_F;
789 *paddr = cpu_to_le16(addr);
790
791 return count;
792 }
793
794 /* Permissions for Vital Product Data capability */
795 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
796 {
797 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
798 return -ENOMEM;
799
800 perm->writefn = vfio_vpd_config_write;
801
802 /*
803 * We always virtualize the next field so we can remove
804 * capabilities from the chain if we want to.
805 */
806 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
807
808 /*
809 * Both the address and data registers are virtualized to
810 * enable access through the pci_vpd_read/write functions
811 */
812 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
813 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
814
815 return 0;
816 }
817
818 /* Permissions for PCI-X capability */
819 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
820 {
821 /* Alloc 24, but only 8 are used in v0 */
822 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
823 return -ENOMEM;
824
825 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
826
827 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
828 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
829 return 0;
830 }
831
832 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
833 int count, struct perm_bits *perm,
834 int offset, __le32 val)
835 {
836 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
837 offset + PCI_EXP_DEVCTL);
838 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ;
839
840 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
841 if (count < 0)
842 return count;
843
844 /*
845 * The FLR bit is virtualized, if set and the device supports PCIe
846 * FLR, issue a reset_function. Regardless, clear the bit, the spec
847 * requires it to be always read as zero. NB, reset_function might
848 * not use a PCIe FLR, we don't have that level of granularity.
849 */
850 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
851 u32 cap;
852 int ret;
853
854 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
855
856 ret = pci_user_read_config_dword(vdev->pdev,
857 pos - offset + PCI_EXP_DEVCAP,
858 &cap);
859
860 if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) {
861 vfio_pci_zap_and_down_write_memory_lock(vdev);
862 pci_try_reset_function(vdev->pdev);
863 up_write(&vdev->memory_lock);
864 }
865 }
866
867 /*
868 * MPS is virtualized to the user, writes do not change the physical
869 * register since determining a proper MPS value requires a system wide
870 * device view. The MRRS is largely independent of MPS, but since the
871 * user does not have that system-wide view, they might set a safe, but
872 * inefficiently low value. Here we allow writes through to hardware,
873 * but we set the floor to the physical device MPS setting, so that
874 * we can at least use full TLPs, as defined by the MPS value.
875 *
876 * NB, if any devices actually depend on an artificially low MRRS
877 * setting, this will need to be revisited, perhaps with a quirk
878 * though pcie_set_readrq().
879 */
880 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) {
881 readrq = 128 <<
882 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12);
883 readrq = max(readrq, pcie_get_mps(vdev->pdev));
884
885 pcie_set_readrq(vdev->pdev, readrq);
886 }
887
888 return count;
889 }
890
891 /* Permissions for PCI Express capability */
892 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
893 {
894 /* Alloc largest of possible sizes */
895 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
896 return -ENOMEM;
897
898 perm->writefn = vfio_exp_config_write;
899
900 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
901
902 /*
903 * Allow writes to device control fields, except devctl_phantom,
904 * which could confuse IOMMU, MPS, which can break communication
905 * with other physical devices, and the ARI bit in devctl2, which
906 * is set at probe time. FLR and MRRS get virtualized via our
907 * writefn.
908 */
909 p_setw(perm, PCI_EXP_DEVCTL,
910 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD |
911 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM);
912 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
913 return 0;
914 }
915
916 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
917 int count, struct perm_bits *perm,
918 int offset, __le32 val)
919 {
920 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
921
922 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
923 if (count < 0)
924 return count;
925
926 /*
927 * The FLR bit is virtualized, if set and the device supports AF
928 * FLR, issue a reset_function. Regardless, clear the bit, the spec
929 * requires it to be always read as zero. NB, reset_function might
930 * not use an AF FLR, we don't have that level of granularity.
931 */
932 if (*ctrl & PCI_AF_CTRL_FLR) {
933 u8 cap;
934 int ret;
935
936 *ctrl &= ~PCI_AF_CTRL_FLR;
937
938 ret = pci_user_read_config_byte(vdev->pdev,
939 pos - offset + PCI_AF_CAP,
940 &cap);
941
942 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) {
943 vfio_pci_zap_and_down_write_memory_lock(vdev);
944 pci_try_reset_function(vdev->pdev);
945 up_write(&vdev->memory_lock);
946 }
947 }
948
949 return count;
950 }
951
952 /* Permissions for Advanced Function capability */
953 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
954 {
955 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
956 return -ENOMEM;
957
958 perm->writefn = vfio_af_config_write;
959
960 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
961 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
962 return 0;
963 }
964
965 /* Permissions for Advanced Error Reporting extended capability */
966 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
967 {
968 u32 mask;
969
970 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
971 return -ENOMEM;
972
973 /*
974 * Virtualize the first dword of all express capabilities
975 * because it includes the next pointer. This lets us later
976 * remove capabilities from the chain if we need to.
977 */
978 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
979
980 /* Writable bits mask */
981 mask = PCI_ERR_UNC_UND | /* Undefined */
982 PCI_ERR_UNC_DLP | /* Data Link Protocol */
983 PCI_ERR_UNC_SURPDN | /* Surprise Down */
984 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
985 PCI_ERR_UNC_FCP | /* Flow Control Protocol */
986 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */
987 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */
988 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */
989 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */
990 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */
991 PCI_ERR_UNC_ECRC | /* ECRC Error Status */
992 PCI_ERR_UNC_UNSUP | /* Unsupported Request */
993 PCI_ERR_UNC_ACSV | /* ACS Violation */
994 PCI_ERR_UNC_INTN | /* internal error */
995 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */
996 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */
997 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */
998 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
999 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
1000 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
1001
1002 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */
1003 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */
1004 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */
1005 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */
1006 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */
1007 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */
1008 PCI_ERR_COR_INTERNAL | /* Corrected Internal */
1009 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */
1010 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
1011 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
1012
1013 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */
1014 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */
1015 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
1016 return 0;
1017 }
1018
1019 /* Permissions for Power Budgeting extended capability */
1020 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
1021 {
1022 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
1023 return -ENOMEM;
1024
1025 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1026
1027 /* Writing the data selector is OK, the info is still read-only */
1028 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
1029 return 0;
1030 }
1031
1032 /*
1033 * Initialize the shared permission tables
1034 */
1035 void vfio_pci_uninit_perm_bits(void)
1036 {
1037 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
1038
1039 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
1040 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
1041 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
1042 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
1043 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
1044
1045 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1046 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1047 }
1048
1049 int __init vfio_pci_init_perm_bits(void)
1050 {
1051 int ret;
1052
1053 /* Basic config space */
1054 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
1055
1056 /* Capabilities */
1057 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1058 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1059 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1060 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1061 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1062 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1063
1064 /* Extended capabilities */
1065 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1066 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1067 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1068
1069 if (ret)
1070 vfio_pci_uninit_perm_bits();
1071
1072 return ret;
1073 }
1074
1075 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1076 {
1077 u8 cap;
1078 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1079 PCI_STD_HEADER_SIZEOF;
1080 cap = vdev->pci_config_map[pos];
1081
1082 if (cap == PCI_CAP_ID_BASIC)
1083 return 0;
1084
1085 /* XXX Can we have to abutting capabilities of the same type? */
1086 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1087 pos--;
1088
1089 return pos;
1090 }
1091
1092 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1093 int count, struct perm_bits *perm,
1094 int offset, __le32 *val)
1095 {
1096 /* Update max available queue size from msi_qmax */
1097 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1098 __le16 *flags;
1099 int start;
1100
1101 start = vfio_find_cap_start(vdev, pos);
1102
1103 flags = (__le16 *)&vdev->vconfig[start];
1104
1105 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1106 *flags |= cpu_to_le16(vdev->msi_qmax << 1);
1107 }
1108
1109 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1110 }
1111
1112 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1113 int count, struct perm_bits *perm,
1114 int offset, __le32 val)
1115 {
1116 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1117 if (count < 0)
1118 return count;
1119
1120 /* Fixup and write configured queue size and enable to hardware */
1121 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1122 __le16 *pflags;
1123 u16 flags;
1124 int start, ret;
1125
1126 start = vfio_find_cap_start(vdev, pos);
1127
1128 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1129
1130 flags = le16_to_cpu(*pflags);
1131
1132 /* MSI is enabled via ioctl */
1133 if (!is_msi(vdev))
1134 flags &= ~PCI_MSI_FLAGS_ENABLE;
1135
1136 /* Check queue size */
1137 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1138 flags &= ~PCI_MSI_FLAGS_QSIZE;
1139 flags |= vdev->msi_qmax << 4;
1140 }
1141
1142 /* Write back to virt and to hardware */
1143 *pflags = cpu_to_le16(flags);
1144 ret = pci_user_write_config_word(vdev->pdev,
1145 start + PCI_MSI_FLAGS,
1146 flags);
1147 if (ret)
1148 return ret;
1149 }
1150
1151 return count;
1152 }
1153
1154 /*
1155 * MSI determination is per-device, so this routine gets used beyond
1156 * initialization time. Don't add __init
1157 */
1158 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1159 {
1160 if (alloc_perm_bits(perm, len))
1161 return -ENOMEM;
1162
1163 perm->readfn = vfio_msi_config_read;
1164 perm->writefn = vfio_msi_config_write;
1165
1166 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1167
1168 /*
1169 * The upper byte of the control register is reserved,
1170 * just setup the lower byte.
1171 */
1172 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1173 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1174 if (flags & PCI_MSI_FLAGS_64BIT) {
1175 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1176 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1177 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1178 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1179 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1180 }
1181 } else {
1182 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1183 if (flags & PCI_MSI_FLAGS_MASKBIT) {
1184 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1185 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1186 }
1187 }
1188 return 0;
1189 }
1190
1191 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1192 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1193 {
1194 struct pci_dev *pdev = vdev->pdev;
1195 int len, ret;
1196 u16 flags;
1197
1198 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1199 if (ret)
1200 return pcibios_err_to_errno(ret);
1201
1202 len = 10; /* Minimum size */
1203 if (flags & PCI_MSI_FLAGS_64BIT)
1204 len += 4;
1205 if (flags & PCI_MSI_FLAGS_MASKBIT)
1206 len += 10;
1207
1208 if (vdev->msi_perm)
1209 return len;
1210
1211 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1212 if (!vdev->msi_perm)
1213 return -ENOMEM;
1214
1215 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1216 if (ret) {
1217 kfree(vdev->msi_perm);
1218 return ret;
1219 }
1220
1221 return len;
1222 }
1223
1224 /* Determine extended capability length for VC (2 & 9) and MFVC */
1225 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1226 {
1227 struct pci_dev *pdev = vdev->pdev;
1228 u32 tmp;
1229 int ret, evcc, phases, vc_arb;
1230 int len = PCI_CAP_VC_BASE_SIZEOF;
1231
1232 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1233 if (ret)
1234 return pcibios_err_to_errno(ret);
1235
1236 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1237 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1238 if (ret)
1239 return pcibios_err_to_errno(ret);
1240
1241 if (tmp & PCI_VC_CAP2_128_PHASE)
1242 phases = 128;
1243 else if (tmp & PCI_VC_CAP2_64_PHASE)
1244 phases = 64;
1245 else if (tmp & PCI_VC_CAP2_32_PHASE)
1246 phases = 32;
1247 else
1248 phases = 0;
1249
1250 vc_arb = phases * 4;
1251
1252 /*
1253 * Port arbitration tables are root & switch only;
1254 * function arbitration tables are function 0 only.
1255 * In either case, we'll never let user write them so
1256 * we don't care how big they are
1257 */
1258 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1259 if (vc_arb) {
1260 len = round_up(len, 16);
1261 len += vc_arb / 8;
1262 }
1263 return len;
1264 }
1265
1266 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1267 {
1268 struct pci_dev *pdev = vdev->pdev;
1269 u32 dword;
1270 u16 word;
1271 u8 byte;
1272 int ret;
1273
1274 switch (cap) {
1275 case PCI_CAP_ID_MSI:
1276 return vfio_msi_cap_len(vdev, pos);
1277 case PCI_CAP_ID_PCIX:
1278 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1279 if (ret)
1280 return pcibios_err_to_errno(ret);
1281
1282 if (PCI_X_CMD_VERSION(word)) {
1283 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1284 /* Test for extended capabilities */
1285 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1286 &dword);
1287 vdev->extended_caps = (dword != 0);
1288 }
1289 return PCI_CAP_PCIX_SIZEOF_V2;
1290 } else
1291 return PCI_CAP_PCIX_SIZEOF_V0;
1292 case PCI_CAP_ID_VNDR:
1293 /* length follows next field */
1294 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1295 if (ret)
1296 return pcibios_err_to_errno(ret);
1297
1298 return byte;
1299 case PCI_CAP_ID_EXP:
1300 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1301 /* Test for extended capabilities */
1302 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1303 vdev->extended_caps = (dword != 0);
1304 }
1305
1306 /* length based on version and type */
1307 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
1308 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1309 return 0xc; /* "All Devices" only, no link */
1310 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1311 } else {
1312 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1313 return 0x2c; /* No link */
1314 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1315 }
1316 case PCI_CAP_ID_HT:
1317 ret = pci_read_config_byte(pdev, pos + 3, &byte);
1318 if (ret)
1319 return pcibios_err_to_errno(ret);
1320
1321 return (byte & HT_3BIT_CAP_MASK) ?
1322 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1323 case PCI_CAP_ID_SATA:
1324 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1325 if (ret)
1326 return pcibios_err_to_errno(ret);
1327
1328 byte &= PCI_SATA_REGS_MASK;
1329 if (byte == PCI_SATA_REGS_INLINE)
1330 return PCI_SATA_SIZEOF_LONG;
1331 else
1332 return PCI_SATA_SIZEOF_SHORT;
1333 default:
1334 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n",
1335 __func__, cap, pos);
1336 }
1337
1338 return 0;
1339 }
1340
1341 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1342 {
1343 struct pci_dev *pdev = vdev->pdev;
1344 u8 byte;
1345 u32 dword;
1346 int ret;
1347
1348 switch (ecap) {
1349 case PCI_EXT_CAP_ID_VNDR:
1350 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1351 if (ret)
1352 return pcibios_err_to_errno(ret);
1353
1354 return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1355 case PCI_EXT_CAP_ID_VC:
1356 case PCI_EXT_CAP_ID_VC9:
1357 case PCI_EXT_CAP_ID_MFVC:
1358 return vfio_vc_cap_len(vdev, epos);
1359 case PCI_EXT_CAP_ID_ACS:
1360 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1361 if (ret)
1362 return pcibios_err_to_errno(ret);
1363
1364 if (byte & PCI_ACS_EC) {
1365 int bits;
1366
1367 ret = pci_read_config_byte(pdev,
1368 epos + PCI_ACS_EGRESS_BITS,
1369 &byte);
1370 if (ret)
1371 return pcibios_err_to_errno(ret);
1372
1373 bits = byte ? round_up(byte, 32) : 256;
1374 return 8 + (bits / 8);
1375 }
1376 return 8;
1377
1378 case PCI_EXT_CAP_ID_REBAR:
1379 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1380 if (ret)
1381 return pcibios_err_to_errno(ret);
1382
1383 byte &= PCI_REBAR_CTRL_NBAR_MASK;
1384 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1385
1386 return 4 + (byte * 8);
1387 case PCI_EXT_CAP_ID_DPA:
1388 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1389 if (ret)
1390 return pcibios_err_to_errno(ret);
1391
1392 byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1393 return PCI_DPA_BASE_SIZEOF + byte + 1;
1394 case PCI_EXT_CAP_ID_TPH:
1395 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1396 if (ret)
1397 return pcibios_err_to_errno(ret);
1398
1399 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1400 int sts;
1401
1402 sts = dword & PCI_TPH_CAP_ST_MASK;
1403 sts >>= PCI_TPH_CAP_ST_SHIFT;
1404 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1405 }
1406 return PCI_TPH_BASE_SIZEOF;
1407 default:
1408 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n",
1409 __func__, ecap, epos);
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1416 int offset, int size)
1417 {
1418 struct pci_dev *pdev = vdev->pdev;
1419 int ret = 0;
1420
1421 /*
1422 * We try to read physical config space in the largest chunks
1423 * we can, assuming that all of the fields support dword access.
1424 * pci_save_state() makes this same assumption and seems to do ok.
1425 */
1426 while (size) {
1427 int filled;
1428
1429 if (size >= 4 && !(offset % 4)) {
1430 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1431 u32 dword;
1432
1433 ret = pci_read_config_dword(pdev, offset, &dword);
1434 if (ret)
1435 return ret;
1436 *dwordp = cpu_to_le32(dword);
1437 filled = 4;
1438 } else if (size >= 2 && !(offset % 2)) {
1439 __le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1440 u16 word;
1441
1442 ret = pci_read_config_word(pdev, offset, &word);
1443 if (ret)
1444 return ret;
1445 *wordp = cpu_to_le16(word);
1446 filled = 2;
1447 } else {
1448 u8 *byte = &vdev->vconfig[offset];
1449 ret = pci_read_config_byte(pdev, offset, byte);
1450 if (ret)
1451 return ret;
1452 filled = 1;
1453 }
1454
1455 offset += filled;
1456 size -= filled;
1457 }
1458
1459 return ret;
1460 }
1461
1462 static int vfio_cap_init(struct vfio_pci_device *vdev)
1463 {
1464 struct pci_dev *pdev = vdev->pdev;
1465 u8 *map = vdev->pci_config_map;
1466 u16 status;
1467 u8 pos, *prev, cap;
1468 int loops, ret, caps = 0;
1469
1470 /* Any capabilities? */
1471 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1472 if (ret)
1473 return ret;
1474
1475 if (!(status & PCI_STATUS_CAP_LIST))
1476 return 0; /* Done */
1477
1478 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1479 if (ret)
1480 return ret;
1481
1482 /* Mark the previous position in case we want to skip a capability */
1483 prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1484
1485 /* We can bound our loop, capabilities are dword aligned */
1486 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1487 while (pos && loops--) {
1488 u8 next;
1489 int i, len = 0;
1490
1491 ret = pci_read_config_byte(pdev, pos, &cap);
1492 if (ret)
1493 return ret;
1494
1495 ret = pci_read_config_byte(pdev,
1496 pos + PCI_CAP_LIST_NEXT, &next);
1497 if (ret)
1498 return ret;
1499
1500 /*
1501 * ID 0 is a NULL capability, conflicting with our fake
1502 * PCI_CAP_ID_BASIC. As it has no content, consider it
1503 * hidden for now.
1504 */
1505 if (cap && cap <= PCI_CAP_ID_MAX) {
1506 len = pci_cap_length[cap];
1507 if (len == 0xFF) { /* Variable length */
1508 len = vfio_cap_len(vdev, cap, pos);
1509 if (len < 0)
1510 return len;
1511 }
1512 }
1513
1514 if (!len) {
1515 pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__,
1516 cap, pos);
1517 *prev = next;
1518 pos = next;
1519 continue;
1520 }
1521
1522 /* Sanity check, do we overlap other capabilities? */
1523 for (i = 0; i < len; i++) {
1524 if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1525 continue;
1526
1527 pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n",
1528 __func__, pos + i, map[pos + i], cap);
1529 }
1530
1531 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1532
1533 memset(map + pos, cap, len);
1534 ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1535 if (ret)
1536 return ret;
1537
1538 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1539 pos = next;
1540 caps++;
1541 }
1542
1543 /* If we didn't fill any capabilities, clear the status flag */
1544 if (!caps) {
1545 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1546 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1547 }
1548
1549 return 0;
1550 }
1551
1552 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1553 {
1554 struct pci_dev *pdev = vdev->pdev;
1555 u8 *map = vdev->pci_config_map;
1556 u16 epos;
1557 __le32 *prev = NULL;
1558 int loops, ret, ecaps = 0;
1559
1560 if (!vdev->extended_caps)
1561 return 0;
1562
1563 epos = PCI_CFG_SPACE_SIZE;
1564
1565 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1566
1567 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1568 u32 header;
1569 u16 ecap;
1570 int i, len = 0;
1571 bool hidden = false;
1572
1573 ret = pci_read_config_dword(pdev, epos, &header);
1574 if (ret)
1575 return ret;
1576
1577 ecap = PCI_EXT_CAP_ID(header);
1578
1579 if (ecap <= PCI_EXT_CAP_ID_MAX) {
1580 len = pci_ext_cap_length[ecap];
1581 if (len == 0xFF) {
1582 len = vfio_ext_cap_len(vdev, ecap, epos);
1583 if (len < 0)
1584 return ret;
1585 }
1586 }
1587
1588 if (!len) {
1589 pci_info(pdev, "%s: hiding ecap %#x@%#x\n",
1590 __func__, ecap, epos);
1591
1592 /* If not the first in the chain, we can skip over it */
1593 if (prev) {
1594 u32 val = epos = PCI_EXT_CAP_NEXT(header);
1595 *prev &= cpu_to_le32(~(0xffcU << 20));
1596 *prev |= cpu_to_le32(val << 20);
1597 continue;
1598 }
1599
1600 /*
1601 * Otherwise, fill in a placeholder, the direct
1602 * readfn will virtualize this automatically
1603 */
1604 len = PCI_CAP_SIZEOF;
1605 hidden = true;
1606 }
1607
1608 for (i = 0; i < len; i++) {
1609 if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1610 continue;
1611
1612 pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n",
1613 __func__, epos + i, map[epos + i], ecap);
1614 }
1615
1616 /*
1617 * Even though ecap is 2 bytes, we're currently a long way
1618 * from exceeding 1 byte capabilities. If we ever make it
1619 * up to 0xFE we'll need to up this to a two-byte, byte map.
1620 */
1621 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1622
1623 memset(map + epos, ecap, len);
1624 ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1625 if (ret)
1626 return ret;
1627
1628 /*
1629 * If we're just using this capability to anchor the list,
1630 * hide the real ID. Only count real ecaps. XXX PCI spec
1631 * indicates to use cap id = 0, version = 0, next = 0 if
1632 * ecaps are absent, hope users check all the way to next.
1633 */
1634 if (hidden)
1635 *(__le32 *)&vdev->vconfig[epos] &=
1636 cpu_to_le32((0xffcU << 20));
1637 else
1638 ecaps++;
1639
1640 prev = (__le32 *)&vdev->vconfig[epos];
1641 epos = PCI_EXT_CAP_NEXT(header);
1642 }
1643
1644 if (!ecaps)
1645 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1646
1647 return 0;
1648 }
1649
1650 /*
1651 * Nag about hardware bugs, hopefully to have vendors fix them, but at least
1652 * to collect a list of dependencies for the VF INTx pin quirk below.
1653 */
1654 static const struct pci_device_id known_bogus_vf_intx_pin[] = {
1655 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
1656 {}
1657 };
1658
1659 /*
1660 * For each device we allocate a pci_config_map that indicates the
1661 * capability occupying each dword and thus the struct perm_bits we
1662 * use for read and write. We also allocate a virtualized config
1663 * space which tracks reads and writes to bits that we emulate for
1664 * the user. Initial values filled from device.
1665 *
1666 * Using shared struct perm_bits between all vfio-pci devices saves
1667 * us from allocating cfg_size buffers for virt and write for every
1668 * device. We could remove vconfig and allocate individual buffers
1669 * for each area requiring emulated bits, but the array of pointers
1670 * would be comparable in size (at least for standard config space).
1671 */
1672 int vfio_config_init(struct vfio_pci_device *vdev)
1673 {
1674 struct pci_dev *pdev = vdev->pdev;
1675 u8 *map, *vconfig;
1676 int ret;
1677
1678 /*
1679 * Config space, caps and ecaps are all dword aligned, so we could
1680 * use one byte per dword to record the type. However, there are
1681 * no requiremenst on the length of a capability, so the gap between
1682 * capabilities needs byte granularity.
1683 */
1684 map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1685 if (!map)
1686 return -ENOMEM;
1687
1688 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1689 if (!vconfig) {
1690 kfree(map);
1691 return -ENOMEM;
1692 }
1693
1694 vdev->pci_config_map = map;
1695 vdev->vconfig = vconfig;
1696
1697 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1698 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1699 pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1700
1701 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1702 if (ret)
1703 goto out;
1704
1705 vdev->bardirty = true;
1706
1707 /*
1708 * XXX can we just pci_load_saved_state/pci_restore_state?
1709 * may need to rebuild vconfig after that
1710 */
1711
1712 /* For restore after reset */
1713 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1714 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1715 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1716 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1717 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1718 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1719 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1720
1721 if (pdev->is_virtfn) {
1722 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1723 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1724
1725 /*
1726 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
1727 * does not apply to VFs and VFs must implement this register
1728 * as read-only with value zero. Userspace is not readily able
1729 * to identify whether a device is a VF and thus that the pin
1730 * definition on the device is bogus should it violate this
1731 * requirement. We already virtualize the pin register for
1732 * other purposes, so we simply need to replace the bogus value
1733 * and consider VFs when we determine INTx IRQ count.
1734 */
1735 if (vconfig[PCI_INTERRUPT_PIN] &&
1736 !pci_match_id(known_bogus_vf_intx_pin, pdev))
1737 pci_warn(pdev,
1738 "Hardware bug: VF reports bogus INTx pin %d\n",
1739 vconfig[PCI_INTERRUPT_PIN]);
1740
1741 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
1742 }
1743 if (pdev->no_command_memory) {
1744 /*
1745 * VFs and devices that set pdev->no_command_memory do not
1746 * implement the memory enable bit of the COMMAND register
1747 * therefore we'll not have it set in our initial copy of
1748 * config space after pci_enable_device(). For consistency
1749 * with PFs, set the virtual enable bit here.
1750 */
1751 *(__le16 *)&vconfig[PCI_COMMAND] |=
1752 cpu_to_le16(PCI_COMMAND_MEMORY);
1753 }
1754
1755 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1756 vconfig[PCI_INTERRUPT_PIN] = 0;
1757
1758 ret = vfio_cap_init(vdev);
1759 if (ret)
1760 goto out;
1761
1762 ret = vfio_ecap_init(vdev);
1763 if (ret)
1764 goto out;
1765
1766 return 0;
1767
1768 out:
1769 kfree(map);
1770 vdev->pci_config_map = NULL;
1771 kfree(vconfig);
1772 vdev->vconfig = NULL;
1773 return pcibios_err_to_errno(ret);
1774 }
1775
1776 void vfio_config_free(struct vfio_pci_device *vdev)
1777 {
1778 kfree(vdev->vconfig);
1779 vdev->vconfig = NULL;
1780 kfree(vdev->pci_config_map);
1781 vdev->pci_config_map = NULL;
1782 if (vdev->msi_perm) {
1783 free_perm_bits(vdev->msi_perm);
1784 kfree(vdev->msi_perm);
1785 vdev->msi_perm = NULL;
1786 }
1787 }
1788
1789 /*
1790 * Find the remaining number of bytes in a dword that match the given
1791 * position. Stop at either the end of the capability or the dword boundary.
1792 */
1793 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1794 loff_t pos)
1795 {
1796 u8 cap = vdev->pci_config_map[pos];
1797 size_t i;
1798
1799 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1800 /* nop */;
1801
1802 return i;
1803 }
1804
1805 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1806 size_t count, loff_t *ppos, bool iswrite)
1807 {
1808 struct pci_dev *pdev = vdev->pdev;
1809 struct perm_bits *perm;
1810 __le32 val = 0;
1811 int cap_start = 0, offset;
1812 u8 cap_id;
1813 ssize_t ret;
1814
1815 if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1816 *ppos + count > pdev->cfg_size)
1817 return -EFAULT;
1818
1819 /*
1820 * Chop accesses into aligned chunks containing no more than a
1821 * single capability. Caller increments to the next chunk.
1822 */
1823 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1824 if (count >= 4 && !(*ppos % 4))
1825 count = 4;
1826 else if (count >= 2 && !(*ppos % 2))
1827 count = 2;
1828 else
1829 count = 1;
1830
1831 ret = count;
1832
1833 cap_id = vdev->pci_config_map[*ppos];
1834
1835 if (cap_id == PCI_CAP_ID_INVALID) {
1836 perm = &unassigned_perms;
1837 cap_start = *ppos;
1838 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1839 perm = &virt_perms;
1840 cap_start = *ppos;
1841 } else {
1842 if (*ppos >= PCI_CFG_SPACE_SIZE) {
1843 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1844
1845 perm = &ecap_perms[cap_id];
1846 cap_start = vfio_find_cap_start(vdev, *ppos);
1847 } else {
1848 WARN_ON(cap_id > PCI_CAP_ID_MAX);
1849
1850 perm = &cap_perms[cap_id];
1851
1852 if (cap_id == PCI_CAP_ID_MSI)
1853 perm = vdev->msi_perm;
1854
1855 if (cap_id > PCI_CAP_ID_BASIC)
1856 cap_start = vfio_find_cap_start(vdev, *ppos);
1857 }
1858 }
1859
1860 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1861 WARN_ON(cap_start > *ppos);
1862
1863 offset = *ppos - cap_start;
1864
1865 if (iswrite) {
1866 if (!perm->writefn)
1867 return ret;
1868
1869 if (copy_from_user(&val, buf, count))
1870 return -EFAULT;
1871
1872 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1873 } else {
1874 if (perm->readfn) {
1875 ret = perm->readfn(vdev, *ppos, count,
1876 perm, offset, &val);
1877 if (ret < 0)
1878 return ret;
1879 }
1880
1881 if (copy_to_user(buf, &val, count))
1882 return -EFAULT;
1883 }
1884
1885 return ret;
1886 }
1887
1888 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1889 size_t count, loff_t *ppos, bool iswrite)
1890 {
1891 size_t done = 0;
1892 int ret = 0;
1893 loff_t pos = *ppos;
1894
1895 pos &= VFIO_PCI_OFFSET_MASK;
1896
1897 while (count) {
1898 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1899 if (ret < 0)
1900 return ret;
1901
1902 count -= ret;
1903 done += ret;
1904 buf += ret;
1905 pos += ret;
1906 }
1907
1908 *ppos += done;
1909
1910 return done;
1911 }
Linux with added FPC-III support