1 // SPDX-License-Identifier: GPL-2.0-only
3 * i740fb - framebuffer driver for Intel740
4 * Copyright (c) 2011 Ondrej Zary
6 * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
7 * which was partially based on:
8 * VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
9 * and Petr Vandrovec <VANDROVE@vc.cvut.cz>
10 * i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
12 * i740fb by Patrick LERDA, v0.9
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/pci_ids.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c-algo-bit.h>
28 #include <linux/console.h>
29 #include <video/vga.h>
33 static char *mode_option
;
37 unsigned char __iomem
*regs
;
41 struct i2c_adapter ddc_adapter
;
42 struct i2c_algo_bit_data ddc_algo
;
43 u32 pseudo_palette
[16];
44 struct mutex open_lock
;
45 unsigned int ref_count
;
54 /* i740 specific registers */
61 u8 video_clk2_mn_msbs
;
62 u8 video_clk2_div_sel
;
69 u8 ext_vert_sync_start
;
70 u8 ext_vert_blank_start
;
75 u32 lmi_fifo_watermark
;
81 #define DACSPEED16 163
82 #define DACSPEED24_SG 136
83 #define DACSPEED24_SD 128
86 static const struct fb_fix_screeninfo i740fb_fix
= {
88 .type
= FB_TYPE_PACKED_PIXELS
,
89 .visual
= FB_VISUAL_TRUECOLOR
,
92 .accel
= FB_ACCEL_NONE
,
95 static inline void i740outb(struct i740fb_par
*par
, u16 port
, u8 val
)
97 vga_mm_w(par
->regs
, port
, val
);
99 static inline u8
i740inb(struct i740fb_par
*par
, u16 port
)
101 return vga_mm_r(par
->regs
, port
);
103 static inline void i740outreg(struct i740fb_par
*par
, u16 port
, u8 reg
, u8 val
)
105 vga_mm_w_fast(par
->regs
, port
, reg
, val
);
107 static inline u8
i740inreg(struct i740fb_par
*par
, u16 port
, u8 reg
)
109 vga_mm_w(par
->regs
, port
, reg
);
110 return vga_mm_r(par
->regs
, port
+1);
112 static inline void i740outreg_mask(struct i740fb_par
*par
, u16 port
, u8 reg
,
115 vga_mm_w_fast(par
->regs
, port
, reg
, (val
& mask
)
116 | (i740inreg(par
, port
, reg
) & ~mask
));
119 #define REG_DDC_DRIVE 0x62
120 #define REG_DDC_STATE 0x63
121 #define DDC_SCL (1 << 3)
122 #define DDC_SDA (1 << 2)
124 static void i740fb_ddc_setscl(void *data
, int val
)
126 struct i740fb_par
*par
= data
;
128 i740outreg_mask(par
, XRX
, REG_DDC_DRIVE
, DDC_SCL
, DDC_SCL
);
129 i740outreg_mask(par
, XRX
, REG_DDC_STATE
, val
? DDC_SCL
: 0, DDC_SCL
);
132 static void i740fb_ddc_setsda(void *data
, int val
)
134 struct i740fb_par
*par
= data
;
136 i740outreg_mask(par
, XRX
, REG_DDC_DRIVE
, DDC_SDA
, DDC_SDA
);
137 i740outreg_mask(par
, XRX
, REG_DDC_STATE
, val
? DDC_SDA
: 0, DDC_SDA
);
140 static int i740fb_ddc_getscl(void *data
)
142 struct i740fb_par
*par
= data
;
144 i740outreg_mask(par
, XRX
, REG_DDC_DRIVE
, 0, DDC_SCL
);
146 return !!(i740inreg(par
, XRX
, REG_DDC_STATE
) & DDC_SCL
);
149 static int i740fb_ddc_getsda(void *data
)
151 struct i740fb_par
*par
= data
;
153 i740outreg_mask(par
, XRX
, REG_DDC_DRIVE
, 0, DDC_SDA
);
155 return !!(i740inreg(par
, XRX
, REG_DDC_STATE
) & DDC_SDA
);
158 static int i740fb_setup_ddc_bus(struct fb_info
*info
)
160 struct i740fb_par
*par
= info
->par
;
162 strlcpy(par
->ddc_adapter
.name
, info
->fix
.id
,
163 sizeof(par
->ddc_adapter
.name
));
164 par
->ddc_adapter
.owner
= THIS_MODULE
;
165 par
->ddc_adapter
.class = I2C_CLASS_DDC
;
166 par
->ddc_adapter
.algo_data
= &par
->ddc_algo
;
167 par
->ddc_adapter
.dev
.parent
= info
->device
;
168 par
->ddc_algo
.setsda
= i740fb_ddc_setsda
;
169 par
->ddc_algo
.setscl
= i740fb_ddc_setscl
;
170 par
->ddc_algo
.getsda
= i740fb_ddc_getsda
;
171 par
->ddc_algo
.getscl
= i740fb_ddc_getscl
;
172 par
->ddc_algo
.udelay
= 10;
173 par
->ddc_algo
.timeout
= 20;
174 par
->ddc_algo
.data
= par
;
176 i2c_set_adapdata(&par
->ddc_adapter
, par
);
178 return i2c_bit_add_bus(&par
->ddc_adapter
);
181 static int i740fb_open(struct fb_info
*info
, int user
)
183 struct i740fb_par
*par
= info
->par
;
185 mutex_lock(&(par
->open_lock
));
187 mutex_unlock(&(par
->open_lock
));
192 static int i740fb_release(struct fb_info
*info
, int user
)
194 struct i740fb_par
*par
= info
->par
;
196 mutex_lock(&(par
->open_lock
));
197 if (par
->ref_count
== 0) {
198 fb_err(info
, "release called with zero refcount\n");
199 mutex_unlock(&(par
->open_lock
));
204 mutex_unlock(&(par
->open_lock
));
209 static u32
i740_calc_fifo(struct i740fb_par
*par
, u32 freq
, int bpp
)
212 * Would like to calculate these values automatically, but a generic
213 * algorithm does not seem possible. Note: These FIFO water mark
214 * values were tested on several cards and seem to eliminate the
215 * all of the snow and vertical banding, but fine adjustments will
216 * probably be required for other cards.
234 if (par
->has_sgram
) {
271 if (par
->has_sgram
) {
306 if (par
->has_sgram
) {
335 /* clock calculation from i740fb by Patrick LERDA */
337 #define I740_RFREQ 1000000
338 #define TARGET_MAX_N 30
339 #define I740_FFIX (1 << 8)
340 #define I740_RFREQ_FIX (I740_RFREQ / I740_FFIX)
341 #define I740_REF_FREQ (6667 * I740_FFIX / 100) /* 66.67 MHz */
342 #define I740_MAX_VCO_FREQ (450 * I740_FFIX) /* 450 MHz */
344 static void i740_calc_vclk(u32 freq
, struct i740fb_par
*par
)
346 const u32 err_max
= freq
/ (200 * I740_RFREQ
/ I740_FFIX
);
347 const u32 err_target
= freq
/ (1000 * I740_RFREQ
/ I740_FFIX
);
348 u32 err_best
= 512 * I740_FFIX
;
350 int m_best
= 0, n_best
= 0, p_best
= 0;
353 p_best
= min(15, ilog2(I740_MAX_VCO_FREQ
/ (freq
/ I740_RFREQ_FIX
)));
354 f_vco
= (freq
* (1 << p_best
)) / I740_RFREQ_FIX
;
355 freq
= freq
/ I740_RFREQ_FIX
;
360 m
= ((f_vco
* n
) / I740_REF_FREQ
+ 2) / 4;
366 u32 f_out
= (((m
* I740_REF_FREQ
* 4)
367 / n
) + ((1 << p_best
) / 2)) / (1 << p_best
);
369 f_err
= (freq
- f_out
);
371 if (abs(f_err
) < err_max
) {
377 } while ((abs(f_err
) >= err_target
) &&
378 ((n
<= TARGET_MAX_N
) || (abs(err_best
) > err_max
)));
380 if (abs(f_err
) < err_target
) {
385 par
->video_clk2_m
= (m_best
- 2) & 0xFF;
386 par
->video_clk2_n
= (n_best
- 2) & 0xFF;
387 par
->video_clk2_mn_msbs
= ((((n_best
- 2) >> 4) & VCO_N_MSBS
)
388 | (((m_best
- 2) >> 8) & VCO_M_MSBS
));
389 par
->video_clk2_div_sel
= ((p_best
<< 4) | REF_DIV_1
);
392 static int i740fb_decode_var(const struct fb_var_screeninfo
*var
,
393 struct i740fb_par
*par
, struct fb_info
*info
)
396 * Get the video params out of 'var'.
397 * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
400 u32 xres
, right
, hslen
, left
, xtotal
;
401 u32 yres
, lower
, vslen
, upper
, ytotal
;
402 u32 vxres
, xoffset
, vyres
, yoffset
;
403 u32 bpp
, base
, dacspeed24
, mem
;
407 dev_dbg(info
->device
, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
408 var
->xres
, var
->yres
, var
->xres_virtual
, var
->xres_virtual
);
409 dev_dbg(info
->device
, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
410 var
->xoffset
, var
->yoffset
, var
->bits_per_pixel
,
412 dev_dbg(info
->device
, " activate: %i, nonstd: %i, vmode: %i\n",
413 var
->activate
, var
->nonstd
, var
->vmode
);
414 dev_dbg(info
->device
, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
415 var
->pixclock
, var
->hsync_len
, var
->vsync_len
);
416 dev_dbg(info
->device
, " left: %i, right: %i, up:%i, lower:%i\n",
417 var
->left_margin
, var
->right_margin
, var
->upper_margin
,
421 bpp
= var
->bits_per_pixel
;
425 if ((1000000 / var
->pixclock
) > DACSPEED8
) {
426 dev_err(info
->device
, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
427 1000000 / var
->pixclock
, DACSPEED8
);
435 if ((1000000 / var
->pixclock
) > DACSPEED16
) {
436 dev_err(info
->device
, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
437 1000000 / var
->pixclock
, DACSPEED16
);
443 dacspeed24
= par
->has_sgram
? DACSPEED24_SG
: DACSPEED24_SD
;
444 if ((1000000 / var
->pixclock
) > dacspeed24
) {
445 dev_err(info
->device
, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
446 1000000 / var
->pixclock
, dacspeed24
);
452 if ((1000000 / var
->pixclock
) > DACSPEED32
) {
453 dev_err(info
->device
, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
454 1000000 / var
->pixclock
, DACSPEED32
);
462 xres
= ALIGN(var
->xres
, 8);
463 vxres
= ALIGN(var
->xres_virtual
, 16);
467 xoffset
= ALIGN(var
->xoffset
, 8);
468 if (xres
+ xoffset
> vxres
)
469 xoffset
= vxres
- xres
;
471 left
= ALIGN(var
->left_margin
, 8);
472 right
= ALIGN(var
->right_margin
, 8);
473 hslen
= ALIGN(var
->hsync_len
, 8);
476 vyres
= var
->yres_virtual
;
480 yoffset
= var
->yoffset
;
481 if (yres
+ yoffset
> vyres
)
482 yoffset
= vyres
- yres
;
484 lower
= var
->lower_margin
;
485 vslen
= var
->vsync_len
;
486 upper
= var
->upper_margin
;
488 mem
= vxres
* vyres
* ((bpp
+ 1) / 8);
489 if (mem
> info
->screen_size
) {
490 dev_err(info
->device
, "not enough video memory (%d KB requested, %ld KB available)\n",
491 mem
>> 10, info
->screen_size
>> 10);
495 if (yoffset
+ yres
> vyres
)
496 yoffset
= vyres
- yres
;
498 xtotal
= xres
+ right
+ hslen
+ left
;
499 ytotal
= yres
+ lower
+ vslen
+ upper
;
501 par
->crtc
[VGA_CRTC_H_TOTAL
] = (xtotal
>> 3) - 5;
502 par
->crtc
[VGA_CRTC_H_DISP
] = (xres
>> 3) - 1;
503 par
->crtc
[VGA_CRTC_H_BLANK_START
] = ((xres
+ right
) >> 3) - 1;
504 par
->crtc
[VGA_CRTC_H_SYNC_START
] = (xres
+ right
) >> 3;
505 par
->crtc
[VGA_CRTC_H_SYNC_END
] = (((xres
+ right
+ hslen
) >> 3) & 0x1F)
506 | ((((xres
+ right
+ hslen
) >> 3) & 0x20) << 2);
507 par
->crtc
[VGA_CRTC_H_BLANK_END
] = ((xres
+ right
+ hslen
) >> 3 & 0x1F)
510 par
->crtc
[VGA_CRTC_V_TOTAL
] = ytotal
- 2;
512 r7
= 0x10; /* disable linecompare */
518 par
->crtc
[VGA_CRTC_PRESET_ROW
] = 0;
519 par
->crtc
[VGA_CRTC_MAX_SCAN
] = 0x40; /* 1 scanline, no linecmp */
520 if (var
->vmode
& FB_VMODE_DOUBLE
)
521 par
->crtc
[VGA_CRTC_MAX_SCAN
] |= 0x80;
522 par
->crtc
[VGA_CRTC_CURSOR_START
] = 0x00;
523 par
->crtc
[VGA_CRTC_CURSOR_END
] = 0x00;
524 par
->crtc
[VGA_CRTC_CURSOR_HI
] = 0x00;
525 par
->crtc
[VGA_CRTC_CURSOR_LO
] = 0x00;
526 par
->crtc
[VGA_CRTC_V_DISP_END
] = yres
-1;
527 if ((yres
-1) & 0x100)
529 if ((yres
-1) & 0x200)
532 par
->crtc
[VGA_CRTC_V_BLANK_START
] = yres
+ lower
- 1;
533 par
->crtc
[VGA_CRTC_V_SYNC_START
] = yres
+ lower
- 1;
534 if ((yres
+ lower
- 1) & 0x100)
536 if ((yres
+ lower
- 1) & 0x200) {
537 par
->crtc
[VGA_CRTC_MAX_SCAN
] |= 0x20;
542 par
->crtc
[VGA_CRTC_V_SYNC_END
] =
543 ((yres
+ lower
- 1 + vslen
) & 0x0F) & ~0x10;
544 /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
545 par
->crtc
[VGA_CRTC_V_BLANK_END
] = (yres
+ lower
- 1 + vslen
) & 0xFF;
547 par
->crtc
[VGA_CRTC_UNDERLINE
] = 0x00;
548 par
->crtc
[VGA_CRTC_MODE
] = 0xC3 ;
549 par
->crtc
[VGA_CRTC_LINE_COMPARE
] = 0xFF;
550 par
->crtc
[VGA_CRTC_OVERFLOW
] = r7
;
552 par
->vss
= 0x00; /* 3DA */
554 for (i
= 0x00; i
< 0x10; i
++)
556 par
->atc
[VGA_ATC_MODE
] = 0x81;
557 par
->atc
[VGA_ATC_OVERSCAN
] = 0x00; /* 0 for EGA, 0xFF for VGA */
558 par
->atc
[VGA_ATC_PLANE_ENABLE
] = 0x0F;
559 par
->atc
[VGA_ATC_COLOR_PAGE
] = 0x00;
562 if (var
->sync
& FB_SYNC_HOR_HIGH_ACT
)
564 if (var
->sync
& FB_SYNC_VERT_HIGH_ACT
)
567 par
->seq
[VGA_SEQ_CLOCK_MODE
] = 0x01;
568 par
->seq
[VGA_SEQ_PLANE_WRITE
] = 0x0F;
569 par
->seq
[VGA_SEQ_CHARACTER_MAP
] = 0x00;
570 par
->seq
[VGA_SEQ_MEMORY_MODE
] = 0x06;
572 par
->gdc
[VGA_GFX_SR_VALUE
] = 0x00;
573 par
->gdc
[VGA_GFX_SR_ENABLE
] = 0x00;
574 par
->gdc
[VGA_GFX_COMPARE_VALUE
] = 0x00;
575 par
->gdc
[VGA_GFX_DATA_ROTATE
] = 0x00;
576 par
->gdc
[VGA_GFX_PLANE_READ
] = 0;
577 par
->gdc
[VGA_GFX_MODE
] = 0x02;
578 par
->gdc
[VGA_GFX_MISC
] = 0x05;
579 par
->gdc
[VGA_GFX_COMPARE_MASK
] = 0x0F;
580 par
->gdc
[VGA_GFX_BIT_MASK
] = 0xFF;
582 base
= (yoffset
* vxres
+ (xoffset
& ~7)) >> 2;
585 par
->crtc
[VGA_CRTC_OFFSET
] = vxres
>> 3;
586 par
->ext_offset
= vxres
>> 11;
587 par
->pixelpipe_cfg1
= DISPLAY_8BPP_MODE
;
588 par
->bitblt_cntl
= COLEXP_8BPP
;
590 case 15: /* 0rrrrrgg gggbbbbb */
591 case 16: /* rrrrrggg gggbbbbb */
592 par
->pixelpipe_cfg1
= (var
->green
.length
== 6) ?
593 DISPLAY_16BPP_MODE
: DISPLAY_15BPP_MODE
;
594 par
->crtc
[VGA_CRTC_OFFSET
] = vxres
>> 2;
595 par
->ext_offset
= vxres
>> 10;
596 par
->bitblt_cntl
= COLEXP_16BPP
;
600 par
->crtc
[VGA_CRTC_OFFSET
] = (vxres
* 3) >> 3;
601 par
->ext_offset
= (vxres
* 3) >> 11;
602 par
->pixelpipe_cfg1
= DISPLAY_24BPP_MODE
;
603 par
->bitblt_cntl
= COLEXP_24BPP
;
604 base
&= 0xFFFFFFFE; /* ...ignore the last bit. */
608 par
->crtc
[VGA_CRTC_OFFSET
] = vxres
>> 1;
609 par
->ext_offset
= vxres
>> 9;
610 par
->pixelpipe_cfg1
= DISPLAY_32BPP_MODE
;
611 par
->bitblt_cntl
= COLEXP_RESERVED
; /* Unimplemented on i740 */
616 par
->crtc
[VGA_CRTC_START_LO
] = base
& 0x000000FF;
617 par
->crtc
[VGA_CRTC_START_HI
] = (base
& 0x0000FF00) >> 8;
618 par
->ext_start_addr
=
619 ((base
& 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE
;
620 par
->ext_start_addr_hi
= (base
& 0x3FC00000) >> 22;
622 par
->pixelpipe_cfg0
= DAC_8_BIT
;
624 par
->pixelpipe_cfg2
= DISPLAY_GAMMA_ENABLE
| OVERLAY_GAMMA_ENABLE
;
625 par
->io_cntl
= EXTENDED_CRTC_CNTL
;
626 par
->address_mapping
= LINEAR_MODE_ENABLE
| PAGE_MAPPING_ENABLE
;
627 par
->display_cntl
= HIRES_MODE
;
629 /* Set the MCLK freq */
630 par
->pll_cntl
= PLL_MEMCLK_100000KHZ
; /* 100 MHz -- use as default */
632 /* Calculate the extended CRTC regs */
633 par
->ext_vert_total
= (ytotal
- 2) >> 8;
634 par
->ext_vert_disp_end
= (yres
- 1) >> 8;
635 par
->ext_vert_sync_start
= (yres
+ lower
) >> 8;
636 par
->ext_vert_blank_start
= (yres
+ lower
) >> 8;
637 par
->ext_horiz_total
= ((xtotal
>> 3) - 5) >> 8;
638 par
->ext_horiz_blank
= (((xres
+ right
) >> 3) & 0x40) >> 6;
640 par
->interlace_cntl
= INTERLACE_DISABLE
;
642 /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
643 par
->atc
[VGA_ATC_OVERSCAN
] = 0;
645 /* Calculate VCLK that most closely matches the requested dot clock */
646 i740_calc_vclk((((u32
)1e9
) / var
->pixclock
) * (u32
)(1e3
), par
);
648 /* Since we program the clocks ourselves, always use VCLK2. */
651 /* Calculate the FIFO Watermark and Burst Length. */
652 par
->lmi_fifo_watermark
=
653 i740_calc_fifo(par
, 1000000 / var
->pixclock
, bpp
);
658 static int i740fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
660 switch (var
->bits_per_pixel
) {
662 var
->red
.offset
= var
->green
.offset
= var
->blue
.offset
= 0;
663 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
666 switch (var
->green
.length
) {
669 var
->red
.offset
= 10;
670 var
->green
.offset
= 5;
671 var
->blue
.offset
= 0;
673 var
->green
.length
= 5;
674 var
->blue
.length
= 5;
677 var
->red
.offset
= 11;
678 var
->green
.offset
= 5;
679 var
->blue
.offset
= 0;
680 var
->red
.length
= var
->blue
.length
= 5;
685 var
->red
.offset
= 16;
686 var
->green
.offset
= 8;
687 var
->blue
.offset
= 0;
688 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
691 var
->transp
.offset
= 24;
692 var
->red
.offset
= 16;
693 var
->green
.offset
= 8;
694 var
->blue
.offset
= 0;
695 var
->transp
.length
= 8;
696 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
702 if (var
->xres
> var
->xres_virtual
)
703 var
->xres_virtual
= var
->xres
;
705 if (var
->yres
> var
->yres_virtual
)
706 var
->yres_virtual
= var
->yres
;
708 if (info
->monspecs
.hfmax
&& info
->monspecs
.vfmax
&&
709 info
->monspecs
.dclkmax
&& fb_validate_mode(var
, info
) < 0)
715 static void vga_protect(struct i740fb_par
*par
)
717 /* disable the display */
718 i740outreg_mask(par
, VGA_SEQ_I
, VGA_SEQ_CLOCK_MODE
, 0x20, 0x20);
721 i740outb(par
, VGA_ATT_W
, 0x00); /* enable palette access */
724 static void vga_unprotect(struct i740fb_par
*par
)
726 /* reenable display */
727 i740outreg_mask(par
, VGA_SEQ_I
, VGA_SEQ_CLOCK_MODE
, 0, 0x20);
730 i740outb(par
, VGA_ATT_W
, 0x20); /* disable palette access */
733 static int i740fb_set_par(struct fb_info
*info
)
735 struct i740fb_par
*par
= info
->par
;
739 i
= i740fb_decode_var(&info
->var
, par
, info
);
743 memset(info
->screen_base
, 0, info
->screen_size
);
747 i740outreg(par
, XRX
, DRAM_EXT_CNTL
, DRAM_REFRESH_DISABLE
);
751 i740outreg(par
, XRX
, VCLK2_VCO_M
, par
->video_clk2_m
);
752 i740outreg(par
, XRX
, VCLK2_VCO_N
, par
->video_clk2_n
);
753 i740outreg(par
, XRX
, VCLK2_VCO_MN_MSBS
, par
->video_clk2_mn_msbs
);
754 i740outreg(par
, XRX
, VCLK2_VCO_DIV_SEL
, par
->video_clk2_div_sel
);
756 i740outreg_mask(par
, XRX
, PIXPIPE_CONFIG_0
,
757 par
->pixelpipe_cfg0
& DAC_8_BIT
, 0x80);
760 i740outb(par
, 0x3C0, 0x00);
762 /* update misc output register */
763 i740outb(par
, VGA_MIS_W
, par
->misc
| 0x01);
765 /* synchronous reset on */
766 i740outreg(par
, VGA_SEQ_I
, VGA_SEQ_RESET
, 0x01);
767 /* write sequencer registers */
768 i740outreg(par
, VGA_SEQ_I
, VGA_SEQ_CLOCK_MODE
,
769 par
->seq
[VGA_SEQ_CLOCK_MODE
] | 0x20);
770 for (i
= 2; i
< VGA_SEQ_C
; i
++)
771 i740outreg(par
, VGA_SEQ_I
, i
, par
->seq
[i
]);
773 /* synchronous reset off */
774 i740outreg(par
, VGA_SEQ_I
, VGA_SEQ_RESET
, 0x03);
776 /* deprotect CRT registers 0-7 */
777 i740outreg(par
, VGA_CRT_IC
, VGA_CRTC_V_SYNC_END
,
778 par
->crtc
[VGA_CRTC_V_SYNC_END
]);
780 /* write CRT registers */
781 for (i
= 0; i
< VGA_CRT_C
; i
++)
782 i740outreg(par
, VGA_CRT_IC
, i
, par
->crtc
[i
]);
784 /* write graphics controller registers */
785 for (i
= 0; i
< VGA_GFX_C
; i
++)
786 i740outreg(par
, VGA_GFX_I
, i
, par
->gdc
[i
]);
788 /* write attribute controller registers */
789 for (i
= 0; i
< VGA_ATT_C
; i
++) {
790 i740inb(par
, VGA_IS1_RC
); /* reset flip-flop */
791 i740outb(par
, VGA_ATT_IW
, i
);
792 i740outb(par
, VGA_ATT_IW
, par
->atc
[i
]);
795 i740inb(par
, VGA_IS1_RC
);
796 i740outb(par
, VGA_ATT_IW
, 0x20);
798 i740outreg(par
, VGA_CRT_IC
, EXT_VERT_TOTAL
, par
->ext_vert_total
);
799 i740outreg(par
, VGA_CRT_IC
, EXT_VERT_DISPLAY
, par
->ext_vert_disp_end
);
800 i740outreg(par
, VGA_CRT_IC
, EXT_VERT_SYNC_START
,
801 par
->ext_vert_sync_start
);
802 i740outreg(par
, VGA_CRT_IC
, EXT_VERT_BLANK_START
,
803 par
->ext_vert_blank_start
);
804 i740outreg(par
, VGA_CRT_IC
, EXT_HORIZ_TOTAL
, par
->ext_horiz_total
);
805 i740outreg(par
, VGA_CRT_IC
, EXT_HORIZ_BLANK
, par
->ext_horiz_blank
);
806 i740outreg(par
, VGA_CRT_IC
, EXT_OFFSET
, par
->ext_offset
);
807 i740outreg(par
, VGA_CRT_IC
, EXT_START_ADDR_HI
, par
->ext_start_addr_hi
);
808 i740outreg(par
, VGA_CRT_IC
, EXT_START_ADDR
, par
->ext_start_addr
);
810 i740outreg_mask(par
, VGA_CRT_IC
, INTERLACE_CNTL
,
811 par
->interlace_cntl
, INTERLACE_ENABLE
);
812 i740outreg_mask(par
, XRX
, ADDRESS_MAPPING
, par
->address_mapping
, 0x1F);
813 i740outreg_mask(par
, XRX
, BITBLT_CNTL
, par
->bitblt_cntl
, COLEXP_MODE
);
814 i740outreg_mask(par
, XRX
, DISPLAY_CNTL
,
815 par
->display_cntl
, VGA_WRAP_MODE
| GUI_MODE
);
816 i740outreg_mask(par
, XRX
, PIXPIPE_CONFIG_0
, par
->pixelpipe_cfg0
, 0x9B);
817 i740outreg_mask(par
, XRX
, PIXPIPE_CONFIG_2
, par
->pixelpipe_cfg2
, 0x0C);
819 i740outreg(par
, XRX
, PLL_CNTL
, par
->pll_cntl
);
821 i740outreg_mask(par
, XRX
, PIXPIPE_CONFIG_1
,
822 par
->pixelpipe_cfg1
, DISPLAY_COLOR_MODE
);
824 itemp
= readl(par
->regs
+ FWATER_BLC
);
825 itemp
&= ~(LMI_BURST_LENGTH
| LMI_FIFO_WATERMARK
);
826 itemp
|= par
->lmi_fifo_watermark
;
827 writel(itemp
, par
->regs
+ FWATER_BLC
);
829 i740outreg(par
, XRX
, DRAM_EXT_CNTL
, DRAM_REFRESH_60HZ
);
831 i740outreg_mask(par
, MRX
, COL_KEY_CNTL_1
, 0, BLANK_DISP_OVERLAY
);
832 i740outreg_mask(par
, XRX
, IO_CTNL
,
833 par
->io_cntl
, EXTENDED_ATTR_CNTL
| EXTENDED_CRTC_CNTL
);
835 if (par
->pixelpipe_cfg1
!= DISPLAY_8BPP_MODE
) {
836 i740outb(par
, VGA_PEL_MSK
, 0xFF);
837 i740outb(par
, VGA_PEL_IW
, 0x00);
838 for (i
= 0; i
< 256; i
++) {
839 itemp
= (par
->pixelpipe_cfg0
& DAC_8_BIT
) ? i
: i
>> 2;
840 i740outb(par
, VGA_PEL_D
, itemp
);
841 i740outb(par
, VGA_PEL_D
, itemp
);
842 i740outb(par
, VGA_PEL_D
, itemp
);
846 /* Wait for screen to stabilize. */
850 info
->fix
.line_length
=
851 info
->var
.xres_virtual
* info
->var
.bits_per_pixel
/ 8;
852 if (info
->var
.bits_per_pixel
== 8)
853 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
855 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
860 static int i740fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
861 unsigned blue
, unsigned transp
,
862 struct fb_info
*info
)
866 dev_dbg(info
->device
, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
867 regno
, red
, green
, blue
, transp
, info
->var
.bits_per_pixel
);
869 switch (info
->fix
.visual
) {
870 case FB_VISUAL_PSEUDOCOLOR
:
873 i740outb(info
->par
, VGA_PEL_IW
, regno
);
874 i740outb(info
->par
, VGA_PEL_D
, red
>> 8);
875 i740outb(info
->par
, VGA_PEL_D
, green
>> 8);
876 i740outb(info
->par
, VGA_PEL_D
, blue
>> 8);
878 case FB_VISUAL_TRUECOLOR
:
881 r
= (red
>> (16 - info
->var
.red
.length
))
882 << info
->var
.red
.offset
;
883 b
= (blue
>> (16 - info
->var
.blue
.length
))
884 << info
->var
.blue
.offset
;
885 g
= (green
>> (16 - info
->var
.green
.length
))
886 << info
->var
.green
.offset
;
887 ((u32
*) info
->pseudo_palette
)[regno
] = r
| g
| b
;
896 static int i740fb_pan_display(struct fb_var_screeninfo
*var
,
897 struct fb_info
*info
)
899 struct i740fb_par
*par
= info
->par
;
900 u32 base
= (var
->yoffset
* info
->var
.xres_virtual
901 + (var
->xoffset
& ~7)) >> 2;
903 dev_dbg(info
->device
, "pan_display: xoffset: %i yoffset: %i base: %i\n",
904 var
->xoffset
, var
->yoffset
, base
);
906 switch (info
->var
.bits_per_pixel
) {
915 * The last bit does not seem to have any effect on the start
916 * address register in 24bpp mode, so...
918 base
&= 0xFFFFFFFE; /* ...ignore the last bit. */
926 par
->crtc
[VGA_CRTC_START_LO
] = base
& 0x000000FF;
927 par
->crtc
[VGA_CRTC_START_HI
] = (base
& 0x0000FF00) >> 8;
928 par
->ext_start_addr_hi
= (base
& 0x3FC00000) >> 22;
929 par
->ext_start_addr
=
930 ((base
& 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE
;
932 i740outreg(par
, VGA_CRT_IC
, VGA_CRTC_START_LO
, base
& 0x000000FF);
933 i740outreg(par
, VGA_CRT_IC
, VGA_CRTC_START_HI
,
934 (base
& 0x0000FF00) >> 8);
935 i740outreg(par
, VGA_CRT_IC
, EXT_START_ADDR_HI
,
936 (base
& 0x3FC00000) >> 22);
937 i740outreg(par
, VGA_CRT_IC
, EXT_START_ADDR
,
938 ((base
& 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE
);
943 static int i740fb_blank(int blank_mode
, struct fb_info
*info
)
945 struct i740fb_par
*par
= info
->par
;
950 switch (blank_mode
) {
951 case FB_BLANK_UNBLANK
:
952 case FB_BLANK_NORMAL
:
954 DPMSSyncSelect
= HSYNC_ON
| VSYNC_ON
;
956 case FB_BLANK_VSYNC_SUSPEND
:
958 DPMSSyncSelect
= HSYNC_ON
| VSYNC_OFF
;
960 case FB_BLANK_HSYNC_SUSPEND
:
962 DPMSSyncSelect
= HSYNC_OFF
| VSYNC_ON
;
964 case FB_BLANK_POWERDOWN
:
966 DPMSSyncSelect
= HSYNC_OFF
| VSYNC_OFF
;
971 /* Turn the screen on/off */
972 i740outb(par
, SRX
, 0x01);
973 SEQ01
|= i740inb(par
, SRX
+ 1) & ~0x20;
974 i740outb(par
, SRX
, 0x01);
975 i740outb(par
, SRX
+ 1, SEQ01
);
977 /* Set the DPMS mode */
978 i740outreg(par
, XRX
, DPMS_SYNC_SELECT
, DPMSSyncSelect
);
980 /* Let fbcon do a soft blank for us */
981 return (blank_mode
== FB_BLANK_NORMAL
) ? 1 : 0;
984 static const struct fb_ops i740fb_ops
= {
985 .owner
= THIS_MODULE
,
986 .fb_open
= i740fb_open
,
987 .fb_release
= i740fb_release
,
988 .fb_check_var
= i740fb_check_var
,
989 .fb_set_par
= i740fb_set_par
,
990 .fb_setcolreg
= i740fb_setcolreg
,
991 .fb_blank
= i740fb_blank
,
992 .fb_pan_display
= i740fb_pan_display
,
993 .fb_fillrect
= cfb_fillrect
,
994 .fb_copyarea
= cfb_copyarea
,
995 .fb_imageblit
= cfb_imageblit
,
998 /* ------------------------------------------------------------------------- */
1000 static int i740fb_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1002 struct fb_info
*info
;
1003 struct i740fb_par
*par
;
1008 info
= framebuffer_alloc(sizeof(struct i740fb_par
), &(dev
->dev
));
1013 mutex_init(&par
->open_lock
);
1015 info
->var
.activate
= FB_ACTIVATE_NOW
;
1016 info
->var
.bits_per_pixel
= 8;
1017 info
->fbops
= &i740fb_ops
;
1018 info
->pseudo_palette
= par
->pseudo_palette
;
1020 ret
= pci_enable_device(dev
);
1022 dev_err(info
->device
, "cannot enable PCI device\n");
1023 goto err_enable_device
;
1026 ret
= pci_request_regions(dev
, info
->fix
.id
);
1028 dev_err(info
->device
, "error requesting regions\n");
1029 goto err_request_regions
;
1032 info
->screen_base
= pci_ioremap_wc_bar(dev
, 0);
1033 if (!info
->screen_base
) {
1034 dev_err(info
->device
, "error remapping base\n");
1039 par
->regs
= pci_ioremap_bar(dev
, 1);
1041 dev_err(info
->device
, "error remapping MMIO\n");
1046 /* detect memory size */
1047 if ((i740inreg(par
, XRX
, DRAM_ROW_TYPE
) & DRAM_ROW_1
)
1048 == DRAM_ROW_1_SDRAM
)
1049 i740outb(par
, XRX
, DRAM_ROW_BNDRY_1
);
1051 i740outb(par
, XRX
, DRAM_ROW_BNDRY_0
);
1052 info
->screen_size
= i740inb(par
, XRX
+ 1) * 1024 * 1024;
1053 /* detect memory type */
1054 tmp
= i740inreg(par
, XRX
, DRAM_ROW_CNTL_LO
);
1055 par
->has_sgram
= !((tmp
& DRAM_RAS_TIMING
) ||
1056 (tmp
& DRAM_RAS_PRECHARGE
));
1058 fb_info(info
, "Intel740 on %s, %ld KB %s\n",
1059 pci_name(dev
), info
->screen_size
>> 10,
1060 par
->has_sgram
? "SGRAM" : "SDRAM");
1062 info
->fix
= i740fb_fix
;
1063 info
->fix
.mmio_start
= pci_resource_start(dev
, 1);
1064 info
->fix
.mmio_len
= pci_resource_len(dev
, 1);
1065 info
->fix
.smem_start
= pci_resource_start(dev
, 0);
1066 info
->fix
.smem_len
= info
->screen_size
;
1067 info
->flags
= FBINFO_DEFAULT
| FBINFO_HWACCEL_YPAN
;
1069 if (i740fb_setup_ddc_bus(info
) == 0) {
1070 par
->ddc_registered
= true;
1071 edid
= fb_ddc_read(&par
->ddc_adapter
);
1073 fb_edid_to_monspecs(edid
, &info
->monspecs
);
1075 if (!info
->monspecs
.modedb
)
1076 dev_err(info
->device
,
1077 "error getting mode database\n");
1079 const struct fb_videomode
*m
;
1081 fb_videomode_to_modelist(
1082 info
->monspecs
.modedb
,
1083 info
->monspecs
.modedb_len
,
1085 m
= fb_find_best_display(&info
->monspecs
,
1088 fb_videomode_to_var(&info
->var
, m
);
1089 /* fill all other info->var's fields */
1090 if (!i740fb_check_var(&info
->var
, info
))
1097 if (!mode_option
&& !found
)
1098 mode_option
= "640x480-8@60";
1101 ret
= fb_find_mode(&info
->var
, info
, mode_option
,
1102 info
->monspecs
.modedb
,
1103 info
->monspecs
.modedb_len
,
1104 NULL
, info
->var
.bits_per_pixel
);
1105 if (!ret
|| ret
== 4) {
1106 dev_err(info
->device
, "mode %s not found\n",
1112 fb_destroy_modedb(info
->monspecs
.modedb
);
1113 info
->monspecs
.modedb
= NULL
;
1115 /* maximize virtual vertical size for fast scrolling */
1116 info
->var
.yres_virtual
= info
->fix
.smem_len
* 8 /
1117 (info
->var
.bits_per_pixel
* info
->var
.xres_virtual
);
1122 ret
= fb_alloc_cmap(&info
->cmap
, 256, 0);
1124 dev_err(info
->device
, "cannot allocate colormap\n");
1125 goto err_alloc_cmap
;
1128 ret
= register_framebuffer(info
);
1130 dev_err(info
->device
, "error registering framebuffer\n");
1131 goto err_reg_framebuffer
;
1134 fb_info(info
, "%s frame buffer device\n", info
->fix
.id
);
1135 pci_set_drvdata(dev
, info
);
1137 par
->wc_cookie
= arch_phys_wc_add(info
->fix
.smem_start
,
1138 info
->fix
.smem_len
);
1141 err_reg_framebuffer
:
1142 fb_dealloc_cmap(&info
->cmap
);
1145 if (par
->ddc_registered
)
1146 i2c_del_adapter(&par
->ddc_adapter
);
1147 pci_iounmap(dev
, par
->regs
);
1149 pci_iounmap(dev
, info
->screen_base
);
1151 pci_release_regions(dev
);
1152 err_request_regions
:
1153 /* pci_disable_device(dev); */
1155 framebuffer_release(info
);
1159 static void i740fb_remove(struct pci_dev
*dev
)
1161 struct fb_info
*info
= pci_get_drvdata(dev
);
1164 struct i740fb_par
*par
= info
->par
;
1165 arch_phys_wc_del(par
->wc_cookie
);
1166 unregister_framebuffer(info
);
1167 fb_dealloc_cmap(&info
->cmap
);
1168 if (par
->ddc_registered
)
1169 i2c_del_adapter(&par
->ddc_adapter
);
1170 pci_iounmap(dev
, par
->regs
);
1171 pci_iounmap(dev
, info
->screen_base
);
1172 pci_release_regions(dev
);
1173 /* pci_disable_device(dev); */
1174 framebuffer_release(info
);
1178 static int __maybe_unused
i740fb_suspend(struct device
*dev
)
1180 struct fb_info
*info
= dev_get_drvdata(dev
);
1181 struct i740fb_par
*par
= info
->par
;
1184 mutex_lock(&(par
->open_lock
));
1186 /* do nothing if framebuffer is not active */
1187 if (par
->ref_count
== 0) {
1188 mutex_unlock(&(par
->open_lock
));
1193 fb_set_suspend(info
, 1);
1195 mutex_unlock(&(par
->open_lock
));
1201 static int __maybe_unused
i740fb_resume(struct device
*dev
)
1203 struct fb_info
*info
= dev_get_drvdata(dev
);
1204 struct i740fb_par
*par
= info
->par
;
1207 mutex_lock(&(par
->open_lock
));
1209 if (par
->ref_count
== 0)
1212 i740fb_set_par(info
);
1213 fb_set_suspend(info
, 0);
1216 mutex_unlock(&(par
->open_lock
));
1221 static const struct dev_pm_ops i740fb_pm_ops
= {
1222 #ifdef CONFIG_PM_SLEEP
1223 .suspend
= i740fb_suspend
,
1224 .resume
= i740fb_resume
,
1226 .thaw
= i740fb_resume
,
1227 .poweroff
= i740fb_suspend
,
1228 .restore
= i740fb_resume
,
1229 #endif /* CONFIG_PM_SLEEP */
1232 #define I740_ID_PCI 0x00d1
1233 #define I740_ID_AGP 0x7800
1235 static const struct pci_device_id i740fb_id_table
[] = {
1236 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, I740_ID_PCI
) },
1237 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, I740_ID_AGP
) },
1240 MODULE_DEVICE_TABLE(pci
, i740fb_id_table
);
1242 static struct pci_driver i740fb_driver
= {
1244 .id_table
= i740fb_id_table
,
1245 .probe
= i740fb_probe
,
1246 .remove
= i740fb_remove
,
1247 .driver
.pm
= &i740fb_pm_ops
,
1251 static int __init
i740fb_setup(char *options
)
1255 if (!options
|| !*options
)
1258 while ((opt
= strsep(&options
, ",")) != NULL
) {
1261 else if (!strncmp(opt
, "mtrr:", 5))
1262 mtrr
= simple_strtoul(opt
+ 5, NULL
, 0);
1271 static int __init
i740fb_init(void)
1274 char *option
= NULL
;
1276 if (fb_get_options("i740fb", &option
))
1278 i740fb_setup(option
);
1281 return pci_register_driver(&i740fb_driver
);
1284 static void __exit
i740fb_exit(void)
1286 pci_unregister_driver(&i740fb_driver
);
1289 module_init(i740fb_init
);
1290 module_exit(i740fb_exit
);
1292 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1293 MODULE_LICENSE("GPL");
1294 MODULE_DESCRIPTION("fbdev driver for Intel740");
1296 module_param(mode_option
, charp
, 0444);
1297 MODULE_PARM_DESC(mode_option
, "Default video mode ('640x480-8@60', etc)");
1299 module_param(mtrr
, int, 0444);
1300 MODULE_PARM_DESC(mtrr
, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");