1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
4 * Copyright 2008 Openmoko Inc.
5 * Copyright 2008-2010 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
9 * Samsung SoC Framebuffer driver
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
21 #include <linux/uaccess.h>
22 #include <linux/interrupt.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/platform_data/video_s3c.h>
26 #include <video/samsung_fimd.h>
28 /* This driver will export a number of framebuffer interfaces depending
29 * on the configuration passed in via the platform data. Each fb instance
30 * maps to a hardware window. Currently there is no support for runtime
31 * setting of the alpha-blending functions that each window has, so only
32 * window 0 is actually useful.
34 * Window 0 is treated specially, it is used for the basis of the LCD
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
39 * has been replaced by using the platform device name to pick the correct
40 * configuration data for the system.
43 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
45 #define writel(v, r) do { \
46 pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
49 #endif /* FB_S3C_DEBUG_REGWRITE */
52 #define S3C_FB_VSYNC_IRQ_EN 0
54 #define VSYNC_TIMEOUT_MSEC 50
58 #define VALID_BPP(x) (1 << ((x) - 1))
60 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
61 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
62 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
63 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
64 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
67 * struct s3c_fb_variant - fb variant information
68 * @is_2443: Set if S3C2443/S3C2416 style hardware.
69 * @nr_windows: The number of windows.
70 * @vidtcon: The base for the VIDTCONx registers
71 * @wincon: The base for the WINxCON registers.
72 * @winmap: The base for the WINxMAP registers.
73 * @keycon: The abse for the WxKEYCON registers.
74 * @buf_start: Offset of buffer start registers.
75 * @buf_size: Offset of buffer size registers.
76 * @buf_end: Offset of buffer end registers.
77 * @osd: The base for the OSD registers.
78 * @palette: Address of palette memory, or 0 if none.
79 * @has_prtcon: Set if has PRTCON register.
80 * @has_shadowcon: Set if has SHADOWCON register.
81 * @has_blendcon: Set if has BLENDCON register.
82 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
83 * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
85 struct s3c_fb_variant
{
86 unsigned int is_2443
:1;
87 unsigned short nr_windows
;
89 unsigned short wincon
;
90 unsigned short winmap
;
91 unsigned short keycon
;
92 unsigned short buf_start
;
93 unsigned short buf_end
;
94 unsigned short buf_size
;
96 unsigned short osd_stride
;
97 unsigned short palette
[S3C_FB_MAX_WIN
];
99 unsigned int has_prtcon
:1;
100 unsigned int has_shadowcon
:1;
101 unsigned int has_blendcon
:1;
102 unsigned int has_clksel
:1;
103 unsigned int has_fixvclk
:1;
107 * struct s3c_fb_win_variant
108 * @has_osd_c: Set if has OSD C register.
109 * @has_osd_d: Set if has OSD D register.
110 * @has_osd_alpha: Set if can change alpha transparency for a window.
111 * @palette_sz: Size of palette in entries.
112 * @palette_16bpp: Set if palette is 16bits wide.
113 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
114 * register is located at the given offset from OSD_BASE.
115 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
117 * valid_bpp bit x is set if (x+1)BPP is supported.
119 struct s3c_fb_win_variant
{
120 unsigned int has_osd_c
:1;
121 unsigned int has_osd_d
:1;
122 unsigned int has_osd_alpha
:1;
123 unsigned int palette_16bpp
:1;
124 unsigned short osd_size_off
;
125 unsigned short palette_sz
;
130 * struct s3c_fb_driverdata - per-device type driver data for init time.
131 * @variant: The variant information for this driver.
132 * @win: The window information for each window.
134 struct s3c_fb_driverdata
{
135 struct s3c_fb_variant variant
;
136 struct s3c_fb_win_variant
*win
[S3C_FB_MAX_WIN
];
140 * struct s3c_fb_palette - palette information
142 * @g: Green bitfield.
144 * @a: Alpha bitfield.
146 struct s3c_fb_palette
{
147 struct fb_bitfield r
;
148 struct fb_bitfield g
;
149 struct fb_bitfield b
;
150 struct fb_bitfield a
;
154 * struct s3c_fb_win - per window private data for each framebuffer.
155 * @windata: The platform data supplied for the window configuration.
156 * @parent: The hardware that this window is part of.
157 * @fbinfo: Pointer pack to the framebuffer info for this window.
158 * @varint: The variant information for this window.
159 * @palette_buffer: Buffer/cache to hold palette entries.
160 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
161 * @index: The window number of this window.
162 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
165 struct s3c_fb_pd_win
*windata
;
166 struct s3c_fb
*parent
;
167 struct fb_info
*fbinfo
;
168 struct s3c_fb_palette palette
;
169 struct s3c_fb_win_variant variant
;
172 u32 pseudo_palette
[16];
177 * struct s3c_fb_vsync - vsync information
178 * @wait: a queue for processes waiting for vsync
179 * @count: vsync interrupt count
181 struct s3c_fb_vsync
{
182 wait_queue_head_t wait
;
187 * struct s3c_fb - overall hardware state of the hardware
188 * @slock: The spinlock protection for this data structure.
189 * @dev: The device that we bound to, for printing, etc.
190 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
191 * @lcd_clk: The clk (sclk) feeding pixclk.
192 * @regs: The mapped hardware registers.
193 * @variant: Variant information for this hardware.
194 * @enabled: A bitmask of enabled hardware windows.
195 * @output_on: Flag if the physical output is enabled.
196 * @pdata: The platform configuration data passed with the device.
197 * @windows: The hardware windows that have been claimed.
198 * @irq_no: IRQ line number
199 * @irq_flags: irq flags
200 * @vsync_info: VSYNC-related information (count, queues...)
208 struct s3c_fb_variant variant
;
210 unsigned char enabled
;
213 struct s3c_fb_platdata
*pdata
;
214 struct s3c_fb_win
*windows
[S3C_FB_MAX_WIN
];
217 unsigned long irq_flags
;
218 struct s3c_fb_vsync vsync_info
;
222 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
223 * @win: The device window.
224 * @bpp: The bit depth.
226 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win
*win
, unsigned int bpp
)
228 return win
->variant
.valid_bpp
& VALID_BPP(bpp
);
232 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
233 * @var: The screen information to verify.
234 * @info: The framebuffer device.
236 * Framebuffer layer call to verify the given information and allow us to
237 * update various information depending on the hardware capabilities.
239 static int s3c_fb_check_var(struct fb_var_screeninfo
*var
,
240 struct fb_info
*info
)
242 struct s3c_fb_win
*win
= info
->par
;
243 struct s3c_fb
*sfb
= win
->parent
;
245 dev_dbg(sfb
->dev
, "checking parameters\n");
247 var
->xres_virtual
= max(var
->xres_virtual
, var
->xres
);
248 var
->yres_virtual
= max(var
->yres_virtual
, var
->yres
);
250 if (!s3c_fb_validate_win_bpp(win
, var
->bits_per_pixel
)) {
251 dev_dbg(sfb
->dev
, "win %d: unsupported bpp %d\n",
252 win
->index
, var
->bits_per_pixel
);
256 /* always ensure these are zero, for drop through cases below */
257 var
->transp
.offset
= 0;
258 var
->transp
.length
= 0;
260 switch (var
->bits_per_pixel
) {
265 if (sfb
->variant
.palette
[win
->index
] != 0) {
266 /* non palletised, A:1,R:2,G:3,B:2 mode */
268 var
->green
.offset
= 2;
269 var
->blue
.offset
= 0;
271 var
->green
.length
= 3;
272 var
->blue
.length
= 2;
273 var
->transp
.offset
= 7;
274 var
->transp
.length
= 1;
277 var
->red
.length
= var
->bits_per_pixel
;
278 var
->green
= var
->red
;
279 var
->blue
= var
->red
;
284 /* 666 with one bit alpha/transparency */
285 var
->transp
.offset
= 18;
286 var
->transp
.length
= 1;
289 var
->bits_per_pixel
= 32;
292 var
->red
.offset
= 12;
293 var
->green
.offset
= 6;
294 var
->blue
.offset
= 0;
296 var
->green
.length
= 6;
297 var
->blue
.length
= 6;
301 /* 16 bpp, 565 format */
302 var
->red
.offset
= 11;
303 var
->green
.offset
= 5;
304 var
->blue
.offset
= 0;
306 var
->green
.length
= 6;
307 var
->blue
.length
= 5;
313 var
->transp
.length
= var
->bits_per_pixel
- 24;
314 var
->transp
.offset
= 24;
317 /* our 24bpp is unpacked, so 32bpp */
318 var
->bits_per_pixel
= 32;
319 var
->red
.offset
= 16;
321 var
->green
.offset
= 8;
322 var
->green
.length
= 8;
323 var
->blue
.offset
= 0;
324 var
->blue
.length
= 8;
328 dev_err(sfb
->dev
, "invalid bpp\n");
332 dev_dbg(sfb
->dev
, "%s: verified parameters\n", __func__
);
337 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
338 * @sfb: The hardware state.
339 * @pixclock: The pixel clock wanted, in picoseconds.
341 * Given the specified pixel clock, work out the necessary divider to get
342 * close to the output frequency.
344 static int s3c_fb_calc_pixclk(struct s3c_fb
*sfb
, unsigned int pixclk
)
347 unsigned long long tmp
;
350 if (sfb
->variant
.has_clksel
)
351 clk
= clk_get_rate(sfb
->bus_clk
);
353 clk
= clk_get_rate(sfb
->lcd_clk
);
355 tmp
= (unsigned long long)clk
;
358 do_div(tmp
, 1000000000UL);
359 result
= (unsigned int)tmp
/ 1000;
361 dev_dbg(sfb
->dev
, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
362 pixclk
, clk
, result
, result
? clk
/ result
: clk
);
368 * s3c_fb_align_word() - align pixel count to word boundary
369 * @bpp: The number of bits per pixel
370 * @pix: The value to be aligned.
372 * Align the given pixel count so that it will start on an 32bit word
375 static int s3c_fb_align_word(unsigned int bpp
, unsigned int pix
)
382 pix_per_word
= (8 * 32) / bpp
;
383 return ALIGN(pix
, pix_per_word
);
387 * vidosd_set_size() - set OSD size for a window
389 * @win: the window to set OSD size for
390 * @size: OSD size register value
392 static void vidosd_set_size(struct s3c_fb_win
*win
, u32 size
)
394 struct s3c_fb
*sfb
= win
->parent
;
396 /* OSD can be set up if osd_size_off != 0 for this window */
397 if (win
->variant
.osd_size_off
)
398 writel(size
, sfb
->regs
+ OSD_BASE(win
->index
, sfb
->variant
)
399 + win
->variant
.osd_size_off
);
403 * vidosd_set_alpha() - set alpha transparency for a window
405 * @win: the window to set OSD size for
406 * @alpha: alpha register value
408 static void vidosd_set_alpha(struct s3c_fb_win
*win
, u32 alpha
)
410 struct s3c_fb
*sfb
= win
->parent
;
412 if (win
->variant
.has_osd_alpha
)
413 writel(alpha
, sfb
->regs
+ VIDOSD_C(win
->index
, sfb
->variant
));
417 * shadow_protect_win() - disable updating values from shadow registers at vsync
419 * @win: window to protect registers for
420 * @protect: 1 to protect (disable updates)
422 static void shadow_protect_win(struct s3c_fb_win
*win
, bool protect
)
424 struct s3c_fb
*sfb
= win
->parent
;
428 if (sfb
->variant
.has_prtcon
) {
429 writel(PRTCON_PROTECT
, sfb
->regs
+ PRTCON
);
430 } else if (sfb
->variant
.has_shadowcon
) {
431 reg
= readl(sfb
->regs
+ SHADOWCON
);
432 writel(reg
| SHADOWCON_WINx_PROTECT(win
->index
),
433 sfb
->regs
+ SHADOWCON
);
436 if (sfb
->variant
.has_prtcon
) {
437 writel(0, sfb
->regs
+ PRTCON
);
438 } else if (sfb
->variant
.has_shadowcon
) {
439 reg
= readl(sfb
->regs
+ SHADOWCON
);
440 writel(reg
& ~SHADOWCON_WINx_PROTECT(win
->index
),
441 sfb
->regs
+ SHADOWCON
);
447 * s3c_fb_enable() - Set the state of the main LCD output
448 * @sfb: The main framebuffer state.
449 * @enable: The state to set.
451 static void s3c_fb_enable(struct s3c_fb
*sfb
, int enable
)
453 u32 vidcon0
= readl(sfb
->regs
+ VIDCON0
);
455 if (enable
&& !sfb
->output_on
)
456 pm_runtime_get_sync(sfb
->dev
);
459 vidcon0
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
461 /* see the note in the framebuffer datasheet about
462 * why you cannot take both of these bits down at the
465 if (vidcon0
& VIDCON0_ENVID
) {
466 vidcon0
|= VIDCON0_ENVID
;
467 vidcon0
&= ~VIDCON0_ENVID_F
;
471 writel(vidcon0
, sfb
->regs
+ VIDCON0
);
473 if (!enable
&& sfb
->output_on
)
474 pm_runtime_put_sync(sfb
->dev
);
476 sfb
->output_on
= enable
;
480 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
481 * @info: The framebuffer to change.
483 * Framebuffer layer request to set a new mode for the specified framebuffer
485 static int s3c_fb_set_par(struct fb_info
*info
)
487 struct fb_var_screeninfo
*var
= &info
->var
;
488 struct s3c_fb_win
*win
= info
->par
;
489 struct s3c_fb
*sfb
= win
->parent
;
490 void __iomem
*regs
= sfb
->regs
;
491 void __iomem
*buf
= regs
;
492 int win_no
= win
->index
;
497 dev_dbg(sfb
->dev
, "setting framebuffer parameters\n");
499 pm_runtime_get_sync(sfb
->dev
);
501 shadow_protect_win(win
, 1);
503 switch (var
->bits_per_pixel
) {
508 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
511 if (win
->variant
.palette_sz
>= 256)
512 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
514 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
517 info
->fix
.visual
= FB_VISUAL_MONO01
;
520 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
524 info
->fix
.line_length
= (var
->xres_virtual
* var
->bits_per_pixel
) / 8;
526 info
->fix
.xpanstep
= info
->var
.xres_virtual
> info
->var
.xres
? 1 : 0;
527 info
->fix
.ypanstep
= info
->var
.yres_virtual
> info
->var
.yres
? 1 : 0;
529 /* disable the window whilst we update it */
530 writel(0, regs
+ WINCON(win_no
));
533 s3c_fb_enable(sfb
, 1);
535 /* write the buffer address */
537 /* start and end registers stride is 8 */
538 buf
= regs
+ win_no
* 8;
540 writel(info
->fix
.smem_start
, buf
+ sfb
->variant
.buf_start
);
542 data
= info
->fix
.smem_start
+ info
->fix
.line_length
* var
->yres
;
543 writel(data
, buf
+ sfb
->variant
.buf_end
);
545 pagewidth
= (var
->xres
* var
->bits_per_pixel
) >> 3;
546 data
= VIDW_BUF_SIZE_OFFSET(info
->fix
.line_length
- pagewidth
) |
547 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth
) |
548 VIDW_BUF_SIZE_OFFSET_E(info
->fix
.line_length
- pagewidth
) |
549 VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth
);
550 writel(data
, regs
+ sfb
->variant
.buf_size
+ (win_no
* 4));
552 /* write 'OSD' registers to control position of framebuffer */
554 data
= VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
555 VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
556 writel(data
, regs
+ VIDOSD_A(win_no
, sfb
->variant
));
558 data
= VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var
->bits_per_pixel
,
560 VIDOSDxB_BOTRIGHT_Y(var
->yres
- 1) |
561 VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var
->bits_per_pixel
,
563 VIDOSDxB_BOTRIGHT_Y_E(var
->yres
- 1);
565 writel(data
, regs
+ VIDOSD_B(win_no
, sfb
->variant
));
567 data
= var
->xres
* var
->yres
;
569 alpha
= VIDISD14C_ALPHA1_R(0xf) |
570 VIDISD14C_ALPHA1_G(0xf) |
571 VIDISD14C_ALPHA1_B(0xf);
573 vidosd_set_alpha(win
, alpha
);
574 vidosd_set_size(win
, data
);
576 /* Enable DMA channel for this window */
577 if (sfb
->variant
.has_shadowcon
) {
578 data
= readl(sfb
->regs
+ SHADOWCON
);
579 data
|= SHADOWCON_CHx_ENABLE(win_no
);
580 writel(data
, sfb
->regs
+ SHADOWCON
);
583 data
= WINCONx_ENWIN
;
584 sfb
->enabled
|= (1 << win
->index
);
586 /* note, since we have to round up the bits-per-pixel, we end up
587 * relying on the bitfield information for r/g/b/a to work out
588 * exactly which mode of operation is intended. */
590 switch (var
->bits_per_pixel
) {
592 data
|= WINCON0_BPPMODE_1BPP
;
593 data
|= WINCONx_BITSWP
;
594 data
|= WINCONx_BURSTLEN_4WORD
;
597 data
|= WINCON0_BPPMODE_2BPP
;
598 data
|= WINCONx_BITSWP
;
599 data
|= WINCONx_BURSTLEN_8WORD
;
602 data
|= WINCON0_BPPMODE_4BPP
;
603 data
|= WINCONx_BITSWP
;
604 data
|= WINCONx_BURSTLEN_8WORD
;
607 if (var
->transp
.length
!= 0)
608 data
|= WINCON1_BPPMODE_8BPP_1232
;
610 data
|= WINCON0_BPPMODE_8BPP_PALETTE
;
611 data
|= WINCONx_BURSTLEN_8WORD
;
612 data
|= WINCONx_BYTSWP
;
615 if (var
->transp
.length
!= 0)
616 data
|= WINCON1_BPPMODE_16BPP_A1555
;
618 data
|= WINCON0_BPPMODE_16BPP_565
;
619 data
|= WINCONx_HAWSWP
;
620 data
|= WINCONx_BURSTLEN_16WORD
;
624 if (var
->red
.length
== 6) {
625 if (var
->transp
.length
!= 0)
626 data
|= WINCON1_BPPMODE_19BPP_A1666
;
628 data
|= WINCON1_BPPMODE_18BPP_666
;
629 } else if (var
->transp
.length
== 1)
630 data
|= WINCON1_BPPMODE_25BPP_A1888
632 else if ((var
->transp
.length
== 4) ||
633 (var
->transp
.length
== 8))
634 data
|= WINCON1_BPPMODE_28BPP_A4888
635 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
637 data
|= WINCON0_BPPMODE_24BPP_888
;
639 data
|= WINCONx_WSWP
;
640 data
|= WINCONx_BURSTLEN_16WORD
;
644 /* Enable the colour keying for the window below this one */
646 u32 keycon0_data
= 0, keycon1_data
= 0;
647 void __iomem
*keycon
= regs
+ sfb
->variant
.keycon
;
649 keycon0_data
= ~(WxKEYCON0_KEYBL_EN
|
651 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
653 keycon1_data
= WxKEYCON1_COLVAL(0xffffff);
655 keycon
+= (win_no
- 1) * 8;
657 writel(keycon0_data
, keycon
+ WKEYCON0
);
658 writel(keycon1_data
, keycon
+ WKEYCON1
);
661 writel(data
, regs
+ sfb
->variant
.wincon
+ (win_no
* 4));
662 writel(0x0, regs
+ sfb
->variant
.winmap
+ (win_no
* 4));
664 /* Set alpha value width */
665 if (sfb
->variant
.has_blendcon
) {
666 data
= readl(sfb
->regs
+ BLENDCON
);
667 data
&= ~BLENDCON_NEW_MASK
;
668 if (var
->transp
.length
> 4)
669 data
|= BLENDCON_NEW_8BIT_ALPHA_VALUE
;
671 data
|= BLENDCON_NEW_4BIT_ALPHA_VALUE
;
672 writel(data
, sfb
->regs
+ BLENDCON
);
675 shadow_protect_win(win
, 0);
677 pm_runtime_put_sync(sfb
->dev
);
683 * s3c_fb_update_palette() - set or schedule a palette update.
684 * @sfb: The hardware information.
685 * @win: The window being updated.
686 * @reg: The palette index being changed.
687 * @value: The computed palette value.
689 * Change the value of a palette register, either by directly writing to
690 * the palette (this requires the palette RAM to be disconnected from the
691 * hardware whilst this is in progress) or schedule the update for later.
693 * At the moment, since we have no VSYNC interrupt support, we simply set
694 * the palette entry directly.
696 static void s3c_fb_update_palette(struct s3c_fb
*sfb
,
697 struct s3c_fb_win
*win
,
701 void __iomem
*palreg
;
704 palreg
= sfb
->regs
+ sfb
->variant
.palette
[win
->index
];
706 dev_dbg(sfb
->dev
, "%s: win %d, reg %d (%p): %08x\n",
707 __func__
, win
->index
, reg
, palreg
, value
);
709 win
->palette_buffer
[reg
] = value
;
711 palcon
= readl(sfb
->regs
+ WPALCON
);
712 writel(palcon
| WPALCON_PAL_UPDATE
, sfb
->regs
+ WPALCON
);
714 if (win
->variant
.palette_16bpp
)
715 writew(value
, palreg
+ (reg
* 2));
717 writel(value
, palreg
+ (reg
* 4));
719 writel(palcon
, sfb
->regs
+ WPALCON
);
722 static inline unsigned int chan_to_field(unsigned int chan
,
723 struct fb_bitfield
*bf
)
726 chan
>>= 16 - bf
->length
;
727 return chan
<< bf
->offset
;
731 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
732 * @regno: The palette index to change.
733 * @red: The red field for the palette data.
734 * @green: The green field for the palette data.
735 * @blue: The blue field for the palette data.
736 * @trans: The transparency (alpha) field for the palette data.
737 * @info: The framebuffer being changed.
739 static int s3c_fb_setcolreg(unsigned regno
,
740 unsigned red
, unsigned green
, unsigned blue
,
741 unsigned transp
, struct fb_info
*info
)
743 struct s3c_fb_win
*win
= info
->par
;
744 struct s3c_fb
*sfb
= win
->parent
;
747 dev_dbg(sfb
->dev
, "%s: win %d: %d => rgb=%d/%d/%d\n",
748 __func__
, win
->index
, regno
, red
, green
, blue
);
750 pm_runtime_get_sync(sfb
->dev
);
752 switch (info
->fix
.visual
) {
753 case FB_VISUAL_TRUECOLOR
:
754 /* true-colour, use pseudo-palette */
757 u32
*pal
= info
->pseudo_palette
;
759 val
= chan_to_field(red
, &info
->var
.red
);
760 val
|= chan_to_field(green
, &info
->var
.green
);
761 val
|= chan_to_field(blue
, &info
->var
.blue
);
767 case FB_VISUAL_PSEUDOCOLOR
:
768 if (regno
< win
->variant
.palette_sz
) {
769 val
= chan_to_field(red
, &win
->palette
.r
);
770 val
|= chan_to_field(green
, &win
->palette
.g
);
771 val
|= chan_to_field(blue
, &win
->palette
.b
);
773 s3c_fb_update_palette(sfb
, win
, regno
, val
);
779 pm_runtime_put_sync(sfb
->dev
);
780 return 1; /* unknown type */
783 pm_runtime_put_sync(sfb
->dev
);
788 * s3c_fb_blank() - blank or unblank the given window
789 * @blank_mode: The blank state from FB_BLANK_*
790 * @info: The framebuffer to blank.
792 * Framebuffer layer request to change the power state.
794 static int s3c_fb_blank(int blank_mode
, struct fb_info
*info
)
796 struct s3c_fb_win
*win
= info
->par
;
797 struct s3c_fb
*sfb
= win
->parent
;
798 unsigned int index
= win
->index
;
800 u32 output_on
= sfb
->output_on
;
802 dev_dbg(sfb
->dev
, "blank mode %d\n", blank_mode
);
804 pm_runtime_get_sync(sfb
->dev
);
806 wincon
= readl(sfb
->regs
+ sfb
->variant
.wincon
+ (index
* 4));
808 switch (blank_mode
) {
809 case FB_BLANK_POWERDOWN
:
810 wincon
&= ~WINCONx_ENWIN
;
811 sfb
->enabled
&= ~(1 << index
);
812 fallthrough
; /* to FB_BLANK_NORMAL */
814 case FB_BLANK_NORMAL
:
815 /* disable the DMA and display 0x0 (black) */
816 shadow_protect_win(win
, 1);
817 writel(WINxMAP_MAP
| WINxMAP_MAP_COLOUR(0x0),
818 sfb
->regs
+ sfb
->variant
.winmap
+ (index
* 4));
819 shadow_protect_win(win
, 0);
822 case FB_BLANK_UNBLANK
:
823 shadow_protect_win(win
, 1);
824 writel(0x0, sfb
->regs
+ sfb
->variant
.winmap
+ (index
* 4));
825 shadow_protect_win(win
, 0);
826 wincon
|= WINCONx_ENWIN
;
827 sfb
->enabled
|= (1 << index
);
830 case FB_BLANK_VSYNC_SUSPEND
:
831 case FB_BLANK_HSYNC_SUSPEND
:
833 pm_runtime_put_sync(sfb
->dev
);
837 shadow_protect_win(win
, 1);
838 writel(wincon
, sfb
->regs
+ sfb
->variant
.wincon
+ (index
* 4));
840 /* Check the enabled state to see if we need to be running the
841 * main LCD interface, as if there are no active windows then
842 * it is highly likely that we also do not need to output
845 s3c_fb_enable(sfb
, sfb
->enabled
? 1 : 0);
846 shadow_protect_win(win
, 0);
848 pm_runtime_put_sync(sfb
->dev
);
850 return output_on
== sfb
->output_on
;
854 * s3c_fb_pan_display() - Pan the display.
856 * Note that the offsets can be written to the device at any time, as their
857 * values are latched at each vsync automatically. This also means that only
858 * the last call to this function will have any effect on next vsync, but
859 * there is no need to sleep waiting for it to prevent tearing.
861 * @var: The screen information to verify.
862 * @info: The framebuffer device.
864 static int s3c_fb_pan_display(struct fb_var_screeninfo
*var
,
865 struct fb_info
*info
)
867 struct s3c_fb_win
*win
= info
->par
;
868 struct s3c_fb
*sfb
= win
->parent
;
869 void __iomem
*buf
= sfb
->regs
+ win
->index
* 8;
870 unsigned int start_boff
, end_boff
;
872 pm_runtime_get_sync(sfb
->dev
);
874 /* Offset in bytes to the start of the displayed area */
875 start_boff
= var
->yoffset
* info
->fix
.line_length
;
876 /* X offset depends on the current bpp */
877 if (info
->var
.bits_per_pixel
>= 8) {
878 start_boff
+= var
->xoffset
* (info
->var
.bits_per_pixel
>> 3);
880 switch (info
->var
.bits_per_pixel
) {
882 start_boff
+= var
->xoffset
>> 1;
885 start_boff
+= var
->xoffset
>> 2;
888 start_boff
+= var
->xoffset
>> 3;
891 dev_err(sfb
->dev
, "invalid bpp\n");
892 pm_runtime_put_sync(sfb
->dev
);
896 /* Offset in bytes to the end of the displayed area */
897 end_boff
= start_boff
+ info
->var
.yres
* info
->fix
.line_length
;
899 /* Temporarily turn off per-vsync update from shadow registers until
900 * both start and end addresses are updated to prevent corruption */
901 shadow_protect_win(win
, 1);
903 writel(info
->fix
.smem_start
+ start_boff
, buf
+ sfb
->variant
.buf_start
);
904 writel(info
->fix
.smem_start
+ end_boff
, buf
+ sfb
->variant
.buf_end
);
906 shadow_protect_win(win
, 0);
908 pm_runtime_put_sync(sfb
->dev
);
913 * s3c_fb_enable_irq() - enable framebuffer interrupts
914 * @sfb: main hardware state
916 static void s3c_fb_enable_irq(struct s3c_fb
*sfb
)
918 void __iomem
*regs
= sfb
->regs
;
921 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN
, &sfb
->irq_flags
)) {
922 /* IRQ disabled, enable it */
923 irq_ctrl_reg
= readl(regs
+ VIDINTCON0
);
925 irq_ctrl_reg
|= VIDINTCON0_INT_ENABLE
;
926 irq_ctrl_reg
|= VIDINTCON0_INT_FRAME
;
928 irq_ctrl_reg
&= ~VIDINTCON0_FRAMESEL0_MASK
;
929 irq_ctrl_reg
|= VIDINTCON0_FRAMESEL0_VSYNC
;
930 irq_ctrl_reg
&= ~VIDINTCON0_FRAMESEL1_MASK
;
931 irq_ctrl_reg
|= VIDINTCON0_FRAMESEL1_NONE
;
933 writel(irq_ctrl_reg
, regs
+ VIDINTCON0
);
938 * s3c_fb_disable_irq() - disable framebuffer interrupts
939 * @sfb: main hardware state
941 static void s3c_fb_disable_irq(struct s3c_fb
*sfb
)
943 void __iomem
*regs
= sfb
->regs
;
946 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN
, &sfb
->irq_flags
)) {
947 /* IRQ enabled, disable it */
948 irq_ctrl_reg
= readl(regs
+ VIDINTCON0
);
950 irq_ctrl_reg
&= ~VIDINTCON0_INT_FRAME
;
951 irq_ctrl_reg
&= ~VIDINTCON0_INT_ENABLE
;
953 writel(irq_ctrl_reg
, regs
+ VIDINTCON0
);
957 static irqreturn_t
s3c_fb_irq(int irq
, void *dev_id
)
959 struct s3c_fb
*sfb
= dev_id
;
960 void __iomem
*regs
= sfb
->regs
;
963 spin_lock(&sfb
->slock
);
965 irq_sts_reg
= readl(regs
+ VIDINTCON1
);
967 if (irq_sts_reg
& VIDINTCON1_INT_FRAME
) {
969 /* VSYNC interrupt, accept it */
970 writel(VIDINTCON1_INT_FRAME
, regs
+ VIDINTCON1
);
972 sfb
->vsync_info
.count
++;
973 wake_up_interruptible(&sfb
->vsync_info
.wait
);
976 /* We only support waiting for VSYNC for now, so it's safe
977 * to always disable irqs here.
979 s3c_fb_disable_irq(sfb
);
981 spin_unlock(&sfb
->slock
);
986 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
987 * @sfb: main hardware state
990 static int s3c_fb_wait_for_vsync(struct s3c_fb
*sfb
, u32 crtc
)
998 pm_runtime_get_sync(sfb
->dev
);
1000 count
= sfb
->vsync_info
.count
;
1001 s3c_fb_enable_irq(sfb
);
1002 ret
= wait_event_interruptible_timeout(sfb
->vsync_info
.wait
,
1003 count
!= sfb
->vsync_info
.count
,
1004 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC
));
1006 pm_runtime_put_sync(sfb
->dev
);
1014 static int s3c_fb_ioctl(struct fb_info
*info
, unsigned int cmd
,
1017 struct s3c_fb_win
*win
= info
->par
;
1018 struct s3c_fb
*sfb
= win
->parent
;
1023 case FBIO_WAITFORVSYNC
:
1024 if (get_user(crtc
, (u32 __user
*)arg
)) {
1029 ret
= s3c_fb_wait_for_vsync(sfb
, crtc
);
1038 static const struct fb_ops s3c_fb_ops
= {
1039 .owner
= THIS_MODULE
,
1040 .fb_check_var
= s3c_fb_check_var
,
1041 .fb_set_par
= s3c_fb_set_par
,
1042 .fb_blank
= s3c_fb_blank
,
1043 .fb_setcolreg
= s3c_fb_setcolreg
,
1044 .fb_fillrect
= cfb_fillrect
,
1045 .fb_copyarea
= cfb_copyarea
,
1046 .fb_imageblit
= cfb_imageblit
,
1047 .fb_pan_display
= s3c_fb_pan_display
,
1048 .fb_ioctl
= s3c_fb_ioctl
,
1052 * s3c_fb_missing_pixclock() - calculates pixel clock
1053 * @mode: The video mode to change.
1055 * Calculate the pixel clock when none has been given through platform data.
1057 static void s3c_fb_missing_pixclock(struct fb_videomode
*mode
)
1059 u64 pixclk
= 1000000000000ULL;
1062 div
= mode
->left_margin
+ mode
->hsync_len
+ mode
->right_margin
+
1064 div
*= mode
->upper_margin
+ mode
->vsync_len
+ mode
->lower_margin
+
1066 div
*= mode
->refresh
? : 60;
1068 do_div(pixclk
, div
);
1070 mode
->pixclock
= pixclk
;
1074 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1075 * @sfb: The base resources for the hardware.
1076 * @win: The window to initialise memory for.
1078 * Allocate memory for the given framebuffer.
1080 static int s3c_fb_alloc_memory(struct s3c_fb
*sfb
, struct s3c_fb_win
*win
)
1082 struct s3c_fb_pd_win
*windata
= win
->windata
;
1083 unsigned int real_size
, virt_size
, size
;
1084 struct fb_info
*fbi
= win
->fbinfo
;
1087 dev_dbg(sfb
->dev
, "allocating memory for display\n");
1089 real_size
= windata
->xres
* windata
->yres
;
1090 virt_size
= windata
->virtual_x
* windata
->virtual_y
;
1092 dev_dbg(sfb
->dev
, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1093 real_size
, windata
->xres
, windata
->yres
,
1094 virt_size
, windata
->virtual_x
, windata
->virtual_y
);
1096 size
= (real_size
> virt_size
) ? real_size
: virt_size
;
1097 size
*= (windata
->max_bpp
> 16) ? 32 : windata
->max_bpp
;
1100 fbi
->fix
.smem_len
= size
;
1101 size
= PAGE_ALIGN(size
);
1103 dev_dbg(sfb
->dev
, "want %u bytes for window\n", size
);
1105 fbi
->screen_buffer
= dma_alloc_wc(sfb
->dev
, size
, &map_dma
, GFP_KERNEL
);
1106 if (!fbi
->screen_buffer
)
1109 dev_dbg(sfb
->dev
, "mapped %x to %p\n",
1110 (unsigned int)map_dma
, fbi
->screen_buffer
);
1112 memset(fbi
->screen_buffer
, 0x0, size
);
1113 fbi
->fix
.smem_start
= map_dma
;
1119 * s3c_fb_free_memory() - free the display memory for the given window
1120 * @sfb: The base resources for the hardware.
1121 * @win: The window to free the display memory for.
1123 * Free the display memory allocated by s3c_fb_alloc_memory().
1125 static void s3c_fb_free_memory(struct s3c_fb
*sfb
, struct s3c_fb_win
*win
)
1127 struct fb_info
*fbi
= win
->fbinfo
;
1129 if (fbi
->screen_buffer
)
1130 dma_free_wc(sfb
->dev
, PAGE_ALIGN(fbi
->fix
.smem_len
),
1131 fbi
->screen_buffer
, fbi
->fix
.smem_start
);
1135 * s3c_fb_release_win() - release resources for a framebuffer window.
1136 * @win: The window to cleanup the resources for.
1138 * Release the resources that where claimed for the hardware window,
1139 * such as the framebuffer instance and any memory claimed for it.
1141 static void s3c_fb_release_win(struct s3c_fb
*sfb
, struct s3c_fb_win
*win
)
1146 if (sfb
->variant
.has_shadowcon
) {
1147 data
= readl(sfb
->regs
+ SHADOWCON
);
1148 data
&= ~SHADOWCON_CHx_ENABLE(win
->index
);
1149 data
&= ~SHADOWCON_CHx_LOCAL_ENABLE(win
->index
);
1150 writel(data
, sfb
->regs
+ SHADOWCON
);
1152 unregister_framebuffer(win
->fbinfo
);
1153 if (win
->fbinfo
->cmap
.len
)
1154 fb_dealloc_cmap(&win
->fbinfo
->cmap
);
1155 s3c_fb_free_memory(sfb
, win
);
1156 framebuffer_release(win
->fbinfo
);
1161 * s3c_fb_probe_win() - register an hardware window
1162 * @sfb: The base resources for the hardware
1163 * @variant: The variant information for this window.
1164 * @res: Pointer to where to place the resultant window.
1166 * Allocate and do the basic initialisation for one of the hardware's graphics
1169 static int s3c_fb_probe_win(struct s3c_fb
*sfb
, unsigned int win_no
,
1170 struct s3c_fb_win_variant
*variant
,
1171 struct s3c_fb_win
**res
)
1173 struct fb_var_screeninfo
*var
;
1174 struct fb_videomode initmode
;
1175 struct s3c_fb_pd_win
*windata
;
1176 struct s3c_fb_win
*win
;
1177 struct fb_info
*fbinfo
;
1181 dev_dbg(sfb
->dev
, "probing window %d, variant %p\n", win_no
, variant
);
1183 init_waitqueue_head(&sfb
->vsync_info
.wait
);
1185 palette_size
= variant
->palette_sz
* 4;
1187 fbinfo
= framebuffer_alloc(sizeof(struct s3c_fb_win
) +
1188 palette_size
* sizeof(u32
), sfb
->dev
);
1192 windata
= sfb
->pdata
->win
[win_no
];
1193 initmode
= *sfb
->pdata
->vtiming
;
1195 WARN_ON(windata
->max_bpp
== 0);
1196 WARN_ON(windata
->xres
== 0);
1197 WARN_ON(windata
->yres
== 0);
1202 win
->variant
= *variant
;
1203 win
->fbinfo
= fbinfo
;
1205 win
->windata
= windata
;
1206 win
->index
= win_no
;
1207 win
->palette_buffer
= (u32
*)(win
+ 1);
1209 ret
= s3c_fb_alloc_memory(sfb
, win
);
1211 dev_err(sfb
->dev
, "failed to allocate display memory\n");
1215 /* setup the r/b/g positions for the window's palette */
1216 if (win
->variant
.palette_16bpp
) {
1217 /* Set RGB 5:6:5 as default */
1218 win
->palette
.r
.offset
= 11;
1219 win
->palette
.r
.length
= 5;
1220 win
->palette
.g
.offset
= 5;
1221 win
->palette
.g
.length
= 6;
1222 win
->palette
.b
.offset
= 0;
1223 win
->palette
.b
.length
= 5;
1226 /* Set 8bpp or 8bpp and 1bit alpha */
1227 win
->palette
.r
.offset
= 16;
1228 win
->palette
.r
.length
= 8;
1229 win
->palette
.g
.offset
= 8;
1230 win
->palette
.g
.length
= 8;
1231 win
->palette
.b
.offset
= 0;
1232 win
->palette
.b
.length
= 8;
1235 /* setup the initial video mode from the window */
1236 initmode
.xres
= windata
->xres
;
1237 initmode
.yres
= windata
->yres
;
1238 fb_videomode_to_var(&fbinfo
->var
, &initmode
);
1240 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
1241 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
1242 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
1243 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
1244 fbinfo
->var
.bits_per_pixel
= windata
->default_bpp
;
1245 fbinfo
->fbops
= &s3c_fb_ops
;
1246 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
1247 fbinfo
->pseudo_palette
= &win
->pseudo_palette
;
1249 /* prepare to actually start the framebuffer */
1251 ret
= s3c_fb_check_var(&fbinfo
->var
, fbinfo
);
1253 dev_err(sfb
->dev
, "check_var failed on initial video params\n");
1257 /* create initial colour map */
1259 ret
= fb_alloc_cmap(&fbinfo
->cmap
, win
->variant
.palette_sz
, 1);
1261 fb_set_cmap(&fbinfo
->cmap
, fbinfo
);
1263 dev_err(sfb
->dev
, "failed to allocate fb cmap\n");
1265 s3c_fb_set_par(fbinfo
);
1267 dev_dbg(sfb
->dev
, "about to register framebuffer\n");
1269 /* run the check_var and set_par on our configuration. */
1271 ret
= register_framebuffer(fbinfo
);
1273 dev_err(sfb
->dev
, "failed to register framebuffer\n");
1277 dev_info(sfb
->dev
, "window %d: fb %s\n", win_no
, fbinfo
->fix
.id
);
1283 * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
1284 * @sfb: The base resources for the hardware.
1286 * Set horizontal and vertical lcd rgb interface timing.
1288 static void s3c_fb_set_rgb_timing(struct s3c_fb
*sfb
)
1290 struct fb_videomode
*vmode
= sfb
->pdata
->vtiming
;
1291 void __iomem
*regs
= sfb
->regs
;
1295 if (!vmode
->pixclock
)
1296 s3c_fb_missing_pixclock(vmode
);
1298 clkdiv
= s3c_fb_calc_pixclk(sfb
, vmode
->pixclock
);
1300 data
= sfb
->pdata
->vidcon0
;
1301 data
&= ~(VIDCON0_CLKVAL_F_MASK
| VIDCON0_CLKDIR
);
1304 data
|= VIDCON0_CLKVAL_F(clkdiv
-1) | VIDCON0_CLKDIR
;
1306 data
&= ~VIDCON0_CLKDIR
; /* 1:1 clock */
1308 if (sfb
->variant
.is_2443
)
1310 writel(data
, regs
+ VIDCON0
);
1312 data
= VIDTCON0_VBPD(vmode
->upper_margin
- 1) |
1313 VIDTCON0_VFPD(vmode
->lower_margin
- 1) |
1314 VIDTCON0_VSPW(vmode
->vsync_len
- 1);
1315 writel(data
, regs
+ sfb
->variant
.vidtcon
);
1317 data
= VIDTCON1_HBPD(vmode
->left_margin
- 1) |
1318 VIDTCON1_HFPD(vmode
->right_margin
- 1) |
1319 VIDTCON1_HSPW(vmode
->hsync_len
- 1);
1320 writel(data
, regs
+ sfb
->variant
.vidtcon
+ 4);
1322 data
= VIDTCON2_LINEVAL(vmode
->yres
- 1) |
1323 VIDTCON2_HOZVAL(vmode
->xres
- 1) |
1324 VIDTCON2_LINEVAL_E(vmode
->yres
- 1) |
1325 VIDTCON2_HOZVAL_E(vmode
->xres
- 1);
1326 writel(data
, regs
+ sfb
->variant
.vidtcon
+ 8);
1330 * s3c_fb_clear_win() - clear hardware window registers.
1331 * @sfb: The base resources for the hardware.
1332 * @win: The window to process.
1334 * Reset the specific window registers to a known state.
1336 static void s3c_fb_clear_win(struct s3c_fb
*sfb
, int win
)
1338 void __iomem
*regs
= sfb
->regs
;
1341 writel(0, regs
+ sfb
->variant
.wincon
+ (win
* 4));
1342 writel(0, regs
+ VIDOSD_A(win
, sfb
->variant
));
1343 writel(0, regs
+ VIDOSD_B(win
, sfb
->variant
));
1344 writel(0, regs
+ VIDOSD_C(win
, sfb
->variant
));
1346 if (sfb
->variant
.has_shadowcon
) {
1347 reg
= readl(sfb
->regs
+ SHADOWCON
);
1348 reg
&= ~(SHADOWCON_WINx_PROTECT(win
) |
1349 SHADOWCON_CHx_ENABLE(win
) |
1350 SHADOWCON_CHx_LOCAL_ENABLE(win
));
1351 writel(reg
, sfb
->regs
+ SHADOWCON
);
1355 static int s3c_fb_probe(struct platform_device
*pdev
)
1357 const struct platform_device_id
*platid
;
1358 struct s3c_fb_driverdata
*fbdrv
;
1359 struct device
*dev
= &pdev
->dev
;
1360 struct s3c_fb_platdata
*pd
;
1362 struct resource
*res
;
1367 platid
= platform_get_device_id(pdev
);
1368 fbdrv
= (struct s3c_fb_driverdata
*)platid
->driver_data
;
1370 if (fbdrv
->variant
.nr_windows
> S3C_FB_MAX_WIN
) {
1371 dev_err(dev
, "too many windows, cannot attach\n");
1375 pd
= dev_get_platdata(&pdev
->dev
);
1377 dev_err(dev
, "no platform data specified\n");
1381 sfb
= devm_kzalloc(dev
, sizeof(*sfb
), GFP_KERNEL
);
1385 dev_dbg(dev
, "allocate new framebuffer %p\n", sfb
);
1389 sfb
->variant
= fbdrv
->variant
;
1391 spin_lock_init(&sfb
->slock
);
1393 sfb
->bus_clk
= devm_clk_get(dev
, "lcd");
1394 if (IS_ERR(sfb
->bus_clk
)) {
1395 dev_err(dev
, "failed to get bus clock\n");
1396 return PTR_ERR(sfb
->bus_clk
);
1399 clk_prepare_enable(sfb
->bus_clk
);
1401 if (!sfb
->variant
.has_clksel
) {
1402 sfb
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
1403 if (IS_ERR(sfb
->lcd_clk
)) {
1404 dev_err(dev
, "failed to get lcd clock\n");
1405 ret
= PTR_ERR(sfb
->lcd_clk
);
1409 clk_prepare_enable(sfb
->lcd_clk
);
1412 pm_runtime_enable(sfb
->dev
);
1414 sfb
->regs
= devm_platform_ioremap_resource(pdev
, 0);
1415 if (IS_ERR(sfb
->regs
)) {
1416 ret
= PTR_ERR(sfb
->regs
);
1420 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1422 dev_err(dev
, "failed to acquire irq resource\n");
1426 sfb
->irq_no
= res
->start
;
1427 ret
= devm_request_irq(dev
, sfb
->irq_no
, s3c_fb_irq
,
1430 dev_err(dev
, "irq request failed\n");
1434 dev_dbg(dev
, "got resources (regs %p), probing windows\n", sfb
->regs
);
1436 platform_set_drvdata(pdev
, sfb
);
1437 pm_runtime_get_sync(sfb
->dev
);
1439 /* setup gpio and output polarity controls */
1443 writel(pd
->vidcon1
, sfb
->regs
+ VIDCON1
);
1445 /* set video clock running at under-run */
1446 if (sfb
->variant
.has_fixvclk
) {
1447 reg
= readl(sfb
->regs
+ VIDCON1
);
1448 reg
&= ~VIDCON1_VCLK_MASK
;
1449 reg
|= VIDCON1_VCLK_RUN
;
1450 writel(reg
, sfb
->regs
+ VIDCON1
);
1453 /* zero all windows before we do anything */
1455 for (win
= 0; win
< fbdrv
->variant
.nr_windows
; win
++)
1456 s3c_fb_clear_win(sfb
, win
);
1458 /* initialise colour key controls */
1459 for (win
= 0; win
< (fbdrv
->variant
.nr_windows
- 1); win
++) {
1460 void __iomem
*regs
= sfb
->regs
+ sfb
->variant
.keycon
;
1463 writel(0xffffff, regs
+ WKEYCON0
);
1464 writel(0xffffff, regs
+ WKEYCON1
);
1467 s3c_fb_set_rgb_timing(sfb
);
1469 /* we have the register setup, start allocating framebuffers */
1471 for (win
= 0; win
< fbdrv
->variant
.nr_windows
; win
++) {
1475 ret
= s3c_fb_probe_win(sfb
, win
, fbdrv
->win
[win
],
1476 &sfb
->windows
[win
]);
1478 dev_err(dev
, "failed to create window %d\n", win
);
1479 for (; win
>= 0; win
--)
1480 s3c_fb_release_win(sfb
, sfb
->windows
[win
]);
1481 goto err_pm_runtime
;
1485 platform_set_drvdata(pdev
, sfb
);
1486 pm_runtime_put_sync(sfb
->dev
);
1491 pm_runtime_put_sync(sfb
->dev
);
1494 pm_runtime_disable(sfb
->dev
);
1496 if (!sfb
->variant
.has_clksel
)
1497 clk_disable_unprepare(sfb
->lcd_clk
);
1500 clk_disable_unprepare(sfb
->bus_clk
);
1506 * s3c_fb_remove() - Cleanup on module finalisation
1507 * @pdev: The platform device we are bound to.
1509 * Shutdown and then release all the resources that the driver allocated
1510 * on initialisation.
1512 static int s3c_fb_remove(struct platform_device
*pdev
)
1514 struct s3c_fb
*sfb
= platform_get_drvdata(pdev
);
1517 pm_runtime_get_sync(sfb
->dev
);
1519 for (win
= 0; win
< S3C_FB_MAX_WIN
; win
++)
1520 if (sfb
->windows
[win
])
1521 s3c_fb_release_win(sfb
, sfb
->windows
[win
]);
1523 if (!sfb
->variant
.has_clksel
)
1524 clk_disable_unprepare(sfb
->lcd_clk
);
1526 clk_disable_unprepare(sfb
->bus_clk
);
1528 pm_runtime_put_sync(sfb
->dev
);
1529 pm_runtime_disable(sfb
->dev
);
1534 #ifdef CONFIG_PM_SLEEP
1535 static int s3c_fb_suspend(struct device
*dev
)
1537 struct s3c_fb
*sfb
= dev_get_drvdata(dev
);
1538 struct s3c_fb_win
*win
;
1541 pm_runtime_get_sync(sfb
->dev
);
1543 for (win_no
= S3C_FB_MAX_WIN
- 1; win_no
>= 0; win_no
--) {
1544 win
= sfb
->windows
[win_no
];
1548 /* use the blank function to push into power-down */
1549 s3c_fb_blank(FB_BLANK_POWERDOWN
, win
->fbinfo
);
1552 if (!sfb
->variant
.has_clksel
)
1553 clk_disable_unprepare(sfb
->lcd_clk
);
1555 clk_disable_unprepare(sfb
->bus_clk
);
1557 pm_runtime_put_sync(sfb
->dev
);
1562 static int s3c_fb_resume(struct device
*dev
)
1564 struct s3c_fb
*sfb
= dev_get_drvdata(dev
);
1565 struct s3c_fb_platdata
*pd
= sfb
->pdata
;
1566 struct s3c_fb_win
*win
;
1570 pm_runtime_get_sync(sfb
->dev
);
1572 clk_prepare_enable(sfb
->bus_clk
);
1574 if (!sfb
->variant
.has_clksel
)
1575 clk_prepare_enable(sfb
->lcd_clk
);
1577 /* setup gpio and output polarity controls */
1579 writel(pd
->vidcon1
, sfb
->regs
+ VIDCON1
);
1581 /* set video clock running at under-run */
1582 if (sfb
->variant
.has_fixvclk
) {
1583 reg
= readl(sfb
->regs
+ VIDCON1
);
1584 reg
&= ~VIDCON1_VCLK_MASK
;
1585 reg
|= VIDCON1_VCLK_RUN
;
1586 writel(reg
, sfb
->regs
+ VIDCON1
);
1589 /* zero all windows before we do anything */
1590 for (win_no
= 0; win_no
< sfb
->variant
.nr_windows
; win_no
++)
1591 s3c_fb_clear_win(sfb
, win_no
);
1593 for (win_no
= 0; win_no
< sfb
->variant
.nr_windows
- 1; win_no
++) {
1594 void __iomem
*regs
= sfb
->regs
+ sfb
->variant
.keycon
;
1595 win
= sfb
->windows
[win_no
];
1599 shadow_protect_win(win
, 1);
1600 regs
+= (win_no
* 8);
1601 writel(0xffffff, regs
+ WKEYCON0
);
1602 writel(0xffffff, regs
+ WKEYCON1
);
1603 shadow_protect_win(win
, 0);
1606 s3c_fb_set_rgb_timing(sfb
);
1608 /* restore framebuffers */
1609 for (win_no
= 0; win_no
< S3C_FB_MAX_WIN
; win_no
++) {
1610 win
= sfb
->windows
[win_no
];
1614 dev_dbg(dev
, "resuming window %d\n", win_no
);
1615 s3c_fb_set_par(win
->fbinfo
);
1618 pm_runtime_put_sync(sfb
->dev
);
1625 static int s3c_fb_runtime_suspend(struct device
*dev
)
1627 struct s3c_fb
*sfb
= dev_get_drvdata(dev
);
1629 if (!sfb
->variant
.has_clksel
)
1630 clk_disable_unprepare(sfb
->lcd_clk
);
1632 clk_disable_unprepare(sfb
->bus_clk
);
1637 static int s3c_fb_runtime_resume(struct device
*dev
)
1639 struct s3c_fb
*sfb
= dev_get_drvdata(dev
);
1640 struct s3c_fb_platdata
*pd
= sfb
->pdata
;
1642 clk_prepare_enable(sfb
->bus_clk
);
1644 if (!sfb
->variant
.has_clksel
)
1645 clk_prepare_enable(sfb
->lcd_clk
);
1647 /* setup gpio and output polarity controls */
1649 writel(pd
->vidcon1
, sfb
->regs
+ VIDCON1
);
1655 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1656 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1658 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins
[] = {
1661 .osd_size_off
= 0x8,
1663 .valid_bpp
= (VALID_BPP1248
| VALID_BPP(16) |
1664 VALID_BPP(18) | VALID_BPP(24)),
1669 .osd_size_off
= 0xc,
1672 .valid_bpp
= (VALID_BPP1248
| VALID_BPP(16) |
1673 VALID_BPP(18) | VALID_BPP(19) |
1674 VALID_BPP(24) | VALID_BPP(25) |
1680 .osd_size_off
= 0xc,
1684 .valid_bpp
= (VALID_BPP1248
| VALID_BPP(16) |
1685 VALID_BPP(18) | VALID_BPP(19) |
1686 VALID_BPP(24) | VALID_BPP(25) |
1694 .valid_bpp
= (VALID_BPP124
| VALID_BPP(16) |
1695 VALID_BPP(18) | VALID_BPP(19) |
1696 VALID_BPP(24) | VALID_BPP(25) |
1704 .valid_bpp
= (VALID_BPP(1) | VALID_BPP(2) |
1705 VALID_BPP(16) | VALID_BPP(18) |
1706 VALID_BPP(19) | VALID_BPP(24) |
1707 VALID_BPP(25) | VALID_BPP(28)),
1711 static struct s3c_fb_driverdata s3c_fb_data_64xx
= {
1714 .vidtcon
= VIDTCON0
,
1715 .wincon
= WINCON(0),
1716 .winmap
= WINxMAP(0),
1720 .buf_start
= VIDW_BUF_START(0),
1721 .buf_size
= VIDW_BUF_SIZE(0),
1722 .buf_end
= VIDW_BUF_END(0),
1735 .win
[0] = &s3c_fb_data_64xx_wins
[0],
1736 .win
[1] = &s3c_fb_data_64xx_wins
[1],
1737 .win
[2] = &s3c_fb_data_64xx_wins
[2],
1738 .win
[3] = &s3c_fb_data_64xx_wins
[3],
1739 .win
[4] = &s3c_fb_data_64xx_wins
[4],
1742 /* S3C2443/S3C2416 style hardware */
1743 static struct s3c_fb_driverdata s3c_fb_data_s3c2443
= {
1764 .win
[0] = &(struct s3c_fb_win_variant
) {
1766 .valid_bpp
= VALID_BPP1248
| VALID_BPP(16) | VALID_BPP(24),
1768 .win
[1] = &(struct s3c_fb_win_variant
) {
1772 .valid_bpp
= (VALID_BPP1248
| VALID_BPP(16) |
1773 VALID_BPP(18) | VALID_BPP(19) |
1774 VALID_BPP(24) | VALID_BPP(25) |
1779 static const struct platform_device_id s3c_fb_driver_ids
[] = {
1782 .driver_data
= (unsigned long)&s3c_fb_data_64xx
,
1784 .name
= "s3c2443-fb",
1785 .driver_data
= (unsigned long)&s3c_fb_data_s3c2443
,
1789 MODULE_DEVICE_TABLE(platform
, s3c_fb_driver_ids
);
1791 static const struct dev_pm_ops s3cfb_pm_ops
= {
1792 SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend
, s3c_fb_resume
)
1793 SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend
, s3c_fb_runtime_resume
,
1797 static struct platform_driver s3c_fb_driver
= {
1798 .probe
= s3c_fb_probe
,
1799 .remove
= s3c_fb_remove
,
1800 .id_table
= s3c_fb_driver_ids
,
1803 .pm
= &s3cfb_pm_ops
,
1807 module_platform_driver(s3c_fb_driver
);
1809 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1810 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1811 MODULE_LICENSE("GPL");
1812 MODULE_ALIAS("platform:s3c-fb");