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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / video / fbdev / s3c2410fb.c
blobd8ae5258de469870ef9f5add8cf6a12b71684a0f
1 /* linux/drivers/video/s3c2410fb.c
2 * Copyright (c) 2004,2005 Arnaud Patard
3 * Copyright (c) 2004-2008 Ben Dooks
4 *
5 * S3C2410 LCD Framebuffer Driver
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * Driver based on skeletonfb.c, sa1100fb.c and others.
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
21 #include <linux/mm.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/fb.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/interrupt.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/cpufreq.h>
31 #include <linux/io.h>
32 #include <linux/platform_data/fb-s3c2410.h>
33
34 #include <asm/div64.h>
35
36 #include <asm/mach/map.h>
37
38 #ifdef CONFIG_PM
39 #include <linux/pm.h>
40 #endif
41
42 #include "s3c2410fb.h"
43 #include "s3c2410fb-regs-lcd.h"
44
45 /* Debugging stuff */
46 static int debug = IS_BUILTIN(CONFIG_FB_S3C2410_DEBUG);
47
48 #define dprintk(msg...) \
49 do { \
50 if (debug) \
51 pr_debug(msg); \
52 } while (0)
53
54 /* useful functions */
55
56 static int is_s3c2412(struct s3c2410fb_info *fbi)
57 {
58 return (fbi->drv_type == DRV_S3C2412);
59 }
60
61 /* s3c2410fb_set_lcdaddr
62 *
63 * initialise lcd controller address pointers
64 */
65 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
66 {
67 unsigned long saddr1, saddr2, saddr3;
68 struct s3c2410fb_info *fbi = info->par;
69 void __iomem *regs = fbi->io;
70
71 saddr1 = info->fix.smem_start >> 1;
72 saddr2 = info->fix.smem_start;
73 saddr2 += info->fix.line_length * info->var.yres;
74 saddr2 >>= 1;
75
76 saddr3 = S3C2410_OFFSIZE(0) |
77 S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
78
79 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
80 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
81 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
82
83 writel(saddr1, regs + S3C2410_LCDSADDR1);
84 writel(saddr2, regs + S3C2410_LCDSADDR2);
85 writel(saddr3, regs + S3C2410_LCDSADDR3);
86 }
87
88 /* s3c2410fb_calc_pixclk()
89 *
90 * calculate divisor for clk->pixclk
91 */
92 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
93 unsigned long pixclk)
94 {
95 unsigned long clk = fbi->clk_rate;
96 unsigned long long div;
97
98 /* pixclk is in picoseconds, our clock is in Hz
99 *
100 * Hz -> picoseconds is / 10^-12
101 */
102
103 div = (unsigned long long)clk * pixclk;
104 div >>= 12; /* div / 2^12 */
105 do_div(div, 625 * 625UL * 625); /* div / 5^12 */
106
107 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
108 return div;
109 }
110
111 /*
112 * s3c2410fb_check_var():
113 * Get the video params out of 'var'. If a value doesn't fit, round it up,
114 * if it's too big, return -EINVAL.
115 *
116 */
117 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
118 struct fb_info *info)
119 {
120 struct s3c2410fb_info *fbi = info->par;
121 struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
122 struct s3c2410fb_display *display = NULL;
123 struct s3c2410fb_display *default_display = mach_info->displays +
124 mach_info->default_display;
125 int type = default_display->type;
126 unsigned i;
127
128 dprintk("check_var(var=%p, info=%p)\n", var, info);
129
130 /* validate x/y resolution */
131 /* choose default mode if possible */
132 if (var->yres == default_display->yres &&
133 var->xres == default_display->xres &&
134 var->bits_per_pixel == default_display->bpp)
135 display = default_display;
136 else
137 for (i = 0; i < mach_info->num_displays; i++)
138 if (type == mach_info->displays[i].type &&
139 var->yres == mach_info->displays[i].yres &&
140 var->xres == mach_info->displays[i].xres &&
141 var->bits_per_pixel == mach_info->displays[i].bpp) {
142 display = mach_info->displays + i;
143 break;
144 }
145
146 if (!display) {
147 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
148 var->xres, var->yres, var->bits_per_pixel);
149 return -EINVAL;
150 }
151
152 /* it is always the size as the display */
153 var->xres_virtual = display->xres;
154 var->yres_virtual = display->yres;
155 var->height = display->height;
156 var->width = display->width;
157
158 /* copy lcd settings */
159 var->pixclock = display->pixclock;
160 var->left_margin = display->left_margin;
161 var->right_margin = display->right_margin;
162 var->upper_margin = display->upper_margin;
163 var->lower_margin = display->lower_margin;
164 var->vsync_len = display->vsync_len;
165 var->hsync_len = display->hsync_len;
166
167 fbi->regs.lcdcon5 = display->lcdcon5;
168 /* set display type */
169 fbi->regs.lcdcon1 = display->type;
170
171 var->transp.offset = 0;
172 var->transp.length = 0;
173 /* set r/g/b positions */
174 switch (var->bits_per_pixel) {
175 case 1:
176 case 2:
177 case 4:
178 var->red.offset = 0;
179 var->red.length = var->bits_per_pixel;
180 var->green = var->red;
181 var->blue = var->red;
182 break;
183 case 8:
184 if (display->type != S3C2410_LCDCON1_TFT) {
185 /* 8 bpp 332 */
186 var->red.length = 3;
187 var->red.offset = 5;
188 var->green.length = 3;
189 var->green.offset = 2;
190 var->blue.length = 2;
191 var->blue.offset = 0;
192 } else {
193 var->red.offset = 0;
194 var->red.length = 8;
195 var->green = var->red;
196 var->blue = var->red;
197 }
198 break;
199 case 12:
200 /* 12 bpp 444 */
201 var->red.length = 4;
202 var->red.offset = 8;
203 var->green.length = 4;
204 var->green.offset = 4;
205 var->blue.length = 4;
206 var->blue.offset = 0;
207 break;
208
209 default:
210 case 16:
211 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
212 /* 16 bpp, 565 format */
213 var->red.offset = 11;
214 var->green.offset = 5;
215 var->blue.offset = 0;
216 var->red.length = 5;
217 var->green.length = 6;
218 var->blue.length = 5;
219 } else {
220 /* 16 bpp, 5551 format */
221 var->red.offset = 11;
222 var->green.offset = 6;
223 var->blue.offset = 1;
224 var->red.length = 5;
225 var->green.length = 5;
226 var->blue.length = 5;
227 }
228 break;
229 case 32:
230 /* 24 bpp 888 and 8 dummy */
231 var->red.length = 8;
232 var->red.offset = 16;
233 var->green.length = 8;
234 var->green.offset = 8;
235 var->blue.length = 8;
236 var->blue.offset = 0;
237 break;
238 }
239 return 0;
240 }
241
242 /* s3c2410fb_calculate_stn_lcd_regs
243 *
244 * calculate register values from var settings
245 */
246 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
247 struct s3c2410fb_hw *regs)
248 {
249 const struct s3c2410fb_info *fbi = info->par;
250 const struct fb_var_screeninfo *var = &info->var;
251 int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
252 int hs = var->xres >> 2;
253 unsigned wdly = (var->left_margin >> 4) - 1;
254 unsigned wlh = (var->hsync_len >> 4) - 1;
255
256 if (type != S3C2410_LCDCON1_STN4)
257 hs >>= 1;
258
259 switch (var->bits_per_pixel) {
260 case 1:
261 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
262 break;
263 case 2:
264 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
265 break;
266 case 4:
267 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
268 break;
269 case 8:
270 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
271 hs *= 3;
272 break;
273 case 12:
274 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
275 hs *= 3;
276 break;
277
278 default:
279 /* invalid pixel depth */
280 dev_err(fbi->dev, "invalid bpp %d\n",
281 var->bits_per_pixel);
282 }
283 /* update X/Y info */
284 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
285 var->left_margin, var->right_margin, var->hsync_len);
286
287 regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
288
289 if (wdly > 3)
290 wdly = 3;
291
292 if (wlh > 3)
293 wlh = 3;
294
295 regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
296 S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
297 S3C2410_LCDCON3_HOZVAL(hs - 1);
298
299 regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
300 }
301
302 /* s3c2410fb_calculate_tft_lcd_regs
303 *
304 * calculate register values from var settings
305 */
306 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
307 struct s3c2410fb_hw *regs)
308 {
309 const struct s3c2410fb_info *fbi = info->par;
310 const struct fb_var_screeninfo *var = &info->var;
311
312 switch (var->bits_per_pixel) {
313 case 1:
314 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
315 break;
316 case 2:
317 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
318 break;
319 case 4:
320 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
321 break;
322 case 8:
323 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
324 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
325 S3C2410_LCDCON5_FRM565;
326 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
327 break;
328 case 16:
329 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
330 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
331 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
332 break;
333 case 32:
334 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
335 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
336 S3C2410_LCDCON5_HWSWP |
337 S3C2410_LCDCON5_BPP24BL);
338 break;
339 default:
340 /* invalid pixel depth */
341 dev_err(fbi->dev, "invalid bpp %d\n",
342 var->bits_per_pixel);
343 }
344 /* update X/Y info */
345 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
346 var->upper_margin, var->lower_margin, var->vsync_len);
347
348 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
349 var->left_margin, var->right_margin, var->hsync_len);
350
351 regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
352 S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
353 S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
354 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
355
356 regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
357 S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
358 S3C2410_LCDCON3_HOZVAL(var->xres - 1);
359
360 regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
361 }
362
363 /* s3c2410fb_activate_var
364 *
365 * activate (set) the controller from the given framebuffer
366 * information
367 */
368 static void s3c2410fb_activate_var(struct fb_info *info)
369 {
370 struct s3c2410fb_info *fbi = info->par;
371 void __iomem *regs = fbi->io;
372 int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
373 struct fb_var_screeninfo *var = &info->var;
374 int clkdiv;
375
376 clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
377
378 dprintk("%s: var->xres = %d\n", __func__, var->xres);
379 dprintk("%s: var->yres = %d\n", __func__, var->yres);
380 dprintk("%s: var->bpp = %d\n", __func__, var->bits_per_pixel);
381
382 if (type == S3C2410_LCDCON1_TFT) {
383 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
384 --clkdiv;
385 if (clkdiv < 0)
386 clkdiv = 0;
387 } else {
388 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
389 if (clkdiv < 2)
390 clkdiv = 2;
391 }
392
393 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
394
395 /* write new registers */
396
397 dprintk("new register set:\n");
398 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
399 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
400 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
401 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
402 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
403
404 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
405 regs + S3C2410_LCDCON1);
406 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
407 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
408 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
409 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
410
411 /* set lcd address pointers */
412 s3c2410fb_set_lcdaddr(info);
413
414 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
415 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
416 }
417
418 /*
419 * s3c2410fb_set_par - Alters the hardware state.
420 * @info: frame buffer structure that represents a single frame buffer
421 *
422 */
423 static int s3c2410fb_set_par(struct fb_info *info)
424 {
425 struct fb_var_screeninfo *var = &info->var;
426
427 switch (var->bits_per_pixel) {
428 case 32:
429 case 16:
430 case 12:
431 info->fix.visual = FB_VISUAL_TRUECOLOR;
432 break;
433 case 1:
434 info->fix.visual = FB_VISUAL_MONO01;
435 break;
436 default:
437 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
438 break;
439 }
440
441 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
442
443 /* activate this new configuration */
444
445 s3c2410fb_activate_var(info);
446 return 0;
447 }
448
449 static void schedule_palette_update(struct s3c2410fb_info *fbi,
450 unsigned int regno, unsigned int val)
451 {
452 unsigned long flags;
453 unsigned long irqen;
454 void __iomem *irq_base = fbi->irq_base;
455
456 local_irq_save(flags);
457
458 fbi->palette_buffer[regno] = val;
459
460 if (!fbi->palette_ready) {
461 fbi->palette_ready = 1;
462
463 /* enable IRQ */
464 irqen = readl(irq_base + S3C24XX_LCDINTMSK);
465 irqen &= ~S3C2410_LCDINT_FRSYNC;
466 writel(irqen, irq_base + S3C24XX_LCDINTMSK);
467 }
468
469 local_irq_restore(flags);
470 }
471
472 /* from pxafb.c */
473 static inline unsigned int chan_to_field(unsigned int chan,
474 struct fb_bitfield *bf)
475 {
476 chan &= 0xffff;
477 chan >>= 16 - bf->length;
478 return chan << bf->offset;
479 }
480
481 static int s3c2410fb_setcolreg(unsigned regno,
482 unsigned red, unsigned green, unsigned blue,
483 unsigned transp, struct fb_info *info)
484 {
485 struct s3c2410fb_info *fbi = info->par;
486 void __iomem *regs = fbi->io;
487 unsigned int val;
488
489 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
490 regno, red, green, blue); */
491
492 switch (info->fix.visual) {
493 case FB_VISUAL_TRUECOLOR:
494 /* true-colour, use pseudo-palette */
495
496 if (regno < 16) {
497 u32 *pal = info->pseudo_palette;
498
499 val = chan_to_field(red, &info->var.red);
500 val |= chan_to_field(green, &info->var.green);
501 val |= chan_to_field(blue, &info->var.blue);
502
503 pal[regno] = val;
504 }
505 break;
506
507 case FB_VISUAL_PSEUDOCOLOR:
508 if (regno < 256) {
509 /* currently assume RGB 5-6-5 mode */
510
511 val = (red >> 0) & 0xf800;
512 val |= (green >> 5) & 0x07e0;
513 val |= (blue >> 11) & 0x001f;
514
515 writel(val, regs + S3C2410_TFTPAL(regno));
516 schedule_palette_update(fbi, regno, val);
517 }
518
519 break;
520
521 default:
522 return 1; /* unknown type */
523 }
524
525 return 0;
526 }
527
528 /* s3c2410fb_lcd_enable
529 *
530 * shutdown the lcd controller
531 */
532 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
533 {
534 unsigned long flags;
535
536 local_irq_save(flags);
537
538 if (enable)
539 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
540 else
541 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
542
543 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
544
545 local_irq_restore(flags);
546 }
547
548
549 /*
550 * s3c2410fb_blank
551 * @blank_mode: the blank mode we want.
552 * @info: frame buffer structure that represents a single frame buffer
553 *
554 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
555 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
556 * video mode which doesn't support it. Implements VESA suspend
557 * and powerdown modes on hardware that supports disabling hsync/vsync:
558 *
559 * Returns negative errno on error, or zero on success.
560 *
561 */
562 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
563 {
564 struct s3c2410fb_info *fbi = info->par;
565 void __iomem *tpal_reg = fbi->io;
566
567 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
568
569 tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
570
571 if (blank_mode == FB_BLANK_POWERDOWN)
572 s3c2410fb_lcd_enable(fbi, 0);
573 else
574 s3c2410fb_lcd_enable(fbi, 1);
575
576 if (blank_mode == FB_BLANK_UNBLANK)
577 writel(0x0, tpal_reg);
578 else {
579 dprintk("setting TPAL to output 0x000000\n");
580 writel(S3C2410_TPAL_EN, tpal_reg);
581 }
582
583 return 0;
584 }
585
586 static int s3c2410fb_debug_show(struct device *dev,
587 struct device_attribute *attr, char *buf)
588 {
589 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
590 }
591
592 static int s3c2410fb_debug_store(struct device *dev,
593 struct device_attribute *attr,
594 const char *buf, size_t len)
595 {
596 if (len < 1)
597 return -EINVAL;
598
599 if (strncasecmp(buf, "on", 2) == 0 ||
600 strncasecmp(buf, "1", 1) == 0) {
601 debug = 1;
602 dev_dbg(dev, "s3c2410fb: Debug On");
603 } else if (strncasecmp(buf, "off", 3) == 0 ||
604 strncasecmp(buf, "0", 1) == 0) {
605 debug = 0;
606 dev_dbg(dev, "s3c2410fb: Debug Off");
607 } else {
608 return -EINVAL;
609 }
610
611 return len;
612 }
613
614 static DEVICE_ATTR(debug, 0664, s3c2410fb_debug_show, s3c2410fb_debug_store);
615
616 static const struct fb_ops s3c2410fb_ops = {
617 .owner = THIS_MODULE,
618 .fb_check_var = s3c2410fb_check_var,
619 .fb_set_par = s3c2410fb_set_par,
620 .fb_blank = s3c2410fb_blank,
621 .fb_setcolreg = s3c2410fb_setcolreg,
622 .fb_fillrect = cfb_fillrect,
623 .fb_copyarea = cfb_copyarea,
624 .fb_imageblit = cfb_imageblit,
625 };
626
627 /*
628 * s3c2410fb_map_video_memory():
629 * Allocates the DRAM memory for the frame buffer. This buffer is
630 * remapped into a non-cached, non-buffered, memory region to
631 * allow palette and pixel writes to occur without flushing the
632 * cache. Once this area is remapped, all virtual memory
633 * access to the video memory should occur at the new region.
634 */
635 static int s3c2410fb_map_video_memory(struct fb_info *info)
636 {
637 struct s3c2410fb_info *fbi = info->par;
638 dma_addr_t map_dma;
639 unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
640
641 dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
642
643 info->screen_base = dma_alloc_wc(fbi->dev, map_size, &map_dma,
644 GFP_KERNEL);
645
646 if (info->screen_base) {
647 /* prevent initial garbage on screen */
648 dprintk("map_video_memory: clear %p:%08x\n",
649 info->screen_base, map_size);
650 memset(info->screen_base, 0x00, map_size);
651
652 info->fix.smem_start = map_dma;
653
654 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
655 info->fix.smem_start, info->screen_base, map_size);
656 }
657
658 return info->screen_base ? 0 : -ENOMEM;
659 }
660
661 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
662 {
663 struct s3c2410fb_info *fbi = info->par;
664
665 dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
666 info->screen_base, info->fix.smem_start);
667 }
668
669 static inline void modify_gpio(void __iomem *reg,
670 unsigned long set, unsigned long mask)
671 {
672 unsigned long tmp;
673
674 if (!reg)
675 return;
676
677 tmp = readl(reg) & ~mask;
678 writel(tmp | set, reg);
679 }
680
681 /*
682 * s3c2410fb_init_registers - Initialise all LCD-related registers
683 */
684 static int s3c2410fb_init_registers(struct fb_info *info)
685 {
686 struct s3c2410fb_info *fbi = info->par;
687 struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
688 unsigned long flags;
689 void __iomem *regs = fbi->io;
690 void __iomem *tpal;
691 void __iomem *lpcsel;
692
693 if (is_s3c2412(fbi)) {
694 tpal = regs + S3C2412_TPAL;
695 lpcsel = regs + S3C2412_TCONSEL;
696 } else {
697 tpal = regs + S3C2410_TPAL;
698 lpcsel = regs + S3C2410_LPCSEL;
699 }
700
701 /* Initialise LCD with values from haret */
702
703 local_irq_save(flags);
704
705 /* modify the gpio(s) with interrupts set (bjd) */
706
707 modify_gpio(mach_info->gpcup_reg, mach_info->gpcup, mach_info->gpcup_mask);
708 modify_gpio(mach_info->gpccon_reg, mach_info->gpccon, mach_info->gpccon_mask);
709 modify_gpio(mach_info->gpdup_reg, mach_info->gpdup, mach_info->gpdup_mask);
710 modify_gpio(mach_info->gpdcon_reg, mach_info->gpdcon, mach_info->gpdcon_mask);
711
712 local_irq_restore(flags);
713
714 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
715 writel(mach_info->lpcsel, lpcsel);
716
717 dprintk("replacing TPAL %08x\n", readl(tpal));
718
719 /* ensure temporary palette disabled */
720 writel(0x00, tpal);
721
722 return 0;
723 }
724
725 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
726 {
727 unsigned int i;
728 void __iomem *regs = fbi->io;
729
730 fbi->palette_ready = 0;
731
732 for (i = 0; i < 256; i++) {
733 unsigned long ent = fbi->palette_buffer[i];
734 if (ent == PALETTE_BUFF_CLEAR)
735 continue;
736
737 writel(ent, regs + S3C2410_TFTPAL(i));
738
739 /* it seems the only way to know exactly
740 * if the palette wrote ok, is to check
741 * to see if the value verifies ok
742 */
743
744 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
745 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
746 else
747 fbi->palette_ready = 1; /* retry */
748 }
749 }
750
751 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
752 {
753 struct s3c2410fb_info *fbi = dev_id;
754 void __iomem *irq_base = fbi->irq_base;
755 unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
756
757 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
758 if (fbi->palette_ready)
759 s3c2410fb_write_palette(fbi);
760
761 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
762 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
763 }
764
765 return IRQ_HANDLED;
766 }
767
768 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
769
770 static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
771 unsigned long val, void *data)
772 {
773 struct s3c2410fb_info *info;
774 struct fb_info *fbinfo;
775 long delta_f;
776
777 info = container_of(nb, struct s3c2410fb_info, freq_transition);
778 fbinfo = dev_get_drvdata(info->dev);
779
780 /* work out change, <0 for speed-up */
781 delta_f = info->clk_rate - clk_get_rate(info->clk);
782
783 if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
784 (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
785 info->clk_rate = clk_get_rate(info->clk);
786 s3c2410fb_activate_var(fbinfo);
787 }
788
789 return 0;
790 }
791
792 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
793 {
794 info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
795
796 return cpufreq_register_notifier(&info->freq_transition,
797 CPUFREQ_TRANSITION_NOTIFIER);
798 }
799
800 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
801 {
802 cpufreq_unregister_notifier(&info->freq_transition,
803 CPUFREQ_TRANSITION_NOTIFIER);
804 }
805
806 #else
807 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
808 {
809 return 0;
810 }
811
812 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
813 {
814 }
815 #endif
816
817
818 static const char driver_name[] = "s3c2410fb";
819
820 static int s3c24xxfb_probe(struct platform_device *pdev,
821 enum s3c_drv_type drv_type)
822 {
823 struct s3c2410fb_info *info;
824 struct s3c2410fb_display *display;
825 struct fb_info *fbinfo;
826 struct s3c2410fb_mach_info *mach_info;
827 struct resource *res;
828 int ret;
829 int irq;
830 int i;
831 int size;
832 u32 lcdcon1;
833
834 mach_info = dev_get_platdata(&pdev->dev);
835 if (mach_info == NULL) {
836 dev_err(&pdev->dev,
837 "no platform data for lcd, cannot attach\n");
838 return -EINVAL;
839 }
840
841 if (mach_info->default_display >= mach_info->num_displays) {
842 dev_err(&pdev->dev, "default is %d but only %d displays\n",
843 mach_info->default_display, mach_info->num_displays);
844 return -EINVAL;
845 }
846
847 display = mach_info->displays + mach_info->default_display;
848
849 irq = platform_get_irq(pdev, 0);
850 if (irq < 0) {
851 dev_err(&pdev->dev, "no irq for device\n");
852 return -ENOENT;
853 }
854
855 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
856 if (!fbinfo)
857 return -ENOMEM;
858
859 platform_set_drvdata(pdev, fbinfo);
860
861 info = fbinfo->par;
862 info->dev = &pdev->dev;
863 info->drv_type = drv_type;
864
865 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
866 if (res == NULL) {
867 dev_err(&pdev->dev, "failed to get memory registers\n");
868 ret = -ENXIO;
869 goto dealloc_fb;
870 }
871
872 size = resource_size(res);
873 info->mem = request_mem_region(res->start, size, pdev->name);
874 if (info->mem == NULL) {
875 dev_err(&pdev->dev, "failed to get memory region\n");
876 ret = -ENOENT;
877 goto dealloc_fb;
878 }
879
880 info->io = ioremap(res->start, size);
881 if (info->io == NULL) {
882 dev_err(&pdev->dev, "ioremap() of registers failed\n");
883 ret = -ENXIO;
884 goto release_mem;
885 }
886
887 if (drv_type == DRV_S3C2412)
888 info->irq_base = info->io + S3C2412_LCDINTBASE;
889 else
890 info->irq_base = info->io + S3C2410_LCDINTBASE;
891
892 dprintk("devinit\n");
893
894 strcpy(fbinfo->fix.id, driver_name);
895
896 /* Stop the video */
897 lcdcon1 = readl(info->io + S3C2410_LCDCON1);
898 writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
899
900 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
901 fbinfo->fix.type_aux = 0;
902 fbinfo->fix.xpanstep = 0;
903 fbinfo->fix.ypanstep = 0;
904 fbinfo->fix.ywrapstep = 0;
905 fbinfo->fix.accel = FB_ACCEL_NONE;
906
907 fbinfo->var.nonstd = 0;
908 fbinfo->var.activate = FB_ACTIVATE_NOW;
909 fbinfo->var.accel_flags = 0;
910 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
911
912 fbinfo->fbops = &s3c2410fb_ops;
913 fbinfo->flags = FBINFO_FLAG_DEFAULT;
914 fbinfo->pseudo_palette = &info->pseudo_pal;
915
916 for (i = 0; i < 256; i++)
917 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
918
919 ret = request_irq(irq, s3c2410fb_irq, 0, pdev->name, info);
920 if (ret) {
921 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
922 ret = -EBUSY;
923 goto release_regs;
924 }
925
926 info->clk = clk_get(NULL, "lcd");
927 if (IS_ERR(info->clk)) {
928 dev_err(&pdev->dev, "failed to get lcd clock source\n");
929 ret = PTR_ERR(info->clk);
930 goto release_irq;
931 }
932
933 clk_prepare_enable(info->clk);
934 dprintk("got and enabled clock\n");
935
936 usleep_range(1000, 1100);
937
938 info->clk_rate = clk_get_rate(info->clk);
939
940 /* find maximum required memory size for display */
941 for (i = 0; i < mach_info->num_displays; i++) {
942 unsigned long smem_len = mach_info->displays[i].xres;
943
944 smem_len *= mach_info->displays[i].yres;
945 smem_len *= mach_info->displays[i].bpp;
946 smem_len >>= 3;
947 if (fbinfo->fix.smem_len < smem_len)
948 fbinfo->fix.smem_len = smem_len;
949 }
950
951 /* Initialize video memory */
952 ret = s3c2410fb_map_video_memory(fbinfo);
953 if (ret) {
954 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
955 ret = -ENOMEM;
956 goto release_clock;
957 }
958
959 dprintk("got video memory\n");
960
961 fbinfo->var.xres = display->xres;
962 fbinfo->var.yres = display->yres;
963 fbinfo->var.bits_per_pixel = display->bpp;
964
965 s3c2410fb_init_registers(fbinfo);
966
967 s3c2410fb_check_var(&fbinfo->var, fbinfo);
968
969 ret = s3c2410fb_cpufreq_register(info);
970 if (ret < 0) {
971 dev_err(&pdev->dev, "Failed to register cpufreq\n");
972 goto free_video_memory;
973 }
974
975 ret = register_framebuffer(fbinfo);
976 if (ret < 0) {
977 dev_err(&pdev->dev, "Failed to register framebuffer device: %d\n",
978 ret);
979 goto free_cpufreq;
980 }
981
982 /* create device files */
983 ret = device_create_file(&pdev->dev, &dev_attr_debug);
984 if (ret)
985 dev_err(&pdev->dev, "failed to add debug attribute\n");
986
987 dev_info(&pdev->dev, "fb%d: %s frame buffer device\n",
988 fbinfo->node, fbinfo->fix.id);
989
990 return 0;
991
992 free_cpufreq:
993 s3c2410fb_cpufreq_deregister(info);
994 free_video_memory:
995 s3c2410fb_unmap_video_memory(fbinfo);
996 release_clock:
997 clk_disable_unprepare(info->clk);
998 clk_put(info->clk);
999 release_irq:
1000 free_irq(irq, info);
1001 release_regs:
1002 iounmap(info->io);
1003 release_mem:
1004 release_mem_region(res->start, size);
1005 dealloc_fb:
1006 framebuffer_release(fbinfo);
1007 return ret;
1008 }
1009
1010 static int s3c2410fb_probe(struct platform_device *pdev)
1011 {
1012 return s3c24xxfb_probe(pdev, DRV_S3C2410);
1013 }
1014
1015 static int s3c2412fb_probe(struct platform_device *pdev)
1016 {
1017 return s3c24xxfb_probe(pdev, DRV_S3C2412);
1018 }
1019
1020
1021 /*
1022 * Cleanup
1023 */
1024 static int s3c2410fb_remove(struct platform_device *pdev)
1025 {
1026 struct fb_info *fbinfo = platform_get_drvdata(pdev);
1027 struct s3c2410fb_info *info = fbinfo->par;
1028 int irq;
1029
1030 unregister_framebuffer(fbinfo);
1031 s3c2410fb_cpufreq_deregister(info);
1032
1033 s3c2410fb_lcd_enable(info, 0);
1034 usleep_range(1000, 1100);
1035
1036 s3c2410fb_unmap_video_memory(fbinfo);
1037
1038 if (info->clk) {
1039 clk_disable_unprepare(info->clk);
1040 clk_put(info->clk);
1041 info->clk = NULL;
1042 }
1043
1044 irq = platform_get_irq(pdev, 0);
1045 free_irq(irq, info);
1046
1047 iounmap(info->io);
1048
1049 release_mem_region(info->mem->start, resource_size(info->mem));
1050
1051 framebuffer_release(fbinfo);
1052
1053 return 0;
1054 }
1055
1056 #ifdef CONFIG_PM
1057
1058 /* suspend and resume support for the lcd controller */
1059 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1060 {
1061 struct fb_info *fbinfo = platform_get_drvdata(dev);
1062 struct s3c2410fb_info *info = fbinfo->par;
1063
1064 s3c2410fb_lcd_enable(info, 0);
1065
1066 /* sleep before disabling the clock, we need to ensure
1067 * the LCD DMA engine is not going to get back on the bus
1068 * before the clock goes off again (bjd) */
1069
1070 usleep_range(1000, 1100);
1071 clk_disable_unprepare(info->clk);
1072
1073 return 0;
1074 }
1075
1076 static int s3c2410fb_resume(struct platform_device *dev)
1077 {
1078 struct fb_info *fbinfo = platform_get_drvdata(dev);
1079 struct s3c2410fb_info *info = fbinfo->par;
1080
1081 clk_prepare_enable(info->clk);
1082 usleep_range(1000, 1100);
1083
1084 s3c2410fb_init_registers(fbinfo);
1085
1086 /* re-activate our display after resume */
1087 s3c2410fb_activate_var(fbinfo);
1088 s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo);
1089
1090 return 0;
1091 }
1092
1093 #else
1094 #define s3c2410fb_suspend NULL
1095 #define s3c2410fb_resume NULL
1096 #endif
1097
1098 static struct platform_driver s3c2410fb_driver = {
1099 .probe = s3c2410fb_probe,
1100 .remove = s3c2410fb_remove,
1101 .suspend = s3c2410fb_suspend,
1102 .resume = s3c2410fb_resume,
1103 .driver = {
1104 .name = "s3c2410-lcd",
1105 },
1106 };
1107
1108 static struct platform_driver s3c2412fb_driver = {
1109 .probe = s3c2412fb_probe,
1110 .remove = s3c2410fb_remove,
1111 .suspend = s3c2410fb_suspend,
1112 .resume = s3c2410fb_resume,
1113 .driver = {
1114 .name = "s3c2412-lcd",
1115 },
1116 };
1117
1118 int __init s3c2410fb_init(void)
1119 {
1120 int ret = platform_driver_register(&s3c2410fb_driver);
1121
1122 if (ret == 0)
1123 ret = platform_driver_register(&s3c2412fb_driver);
1124
1125 return ret;
1126 }
1127
1128 static void __exit s3c2410fb_cleanup(void)
1129 {
1130 platform_driver_unregister(&s3c2410fb_driver);
1131 platform_driver_unregister(&s3c2412fb_driver);
1132 }
1133
1134 module_init(s3c2410fb_init);
1135 module_exit(s3c2410fb_cleanup);
1136
1137 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
1138 MODULE_AUTHOR("Ben Dooks <ben-linux@fluff.org>");
1139 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1140 MODULE_LICENSE("GPL");
1141 MODULE_ALIAS("platform:s3c2410-lcd");
1142 MODULE_ALIAS("platform:s3c2412-lcd");
Linux with added FPC-III support