?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / video / fbdev / tridentfb.c
blob4d20cb557ff0f6e3f2bf959368828818ad2804c1
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Frame buffer driver for Trident TGUI, Blade and Image series
4 *
5 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
6 * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
7 *
8 * CREDITS:(in order of appearance)
9 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
10 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
11 * much inspired by the XFree86 4.x Trident driver sources
12 * by Alan Hourihane the FreeVGA project
13 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
14 * code, suggestions
15 * TODO:
16 * timing value tweaking so it looks good on every monitor in every mode
17 */
18
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
24
25 #include <linux/delay.h>
26 #include <video/vga.h>
27 #include <video/trident.h>
28
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31
32 struct tridentfb_par {
33 void __iomem *io_virt; /* iospace virtual memory address */
34 u32 pseudo_pal[16];
35 int chip_id;
36 int flatpanel;
37 void (*init_accel) (struct tridentfb_par *, int, int);
38 void (*wait_engine) (struct tridentfb_par *);
39 void (*fill_rect)
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
41 void (*copy_rect)
42 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 void (*image_blit)
44 (struct tridentfb_par *par, const char*,
45 u32, u32, u32, u32, u32, u32);
46 unsigned char eng_oper; /* engine operation... */
47 bool ddc_registered;
48 struct i2c_adapter ddc_adapter;
49 struct i2c_algo_bit_data ddc_algo;
50 };
51
52 static struct fb_fix_screeninfo tridentfb_fix = {
53 .id = "Trident",
54 .type = FB_TYPE_PACKED_PIXELS,
55 .ypanstep = 1,
56 .visual = FB_VISUAL_PSEUDOCOLOR,
57 .accel = FB_ACCEL_NONE,
58 };
59
60 /* defaults which are normally overriden by user values */
61
62 /* video mode */
63 static char *mode_option;
64 static int bpp = 8;
65
66 static int noaccel;
67
68 static int center;
69 static int stretch;
70
71 static int fp;
72 static int crt;
73
74 static int memsize;
75 static int memdiff;
76 static int nativex;
77
78 module_param(mode_option, charp, 0);
79 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
80 module_param_named(mode, mode_option, charp, 0);
81 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
82 module_param(bpp, int, 0);
83 module_param(center, int, 0);
84 module_param(stretch, int, 0);
85 module_param(noaccel, int, 0);
86 module_param(memsize, int, 0);
87 module_param(memdiff, int, 0);
88 module_param(nativex, int, 0);
89 module_param(fp, int, 0);
90 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
91 module_param(crt, int, 0);
92 MODULE_PARM_DESC(crt, "Define if CRT is connected");
93
94 static inline int is_oldclock(int id)
95 {
96 return (id == TGUI9440) ||
97 (id == TGUI9660) ||
98 (id == CYBER9320);
99 }
100
101 static inline int is_oldprotect(int id)
102 {
103 return is_oldclock(id) ||
104 (id == PROVIDIA9685) ||
105 (id == CYBER9382) ||
106 (id == CYBER9385);
107 }
108
109 static inline int is_blade(int id)
110 {
111 return (id == BLADE3D) ||
112 (id == CYBERBLADEE4) ||
113 (id == CYBERBLADEi7) ||
114 (id == CYBERBLADEi7D) ||
115 (id == CYBERBLADEi1) ||
116 (id == CYBERBLADEi1D) ||
117 (id == CYBERBLADEAi1) ||
118 (id == CYBERBLADEAi1D);
119 }
120
121 static inline int is_xp(int id)
122 {
123 return (id == CYBERBLADEXPAi1) ||
124 (id == CYBERBLADEXPm8) ||
125 (id == CYBERBLADEXPm16);
126 }
127
128 static inline int is3Dchip(int id)
129 {
130 return is_blade(id) || is_xp(id) ||
131 (id == CYBER9397) || (id == CYBER9397DVD) ||
132 (id == CYBER9520) || (id == CYBER9525DVD) ||
133 (id == IMAGE975) || (id == IMAGE985);
134 }
135
136 static inline int iscyber(int id)
137 {
138 switch (id) {
139 case CYBER9388:
140 case CYBER9382:
141 case CYBER9385:
142 case CYBER9397:
143 case CYBER9397DVD:
144 case CYBER9520:
145 case CYBER9525DVD:
146 case CYBERBLADEE4:
147 case CYBERBLADEi7D:
148 case CYBERBLADEi1:
149 case CYBERBLADEi1D:
150 case CYBERBLADEAi1:
151 case CYBERBLADEAi1D:
152 case CYBERBLADEXPAi1:
153 return 1;
154
155 case CYBER9320:
156 case CYBERBLADEi7: /* VIA MPV4 integrated version */
157 default:
158 /* case CYBERBLDAEXPm8: Strange */
159 /* case CYBERBLDAEXPm16: Strange */
160 return 0;
161 }
162 }
163
164 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
165 {
166 fb_writeb(val, p->io_virt + reg);
167 }
168
169 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
170 {
171 return fb_readb(p->io_virt + reg);
172 }
173
174 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
175 {
176 fb_writel(v, par->io_virt + r);
177 }
178
179 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
180 {
181 return fb_readl(par->io_virt + r);
182 }
183
184 #define DDC_SDA_TGUI BIT(0)
185 #define DDC_SCL_TGUI BIT(1)
186 #define DDC_SCL_DRIVE_TGUI BIT(2)
187 #define DDC_SDA_DRIVE_TGUI BIT(3)
188 #define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
189
190 static void tridentfb_ddc_setscl_tgui(void *data, int val)
191 {
192 struct tridentfb_par *par = data;
193 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
194
195 if (val)
196 reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
197 else
198 reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
199
200 vga_mm_wcrt(par->io_virt, I2C, reg);
201 }
202
203 static void tridentfb_ddc_setsda_tgui(void *data, int val)
204 {
205 struct tridentfb_par *par = data;
206 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
207
208 if (val)
209 reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
210 else
211 reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
212
213 vga_mm_wcrt(par->io_virt, I2C, reg);
214 }
215
216 static int tridentfb_ddc_getsda_tgui(void *data)
217 {
218 struct tridentfb_par *par = data;
219
220 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
221 }
222
223 #define DDC_SDA_IN BIT(0)
224 #define DDC_SCL_OUT BIT(1)
225 #define DDC_SDA_OUT BIT(3)
226 #define DDC_SCL_IN BIT(6)
227 #define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT)
228
229 static void tridentfb_ddc_setscl(void *data, int val)
230 {
231 struct tridentfb_par *par = data;
232 unsigned char reg;
233
234 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
235 if (val)
236 reg |= DDC_SCL_OUT;
237 else
238 reg &= ~DDC_SCL_OUT;
239 vga_mm_wcrt(par->io_virt, I2C, reg);
240 }
241
242 static void tridentfb_ddc_setsda(void *data, int val)
243 {
244 struct tridentfb_par *par = data;
245 unsigned char reg;
246
247 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
248 if (!val)
249 reg |= DDC_SDA_OUT;
250 else
251 reg &= ~DDC_SDA_OUT;
252 vga_mm_wcrt(par->io_virt, I2C, reg);
253 }
254
255 static int tridentfb_ddc_getscl(void *data)
256 {
257 struct tridentfb_par *par = data;
258
259 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
260 }
261
262 static int tridentfb_ddc_getsda(void *data)
263 {
264 struct tridentfb_par *par = data;
265
266 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
267 }
268
269 static int tridentfb_setup_ddc_bus(struct fb_info *info)
270 {
271 struct tridentfb_par *par = info->par;
272
273 strlcpy(par->ddc_adapter.name, info->fix.id,
274 sizeof(par->ddc_adapter.name));
275 par->ddc_adapter.owner = THIS_MODULE;
276 par->ddc_adapter.class = I2C_CLASS_DDC;
277 par->ddc_adapter.algo_data = &par->ddc_algo;
278 par->ddc_adapter.dev.parent = info->device;
279 if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
280 par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
281 par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
282 par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
283 /* no getscl */
284 } else {
285 par->ddc_algo.setsda = tridentfb_ddc_setsda;
286 par->ddc_algo.setscl = tridentfb_ddc_setscl;
287 par->ddc_algo.getsda = tridentfb_ddc_getsda;
288 par->ddc_algo.getscl = tridentfb_ddc_getscl;
289 }
290 par->ddc_algo.udelay = 10;
291 par->ddc_algo.timeout = 20;
292 par->ddc_algo.data = par;
293
294 i2c_set_adapdata(&par->ddc_adapter, par);
295
296 return i2c_bit_add_bus(&par->ddc_adapter);
297 }
298
299 /*
300 * Blade specific acceleration.
301 */
302
303 #define point(x, y) ((y) << 16 | (x))
304
305 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
306 {
307 int v1 = (pitch >> 3) << 20;
308 int tmp = bpp == 24 ? 2 : (bpp >> 4);
309 int v2 = v1 | (tmp << 29);
310
311 writemmr(par, 0x21C0, v2);
312 writemmr(par, 0x21C4, v2);
313 writemmr(par, 0x21B8, v2);
314 writemmr(par, 0x21BC, v2);
315 writemmr(par, 0x21D0, v1);
316 writemmr(par, 0x21D4, v1);
317 writemmr(par, 0x21C8, v1);
318 writemmr(par, 0x21CC, v1);
319 writemmr(par, 0x216C, 0);
320 }
321
322 static void blade_wait_engine(struct tridentfb_par *par)
323 {
324 while (readmmr(par, STATUS) & 0xFA800000)
325 cpu_relax();
326 }
327
328 static void blade_fill_rect(struct tridentfb_par *par,
329 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
330 {
331 writemmr(par, COLOR, c);
332 writemmr(par, ROP, rop ? ROP_X : ROP_S);
333 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
334
335 writemmr(par, DST1, point(x, y));
336 writemmr(par, DST2, point(x + w - 1, y + h - 1));
337 }
338
339 static void blade_image_blit(struct tridentfb_par *par, const char *data,
340 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
341 {
342 unsigned size = ((w + 31) >> 5) * h;
343
344 writemmr(par, COLOR, c);
345 writemmr(par, BGCOLOR, b);
346 writemmr(par, CMD, 0xa0000000 | 3 << 19);
347
348 writemmr(par, DST1, point(x, y));
349 writemmr(par, DST2, point(x + w - 1, y + h - 1));
350
351 iowrite32_rep(par->io_virt + 0x10000, data, size);
352 }
353
354 static void blade_copy_rect(struct tridentfb_par *par,
355 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
356 {
357 int direction = 2;
358 u32 s1 = point(x1, y1);
359 u32 s2 = point(x1 + w - 1, y1 + h - 1);
360 u32 d1 = point(x2, y2);
361 u32 d2 = point(x2 + w - 1, y2 + h - 1);
362
363 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
364 direction = 0;
365
366 writemmr(par, ROP, ROP_S);
367 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
368
369 writemmr(par, SRC1, direction ? s2 : s1);
370 writemmr(par, SRC2, direction ? s1 : s2);
371 writemmr(par, DST1, direction ? d2 : d1);
372 writemmr(par, DST2, direction ? d1 : d2);
373 }
374
375 /*
376 * BladeXP specific acceleration functions
377 */
378
379 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
380 {
381 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
382 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
383
384 switch (pitch << (bpp >> 3)) {
385 case 8192:
386 case 512:
387 x |= 0x00;
388 break;
389 case 1024:
390 x |= 0x04;
391 break;
392 case 2048:
393 x |= 0x08;
394 break;
395 case 4096:
396 x |= 0x0C;
397 break;
398 }
399
400 t_outb(par, x, 0x2125);
401
402 par->eng_oper = x | 0x40;
403
404 writemmr(par, 0x2154, v1);
405 writemmr(par, 0x2150, v1);
406 t_outb(par, 3, 0x2126);
407 }
408
409 static void xp_wait_engine(struct tridentfb_par *par)
410 {
411 int count = 0;
412 int timeout = 0;
413
414 while (t_inb(par, STATUS) & 0x80) {
415 count++;
416 if (count == 10000000) {
417 /* Timeout */
418 count = 9990000;
419 timeout++;
420 if (timeout == 8) {
421 /* Reset engine */
422 t_outb(par, 0x00, STATUS);
423 return;
424 }
425 }
426 cpu_relax();
427 }
428 }
429
430 static void xp_fill_rect(struct tridentfb_par *par,
431 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
432 {
433 writemmr(par, 0x2127, ROP_P);
434 writemmr(par, 0x2158, c);
435 writemmr(par, DRAWFL, 0x4000);
436 writemmr(par, OLDDIM, point(h, w));
437 writemmr(par, OLDDST, point(y, x));
438 t_outb(par, 0x01, OLDCMD);
439 t_outb(par, par->eng_oper, 0x2125);
440 }
441
442 static void xp_copy_rect(struct tridentfb_par *par,
443 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
444 {
445 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
446 int direction = 0x0004;
447
448 if ((x1 < x2) && (y1 == y2)) {
449 direction |= 0x0200;
450 x1_tmp = x1 + w - 1;
451 x2_tmp = x2 + w - 1;
452 } else {
453 x1_tmp = x1;
454 x2_tmp = x2;
455 }
456
457 if (y1 < y2) {
458 direction |= 0x0100;
459 y1_tmp = y1 + h - 1;
460 y2_tmp = y2 + h - 1;
461 } else {
462 y1_tmp = y1;
463 y2_tmp = y2;
464 }
465
466 writemmr(par, DRAWFL, direction);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
469 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
470 writemmr(par, OLDDIM, point(h, w));
471 t_outb(par, 0x01, OLDCMD);
472 }
473
474 /*
475 * Image specific acceleration functions
476 */
477 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
478 {
479 int tmp = bpp == 24 ? 2: (bpp >> 4);
480
481 writemmr(par, 0x2120, 0xF0000000);
482 writemmr(par, 0x2120, 0x40000000 | tmp);
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2144, 0x00000000);
485 writemmr(par, 0x2148, 0x00000000);
486 writemmr(par, 0x2150, 0x00000000);
487 writemmr(par, 0x2154, 0x00000000);
488 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
489 writemmr(par, 0x216C, 0x00000000);
490 writemmr(par, 0x2170, 0x00000000);
491 writemmr(par, 0x217C, 0x00000000);
492 writemmr(par, 0x2120, 0x10000000);
493 writemmr(par, 0x2130, (2047 << 16) | 2047);
494 }
495
496 static void image_wait_engine(struct tridentfb_par *par)
497 {
498 while (readmmr(par, 0x2164) & 0xF0000000)
499 cpu_relax();
500 }
501
502 static void image_fill_rect(struct tridentfb_par *par,
503 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
504 {
505 writemmr(par, 0x2120, 0x80000000);
506 writemmr(par, 0x2120, 0x90000000 | ROP_S);
507
508 writemmr(par, 0x2144, c);
509
510 writemmr(par, DST1, point(x, y));
511 writemmr(par, DST2, point(x + w - 1, y + h - 1));
512
513 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
514 }
515
516 static void image_copy_rect(struct tridentfb_par *par,
517 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
518 {
519 int direction = 0x4;
520 u32 s1 = point(x1, y1);
521 u32 s2 = point(x1 + w - 1, y1 + h - 1);
522 u32 d1 = point(x2, y2);
523 u32 d2 = point(x2 + w - 1, y2 + h - 1);
524
525 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
526 direction = 0;
527
528 writemmr(par, 0x2120, 0x80000000);
529 writemmr(par, 0x2120, 0x90000000 | ROP_S);
530
531 writemmr(par, SRC1, direction ? s2 : s1);
532 writemmr(par, SRC2, direction ? s1 : s2);
533 writemmr(par, DST1, direction ? d2 : d1);
534 writemmr(par, DST2, direction ? d1 : d2);
535 writemmr(par, 0x2124,
536 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
537 }
538
539 /*
540 * TGUI 9440/96XX acceleration
541 */
542
543 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
544 {
545 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
546
547 /* disable clipping */
548 writemmr(par, 0x2148, 0);
549 writemmr(par, 0x214C, point(4095, 2047));
550
551 switch ((pitch * bpp) / 8) {
552 case 8192:
553 case 512:
554 x |= 0x00;
555 break;
556 case 1024:
557 x |= 0x04;
558 break;
559 case 2048:
560 x |= 0x08;
561 break;
562 case 4096:
563 x |= 0x0C;
564 break;
565 }
566
567 fb_writew(x, par->io_virt + 0x2122);
568 }
569
570 static void tgui_fill_rect(struct tridentfb_par *par,
571 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
572 {
573 t_outb(par, ROP_P, 0x2127);
574 writemmr(par, OLDCLR, c);
575 writemmr(par, DRAWFL, 0x4020);
576 writemmr(par, OLDDIM, point(w - 1, h - 1));
577 writemmr(par, OLDDST, point(x, y));
578 t_outb(par, 1, OLDCMD);
579 }
580
581 static void tgui_copy_rect(struct tridentfb_par *par,
582 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
583 {
584 int flags = 0;
585 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
586
587 if ((x1 < x2) && (y1 == y2)) {
588 flags |= 0x0200;
589 x1_tmp = x1 + w - 1;
590 x2_tmp = x2 + w - 1;
591 } else {
592 x1_tmp = x1;
593 x2_tmp = x2;
594 }
595
596 if (y1 < y2) {
597 flags |= 0x0100;
598 y1_tmp = y1 + h - 1;
599 y2_tmp = y2 + h - 1;
600 } else {
601 y1_tmp = y1;
602 y2_tmp = y2;
603 }
604
605 writemmr(par, DRAWFL, 0x4 | flags);
606 t_outb(par, ROP_S, 0x2127);
607 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
608 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
609 writemmr(par, OLDDIM, point(w - 1, h - 1));
610 t_outb(par, 1, OLDCMD);
611 }
612
613 /*
614 * Accel functions called by the upper layers
615 */
616 static void tridentfb_fillrect(struct fb_info *info,
617 const struct fb_fillrect *fr)
618 {
619 struct tridentfb_par *par = info->par;
620 int col;
621
622 if (info->flags & FBINFO_HWACCEL_DISABLED) {
623 cfb_fillrect(info, fr);
624 return;
625 }
626 if (info->var.bits_per_pixel == 8) {
627 col = fr->color;
628 col |= col << 8;
629 col |= col << 16;
630 } else
631 col = ((u32 *)(info->pseudo_palette))[fr->color];
632
633 par->wait_engine(par);
634 par->fill_rect(par, fr->dx, fr->dy, fr->width,
635 fr->height, col, fr->rop);
636 }
637
638 static void tridentfb_imageblit(struct fb_info *info,
639 const struct fb_image *img)
640 {
641 struct tridentfb_par *par = info->par;
642 int col, bgcol;
643
644 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
645 cfb_imageblit(info, img);
646 return;
647 }
648 if (info->var.bits_per_pixel == 8) {
649 col = img->fg_color;
650 col |= col << 8;
651 col |= col << 16;
652 bgcol = img->bg_color;
653 bgcol |= bgcol << 8;
654 bgcol |= bgcol << 16;
655 } else {
656 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
657 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
658 }
659
660 par->wait_engine(par);
661 if (par->image_blit)
662 par->image_blit(par, img->data, img->dx, img->dy,
663 img->width, img->height, col, bgcol);
664 else
665 cfb_imageblit(info, img);
666 }
667
668 static void tridentfb_copyarea(struct fb_info *info,
669 const struct fb_copyarea *ca)
670 {
671 struct tridentfb_par *par = info->par;
672
673 if (info->flags & FBINFO_HWACCEL_DISABLED) {
674 cfb_copyarea(info, ca);
675 return;
676 }
677 par->wait_engine(par);
678 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
679 ca->width, ca->height);
680 }
681
682 static int tridentfb_sync(struct fb_info *info)
683 {
684 struct tridentfb_par *par = info->par;
685
686 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
687 par->wait_engine(par);
688 return 0;
689 }
690
691 /*
692 * Hardware access functions
693 */
694
695 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
696 {
697 return vga_mm_rcrt(par->io_virt, reg);
698 }
699
700 static inline void write3X4(struct tridentfb_par *par, int reg,
701 unsigned char val)
702 {
703 vga_mm_wcrt(par->io_virt, reg, val);
704 }
705
706 static inline unsigned char read3CE(struct tridentfb_par *par,
707 unsigned char reg)
708 {
709 return vga_mm_rgfx(par->io_virt, reg);
710 }
711
712 static inline void writeAttr(struct tridentfb_par *par, int reg,
713 unsigned char val)
714 {
715 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
716 vga_mm_wattr(par->io_virt, reg, val);
717 }
718
719 static inline void write3CE(struct tridentfb_par *par, int reg,
720 unsigned char val)
721 {
722 vga_mm_wgfx(par->io_virt, reg, val);
723 }
724
725 static void enable_mmio(struct tridentfb_par *par)
726 {
727 /* Goto New Mode */
728 vga_io_rseq(0x0B);
729
730 /* Unprotect registers */
731 vga_io_wseq(NewMode1, 0x80);
732 if (!is_oldprotect(par->chip_id))
733 vga_io_wseq(Protection, 0x92);
734
735 /* Enable MMIO */
736 outb(PCIReg, 0x3D4);
737 outb(inb(0x3D5) | 0x01, 0x3D5);
738 }
739
740 static void disable_mmio(struct tridentfb_par *par)
741 {
742 /* Goto New Mode */
743 vga_mm_rseq(par->io_virt, 0x0B);
744
745 /* Unprotect registers */
746 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
747 if (!is_oldprotect(par->chip_id))
748 vga_mm_wseq(par->io_virt, Protection, 0x92);
749
750 /* Disable MMIO */
751 t_outb(par, PCIReg, 0x3D4);
752 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
753 }
754
755 static inline void crtc_unlock(struct tridentfb_par *par)
756 {
757 write3X4(par, VGA_CRTC_V_SYNC_END,
758 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
759 }
760
761 /* Return flat panel's maximum x resolution */
762 static int get_nativex(struct tridentfb_par *par)
763 {
764 int x, y, tmp;
765
766 if (nativex)
767 return nativex;
768
769 tmp = (read3CE(par, VertStretch) >> 4) & 3;
770
771 switch (tmp) {
772 case 0:
773 x = 1280; y = 1024;
774 break;
775 case 2:
776 x = 1024; y = 768;
777 break;
778 case 3:
779 x = 800; y = 600;
780 break;
781 case 1:
782 default:
783 x = 640; y = 480;
784 break;
785 }
786
787 output("%dx%d flat panel found\n", x, y);
788 return x;
789 }
790
791 /* Set pitch */
792 static inline void set_lwidth(struct tridentfb_par *par, int width)
793 {
794 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
795 /* chips older than TGUI9660 have only 1 width bit in AddColReg */
796 /* touching the other one breaks I2C/DDC */
797 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
798 write3X4(par, AddColReg,
799 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
800 else
801 write3X4(par, AddColReg,
802 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
803 }
804
805 /* For resolutions smaller than FP resolution stretch */
806 static void screen_stretch(struct tridentfb_par *par)
807 {
808 if (par->chip_id != CYBERBLADEXPAi1)
809 write3CE(par, BiosReg, 0);
810 else
811 write3CE(par, BiosReg, 8);
812 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
813 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
814 }
815
816 /* For resolutions smaller than FP resolution center */
817 static inline void screen_center(struct tridentfb_par *par)
818 {
819 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
820 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
821 }
822
823 /* Address of first shown pixel in display memory */
824 static void set_screen_start(struct tridentfb_par *par, int base)
825 {
826 u8 tmp;
827 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
828 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
829 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
830 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
831 tmp = read3X4(par, CRTHiOrd) & 0xF8;
832 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
833 }
834
835 /* Set dotclock frequency */
836 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
837 {
838 int m, n, k;
839 unsigned long fi, d, di;
840 unsigned char best_m = 0, best_n = 0, best_k = 0;
841 unsigned char hi, lo;
842 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
843
844 d = 20000;
845 for (k = shift; k >= 0; k--)
846 for (m = 1; m < 32; m++) {
847 n = ((m + 2) << shift) - 8;
848 for (n = (n < 0 ? 0 : n); n < 122; n++) {
849 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
850 di = abs(fi - freq);
851 if (di < d || (di == d && k == best_k)) {
852 d = di;
853 best_n = n;
854 best_m = m;
855 best_k = k;
856 }
857 if (fi > freq)
858 break;
859 }
860 }
861
862 if (is_oldclock(par->chip_id)) {
863 lo = best_n | (best_m << 7);
864 hi = (best_m >> 1) | (best_k << 4);
865 } else {
866 lo = best_n;
867 hi = best_m | (best_k << 6);
868 }
869
870 if (is3Dchip(par->chip_id)) {
871 vga_mm_wseq(par->io_virt, ClockHigh, hi);
872 vga_mm_wseq(par->io_virt, ClockLow, lo);
873 } else {
874 t_outb(par, lo, 0x43C8);
875 t_outb(par, hi, 0x43C9);
876 }
877 debug("VCLK = %X %X\n", hi, lo);
878 }
879
880 /* Set number of lines for flat panels*/
881 static void set_number_of_lines(struct tridentfb_par *par, int lines)
882 {
883 int tmp = read3CE(par, CyberEnhance) & 0x8F;
884 if (lines > 1024)
885 tmp |= 0x50;
886 else if (lines > 768)
887 tmp |= 0x30;
888 else if (lines > 600)
889 tmp |= 0x20;
890 else if (lines > 480)
891 tmp |= 0x10;
892 write3CE(par, CyberEnhance, tmp);
893 }
894
895 /*
896 * If we see that FP is active we assume we have one.
897 * Otherwise we have a CRT display. User can override.
898 */
899 static int is_flatpanel(struct tridentfb_par *par)
900 {
901 if (fp)
902 return 1;
903 if (crt || !iscyber(par->chip_id))
904 return 0;
905 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
906 }
907
908 /* Try detecting the video memory size */
909 static unsigned int get_memsize(struct tridentfb_par *par)
910 {
911 unsigned char tmp, tmp2;
912 unsigned int k;
913
914 /* If memory size provided by user */
915 if (memsize)
916 k = memsize * Kb;
917 else
918 switch (par->chip_id) {
919 case CYBER9525DVD:
920 k = 2560 * Kb;
921 break;
922 default:
923 tmp = read3X4(par, SPR) & 0x0F;
924 switch (tmp) {
925
926 case 0x01:
927 k = 512 * Kb;
928 break;
929 case 0x02:
930 k = 6 * Mb; /* XP */
931 break;
932 case 0x03:
933 k = 1 * Mb;
934 break;
935 case 0x04:
936 k = 8 * Mb;
937 break;
938 case 0x06:
939 k = 10 * Mb; /* XP */
940 break;
941 case 0x07:
942 k = 2 * Mb;
943 break;
944 case 0x08:
945 k = 12 * Mb; /* XP */
946 break;
947 case 0x0A:
948 k = 14 * Mb; /* XP */
949 break;
950 case 0x0C:
951 k = 16 * Mb; /* XP */
952 break;
953 case 0x0E: /* XP */
954
955 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
956 switch (tmp2) {
957 case 0x00:
958 k = 20 * Mb;
959 break;
960 case 0x01:
961 k = 24 * Mb;
962 break;
963 case 0x10:
964 k = 28 * Mb;
965 break;
966 case 0x11:
967 k = 32 * Mb;
968 break;
969 default:
970 k = 1 * Mb;
971 break;
972 }
973 break;
974
975 case 0x0F:
976 k = 4 * Mb;
977 break;
978 default:
979 k = 1 * Mb;
980 break;
981 }
982 }
983
984 k -= memdiff * Kb;
985 output("framebuffer size = %d Kb\n", k / Kb);
986 return k;
987 }
988
989 /* See if we can handle the video mode described in var */
990 static int tridentfb_check_var(struct fb_var_screeninfo *var,
991 struct fb_info *info)
992 {
993 struct tridentfb_par *par = info->par;
994 int bpp = var->bits_per_pixel;
995 int line_length;
996 int ramdac = 230000; /* 230MHz for most 3D chips */
997 debug("enter\n");
998
999 /* check color depth */
1000 if (bpp == 24)
1001 bpp = var->bits_per_pixel = 32;
1002 if (bpp != 8 && bpp != 16 && bpp != 32)
1003 return -EINVAL;
1004 if (par->chip_id == TGUI9440 && bpp == 32)
1005 return -EINVAL;
1006 /* check whether resolution fits on panel and in memory */
1007 if (par->flatpanel && nativex && var->xres > nativex)
1008 return -EINVAL;
1009 /* various resolution checks */
1010 var->xres = (var->xres + 7) & ~0x7;
1011 if (var->xres > var->xres_virtual)
1012 var->xres_virtual = var->xres;
1013 if (var->yres > var->yres_virtual)
1014 var->yres_virtual = var->yres;
1015 if (var->xres_virtual > 4095 || var->yres > 2048)
1016 return -EINVAL;
1017 /* prevent from position overflow for acceleration */
1018 if (var->yres_virtual > 0xffff)
1019 return -EINVAL;
1020 line_length = var->xres_virtual * bpp / 8;
1021
1022 if (!is3Dchip(par->chip_id) &&
1023 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
1024 /* acceleration requires line length to be power of 2 */
1025 if (line_length <= 512)
1026 var->xres_virtual = 512 * 8 / bpp;
1027 else if (line_length <= 1024)
1028 var->xres_virtual = 1024 * 8 / bpp;
1029 else if (line_length <= 2048)
1030 var->xres_virtual = 2048 * 8 / bpp;
1031 else if (line_length <= 4096)
1032 var->xres_virtual = 4096 * 8 / bpp;
1033 else if (line_length <= 8192)
1034 var->xres_virtual = 8192 * 8 / bpp;
1035 else
1036 return -EINVAL;
1037
1038 line_length = var->xres_virtual * bpp / 8;
1039 }
1040
1041 /* datasheet specifies how to set panning only up to 4 MB */
1042 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
1043 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
1044
1045 if (line_length * var->yres_virtual > info->fix.smem_len)
1046 return -EINVAL;
1047
1048 switch (bpp) {
1049 case 8:
1050 var->red.offset = 0;
1051 var->red.length = 8;
1052 var->green = var->red;
1053 var->blue = var->red;
1054 break;
1055 case 16:
1056 var->red.offset = 11;
1057 var->green.offset = 5;
1058 var->blue.offset = 0;
1059 var->red.length = 5;
1060 var->green.length = 6;
1061 var->blue.length = 5;
1062 break;
1063 case 32:
1064 var->red.offset = 16;
1065 var->green.offset = 8;
1066 var->blue.offset = 0;
1067 var->red.length = 8;
1068 var->green.length = 8;
1069 var->blue.length = 8;
1070 break;
1071 default:
1072 return -EINVAL;
1073 }
1074
1075 if (is_xp(par->chip_id))
1076 ramdac = 350000;
1077
1078 switch (par->chip_id) {
1079 case TGUI9440:
1080 ramdac = (bpp >= 16) ? 45000 : 90000;
1081 break;
1082 case CYBER9320:
1083 case TGUI9660:
1084 ramdac = 135000;
1085 break;
1086 case PROVIDIA9685:
1087 case CYBER9388:
1088 case CYBER9382:
1089 case CYBER9385:
1090 ramdac = 170000;
1091 break;
1092 }
1093
1094 /* The clock is doubled for 32 bpp */
1095 if (bpp == 32)
1096 ramdac /= 2;
1097
1098 if (PICOS2KHZ(var->pixclock) > ramdac)
1099 return -EINVAL;
1100
1101 debug("exit\n");
1102
1103 return 0;
1104
1105 }
1106
1107 /* Pan the display */
1108 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1109 struct fb_info *info)
1110 {
1111 struct tridentfb_par *par = info->par;
1112 unsigned int offset;
1113
1114 debug("enter\n");
1115 offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
1116 * info->var.bits_per_pixel / 32;
1117 set_screen_start(par, offset);
1118 debug("exit\n");
1119 return 0;
1120 }
1121
1122 static inline void shadowmode_on(struct tridentfb_par *par)
1123 {
1124 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1125 }
1126
1127 static inline void shadowmode_off(struct tridentfb_par *par)
1128 {
1129 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1130 }
1131
1132 /* Set the hardware to the requested video mode */
1133 static int tridentfb_set_par(struct fb_info *info)
1134 {
1135 struct tridentfb_par *par = info->par;
1136 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1137 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1138 struct fb_var_screeninfo *var = &info->var;
1139 int bpp = var->bits_per_pixel;
1140 unsigned char tmp;
1141 unsigned long vclk;
1142
1143 debug("enter\n");
1144 hdispend = var->xres / 8 - 1;
1145 hsyncstart = (var->xres + var->right_margin) / 8;
1146 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1147 htotal = (var->xres + var->left_margin + var->right_margin +
1148 var->hsync_len) / 8 - 5;
1149 hblankstart = hdispend + 1;
1150 hblankend = htotal + 3;
1151
1152 vdispend = var->yres - 1;
1153 vsyncstart = var->yres + var->lower_margin;
1154 vsyncend = vsyncstart + var->vsync_len;
1155 vtotal = var->upper_margin + vsyncend - 2;
1156 vblankstart = vdispend + 1;
1157 vblankend = vtotal;
1158
1159 if (info->var.vmode & FB_VMODE_INTERLACED) {
1160 vtotal /= 2;
1161 vdispend /= 2;
1162 vsyncstart /= 2;
1163 vsyncend /= 2;
1164 vblankstart /= 2;
1165 vblankend /= 2;
1166 }
1167
1168 enable_mmio(par);
1169 crtc_unlock(par);
1170 write3CE(par, CyberControl, 8);
1171 tmp = 0xEB;
1172 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1173 tmp &= ~0x40;
1174 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1175 tmp &= ~0x80;
1176
1177 if (par->flatpanel && var->xres < nativex) {
1178 /*
1179 * on flat panels with native size larger
1180 * than requested resolution decide whether
1181 * we stretch or center
1182 */
1183 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1184
1185 shadowmode_on(par);
1186
1187 if (center)
1188 screen_center(par);
1189 else if (stretch)
1190 screen_stretch(par);
1191
1192 } else {
1193 t_outb(par, tmp, VGA_MIS_W);
1194 write3CE(par, CyberControl, 8);
1195 }
1196
1197 /* vertical timing values */
1198 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1199 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1200 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1201 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1202 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1203 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1204
1205 /* horizontal timing values */
1206 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1207 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1208 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1209 write3X4(par, VGA_CRTC_H_SYNC_END,
1210 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1211 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1212 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1213
1214 /* higher bits of vertical timing values */
1215 tmp = 0x10;
1216 if (vtotal & 0x100) tmp |= 0x01;
1217 if (vdispend & 0x100) tmp |= 0x02;
1218 if (vsyncstart & 0x100) tmp |= 0x04;
1219 if (vblankstart & 0x100) tmp |= 0x08;
1220
1221 if (vtotal & 0x200) tmp |= 0x20;
1222 if (vdispend & 0x200) tmp |= 0x40;
1223 if (vsyncstart & 0x200) tmp |= 0x80;
1224 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1225
1226 tmp = read3X4(par, CRTHiOrd) & 0x07;
1227 tmp |= 0x08; /* line compare bit 10 */
1228 if (vtotal & 0x400) tmp |= 0x80;
1229 if (vblankstart & 0x400) tmp |= 0x40;
1230 if (vsyncstart & 0x400) tmp |= 0x20;
1231 if (vdispend & 0x400) tmp |= 0x10;
1232 write3X4(par, CRTHiOrd, tmp);
1233
1234 tmp = (htotal >> 8) & 0x01;
1235 tmp |= (hdispend >> 7) & 0x02;
1236 tmp |= (hsyncstart >> 5) & 0x08;
1237 tmp |= (hblankstart >> 4) & 0x10;
1238 write3X4(par, HorizOverflow, tmp);
1239
1240 tmp = 0x40;
1241 if (vblankstart & 0x200) tmp |= 0x20;
1242 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1243 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1244
1245 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1246 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1247 write3X4(par, VGA_CRTC_MODE, 0xC3);
1248
1249 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1250
1251 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1252 /* enable access extended memory */
1253 write3X4(par, CRTCModuleTest, tmp);
1254 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1255 if (info->var.vmode & FB_VMODE_INTERLACED)
1256 tmp |= 0x4;
1257 write3CE(par, MiscIntContReg, tmp);
1258
1259 /* enable GE for text acceleration */
1260 write3X4(par, GraphEngReg, 0x80);
1261
1262 switch (bpp) {
1263 case 8:
1264 tmp = 0x00;
1265 break;
1266 case 16:
1267 tmp = 0x05;
1268 break;
1269 case 24:
1270 tmp = 0x29;
1271 break;
1272 case 32:
1273 tmp = 0x09;
1274 break;
1275 }
1276
1277 write3X4(par, PixelBusReg, tmp);
1278
1279 tmp = read3X4(par, DRAMControl);
1280 if (!is_oldprotect(par->chip_id))
1281 tmp |= 0x10;
1282 if (iscyber(par->chip_id))
1283 tmp |= 0x20;
1284 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1285
1286 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1287 if (!is_xp(par->chip_id))
1288 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1289 /* MMIO & PCI read and write burst enable */
1290 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1291 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1292
1293 vga_mm_wseq(par->io_virt, 0, 3);
1294 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1295 /* enable 4 maps because needed in chain4 mode */
1296 vga_mm_wseq(par->io_virt, 2, 0x0F);
1297 vga_mm_wseq(par->io_virt, 3, 0);
1298 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1299
1300 /* convert from picoseconds to kHz */
1301 vclk = PICOS2KHZ(info->var.pixclock);
1302
1303 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1304 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1305 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1306 tmp |= 8;
1307 vclk *= 2;
1308 }
1309 set_vclk(par, vclk);
1310 write3CE(par, MiscExtFunc, tmp | 0x12);
1311 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1312 write3CE(par, 0x6, 0x05); /* graphics mode */
1313 write3CE(par, 0x7, 0x0F); /* planes? */
1314
1315 /* graphics mode and support 256 color modes */
1316 writeAttr(par, 0x10, 0x41);
1317 writeAttr(par, 0x12, 0x0F); /* planes */
1318 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1319
1320 /* colors */
1321 for (tmp = 0; tmp < 0x10; tmp++)
1322 writeAttr(par, tmp, tmp);
1323 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1324 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1325
1326 switch (bpp) {
1327 case 8:
1328 tmp = 0;
1329 break;
1330 case 16:
1331 tmp = 0x30;
1332 break;
1333 case 24:
1334 case 32:
1335 tmp = 0xD0;
1336 break;
1337 }
1338
1339 t_inb(par, VGA_PEL_IW);
1340 t_inb(par, VGA_PEL_MSK);
1341 t_inb(par, VGA_PEL_MSK);
1342 t_inb(par, VGA_PEL_MSK);
1343 t_inb(par, VGA_PEL_MSK);
1344 t_outb(par, tmp, VGA_PEL_MSK);
1345 t_inb(par, VGA_PEL_IW);
1346
1347 if (par->flatpanel)
1348 set_number_of_lines(par, info->var.yres);
1349 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1350 set_lwidth(par, info->fix.line_length / 8);
1351
1352 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1353 par->init_accel(par, info->var.xres_virtual, bpp);
1354
1355 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1356 info->cmap.len = (bpp == 8) ? 256 : 16;
1357 debug("exit\n");
1358 return 0;
1359 }
1360
1361 /* Set one color register */
1362 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1363 unsigned blue, unsigned transp,
1364 struct fb_info *info)
1365 {
1366 int bpp = info->var.bits_per_pixel;
1367 struct tridentfb_par *par = info->par;
1368
1369 if (regno >= info->cmap.len)
1370 return 1;
1371
1372 if (bpp == 8) {
1373 t_outb(par, 0xFF, VGA_PEL_MSK);
1374 t_outb(par, regno, VGA_PEL_IW);
1375
1376 t_outb(par, red >> 10, VGA_PEL_D);
1377 t_outb(par, green >> 10, VGA_PEL_D);
1378 t_outb(par, blue >> 10, VGA_PEL_D);
1379
1380 } else if (regno < 16) {
1381 if (bpp == 16) { /* RGB 565 */
1382 u32 col;
1383
1384 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1385 ((blue & 0xF800) >> 11);
1386 col |= col << 16;
1387 ((u32 *)(info->pseudo_palette))[regno] = col;
1388 } else if (bpp == 32) /* ARGB 8888 */
1389 ((u32 *)info->pseudo_palette)[regno] =
1390 ((transp & 0xFF00) << 16) |
1391 ((red & 0xFF00) << 8) |
1392 ((green & 0xFF00)) |
1393 ((blue & 0xFF00) >> 8);
1394 }
1395
1396 return 0;
1397 }
1398
1399 /* Try blanking the screen. For flat panels it does nothing */
1400 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1401 {
1402 unsigned char PMCont, DPMSCont;
1403 struct tridentfb_par *par = info->par;
1404
1405 debug("enter\n");
1406 if (par->flatpanel)
1407 return 0;
1408 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1409 PMCont = t_inb(par, 0x83C6) & 0xFC;
1410 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1411 switch (blank_mode) {
1412 case FB_BLANK_UNBLANK:
1413 /* Screen: On, HSync: On, VSync: On */
1414 case FB_BLANK_NORMAL:
1415 /* Screen: Off, HSync: On, VSync: On */
1416 PMCont |= 0x03;
1417 DPMSCont |= 0x00;
1418 break;
1419 case FB_BLANK_HSYNC_SUSPEND:
1420 /* Screen: Off, HSync: Off, VSync: On */
1421 PMCont |= 0x02;
1422 DPMSCont |= 0x01;
1423 break;
1424 case FB_BLANK_VSYNC_SUSPEND:
1425 /* Screen: Off, HSync: On, VSync: Off */
1426 PMCont |= 0x02;
1427 DPMSCont |= 0x02;
1428 break;
1429 case FB_BLANK_POWERDOWN:
1430 /* Screen: Off, HSync: Off, VSync: Off */
1431 PMCont |= 0x00;
1432 DPMSCont |= 0x03;
1433 break;
1434 }
1435
1436 write3CE(par, PowerStatus, DPMSCont);
1437 t_outb(par, 4, 0x83C8);
1438 t_outb(par, PMCont, 0x83C6);
1439
1440 debug("exit\n");
1441
1442 /* let fbcon do a softblank for us */
1443 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1444 }
1445
1446 static const struct fb_ops tridentfb_ops = {
1447 .owner = THIS_MODULE,
1448 .fb_setcolreg = tridentfb_setcolreg,
1449 .fb_pan_display = tridentfb_pan_display,
1450 .fb_blank = tridentfb_blank,
1451 .fb_check_var = tridentfb_check_var,
1452 .fb_set_par = tridentfb_set_par,
1453 .fb_fillrect = tridentfb_fillrect,
1454 .fb_copyarea = tridentfb_copyarea,
1455 .fb_imageblit = tridentfb_imageblit,
1456 .fb_sync = tridentfb_sync,
1457 };
1458
1459 static int trident_pci_probe(struct pci_dev *dev,
1460 const struct pci_device_id *id)
1461 {
1462 int err;
1463 unsigned char revision;
1464 struct fb_info *info;
1465 struct tridentfb_par *default_par;
1466 int chip3D;
1467 int chip_id;
1468 bool found = false;
1469
1470 err = pci_enable_device(dev);
1471 if (err)
1472 return err;
1473
1474 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1475 if (!info)
1476 return -ENOMEM;
1477 default_par = info->par;
1478
1479 chip_id = id->device;
1480
1481 /* If PCI id is 0x9660 then further detect chip type */
1482
1483 if (chip_id == TGUI9660) {
1484 revision = vga_io_rseq(RevisionID);
1485
1486 switch (revision) {
1487 case 0x21:
1488 chip_id = PROVIDIA9685;
1489 break;
1490 case 0x22:
1491 case 0x23:
1492 chip_id = CYBER9397;
1493 break;
1494 case 0x2A:
1495 chip_id = CYBER9397DVD;
1496 break;
1497 case 0x30:
1498 case 0x33:
1499 case 0x34:
1500 case 0x35:
1501 case 0x38:
1502 case 0x3A:
1503 case 0xB3:
1504 chip_id = CYBER9385;
1505 break;
1506 case 0x40 ... 0x43:
1507 chip_id = CYBER9382;
1508 break;
1509 case 0x4A:
1510 chip_id = CYBER9388;
1511 break;
1512 default:
1513 break;
1514 }
1515 }
1516
1517 chip3D = is3Dchip(chip_id);
1518
1519 if (is_xp(chip_id)) {
1520 default_par->init_accel = xp_init_accel;
1521 default_par->wait_engine = xp_wait_engine;
1522 default_par->fill_rect = xp_fill_rect;
1523 default_par->copy_rect = xp_copy_rect;
1524 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1525 } else if (is_blade(chip_id)) {
1526 default_par->init_accel = blade_init_accel;
1527 default_par->wait_engine = blade_wait_engine;
1528 default_par->fill_rect = blade_fill_rect;
1529 default_par->copy_rect = blade_copy_rect;
1530 default_par->image_blit = blade_image_blit;
1531 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1532 } else if (chip3D) { /* 3DImage family left */
1533 default_par->init_accel = image_init_accel;
1534 default_par->wait_engine = image_wait_engine;
1535 default_par->fill_rect = image_fill_rect;
1536 default_par->copy_rect = image_copy_rect;
1537 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1538 } else { /* TGUI 9440/96XX family */
1539 default_par->init_accel = tgui_init_accel;
1540 default_par->wait_engine = xp_wait_engine;
1541 default_par->fill_rect = tgui_fill_rect;
1542 default_par->copy_rect = tgui_copy_rect;
1543 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1544 }
1545
1546 default_par->chip_id = chip_id;
1547
1548 /* setup MMIO region */
1549 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1550 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1551
1552 if (!request_mem_region(tridentfb_fix.mmio_start,
1553 tridentfb_fix.mmio_len, "tridentfb")) {
1554 debug("request_region failed!\n");
1555 framebuffer_release(info);
1556 return -1;
1557 }
1558
1559 default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
1560 tridentfb_fix.mmio_len);
1561
1562 if (!default_par->io_virt) {
1563 debug("ioremap failed\n");
1564 err = -1;
1565 goto out_unmap1;
1566 }
1567
1568 enable_mmio(default_par);
1569
1570 /* setup framebuffer memory */
1571 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1572 tridentfb_fix.smem_len = get_memsize(default_par);
1573
1574 if (!request_mem_region(tridentfb_fix.smem_start,
1575 tridentfb_fix.smem_len, "tridentfb")) {
1576 debug("request_mem_region failed!\n");
1577 disable_mmio(info->par);
1578 err = -1;
1579 goto out_unmap1;
1580 }
1581
1582 info->screen_base = ioremap(tridentfb_fix.smem_start,
1583 tridentfb_fix.smem_len);
1584
1585 if (!info->screen_base) {
1586 debug("ioremap failed\n");
1587 err = -1;
1588 goto out_unmap2;
1589 }
1590
1591 default_par->flatpanel = is_flatpanel(default_par);
1592
1593 if (default_par->flatpanel)
1594 nativex = get_nativex(default_par);
1595
1596 info->fix = tridentfb_fix;
1597 info->fbops = &tridentfb_ops;
1598 info->pseudo_palette = default_par->pseudo_pal;
1599
1600 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1601 if (!noaccel && default_par->init_accel) {
1602 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1603 info->flags |= FBINFO_HWACCEL_COPYAREA;
1604 info->flags |= FBINFO_HWACCEL_FILLRECT;
1605 } else
1606 info->flags |= FBINFO_HWACCEL_DISABLED;
1607
1608 if (is_blade(chip_id) && chip_id != BLADE3D)
1609 info->flags |= FBINFO_READS_FAST;
1610
1611 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1612 if (!info->pixmap.addr) {
1613 err = -ENOMEM;
1614 goto out_unmap2;
1615 }
1616
1617 info->pixmap.size = 4096;
1618 info->pixmap.buf_align = 4;
1619 info->pixmap.scan_align = 1;
1620 info->pixmap.access_align = 32;
1621 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1622 info->var.bits_per_pixel = 8;
1623
1624 if (default_par->image_blit) {
1625 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1626 info->pixmap.scan_align = 4;
1627 }
1628
1629 if (noaccel) {
1630 printk(KERN_DEBUG "disabling acceleration\n");
1631 info->flags |= FBINFO_HWACCEL_DISABLED;
1632 info->pixmap.scan_align = 1;
1633 }
1634
1635 if (tridentfb_setup_ddc_bus(info) == 0) {
1636 u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
1637
1638 default_par->ddc_registered = true;
1639 if (edid) {
1640 fb_edid_to_monspecs(edid, &info->monspecs);
1641 kfree(edid);
1642 if (!info->monspecs.modedb)
1643 dev_err(info->device, "error getting mode database\n");
1644 else {
1645 const struct fb_videomode *m;
1646
1647 fb_videomode_to_modelist(info->monspecs.modedb,
1648 info->monspecs.modedb_len,
1649 &info->modelist);
1650 m = fb_find_best_display(&info->monspecs,
1651 &info->modelist);
1652 if (m) {
1653 fb_videomode_to_var(&info->var, m);
1654 /* fill all other info->var's fields */
1655 if (tridentfb_check_var(&info->var,
1656 info) == 0)
1657 found = true;
1658 }
1659 }
1660 }
1661 }
1662
1663 if (!mode_option && !found)
1664 mode_option = "640x480-8@60";
1665
1666 /* Prepare startup mode */
1667 if (mode_option) {
1668 err = fb_find_mode(&info->var, info, mode_option,
1669 info->monspecs.modedb,
1670 info->monspecs.modedb_len,
1671 NULL, info->var.bits_per_pixel);
1672 if (!err || err == 4) {
1673 err = -EINVAL;
1674 dev_err(info->device, "mode %s not found\n",
1675 mode_option);
1676 fb_destroy_modedb(info->monspecs.modedb);
1677 info->monspecs.modedb = NULL;
1678 goto out_unmap2;
1679 }
1680 }
1681
1682 fb_destroy_modedb(info->monspecs.modedb);
1683 info->monspecs.modedb = NULL;
1684
1685 err = fb_alloc_cmap(&info->cmap, 256, 0);
1686 if (err < 0)
1687 goto out_unmap2;
1688
1689 info->var.activate |= FB_ACTIVATE_NOW;
1690 info->device = &dev->dev;
1691 if (register_framebuffer(info) < 0) {
1692 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1693 fb_dealloc_cmap(&info->cmap);
1694 err = -EINVAL;
1695 goto out_unmap2;
1696 }
1697 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1698 info->node, info->fix.id, info->var.xres,
1699 info->var.yres, info->var.bits_per_pixel);
1700
1701 pci_set_drvdata(dev, info);
1702 return 0;
1703
1704 out_unmap2:
1705 if (default_par->ddc_registered)
1706 i2c_del_adapter(&default_par->ddc_adapter);
1707 kfree(info->pixmap.addr);
1708 if (info->screen_base)
1709 iounmap(info->screen_base);
1710 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1711 disable_mmio(info->par);
1712 out_unmap1:
1713 if (default_par->io_virt)
1714 iounmap(default_par->io_virt);
1715 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1716 framebuffer_release(info);
1717 return err;
1718 }
1719
1720 static void trident_pci_remove(struct pci_dev *dev)
1721 {
1722 struct fb_info *info = pci_get_drvdata(dev);
1723 struct tridentfb_par *par = info->par;
1724
1725 unregister_framebuffer(info);
1726 if (par->ddc_registered)
1727 i2c_del_adapter(&par->ddc_adapter);
1728 iounmap(par->io_virt);
1729 iounmap(info->screen_base);
1730 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1731 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1732 kfree(info->pixmap.addr);
1733 fb_dealloc_cmap(&info->cmap);
1734 framebuffer_release(info);
1735 }
1736
1737 /* List of boards that we are trying to support */
1738 static const struct pci_device_id trident_devices[] = {
1739 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1740 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1741 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1742 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1743 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1744 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1745 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1746 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1747 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1748 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1749 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1750 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1751 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1752 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1753 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1754 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1755 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1756 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1757 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1758 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1759 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1760 {0,}
1761 };
1762
1763 MODULE_DEVICE_TABLE(pci, trident_devices);
1764
1765 static struct pci_driver tridentfb_pci_driver = {
1766 .name = "tridentfb",
1767 .id_table = trident_devices,
1768 .probe = trident_pci_probe,
1769 .remove = trident_pci_remove,
1770 };
1771
1772 /*
1773 * Parse user specified options (`video=trident:')
1774 * example:
1775 * video=trident:800x600,bpp=16,noaccel
1776 */
1777 #ifndef MODULE
1778 static int __init tridentfb_setup(char *options)
1779 {
1780 char *opt;
1781 if (!options || !*options)
1782 return 0;
1783 while ((opt = strsep(&options, ",")) != NULL) {
1784 if (!*opt)
1785 continue;
1786 if (!strncmp(opt, "noaccel", 7))
1787 noaccel = 1;
1788 else if (!strncmp(opt, "fp", 2))
1789 fp = 1;
1790 else if (!strncmp(opt, "crt", 3))
1791 fp = 0;
1792 else if (!strncmp(opt, "bpp=", 4))
1793 bpp = simple_strtoul(opt + 4, NULL, 0);
1794 else if (!strncmp(opt, "center", 6))
1795 center = 1;
1796 else if (!strncmp(opt, "stretch", 7))
1797 stretch = 1;
1798 else if (!strncmp(opt, "memsize=", 8))
1799 memsize = simple_strtoul(opt + 8, NULL, 0);
1800 else if (!strncmp(opt, "memdiff=", 8))
1801 memdiff = simple_strtoul(opt + 8, NULL, 0);
1802 else if (!strncmp(opt, "nativex=", 8))
1803 nativex = simple_strtoul(opt + 8, NULL, 0);
1804 else
1805 mode_option = opt;
1806 }
1807 return 0;
1808 }
1809 #endif
1810
1811 static int __init tridentfb_init(void)
1812 {
1813 #ifndef MODULE
1814 char *option = NULL;
1815
1816 if (fb_get_options("tridentfb", &option))
1817 return -ENODEV;
1818 tridentfb_setup(option);
1819 #endif
1820 return pci_register_driver(&tridentfb_pci_driver);
1821 }
1822
1823 static void __exit tridentfb_exit(void)
1824 {
1825 pci_unregister_driver(&tridentfb_pci_driver);
1826 }
1827
1828 module_init(tridentfb_init);
1829 module_exit(tridentfb_exit);
1830
1831 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1832 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1833 MODULE_LICENSE("GPL");
1834 MODULE_ALIAS("cyblafb");
1835
Linux with added FPC-III support