drivers/watchdog/sirfsoc_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
   4  *
   5  * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/watchdog.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/of.h>
  13 #include <linux/io.h>
  14 #include <linux/uaccess.h>
  15
  16 #define CLOCK_FREQ      1000000
  17
  18 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
  19 #define SIRFSOC_TIMER_MATCH_0           0x0008
  20 #define SIRFSOC_TIMER_INT_EN            0x0024
  21 #define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
  22 #define SIRFSOC_TIMER_LATCH             0x0030
  23 #define SIRFSOC_TIMER_LATCHED_LO        0x0034
  24
  25 #define SIRFSOC_TIMER_WDT_INDEX         5
  26
  27 #define SIRFSOC_WDT_MIN_TIMEOUT         30              /* 30 secs */
  28 #define SIRFSOC_WDT_MAX_TIMEOUT         (10 * 60)       /* 10 mins */
  29 #define SIRFSOC_WDT_DEFAULT_TIMEOUT     30              /* 30 secs */
  30
  31 static unsigned int timeout;
  32 static bool nowayout = WATCHDOG_NOWAYOUT;
  33
  34 module_param(timeout, uint, 0);
  35 module_param(nowayout, bool, 0);
  36
  37 MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)");
  38 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  39                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  40
  41 static void __iomem *sirfsoc_wdt_base(struct watchdog_device *wdd)
  42 {
  43         return (void __iomem __force *)watchdog_get_drvdata(wdd);
  44 }
  45
  46 static unsigned int sirfsoc_wdt_gettimeleft(struct watchdog_device *wdd)
  47 {
  48         u32 counter, match;
  49         void __iomem *wdt_base;
  50         int time_left;
  51
  52         wdt_base = sirfsoc_wdt_base(wdd);
  53         counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO);
  54         match = readl(wdt_base +
  55                 SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
  56
  57         time_left = match - counter;
  58
  59         return time_left / CLOCK_FREQ;
  60 }
  61
  62 static int sirfsoc_wdt_updatetimeout(struct watchdog_device *wdd)
  63 {
  64         u32 counter, timeout_ticks;
  65         void __iomem *wdt_base;
  66
  67         timeout_ticks = wdd->timeout * CLOCK_FREQ;
  68         wdt_base = sirfsoc_wdt_base(wdd);
  69
  70         /* Enable the latch before reading the LATCH_LO register */
  71         writel(1, wdt_base + SIRFSOC_TIMER_LATCH);
  72
  73         /* Set the TO value */
  74         counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO);
  75
  76         counter += timeout_ticks;
  77
  78         writel(counter, wdt_base +
  79                 SIRFSOC_TIMER_MATCH_0 + (SIRFSOC_TIMER_WDT_INDEX << 2));
  80
  81         return 0;
  82 }
  83
  84 static int sirfsoc_wdt_enable(struct watchdog_device *wdd)
  85 {
  86         void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
  87         sirfsoc_wdt_updatetimeout(wdd);
  88
  89         /*
  90          * NOTE: If interrupt is not enabled
  91          * then WD-Reset doesn't get generated at all.
  92          */
  93         writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
  94                 | (1 << SIRFSOC_TIMER_WDT_INDEX),
  95                 wdt_base + SIRFSOC_TIMER_INT_EN);
  96         writel(1, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
  97
  98         return 0;
  99 }
 100
 101 static int sirfsoc_wdt_disable(struct watchdog_device *wdd)
 102 {
 103         void __iomem *wdt_base = sirfsoc_wdt_base(wdd);
 104
 105         writel(0, wdt_base + SIRFSOC_TIMER_WATCHDOG_EN);
 106         writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN)
 107                 & (~(1 << SIRFSOC_TIMER_WDT_INDEX)),
 108                 wdt_base + SIRFSOC_TIMER_INT_EN);
 109
 110         return 0;
 111 }
 112
 113 static int sirfsoc_wdt_settimeout(struct watchdog_device *wdd, unsigned int to)
 114 {
 115         wdd->timeout = to;
 116         sirfsoc_wdt_updatetimeout(wdd);
 117
 118         return 0;
 119 }
 120
 121 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 122
 123 static const struct watchdog_info sirfsoc_wdt_ident = {
 124         .options          =     OPTIONS,
 125         .firmware_version =     0,
 126         .identity         =     "SiRFSOC Watchdog",
 127 };
 128
 129 static const struct watchdog_ops sirfsoc_wdt_ops = {
 130         .owner = THIS_MODULE,
 131         .start = sirfsoc_wdt_enable,
 132         .stop = sirfsoc_wdt_disable,
 133         .get_timeleft = sirfsoc_wdt_gettimeleft,
 134         .ping = sirfsoc_wdt_updatetimeout,
 135         .set_timeout = sirfsoc_wdt_settimeout,
 136 };
 137
 138 static struct watchdog_device sirfsoc_wdd = {
 139         .info = &sirfsoc_wdt_ident,
 140         .ops = &sirfsoc_wdt_ops,
 141         .timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT,
 142         .min_timeout = SIRFSOC_WDT_MIN_TIMEOUT,
 143         .max_timeout = SIRFSOC_WDT_MAX_TIMEOUT,
 144 };
 145
 146 static int sirfsoc_wdt_probe(struct platform_device *pdev)
 147 {
 148         struct device *dev = &pdev->dev;
 149         int ret;
 150         void __iomem *base;
 151
 152         base = devm_platform_ioremap_resource(pdev, 0);
 153         if (IS_ERR(base))
 154                 return PTR_ERR(base);
 155
 156         watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base);
 157
 158         watchdog_init_timeout(&sirfsoc_wdd, timeout, dev);
 159         watchdog_set_nowayout(&sirfsoc_wdd, nowayout);
 160         sirfsoc_wdd.parent = dev;
 161
 162         watchdog_stop_on_reboot(&sirfsoc_wdd);
 163         watchdog_stop_on_unregister(&sirfsoc_wdd);
 164         ret = devm_watchdog_register_device(dev, &sirfsoc_wdd);
 165         if (ret)
 166                 return ret;
 167
 168         platform_set_drvdata(pdev, &sirfsoc_wdd);
 169
 170         return 0;
 171 }
 172
 173 #ifdef  CONFIG_PM_SLEEP
 174 static int sirfsoc_wdt_suspend(struct device *dev)
 175 {
 176         return 0;
 177 }
 178
 179 static int sirfsoc_wdt_resume(struct device *dev)
 180 {
 181         struct watchdog_device *wdd = dev_get_drvdata(dev);
 182
 183         /*
 184          * NOTE: Since timer controller registers settings are saved
 185          * and restored back by the timer-prima2.c, so we need not
 186          * update WD settings except refreshing timeout.
 187          */
 188         sirfsoc_wdt_updatetimeout(wdd);
 189
 190         return 0;
 191 }
 192 #endif
 193
 194 static SIMPLE_DEV_PM_OPS(sirfsoc_wdt_pm_ops,
 195                 sirfsoc_wdt_suspend, sirfsoc_wdt_resume);
 196
 197 static const struct of_device_id sirfsoc_wdt_of_match[] = {
 198         { .compatible = "sirf,prima2-tick"},
 199         {},
 200 };
 201 MODULE_DEVICE_TABLE(of, sirfsoc_wdt_of_match);
 202
 203 static struct platform_driver sirfsoc_wdt_driver = {
 204         .driver = {
 205                 .name = "sirfsoc-wdt",
 206                 .pm = &sirfsoc_wdt_pm_ops,
 207                 .of_match_table = sirfsoc_wdt_of_match,
 208         },
 209         .probe = sirfsoc_wdt_probe,
 210 };
 211 module_platform_driver(sirfsoc_wdt_driver);
 212
 213 MODULE_DESCRIPTION("SiRF SoC watchdog driver");
 214 MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
 215 MODULE_LICENSE("GPL v2");
 216 MODULE_ALIAS("platform:sirfsoc-wdt");