drivers/crypto/hisilicon/qm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2019 HiSilicon Limited. */
   3 #ifndef HISI_ACC_QM_H
   4 #define HISI_ACC_QM_H
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/module.h>
   9 #include <linux/pci.h>
  10
  11 /* qm user domain */
  12 #define QM_ARUSER_M_CFG_1               0x100088
  13 #define AXUSER_SNOOP_ENABLE             BIT(30)
  14 #define AXUSER_CMD_TYPE                 GENMASK(14, 12)
  15 #define AXUSER_CMD_SMMU_NORMAL          1
  16 #define AXUSER_NS                       BIT(6)
  17 #define AXUSER_NO                       BIT(5)
  18 #define AXUSER_FP                       BIT(4)
  19 #define AXUSER_SSV                      BIT(0)
  20 #define AXUSER_BASE                     (AXUSER_SNOOP_ENABLE |          \
  21                                         FIELD_PREP(AXUSER_CMD_TYPE,     \
  22                                         AXUSER_CMD_SMMU_NORMAL) |       \
  23                                         AXUSER_NS | AXUSER_NO | AXUSER_FP)
  24 #define QM_ARUSER_M_CFG_ENABLE          0x100090
  25 #define ARUSER_M_CFG_ENABLE             0xfffffffe
  26 #define QM_AWUSER_M_CFG_1               0x100098
  27 #define QM_AWUSER_M_CFG_ENABLE          0x1000a0
  28 #define AWUSER_M_CFG_ENABLE             0xfffffffe
  29 #define QM_WUSER_M_CFG_ENABLE           0x1000a8
  30 #define WUSER_M_CFG_ENABLE              0xffffffff
  31
  32 /* qm cache */
  33 #define QM_CACHE_CTL                    0x100050
  34 #define SQC_CACHE_ENABLE                BIT(0)
  35 #define CQC_CACHE_ENABLE                BIT(1)
  36 #define SQC_CACHE_WB_ENABLE             BIT(4)
  37 #define SQC_CACHE_WB_THRD               GENMASK(10, 5)
  38 #define CQC_CACHE_WB_ENABLE             BIT(11)
  39 #define CQC_CACHE_WB_THRD               GENMASK(17, 12)
  40 #define QM_AXI_M_CFG                    0x1000ac
  41 #define AXI_M_CFG                       0xffff
  42 #define QM_AXI_M_CFG_ENABLE             0x1000b0
  43 #define AXI_M_CFG_ENABLE                0xffffffff
  44 #define QM_PEH_AXUSER_CFG               0x1000cc
  45 #define QM_PEH_AXUSER_CFG_ENABLE        0x1000d0
  46 #define PEH_AXUSER_CFG                  0x401001
  47 #define PEH_AXUSER_CFG_ENABLE           0xffffffff
  48
  49 #define QM_DFX_MB_CNT_VF                0x104010
  50 #define QM_DFX_DB_CNT_VF                0x104020
  51 #define QM_DFX_SQE_CNT_VF_SQN           0x104030
  52 #define QM_DFX_CQE_CNT_VF_CQN           0x104040
  53 #define QM_DFX_QN_SHIFT                 16
  54 #define CURRENT_FUN_MASK                GENMASK(5, 0)
  55 #define CURRENT_Q_MASK                  GENMASK(31, 16)
  56
  57 #define QM_AXI_RRESP                    BIT(0)
  58 #define QM_AXI_BRESP                    BIT(1)
  59 #define QM_ECC_MBIT                     BIT(2)
  60 #define QM_ECC_1BIT                     BIT(3)
  61 #define QM_ACC_GET_TASK_TIMEOUT         BIT(4)
  62 #define QM_ACC_DO_TASK_TIMEOUT          BIT(5)
  63 #define QM_ACC_WB_NOT_READY_TIMEOUT     BIT(6)
  64 #define QM_SQ_CQ_VF_INVALID             BIT(7)
  65 #define QM_CQ_VF_INVALID                BIT(8)
  66 #define QM_SQ_VF_INVALID                BIT(9)
  67 #define QM_DB_TIMEOUT                   BIT(10)
  68 #define QM_OF_FIFO_OF                   BIT(11)
  69 #define QM_DB_RANDOM_INVALID            BIT(12)
  70
  71 #define QM_BASE_NFE     (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
  72                          QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
  73                          QM_OF_FIFO_OF)
  74 #define QM_BASE_CE                      QM_ECC_1BIT
  75
  76 #define QM_Q_DEPTH                      1024
  77
  78 #define HISI_ACC_SGL_SGE_NR_MAX         255
  79
  80 /* page number for queue file region */
  81 #define QM_DOORBELL_PAGE_NR             1
  82
  83 enum qp_state {
  84         QP_STOP,
  85 };
  86
  87 enum qm_hw_ver {
  88         QM_HW_UNKNOWN = -1,
  89         QM_HW_V1 = 0x20,
  90         QM_HW_V2 = 0x21,
  91 };
  92
  93 enum qm_fun_type {
  94         QM_HW_PF,
  95         QM_HW_VF,
  96 };
  97
  98 enum qm_debug_file {
  99         CURRENT_Q,
 100         CLEAR_ENABLE,
 101         DEBUG_FILE_NUM,
 102 };
 103
 104 struct debugfs_file {
 105         enum qm_debug_file index;
 106         struct mutex lock;
 107         struct qm_debug *debug;
 108 };
 109
 110 struct qm_debug {
 111         u32 curr_qm_qp_num;
 112         struct dentry *debug_root;
 113         struct dentry *qm_d;
 114         struct debugfs_file files[DEBUG_FILE_NUM];
 115 };
 116
 117 struct qm_dma {
 118         void *va;
 119         dma_addr_t dma;
 120         size_t size;
 121 };
 122
 123 struct hisi_qm_status {
 124         u32 eq_head;
 125         bool eqc_phase;
 126         u32 aeq_head;
 127         bool aeqc_phase;
 128         unsigned long flags;
 129 };
 130
 131 struct hisi_qm;
 132
 133 struct hisi_qm_err_info {
 134         u32 ce;
 135         u32 nfe;
 136         u32 fe;
 137         u32 msi;
 138 };
 139
 140 struct hisi_qm_err_ini {
 141         void (*hw_err_enable)(struct hisi_qm *qm);
 142         void (*hw_err_disable)(struct hisi_qm *qm);
 143         u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
 144         void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
 145         struct hisi_qm_err_info err_info;
 146 };
 147
 148 struct hisi_qm_list {
 149         struct mutex lock;
 150         struct list_head list;
 151 };
 152
 153 struct hisi_qm {
 154         enum qm_hw_ver ver;
 155         enum qm_fun_type fun_type;
 156         const char *dev_name;
 157         struct pci_dev *pdev;
 158         void __iomem *io_base;
 159         u32 sqe_size;
 160         u32 qp_base;
 161         u32 qp_num;
 162         u32 qp_in_used;
 163         u32 ctrl_qp_num;
 164         struct list_head list;
 165
 166         struct qm_dma qdma;
 167         struct qm_sqc *sqc;
 168         struct qm_cqc *cqc;
 169         struct qm_eqe *eqe;
 170         struct qm_aeqe *aeqe;
 171         dma_addr_t sqc_dma;
 172         dma_addr_t cqc_dma;
 173         dma_addr_t eqe_dma;
 174         dma_addr_t aeqe_dma;
 175
 176         struct hisi_qm_status status;
 177         const struct hisi_qm_err_ini *err_ini;
 178
 179         rwlock_t qps_lock;
 180         unsigned long *qp_bitmap;
 181         struct hisi_qp **qp_array;
 182
 183         struct mutex mailbox_lock;
 184
 185         const struct hisi_qm_hw_ops *ops;
 186
 187         struct qm_debug debug;
 188
 189         u32 error_mask;
 190         u32 msi_mask;
 191
 192         struct workqueue_struct *wq;
 193         struct work_struct work;
 194
 195         const char *algs;
 196         bool use_dma_api;
 197         bool use_sva;
 198         resource_size_t phys_base;
 199         resource_size_t phys_size;
 200         struct uacce_device *uacce;
 201 };
 202
 203 struct hisi_qp_status {
 204         atomic_t used;
 205         u16 sq_tail;
 206         u16 cq_head;
 207         bool cqc_phase;
 208         unsigned long flags;
 209 };
 210
 211 struct hisi_qp_ops {
 212         int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
 213 };
 214
 215 struct hisi_qp {
 216         u32 qp_id;
 217         u8 alg_type;
 218         u8 req_type;
 219
 220         struct qm_dma qdma;
 221         void *sqe;
 222         struct qm_cqe *cqe;
 223         dma_addr_t sqe_dma;
 224         dma_addr_t cqe_dma;
 225
 226         struct hisi_qp_status qp_status;
 227         struct hisi_qp_ops *hw_ops;
 228         void *qp_ctx;
 229         void (*req_cb)(struct hisi_qp *qp, void *data);
 230         void (*event_cb)(struct hisi_qp *qp);
 231
 232         struct hisi_qm *qm;
 233         u16 pasid;
 234         struct uacce_queue *uacce_q;
 235 };
 236
 237 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
 238 {
 239         INIT_LIST_HEAD(&qm_list->list);
 240         mutex_init(&qm_list->lock);
 241 }
 242
 243 static inline void hisi_qm_add_to_list(struct hisi_qm *qm,
 244                                        struct hisi_qm_list *qm_list)
 245 {
 246         mutex_lock(&qm_list->lock);
 247         list_add_tail(&qm->list, &qm_list->list);
 248         mutex_unlock(&qm_list->lock);
 249 }
 250
 251 static inline void hisi_qm_del_from_list(struct hisi_qm *qm,
 252                                          struct hisi_qm_list *qm_list)
 253 {
 254         mutex_lock(&qm_list->lock);
 255         list_del(&qm->list);
 256         mutex_unlock(&qm_list->lock);
 257 }
 258
 259 int hisi_qm_init(struct hisi_qm *qm);
 260 void hisi_qm_uninit(struct hisi_qm *qm);
 261 int hisi_qm_start(struct hisi_qm *qm);
 262 int hisi_qm_stop(struct hisi_qm *qm);
 263 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
 264 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
 265 int hisi_qm_stop_qp(struct hisi_qp *qp);
 266 void hisi_qm_release_qp(struct hisi_qp *qp);
 267 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
 268 int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
 269 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
 270 int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
 271 int hisi_qm_debug_init(struct hisi_qm *qm);
 272 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
 273 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
 274 void hisi_qm_dev_err_init(struct hisi_qm *qm);
 275 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
 276 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
 277                                           pci_channel_state_t state);
 278
 279 struct hisi_acc_sgl_pool;
 280 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
 281         struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
 282         u32 index, dma_addr_t *hw_sgl_dma);
 283 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
 284                            struct hisi_acc_hw_sgl *hw_sgl);
 285 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
 286                                                    u32 count, u32 sge_nr);
 287 void hisi_acc_free_sgl_pool(struct device *dev,
 288                             struct hisi_acc_sgl_pool *pool);
 289 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
 290                            u8 alg_type, int node, struct hisi_qp **qps);
 291 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
 292 #endif