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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / crypto / hisilicon / sec2 / sec_main.c
blob1f54ebe164b648316b3b01a78f54191391762b25
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/aer.h>
6 #include <linux/bitops.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
9 #include <linux/io.h>
10 #include <linux/iommu.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/seq_file.h>
15 #include <linux/topology.h>
16
17 #include "sec.h"
18
19 #define SEC_VF_NUM 63
20 #define SEC_QUEUE_NUM_V1 4096
21 #define SEC_QUEUE_NUM_V2 1024
22 #define SEC_PF_PCI_DEVICE_ID 0xa255
23 #define SEC_VF_PCI_DEVICE_ID 0xa256
24
25 #define SEC_XTS_MIV_ENABLE_REG 0x301384
26 #define SEC_XTS_MIV_ENABLE_MSK 0x7FFFFFFF
27 #define SEC_XTS_MIV_DISABLE_MSK 0xFFFFFFFF
28 #define SEC_BD_ERR_CHK_EN1 0xfffff7fd
29 #define SEC_BD_ERR_CHK_EN2 0xffffbfff
30
31 #define SEC_SQE_SIZE 128
32 #define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH)
33 #define SEC_PF_DEF_Q_NUM 64
34 #define SEC_PF_DEF_Q_BASE 0
35 #define SEC_CTX_Q_NUM_DEF 24
36 #define SEC_CTX_Q_NUM_MAX 32
37
38 #define SEC_CTRL_CNT_CLR_CE 0x301120
39 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
40 #define SEC_ENGINE_PF_CFG_OFF 0x300000
41 #define SEC_ACC_COMMON_REG_OFF 0x1000
42 #define SEC_CORE_INT_SOURCE 0x301010
43 #define SEC_CORE_INT_MASK 0x301000
44 #define SEC_CORE_INT_STATUS 0x301008
45 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
46 #define SEC_ECC_NUM(err) (((err) >> 16) & 0xFF)
47 #define SEC_ECC_ADDR(err) ((err) >> 0)
48 #define SEC_CORE_INT_DISABLE 0x0
49 #define SEC_CORE_INT_ENABLE 0x1ff
50
51 #define SEC_RAS_CE_REG 0x50
52 #define SEC_RAS_FE_REG 0x54
53 #define SEC_RAS_NFE_REG 0x58
54 #define SEC_RAS_CE_ENB_MSK 0x88
55 #define SEC_RAS_FE_ENB_MSK 0x0
56 #define SEC_RAS_NFE_ENB_MSK 0x177
57 #define SEC_RAS_DISABLE 0x0
58 #define SEC_MEM_START_INIT_REG 0x0100
59 #define SEC_MEM_INIT_DONE_REG 0x0104
60 #define SEC_QM_ABNORMAL_INT_MASK 0x100004
61
62 #define SEC_CONTROL_REG 0x0200
63 #define SEC_TRNG_EN_SHIFT 8
64 #define SEC_CLK_GATE_ENABLE BIT(3)
65 #define SEC_CLK_GATE_DISABLE (~BIT(3))
66 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
67 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
68
69 #define SEC_INTERFACE_USER_CTRL0_REG 0x0220
70 #define SEC_INTERFACE_USER_CTRL1_REG 0x0224
71 #define SEC_BD_ERR_CHK_EN_REG1 0x0384
72 #define SEC_BD_ERR_CHK_EN_REG2 0x038c
73
74 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
75 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
76 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
77
78 #define SEC_DELAY_10_US 10
79 #define SEC_POLL_TIMEOUT_US 1000
80 #define SEC_VF_CNT_MASK 0xffffffc0
81 #define SEC_DBGFS_VAL_MAX_LEN 20
82
83 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
84 SEC_ENGINE_PF_CFG_OFF + SEC_ACC_COMMON_REG_OFF)
85
86 struct sec_hw_error {
87 u32 int_msk;
88 const char *msg;
89 };
90
91 static const char sec_name[] = "hisi_sec2";
92 static struct dentry *sec_debugfs_root;
93 static struct hisi_qm_list sec_devices;
94
95 static const struct sec_hw_error sec_hw_errors[] = {
96 {.int_msk = BIT(0), .msg = "sec_axi_rresp_err_rint"},
97 {.int_msk = BIT(1), .msg = "sec_axi_bresp_err_rint"},
98 {.int_msk = BIT(2), .msg = "sec_ecc_2bit_err_rint"},
99 {.int_msk = BIT(3), .msg = "sec_ecc_1bit_err_rint"},
100 {.int_msk = BIT(4), .msg = "sec_req_trng_timeout_rint"},
101 {.int_msk = BIT(5), .msg = "sec_fsm_hbeat_rint"},
102 {.int_msk = BIT(6), .msg = "sec_channel_req_rng_timeout_rint"},
103 {.int_msk = BIT(7), .msg = "sec_bd_err_rint"},
104 {.int_msk = BIT(8), .msg = "sec_chain_buff_err_rint"},
105 { /* sentinel */ }
106 };
107
108 static const char * const sec_dbg_file_name[] = {
109 [SEC_CURRENT_QM] = "current_qm",
110 [SEC_CLEAR_ENABLE] = "clear_enable",
111 };
112
113 static struct debugfs_reg32 sec_dfx_regs[] = {
114 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
115 {"SEC_SAA_EN ", 0x301270},
116 {"SEC_BD_LATENCY_MIN ", 0x301600},
117 {"SEC_BD_LATENCY_MAX ", 0x301608},
118 {"SEC_BD_LATENCY_AVG ", 0x30160C},
119 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
120 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
121 {"SEC_BD_NUM_IN_SEC ", 0x301680},
122 {"SEC_ECC_1BIT_CNT ", 0x301C00},
123 {"SEC_ECC_1BIT_INFO ", 0x301C04},
124 {"SEC_ECC_2BIT_CNT ", 0x301C10},
125 {"SEC_ECC_2BIT_INFO ", 0x301C14},
126 {"SEC_BD_SAA0 ", 0x301C20},
127 {"SEC_BD_SAA1 ", 0x301C24},
128 {"SEC_BD_SAA2 ", 0x301C28},
129 {"SEC_BD_SAA3 ", 0x301C2C},
130 {"SEC_BD_SAA4 ", 0x301C30},
131 {"SEC_BD_SAA5 ", 0x301C34},
132 {"SEC_BD_SAA6 ", 0x301C38},
133 {"SEC_BD_SAA7 ", 0x301C3C},
134 {"SEC_BD_SAA8 ", 0x301C40},
135 };
136
137 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
138 {
139 struct pci_dev *pdev;
140 u32 n, q_num;
141 u8 rev_id;
142 int ret;
143
144 if (!val)
145 return -EINVAL;
146
147 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
148 SEC_PF_PCI_DEVICE_ID, NULL);
149 if (!pdev) {
150 q_num = min_t(u32, SEC_QUEUE_NUM_V1, SEC_QUEUE_NUM_V2);
151 pr_info("No device, suppose queue number is %d!\n", q_num);
152 } else {
153 rev_id = pdev->revision;
154
155 switch (rev_id) {
156 case QM_HW_V1:
157 q_num = SEC_QUEUE_NUM_V1;
158 break;
159 case QM_HW_V2:
160 q_num = SEC_QUEUE_NUM_V2;
161 break;
162 default:
163 return -EINVAL;
164 }
165 }
166
167 ret = kstrtou32(val, 10, &n);
168 if (ret || !n || n > q_num)
169 return -EINVAL;
170
171 return param_set_int(val, kp);
172 }
173
174 static const struct kernel_param_ops sec_pf_q_num_ops = {
175 .set = sec_pf_q_num_set,
176 .get = param_get_int,
177 };
178 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
179 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
180 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 0-4096, v2 0-1024)");
181
182 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
183 {
184 u32 ctx_q_num;
185 int ret;
186
187 if (!val)
188 return -EINVAL;
189
190 ret = kstrtou32(val, 10, &ctx_q_num);
191 if (ret)
192 return -EINVAL;
193
194 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
195 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
196 return -EINVAL;
197 }
198
199 return param_set_int(val, kp);
200 }
201
202 static const struct kernel_param_ops sec_ctx_q_num_ops = {
203 .set = sec_ctx_q_num_set,
204 .get = param_get_int,
205 };
206 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
207 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
208 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)");
209
210 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
211 {
212 hisi_qm_free_qps(qps, qp_num);
213 kfree(qps);
214 }
215
216 struct hisi_qp **sec_create_qps(void)
217 {
218 int node = cpu_to_node(smp_processor_id());
219 u32 ctx_num = ctx_q_num;
220 struct hisi_qp **qps;
221 int ret;
222
223 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL);
224 if (!qps)
225 return NULL;
226
227 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps);
228 if (!ret)
229 return qps;
230
231 kfree(qps);
232 return NULL;
233 }
234
235
236 static const struct pci_device_id sec_dev_ids[] = {
237 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PF_PCI_DEVICE_ID) },
238 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_VF_PCI_DEVICE_ID) },
239 { 0, }
240 };
241 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
242
243 static u8 sec_get_endian(struct sec_dev *sec)
244 {
245 struct hisi_qm *qm = &sec->qm;
246 u32 reg;
247
248 /*
249 * As for VF, it is a wrong way to get endian setting by
250 * reading a register of the engine
251 */
252 if (qm->pdev->is_virtfn) {
253 dev_err_ratelimited(&qm->pdev->dev,
254 "cannot access a register in VF!\n");
255 return SEC_LE;
256 }
257 reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF +
258 SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG);
259
260 /* BD little endian mode */
261 if (!(reg & BIT(0)))
262 return SEC_LE;
263
264 /* BD 32-bits big endian mode */
265 else if (!(reg & BIT(1)))
266 return SEC_32BE;
267
268 /* BD 64-bits big endian mode */
269 else
270 return SEC_64BE;
271 }
272
273 static int sec_engine_init(struct sec_dev *sec)
274 {
275 struct hisi_qm *qm = &sec->qm;
276 int ret;
277 u32 reg;
278
279 /* disable clock gate control */
280 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
281 reg &= SEC_CLK_GATE_DISABLE;
282 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
283
284 writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG));
285
286 ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG),
287 reg, reg & 0x1, SEC_DELAY_10_US,
288 SEC_POLL_TIMEOUT_US);
289 if (ret) {
290 dev_err(&qm->pdev->dev, "fail to init sec mem\n");
291 return ret;
292 }
293
294 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
295 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
296 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
297
298 reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));
299 reg |= SEC_USER0_SMMU_NORMAL;
300 writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG));
301
302 reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));
303 reg |= SEC_USER1_SMMU_NORMAL;
304 writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG));
305
306 writel_relaxed(SEC_BD_ERR_CHK_EN1,
307 SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG1));
308 writel_relaxed(SEC_BD_ERR_CHK_EN2,
309 SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG2));
310
311 /* enable clock gate control */
312 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
313 reg |= SEC_CLK_GATE_ENABLE;
314 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
315
316 /* config endian */
317 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
318 reg |= sec_get_endian(sec);
319 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
320
321 /* Enable sm4 xts mode multiple iv */
322 writel_relaxed(SEC_XTS_MIV_ENABLE_MSK,
323 qm->io_base + SEC_XTS_MIV_ENABLE_REG);
324
325 return 0;
326 }
327
328 static int sec_set_user_domain_and_cache(struct sec_dev *sec)
329 {
330 struct hisi_qm *qm = &sec->qm;
331
332 /* qm user domain */
333 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
334 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
335 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
336 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
337 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
338
339 /* qm cache */
340 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
341 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
342
343 /* disable FLR triggered by BME(bus master enable) */
344 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
345 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
346
347 /* enable sqc,cqc writeback */
348 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
349 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
350 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
351
352 return sec_engine_init(sec);
353 }
354
355 /* sec_debug_regs_clear() - clear the sec debug regs */
356 static void sec_debug_regs_clear(struct hisi_qm *qm)
357 {
358 /* clear current_qm */
359 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
360 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
361
362 /* clear rdclr_en */
363 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
364
365 hisi_qm_debug_regs_clear(qm);
366 }
367
368 static void sec_hw_error_enable(struct hisi_qm *qm)
369 {
370 u32 val;
371
372 if (qm->ver == QM_HW_V1) {
373 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
374 dev_info(&qm->pdev->dev, "V1 not support hw error handle\n");
375 return;
376 }
377
378 val = readl(qm->io_base + SEC_CONTROL_REG);
379
380 /* clear SEC hw error source if having */
381 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_SOURCE);
382
383 /* enable SEC hw error interrupts */
384 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK);
385
386 /* enable RAS int */
387 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG);
388 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
389 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG);
390
391 /* enable SEC block master OOO when m-bit error occur */
392 val = val | SEC_AXI_SHUTDOWN_ENABLE;
393
394 writel(val, qm->io_base + SEC_CONTROL_REG);
395 }
396
397 static void sec_hw_error_disable(struct hisi_qm *qm)
398 {
399 u32 val;
400
401 val = readl(qm->io_base + SEC_CONTROL_REG);
402
403 /* disable RAS int */
404 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
405 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
406 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
407
408 /* disable SEC hw error interrupts */
409 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
410
411 /* disable SEC block master OOO when m-bit error occur */
412 val = val & SEC_AXI_SHUTDOWN_DISABLE;
413
414 writel(val, qm->io_base + SEC_CONTROL_REG);
415 }
416
417 static u32 sec_current_qm_read(struct sec_debug_file *file)
418 {
419 struct hisi_qm *qm = file->qm;
420
421 return readl(qm->io_base + QM_DFX_MB_CNT_VF);
422 }
423
424 static int sec_current_qm_write(struct sec_debug_file *file, u32 val)
425 {
426 struct hisi_qm *qm = file->qm;
427 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
428 u32 vfq_num;
429 u32 tmp;
430
431 if (val > sec->num_vfs)
432 return -EINVAL;
433
434 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
435 if (!val) {
436 qm->debug.curr_qm_qp_num = qm->qp_num;
437 } else {
438 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / sec->num_vfs;
439
440 if (val == sec->num_vfs)
441 qm->debug.curr_qm_qp_num =
442 qm->ctrl_qp_num - qm->qp_num -
443 (sec->num_vfs - 1) * vfq_num;
444 else
445 qm->debug.curr_qm_qp_num = vfq_num;
446 }
447
448 writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
449 writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
450
451 tmp = val |
452 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
453 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
454
455 tmp = val |
456 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
457 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
458
459 return 0;
460 }
461
462 static u32 sec_clear_enable_read(struct sec_debug_file *file)
463 {
464 struct hisi_qm *qm = file->qm;
465
466 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
467 SEC_CTRL_CNT_CLR_CE_BIT;
468 }
469
470 static int sec_clear_enable_write(struct sec_debug_file *file, u32 val)
471 {
472 struct hisi_qm *qm = file->qm;
473 u32 tmp;
474
475 if (val != 1 && val)
476 return -EINVAL;
477
478 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
479 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
480 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
481
482 return 0;
483 }
484
485 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
486 size_t count, loff_t *pos)
487 {
488 struct sec_debug_file *file = filp->private_data;
489 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
490 u32 val;
491 int ret;
492
493 spin_lock_irq(&file->lock);
494
495 switch (file->index) {
496 case SEC_CURRENT_QM:
497 val = sec_current_qm_read(file);
498 break;
499 case SEC_CLEAR_ENABLE:
500 val = sec_clear_enable_read(file);
501 break;
502 default:
503 spin_unlock_irq(&file->lock);
504 return -EINVAL;
505 }
506
507 spin_unlock_irq(&file->lock);
508 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
509
510 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
511 }
512
513 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
514 size_t count, loff_t *pos)
515 {
516 struct sec_debug_file *file = filp->private_data;
517 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
518 unsigned long val;
519 int len, ret;
520
521 if (*pos != 0)
522 return 0;
523
524 if (count >= SEC_DBGFS_VAL_MAX_LEN)
525 return -ENOSPC;
526
527 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
528 pos, buf, count);
529 if (len < 0)
530 return len;
531
532 tbuf[len] = '\0';
533 if (kstrtoul(tbuf, 0, &val))
534 return -EFAULT;
535
536 spin_lock_irq(&file->lock);
537
538 switch (file->index) {
539 case SEC_CURRENT_QM:
540 ret = sec_current_qm_write(file, val);
541 if (ret)
542 goto err_input;
543 break;
544 case SEC_CLEAR_ENABLE:
545 ret = sec_clear_enable_write(file, val);
546 if (ret)
547 goto err_input;
548 break;
549 default:
550 ret = -EINVAL;
551 goto err_input;
552 }
553
554 spin_unlock_irq(&file->lock);
555
556 return count;
557
558 err_input:
559 spin_unlock_irq(&file->lock);
560 return ret;
561 }
562
563 static const struct file_operations sec_dbg_fops = {
564 .owner = THIS_MODULE,
565 .open = simple_open,
566 .read = sec_debug_read,
567 .write = sec_debug_write,
568 };
569
570 static int sec_debugfs_atomic64_get(void *data, u64 *val)
571 {
572 *val = atomic64_read((atomic64_t *)data);
573 return 0;
574 }
575 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
576 NULL, "%lld\n");
577
578 static int sec_core_debug_init(struct sec_dev *sec)
579 {
580 struct hisi_qm *qm = &sec->qm;
581 struct device *dev = &qm->pdev->dev;
582 struct sec_dfx *dfx = &sec->debug.dfx;
583 struct debugfs_regset32 *regset;
584 struct dentry *tmp_d;
585
586 tmp_d = debugfs_create_dir("sec_dfx", sec->qm.debug.debug_root);
587
588 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
589 if (!regset)
590 return -ENOENT;
591
592 regset->regs = sec_dfx_regs;
593 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
594 regset->base = qm->io_base;
595
596 debugfs_create_regset32("regs", 0444, tmp_d, regset);
597
598 debugfs_create_file("send_cnt", 0444, tmp_d,
599 &dfx->send_cnt, &sec_atomic64_ops);
600
601 debugfs_create_file("recv_cnt", 0444, tmp_d,
602 &dfx->recv_cnt, &sec_atomic64_ops);
603
604 return 0;
605 }
606
607 static int sec_debug_init(struct sec_dev *sec)
608 {
609 int i;
610
611 for (i = SEC_CURRENT_QM; i < SEC_DEBUG_FILE_NUM; i++) {
612 spin_lock_init(&sec->debug.files[i].lock);
613 sec->debug.files[i].index = i;
614 sec->debug.files[i].qm = &sec->qm;
615
616 debugfs_create_file(sec_dbg_file_name[i], 0600,
617 sec->qm.debug.debug_root,
618 sec->debug.files + i,
619 &sec_dbg_fops);
620 }
621
622 return sec_core_debug_init(sec);
623 }
624
625 static int sec_debugfs_init(struct sec_dev *sec)
626 {
627 struct hisi_qm *qm = &sec->qm;
628 struct device *dev = &qm->pdev->dev;
629 int ret;
630
631 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
632 sec_debugfs_root);
633 ret = hisi_qm_debug_init(qm);
634 if (ret)
635 goto failed_to_create;
636
637 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) {
638 ret = sec_debug_init(sec);
639 if (ret)
640 goto failed_to_create;
641 }
642
643 return 0;
644
645 failed_to_create:
646 debugfs_remove_recursive(sec_debugfs_root);
647
648 return ret;
649 }
650
651 static void sec_debugfs_exit(struct sec_dev *sec)
652 {
653 debugfs_remove_recursive(sec->qm.debug.debug_root);
654 }
655
656 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
657 {
658 const struct sec_hw_error *errs = sec_hw_errors;
659 struct device *dev = &qm->pdev->dev;
660 u32 err_val;
661
662 while (errs->msg) {
663 if (errs->int_msk & err_sts) {
664 dev_err(dev, "%s [error status=0x%x] found\n",
665 errs->msg, errs->int_msk);
666
667 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
668 err_val = readl(qm->io_base +
669 SEC_CORE_SRAM_ECC_ERR_INFO);
670 dev_err(dev, "multi ecc sram num=0x%x\n",
671 SEC_ECC_NUM(err_val));
672 dev_err(dev, "multi ecc sram addr=0x%x\n",
673 SEC_ECC_ADDR(err_val));
674 }
675 }
676 errs++;
677 }
678
679 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
680 }
681
682 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
683 {
684 return readl(qm->io_base + SEC_CORE_INT_STATUS);
685 }
686
687 static const struct hisi_qm_err_ini sec_err_ini = {
688 .hw_err_enable = sec_hw_error_enable,
689 .hw_err_disable = sec_hw_error_disable,
690 .get_dev_hw_err_status = sec_get_hw_err_status,
691 .log_dev_hw_err = sec_log_hw_error,
692 .err_info = {
693 .ce = QM_BASE_CE,
694 .nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT |
695 QM_ACC_WB_NOT_READY_TIMEOUT,
696 .fe = 0,
697 .msi = QM_DB_RANDOM_INVALID,
698 }
699 };
700
701 static int sec_pf_probe_init(struct sec_dev *sec)
702 {
703 struct hisi_qm *qm = &sec->qm;
704 int ret;
705
706 switch (qm->ver) {
707 case QM_HW_V1:
708 qm->ctrl_qp_num = SEC_QUEUE_NUM_V1;
709 break;
710
711 case QM_HW_V2:
712 qm->ctrl_qp_num = SEC_QUEUE_NUM_V2;
713 break;
714
715 default:
716 return -EINVAL;
717 }
718
719 qm->err_ini = &sec_err_ini;
720
721 ret = sec_set_user_domain_and_cache(sec);
722 if (ret)
723 return ret;
724
725 hisi_qm_dev_err_init(qm);
726 sec_debug_regs_clear(qm);
727
728 return 0;
729 }
730
731 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
732 {
733 enum qm_hw_ver rev_id;
734
735 rev_id = hisi_qm_get_hw_version(pdev);
736 if (rev_id == QM_HW_UNKNOWN)
737 return -ENODEV;
738
739 qm->pdev = pdev;
740 qm->ver = rev_id;
741
742 qm->sqe_size = SEC_SQE_SIZE;
743 qm->dev_name = sec_name;
744 qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ?
745 QM_HW_PF : QM_HW_VF;
746 qm->use_dma_api = true;
747
748 return hisi_qm_init(qm);
749 }
750
751 static void sec_qm_uninit(struct hisi_qm *qm)
752 {
753 hisi_qm_uninit(qm);
754 }
755
756 static int sec_probe_init(struct hisi_qm *qm, struct sec_dev *sec)
757 {
758 int ret;
759
760 /*
761 * WQ_HIGHPRI: SEC request must be low delayed,
762 * so need a high priority workqueue.
763 * WQ_UNBOUND: SEC task is likely with long
764 * running CPU intensive workloads.
765 */
766 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI |
767 WQ_MEM_RECLAIM | WQ_UNBOUND, num_online_cpus(),
768 pci_name(qm->pdev));
769 if (!qm->wq) {
770 pci_err(qm->pdev, "fail to alloc workqueue\n");
771 return -ENOMEM;
772 }
773
774 if (qm->fun_type == QM_HW_PF) {
775 qm->qp_base = SEC_PF_DEF_Q_BASE;
776 qm->qp_num = pf_q_num;
777 qm->debug.curr_qm_qp_num = pf_q_num;
778
779 ret = sec_pf_probe_init(sec);
780 if (ret)
781 goto err_probe_uninit;
782 } else if (qm->fun_type == QM_HW_VF) {
783 /*
784 * have no way to get qm configure in VM in v1 hardware,
785 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
786 * to trigger only one VF in v1 hardware.
787 * v2 hardware has no such problem.
788 */
789 if (qm->ver == QM_HW_V1) {
790 qm->qp_base = SEC_PF_DEF_Q_NUM;
791 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
792 } else if (qm->ver == QM_HW_V2) {
793 /* v2 starts to support get vft by mailbox */
794 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
795 if (ret)
796 goto err_probe_uninit;
797 }
798 } else {
799 ret = -ENODEV;
800 goto err_probe_uninit;
801 }
802
803 return 0;
804 err_probe_uninit:
805 destroy_workqueue(qm->wq);
806 return ret;
807 }
808
809 static void sec_probe_uninit(struct hisi_qm *qm)
810 {
811 hisi_qm_dev_err_uninit(qm);
812
813 destroy_workqueue(qm->wq);
814 }
815
816 static void sec_iommu_used_check(struct sec_dev *sec)
817 {
818 struct iommu_domain *domain;
819 struct device *dev = &sec->qm.pdev->dev;
820
821 domain = iommu_get_domain_for_dev(dev);
822
823 /* Check if iommu is used */
824 sec->iommu_used = false;
825 if (domain) {
826 if (domain->type & __IOMMU_DOMAIN_PAGING)
827 sec->iommu_used = true;
828 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
829 domain->type);
830 }
831 }
832
833 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
834 {
835 struct sec_dev *sec;
836 struct hisi_qm *qm;
837 int ret;
838
839 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
840 if (!sec)
841 return -ENOMEM;
842
843 pci_set_drvdata(pdev, sec);
844
845 sec->ctx_q_num = ctx_q_num;
846 sec_iommu_used_check(sec);
847
848 qm = &sec->qm;
849
850 ret = sec_qm_init(qm, pdev);
851 if (ret) {
852 pci_err(pdev, "Failed to pre init qm!\n");
853 return ret;
854 }
855
856 ret = sec_probe_init(qm, sec);
857 if (ret) {
858 pci_err(pdev, "Failed to probe!\n");
859 goto err_qm_uninit;
860 }
861
862 ret = hisi_qm_start(qm);
863 if (ret) {
864 pci_err(pdev, "Failed to start sec qm!\n");
865 goto err_probe_uninit;
866 }
867
868 ret = sec_debugfs_init(sec);
869 if (ret)
870 pci_warn(pdev, "Failed to init debugfs!\n");
871
872 hisi_qm_add_to_list(qm, &sec_devices);
873
874 ret = sec_register_to_crypto();
875 if (ret < 0) {
876 pr_err("Failed to register driver to crypto.\n");
877 goto err_remove_from_list;
878 }
879
880 return 0;
881
882 err_remove_from_list:
883 hisi_qm_del_from_list(qm, &sec_devices);
884 sec_debugfs_exit(sec);
885 hisi_qm_stop(qm);
886
887 err_probe_uninit:
888 sec_probe_uninit(qm);
889
890 err_qm_uninit:
891 sec_qm_uninit(qm);
892
893 return ret;
894 }
895
896 /* now we only support equal assignment */
897 static int sec_vf_q_assign(struct sec_dev *sec, u32 num_vfs)
898 {
899 struct hisi_qm *qm = &sec->qm;
900 u32 qp_num = qm->qp_num;
901 u32 q_base = qp_num;
902 u32 q_num, remain_q_num;
903 int i, j, ret;
904
905 if (!num_vfs)
906 return -EINVAL;
907
908 remain_q_num = qm->ctrl_qp_num - qp_num;
909 q_num = remain_q_num / num_vfs;
910
911 for (i = 1; i <= num_vfs; i++) {
912 if (i == num_vfs)
913 q_num += remain_q_num % num_vfs;
914 ret = hisi_qm_set_vft(qm, i, q_base, q_num);
915 if (ret) {
916 for (j = i; j > 0; j--)
917 hisi_qm_set_vft(qm, j, 0, 0);
918 return ret;
919 }
920 q_base += q_num;
921 }
922
923 return 0;
924 }
925
926 static int sec_clear_vft_config(struct sec_dev *sec)
927 {
928 struct hisi_qm *qm = &sec->qm;
929 u32 num_vfs = sec->num_vfs;
930 int ret;
931 u32 i;
932
933 for (i = 1; i <= num_vfs; i++) {
934 ret = hisi_qm_set_vft(qm, i, 0, 0);
935 if (ret)
936 return ret;
937 }
938
939 sec->num_vfs = 0;
940
941 return 0;
942 }
943
944 static int sec_sriov_enable(struct pci_dev *pdev, int max_vfs)
945 {
946 struct sec_dev *sec = pci_get_drvdata(pdev);
947 int pre_existing_vfs, ret;
948 u32 num_vfs;
949
950 pre_existing_vfs = pci_num_vf(pdev);
951
952 if (pre_existing_vfs) {
953 pci_err(pdev, "Can't enable VF. Please disable at first!\n");
954 return 0;
955 }
956
957 num_vfs = min_t(u32, max_vfs, SEC_VF_NUM);
958
959 ret = sec_vf_q_assign(sec, num_vfs);
960 if (ret) {
961 pci_err(pdev, "Can't assign queues for VF!\n");
962 return ret;
963 }
964
965 sec->num_vfs = num_vfs;
966
967 ret = pci_enable_sriov(pdev, num_vfs);
968 if (ret) {
969 pci_err(pdev, "Can't enable VF!\n");
970 sec_clear_vft_config(sec);
971 return ret;
972 }
973
974 return num_vfs;
975 }
976
977 static int sec_sriov_disable(struct pci_dev *pdev)
978 {
979 struct sec_dev *sec = pci_get_drvdata(pdev);
980
981 if (pci_vfs_assigned(pdev)) {
982 pci_err(pdev, "Can't disable VFs while VFs are assigned!\n");
983 return -EPERM;
984 }
985
986 /* remove in sec_pci_driver will be called to free VF resources */
987 pci_disable_sriov(pdev);
988
989 return sec_clear_vft_config(sec);
990 }
991
992 static int sec_sriov_configure(struct pci_dev *pdev, int num_vfs)
993 {
994 if (num_vfs)
995 return sec_sriov_enable(pdev, num_vfs);
996 else
997 return sec_sriov_disable(pdev);
998 }
999
1000 static void sec_remove(struct pci_dev *pdev)
1001 {
1002 struct sec_dev *sec = pci_get_drvdata(pdev);
1003 struct hisi_qm *qm = &sec->qm;
1004
1005 sec_unregister_from_crypto();
1006
1007 hisi_qm_del_from_list(qm, &sec_devices);
1008
1009 if (qm->fun_type == QM_HW_PF && sec->num_vfs)
1010 (void)sec_sriov_disable(pdev);
1011
1012 sec_debugfs_exit(sec);
1013
1014 (void)hisi_qm_stop(qm);
1015
1016 if (qm->fun_type == QM_HW_PF)
1017 sec_debug_regs_clear(qm);
1018
1019 sec_probe_uninit(qm);
1020
1021 sec_qm_uninit(qm);
1022 }
1023
1024 static const struct pci_error_handlers sec_err_handler = {
1025 .error_detected = hisi_qm_dev_err_detected,
1026 };
1027
1028 static struct pci_driver sec_pci_driver = {
1029 .name = "hisi_sec2",
1030 .id_table = sec_dev_ids,
1031 .probe = sec_probe,
1032 .remove = sec_remove,
1033 .err_handler = &sec_err_handler,
1034 .sriov_configure = sec_sriov_configure,
1035 };
1036
1037 static void sec_register_debugfs(void)
1038 {
1039 if (!debugfs_initialized())
1040 return;
1041
1042 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1043 }
1044
1045 static void sec_unregister_debugfs(void)
1046 {
1047 debugfs_remove_recursive(sec_debugfs_root);
1048 }
1049
1050 static int __init sec_init(void)
1051 {
1052 int ret;
1053
1054 hisi_qm_init_list(&sec_devices);
1055 sec_register_debugfs();
1056
1057 ret = pci_register_driver(&sec_pci_driver);
1058 if (ret < 0) {
1059 sec_unregister_debugfs();
1060 pr_err("Failed to register pci driver.\n");
1061 return ret;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static void __exit sec_exit(void)
1068 {
1069 pci_unregister_driver(&sec_pci_driver);
1070 sec_unregister_debugfs();
1071 }
1072
1073 module_init(sec_init);
1074 module_exit(sec_exit);
1075
1076 MODULE_LICENSE("GPL v2");
1077 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1078 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1079 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1080 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
Linux with added FPC-III support