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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / crypto / hisilicon / zip / zip_main.c
blobfcc85d2dbd0720031dfa3318176d6280a0bf1a0f
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/aer.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/seq_file.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "zip.h"
16
17 #define PCI_DEVICE_ID_ZIP_PF 0xa250
18 #define PCI_DEVICE_ID_ZIP_VF 0xa251
19
20 #define HZIP_VF_NUM 63
21 #define HZIP_QUEUE_NUM_V1 4096
22 #define HZIP_QUEUE_NUM_V2 1024
23
24 #define HZIP_CLOCK_GATE_CTRL 0x301004
25 #define COMP0_ENABLE BIT(0)
26 #define COMP1_ENABLE BIT(1)
27 #define DECOMP0_ENABLE BIT(2)
28 #define DECOMP1_ENABLE BIT(3)
29 #define DECOMP2_ENABLE BIT(4)
30 #define DECOMP3_ENABLE BIT(5)
31 #define DECOMP4_ENABLE BIT(6)
32 #define DECOMP5_ENABLE BIT(7)
33 #define ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \
34 DECOMP0_ENABLE | DECOMP1_ENABLE | \
35 DECOMP2_ENABLE | DECOMP3_ENABLE | \
36 DECOMP4_ENABLE | DECOMP5_ENABLE)
37 #define DECOMP_CHECK_ENABLE BIT(16)
38 #define HZIP_FSM_MAX_CNT 0x301008
39
40 #define HZIP_PORT_ARCA_CHE_0 0x301040
41 #define HZIP_PORT_ARCA_CHE_1 0x301044
42 #define HZIP_PORT_AWCA_CHE_0 0x301060
43 #define HZIP_PORT_AWCA_CHE_1 0x301064
44 #define CACHE_ALL_EN 0xffffffff
45
46 #define HZIP_BD_RUSER_32_63 0x301110
47 #define HZIP_SGL_RUSER_32_63 0x30111c
48 #define HZIP_DATA_RUSER_32_63 0x301128
49 #define HZIP_DATA_WUSER_32_63 0x301134
50 #define HZIP_BD_WUSER_32_63 0x301140
51
52 #define HZIP_QM_IDEL_STATUS 0x3040e4
53
54 #define HZIP_CORE_DEBUG_COMP_0 0x302000
55 #define HZIP_CORE_DEBUG_COMP_1 0x303000
56 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000
57 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000
58 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000
59 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000
60 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000
61 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000
62
63 #define HZIP_CORE_INT_SOURCE 0x3010A0
64 #define HZIP_CORE_INT_MASK_REG 0x3010A4
65 #define HZIP_CORE_INT_STATUS 0x3010AC
66 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1)
67 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148
68 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160
69 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164
70 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168
71 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x7FE
72 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16
73 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24
74 #define HZIP_CORE_INT_MASK_ALL GENMASK(10, 0)
75 #define HZIP_COMP_CORE_NUM 2
76 #define HZIP_DECOMP_CORE_NUM 6
77 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \
78 HZIP_DECOMP_CORE_NUM)
79 #define HZIP_SQE_SIZE 128
80 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH)
81 #define HZIP_PF_DEF_Q_NUM 64
82 #define HZIP_PF_DEF_Q_BASE 0
83
84 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000
85 #define SOFT_CTRL_CNT_CLR_CE_BIT BIT(0)
86
87 #define HZIP_BUF_SIZE 22
88
89 static const char hisi_zip_name[] = "hisi_zip";
90 static struct dentry *hzip_debugfs_root;
91 static struct hisi_qm_list zip_devices;
92
93 struct hisi_zip_hw_error {
94 u32 int_msk;
95 const char *msg;
96 };
97
98 static const struct hisi_zip_hw_error zip_hw_error[] = {
99 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
100 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" },
101 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" },
102 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" },
103 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" },
104 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" },
105 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" },
106 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" },
107 { .int_msk = BIT(8), .msg = "zip_com_inf_err" },
108 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" },
109 { .int_msk = BIT(10), .msg = "zip_pre_out_err" },
110 { /* sentinel */ }
111 };
112
113 enum ctrl_debug_file_index {
114 HZIP_CURRENT_QM,
115 HZIP_CLEAR_ENABLE,
116 HZIP_DEBUG_FILE_NUM,
117 };
118
119 static const char * const ctrl_debug_file_name[] = {
120 [HZIP_CURRENT_QM] = "current_qm",
121 [HZIP_CLEAR_ENABLE] = "clear_enable",
122 };
123
124 struct ctrl_debug_file {
125 enum ctrl_debug_file_index index;
126 spinlock_t lock;
127 struct hisi_zip_ctrl *ctrl;
128 };
129
130 /*
131 * One ZIP controller has one PF and multiple VFs, some global configurations
132 * which PF has need this structure.
133 *
134 * Just relevant for PF.
135 */
136 struct hisi_zip_ctrl {
137 u32 num_vfs;
138 struct hisi_zip *hisi_zip;
139 struct dentry *debug_root;
140 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM];
141 };
142
143 enum {
144 HZIP_COMP_CORE0,
145 HZIP_COMP_CORE1,
146 HZIP_DECOMP_CORE0,
147 HZIP_DECOMP_CORE1,
148 HZIP_DECOMP_CORE2,
149 HZIP_DECOMP_CORE3,
150 HZIP_DECOMP_CORE4,
151 HZIP_DECOMP_CORE5,
152 };
153
154 static const u64 core_offsets[] = {
155 [HZIP_COMP_CORE0] = 0x302000,
156 [HZIP_COMP_CORE1] = 0x303000,
157 [HZIP_DECOMP_CORE0] = 0x304000,
158 [HZIP_DECOMP_CORE1] = 0x305000,
159 [HZIP_DECOMP_CORE2] = 0x306000,
160 [HZIP_DECOMP_CORE3] = 0x307000,
161 [HZIP_DECOMP_CORE4] = 0x308000,
162 [HZIP_DECOMP_CORE5] = 0x309000,
163 };
164
165 static struct debugfs_reg32 hzip_dfx_regs[] = {
166 {"HZIP_GET_BD_NUM ", 0x00ull},
167 {"HZIP_GET_RIGHT_BD ", 0x04ull},
168 {"HZIP_GET_ERROR_BD ", 0x08ull},
169 {"HZIP_DONE_BD_NUM ", 0x0cull},
170 {"HZIP_WORK_CYCLE ", 0x10ull},
171 {"HZIP_IDLE_CYCLE ", 0x18ull},
172 {"HZIP_MAX_DELAY ", 0x20ull},
173 {"HZIP_MIN_DELAY ", 0x24ull},
174 {"HZIP_AVG_DELAY ", 0x28ull},
175 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull},
176 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull},
177 {"HZIP_COMSUMED_BYTE ", 0x38ull},
178 {"HZIP_PRODUCED_BYTE ", 0x40ull},
179 {"HZIP_COMP_INF ", 0x70ull},
180 {"HZIP_PRE_OUT ", 0x78ull},
181 {"HZIP_BD_RD ", 0x7cull},
182 {"HZIP_BD_WR ", 0x80ull},
183 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull},
184 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull},
185 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull},
186 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull},
187 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull},
188 };
189
190 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
191 {
192 struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
193 PCI_DEVICE_ID_ZIP_PF, NULL);
194 u32 n, q_num;
195 u8 rev_id;
196 int ret;
197
198 if (!val)
199 return -EINVAL;
200
201 if (!pdev) {
202 q_num = min_t(u32, HZIP_QUEUE_NUM_V1, HZIP_QUEUE_NUM_V2);
203 pr_info("No device found currently, suppose queue number is %d\n",
204 q_num);
205 } else {
206 rev_id = pdev->revision;
207 switch (rev_id) {
208 case QM_HW_V1:
209 q_num = HZIP_QUEUE_NUM_V1;
210 break;
211 case QM_HW_V2:
212 q_num = HZIP_QUEUE_NUM_V2;
213 break;
214 default:
215 return -EINVAL;
216 }
217 }
218
219 ret = kstrtou32(val, 10, &n);
220 if (ret != 0 || n > q_num || n == 0)
221 return -EINVAL;
222
223 return param_set_int(val, kp);
224 }
225
226 static const struct kernel_param_ops pf_q_num_ops = {
227 .set = pf_q_num_set,
228 .get = param_get_int,
229 };
230
231 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
232 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
233 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 1-4096, v2 1-1024)");
234
235 static u32 vfs_num;
236 module_param(vfs_num, uint, 0444);
237 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63)");
238
239 static const struct pci_device_id hisi_zip_dev_ids[] = {
240 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) },
241 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) },
242 { 0, }
243 };
244 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids);
245
246 int zip_create_qps(struct hisi_qp **qps, int qp_num)
247 {
248 int node = cpu_to_node(smp_processor_id());
249
250 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
251 }
252
253 static void hisi_zip_set_user_domain_and_cache(struct hisi_zip *hisi_zip)
254 {
255 void __iomem *base = hisi_zip->qm.io_base;
256
257 /* qm user domain */
258 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
259 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
260 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
261 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
262 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
263
264 /* qm cache */
265 writel(AXI_M_CFG, base + QM_AXI_M_CFG);
266 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
267 /* disable FLR triggered by BME(bus master enable) */
268 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
269 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
270
271 /* cache */
272 writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
273 writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
274 writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
275 writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
276
277 /* user domain configurations */
278 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
279 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
280 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
281
282 if (hisi_zip->qm.use_sva) {
283 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
284 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
285 } else {
286 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
287 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
288 }
289
290 /* let's open all compression/decompression cores */
291 writel(DECOMP_CHECK_ENABLE | ALL_COMP_DECOMP_EN,
292 base + HZIP_CLOCK_GATE_CTRL);
293
294 /* enable sqc writeback */
295 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
296 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
297 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
298 }
299
300 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
301 {
302 if (qm->ver == QM_HW_V1) {
303 writel(HZIP_CORE_INT_MASK_ALL,
304 qm->io_base + HZIP_CORE_INT_MASK_REG);
305 dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
306 return;
307 }
308
309 /* clear ZIP hw error source if having */
310 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);
311
312 /* configure error type */
313 writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
314 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
315 writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
316 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
317
318 /* enable ZIP hw error interrupts */
319 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
320 }
321
322 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
323 {
324 /* disable ZIP hw error interrupts */
325 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);
326 }
327
328 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
329 {
330 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip;
331
332 return &hisi_zip->qm;
333 }
334
335 static u32 current_qm_read(struct ctrl_debug_file *file)
336 {
337 struct hisi_qm *qm = file_to_qm(file);
338
339 return readl(qm->io_base + QM_DFX_MB_CNT_VF);
340 }
341
342 static int current_qm_write(struct ctrl_debug_file *file, u32 val)
343 {
344 struct hisi_qm *qm = file_to_qm(file);
345 struct hisi_zip_ctrl *ctrl = file->ctrl;
346 u32 vfq_num;
347 u32 tmp;
348
349 if (val > ctrl->num_vfs)
350 return -EINVAL;
351
352 /* Calculate curr_qm_qp_num and store */
353 if (val == 0) {
354 qm->debug.curr_qm_qp_num = qm->qp_num;
355 } else {
356 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / ctrl->num_vfs;
357 if (val == ctrl->num_vfs)
358 qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
359 qm->qp_num - (ctrl->num_vfs - 1) * vfq_num;
360 else
361 qm->debug.curr_qm_qp_num = vfq_num;
362 }
363
364 writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
365 writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
366
367 tmp = val |
368 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
369 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
370
371 tmp = val |
372 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
373 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
374
375 return 0;
376 }
377
378 static u32 clear_enable_read(struct ctrl_debug_file *file)
379 {
380 struct hisi_qm *qm = file_to_qm(file);
381
382 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
383 SOFT_CTRL_CNT_CLR_CE_BIT;
384 }
385
386 static int clear_enable_write(struct ctrl_debug_file *file, u32 val)
387 {
388 struct hisi_qm *qm = file_to_qm(file);
389 u32 tmp;
390
391 if (val != 1 && val != 0)
392 return -EINVAL;
393
394 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
395 ~SOFT_CTRL_CNT_CLR_CE_BIT) | val;
396 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
397
398 return 0;
399 }
400
401 static ssize_t ctrl_debug_read(struct file *filp, char __user *buf,
402 size_t count, loff_t *pos)
403 {
404 struct ctrl_debug_file *file = filp->private_data;
405 char tbuf[HZIP_BUF_SIZE];
406 u32 val;
407 int ret;
408
409 spin_lock_irq(&file->lock);
410 switch (file->index) {
411 case HZIP_CURRENT_QM:
412 val = current_qm_read(file);
413 break;
414 case HZIP_CLEAR_ENABLE:
415 val = clear_enable_read(file);
416 break;
417 default:
418 spin_unlock_irq(&file->lock);
419 return -EINVAL;
420 }
421 spin_unlock_irq(&file->lock);
422 ret = sprintf(tbuf, "%u\n", val);
423 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
424 }
425
426 static ssize_t ctrl_debug_write(struct file *filp, const char __user *buf,
427 size_t count, loff_t *pos)
428 {
429 struct ctrl_debug_file *file = filp->private_data;
430 char tbuf[HZIP_BUF_SIZE];
431 unsigned long val;
432 int len, ret;
433
434 if (*pos != 0)
435 return 0;
436
437 if (count >= HZIP_BUF_SIZE)
438 return -ENOSPC;
439
440 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count);
441 if (len < 0)
442 return len;
443
444 tbuf[len] = '\0';
445 if (kstrtoul(tbuf, 0, &val))
446 return -EFAULT;
447
448 spin_lock_irq(&file->lock);
449 switch (file->index) {
450 case HZIP_CURRENT_QM:
451 ret = current_qm_write(file, val);
452 if (ret)
453 goto err_input;
454 break;
455 case HZIP_CLEAR_ENABLE:
456 ret = clear_enable_write(file, val);
457 if (ret)
458 goto err_input;
459 break;
460 default:
461 ret = -EINVAL;
462 goto err_input;
463 }
464 spin_unlock_irq(&file->lock);
465
466 return count;
467
468 err_input:
469 spin_unlock_irq(&file->lock);
470 return ret;
471 }
472
473 static const struct file_operations ctrl_debug_fops = {
474 .owner = THIS_MODULE,
475 .open = simple_open,
476 .read = ctrl_debug_read,
477 .write = ctrl_debug_write,
478 };
479
480 static int hisi_zip_core_debug_init(struct hisi_zip_ctrl *ctrl)
481 {
482 struct hisi_zip *hisi_zip = ctrl->hisi_zip;
483 struct hisi_qm *qm = &hisi_zip->qm;
484 struct device *dev = &qm->pdev->dev;
485 struct debugfs_regset32 *regset;
486 struct dentry *tmp_d;
487 char buf[HZIP_BUF_SIZE];
488 int i;
489
490 for (i = 0; i < HZIP_CORE_NUM; i++) {
491 if (i < HZIP_COMP_CORE_NUM)
492 sprintf(buf, "comp_core%d", i);
493 else
494 sprintf(buf, "decomp_core%d", i - HZIP_COMP_CORE_NUM);
495
496 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
497 if (!regset)
498 return -ENOENT;
499
500 regset->regs = hzip_dfx_regs;
501 regset->nregs = ARRAY_SIZE(hzip_dfx_regs);
502 regset->base = qm->io_base + core_offsets[i];
503
504 tmp_d = debugfs_create_dir(buf, ctrl->debug_root);
505 debugfs_create_regset32("regs", 0444, tmp_d, regset);
506 }
507
508 return 0;
509 }
510
511 static int hisi_zip_ctrl_debug_init(struct hisi_zip_ctrl *ctrl)
512 {
513 int i;
514
515 for (i = HZIP_CURRENT_QM; i < HZIP_DEBUG_FILE_NUM; i++) {
516 spin_lock_init(&ctrl->files[i].lock);
517 ctrl->files[i].ctrl = ctrl;
518 ctrl->files[i].index = i;
519
520 debugfs_create_file(ctrl_debug_file_name[i], 0600,
521 ctrl->debug_root, ctrl->files + i,
522 &ctrl_debug_fops);
523 }
524
525 return hisi_zip_core_debug_init(ctrl);
526 }
527
528 static int hisi_zip_debugfs_init(struct hisi_zip *hisi_zip)
529 {
530 struct hisi_qm *qm = &hisi_zip->qm;
531 struct device *dev = &qm->pdev->dev;
532 struct dentry *dev_d;
533 int ret;
534
535 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root);
536
537 qm->debug.debug_root = dev_d;
538 ret = hisi_qm_debug_init(qm);
539 if (ret)
540 goto failed_to_create;
541
542 if (qm->fun_type == QM_HW_PF) {
543 hisi_zip->ctrl->debug_root = dev_d;
544 ret = hisi_zip_ctrl_debug_init(hisi_zip->ctrl);
545 if (ret)
546 goto failed_to_create;
547 }
548
549 return 0;
550
551 failed_to_create:
552 debugfs_remove_recursive(hzip_debugfs_root);
553 return ret;
554 }
555
556 static void hisi_zip_debug_regs_clear(struct hisi_zip *hisi_zip)
557 {
558 struct hisi_qm *qm = &hisi_zip->qm;
559
560 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
561 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
562 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
563
564 hisi_qm_debug_regs_clear(qm);
565 }
566
567 static void hisi_zip_debugfs_exit(struct hisi_zip *hisi_zip)
568 {
569 struct hisi_qm *qm = &hisi_zip->qm;
570
571 debugfs_remove_recursive(qm->debug.debug_root);
572
573 if (qm->fun_type == QM_HW_PF)
574 hisi_zip_debug_regs_clear(hisi_zip);
575 }
576
577 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
578 {
579 const struct hisi_zip_hw_error *err = zip_hw_error;
580 struct device *dev = &qm->pdev->dev;
581 u32 err_val;
582
583 while (err->msg) {
584 if (err->int_msk & err_sts) {
585 dev_err(dev, "%s [error status=0x%x] found\n",
586 err->msg, err->int_msk);
587
588 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
589 err_val = readl(qm->io_base +
590 HZIP_CORE_SRAM_ECC_ERR_INFO);
591 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
592 ((err_val >>
593 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
594 dev_err(dev, "hisi-zip multi ecc sram addr=0x%x\n",
595 (err_val >>
596 HZIP_SRAM_ECC_ERR_ADDR_SHIFT));
597 }
598 }
599 err++;
600 }
601
602 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
603 }
604
605 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
606 {
607 return readl(qm->io_base + HZIP_CORE_INT_STATUS);
608 }
609
610 static const struct hisi_qm_err_ini hisi_zip_err_ini = {
611 .hw_err_enable = hisi_zip_hw_error_enable,
612 .hw_err_disable = hisi_zip_hw_error_disable,
613 .get_dev_hw_err_status = hisi_zip_get_hw_err_status,
614 .log_dev_hw_err = hisi_zip_log_hw_error,
615 .err_info = {
616 .ce = QM_BASE_CE,
617 .nfe = QM_BASE_NFE |
618 QM_ACC_WB_NOT_READY_TIMEOUT,
619 .fe = 0,
620 .msi = QM_DB_RANDOM_INVALID,
621 }
622 };
623
624 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
625 {
626 struct hisi_qm *qm = &hisi_zip->qm;
627 struct hisi_zip_ctrl *ctrl;
628
629 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
630 if (!ctrl)
631 return -ENOMEM;
632
633 hisi_zip->ctrl = ctrl;
634 ctrl->hisi_zip = hisi_zip;
635
636 switch (qm->ver) {
637 case QM_HW_V1:
638 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
639 break;
640
641 case QM_HW_V2:
642 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
643 break;
644
645 default:
646 return -EINVAL;
647 }
648
649 qm->err_ini = &hisi_zip_err_ini;
650
651 hisi_zip_set_user_domain_and_cache(hisi_zip);
652 hisi_qm_dev_err_init(qm);
653 hisi_zip_debug_regs_clear(hisi_zip);
654
655 return 0;
656 }
657
658 /* Currently we only support equal assignment */
659 static int hisi_zip_vf_q_assign(struct hisi_zip *hisi_zip, int num_vfs)
660 {
661 struct hisi_qm *qm = &hisi_zip->qm;
662 u32 qp_num = qm->qp_num;
663 u32 q_base = qp_num;
664 u32 q_num, remain_q_num, i;
665 int ret;
666
667 if (!num_vfs)
668 return -EINVAL;
669
670 remain_q_num = qm->ctrl_qp_num - qp_num;
671 if (remain_q_num < num_vfs)
672 return -EINVAL;
673
674 q_num = remain_q_num / num_vfs;
675 for (i = 1; i <= num_vfs; i++) {
676 if (i == num_vfs)
677 q_num += remain_q_num % num_vfs;
678 ret = hisi_qm_set_vft(qm, i, q_base, q_num);
679 if (ret)
680 return ret;
681 q_base += q_num;
682 }
683
684 return 0;
685 }
686
687 static int hisi_zip_clear_vft_config(struct hisi_zip *hisi_zip)
688 {
689 struct hisi_zip_ctrl *ctrl = hisi_zip->ctrl;
690 struct hisi_qm *qm = &hisi_zip->qm;
691 u32 i, num_vfs = ctrl->num_vfs;
692 int ret;
693
694 for (i = 1; i <= num_vfs; i++) {
695 ret = hisi_qm_set_vft(qm, i, 0, 0);
696 if (ret)
697 return ret;
698 }
699
700 ctrl->num_vfs = 0;
701
702 return 0;
703 }
704
705 static int hisi_zip_sriov_enable(struct pci_dev *pdev, int max_vfs)
706 {
707 struct hisi_zip *hisi_zip = pci_get_drvdata(pdev);
708 int pre_existing_vfs, num_vfs, ret;
709
710 pre_existing_vfs = pci_num_vf(pdev);
711
712 if (pre_existing_vfs) {
713 dev_err(&pdev->dev,
714 "Can't enable VF. Please disable pre-enabled VFs!\n");
715 return 0;
716 }
717
718 num_vfs = min_t(int, max_vfs, HZIP_VF_NUM);
719
720 ret = hisi_zip_vf_q_assign(hisi_zip, num_vfs);
721 if (ret) {
722 dev_err(&pdev->dev, "Can't assign queues for VF!\n");
723 return ret;
724 }
725
726 hisi_zip->ctrl->num_vfs = num_vfs;
727
728 ret = pci_enable_sriov(pdev, num_vfs);
729 if (ret) {
730 dev_err(&pdev->dev, "Can't enable VF!\n");
731 hisi_zip_clear_vft_config(hisi_zip);
732 return ret;
733 }
734
735 return num_vfs;
736 }
737
738 static int hisi_zip_sriov_disable(struct pci_dev *pdev)
739 {
740 struct hisi_zip *hisi_zip = pci_get_drvdata(pdev);
741
742 if (pci_vfs_assigned(pdev)) {
743 dev_err(&pdev->dev,
744 "Can't disable VFs while VFs are assigned!\n");
745 return -EPERM;
746 }
747
748 /* remove in hisi_zip_pci_driver will be called to free VF resources */
749 pci_disable_sriov(pdev);
750
751 return hisi_zip_clear_vft_config(hisi_zip);
752 }
753
754 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
755 {
756 struct hisi_zip *hisi_zip;
757 enum qm_hw_ver rev_id;
758 struct hisi_qm *qm;
759 int ret;
760
761 rev_id = hisi_qm_get_hw_version(pdev);
762 if (rev_id == QM_HW_UNKNOWN)
763 return -EINVAL;
764
765 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL);
766 if (!hisi_zip)
767 return -ENOMEM;
768 pci_set_drvdata(pdev, hisi_zip);
769
770 qm = &hisi_zip->qm;
771 qm->use_dma_api = true;
772 qm->pdev = pdev;
773 qm->ver = rev_id;
774
775 qm->algs = "zlib\ngzip";
776 qm->sqe_size = HZIP_SQE_SIZE;
777 qm->dev_name = hisi_zip_name;
778 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? QM_HW_PF :
779 QM_HW_VF;
780 ret = hisi_qm_init(qm);
781 if (ret) {
782 dev_err(&pdev->dev, "Failed to init qm!\n");
783 return ret;
784 }
785
786 if (qm->fun_type == QM_HW_PF) {
787 ret = hisi_zip_pf_probe_init(hisi_zip);
788 if (ret)
789 return ret;
790
791 qm->qp_base = HZIP_PF_DEF_Q_BASE;
792 qm->qp_num = pf_q_num;
793 } else if (qm->fun_type == QM_HW_VF) {
794 /*
795 * have no way to get qm configure in VM in v1 hardware,
796 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force
797 * to trigger only one VF in v1 hardware.
798 *
799 * v2 hardware has no such problem.
800 */
801 if (qm->ver == QM_HW_V1) {
802 qm->qp_base = HZIP_PF_DEF_Q_NUM;
803 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
804 } else if (qm->ver == QM_HW_V2)
805 /* v2 starts to support get vft by mailbox */
806 hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
807 }
808
809 ret = hisi_qm_start(qm);
810 if (ret)
811 goto err_qm_uninit;
812
813 ret = hisi_zip_debugfs_init(hisi_zip);
814 if (ret)
815 dev_err(&pdev->dev, "Failed to init debugfs (%d)!\n", ret);
816
817 hisi_qm_add_to_list(qm, &zip_devices);
818
819 if (qm->uacce) {
820 ret = uacce_register(qm->uacce);
821 if (ret)
822 goto err_qm_uninit;
823 }
824
825 if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
826 ret = hisi_zip_sriov_enable(pdev, vfs_num);
827 if (ret < 0)
828 goto err_remove_from_list;
829 }
830
831 return 0;
832
833 err_remove_from_list:
834 hisi_qm_del_from_list(qm, &zip_devices);
835 hisi_zip_debugfs_exit(hisi_zip);
836 hisi_qm_stop(qm);
837 err_qm_uninit:
838 hisi_qm_uninit(qm);
839 return ret;
840 }
841
842 static int hisi_zip_sriov_configure(struct pci_dev *pdev, int num_vfs)
843 {
844 if (num_vfs == 0)
845 return hisi_zip_sriov_disable(pdev);
846 else
847 return hisi_zip_sriov_enable(pdev, num_vfs);
848 }
849
850 static void hisi_zip_remove(struct pci_dev *pdev)
851 {
852 struct hisi_zip *hisi_zip = pci_get_drvdata(pdev);
853 struct hisi_qm *qm = &hisi_zip->qm;
854
855 if (qm->fun_type == QM_HW_PF && hisi_zip->ctrl->num_vfs != 0)
856 hisi_zip_sriov_disable(pdev);
857
858 hisi_zip_debugfs_exit(hisi_zip);
859 hisi_qm_stop(qm);
860
861 hisi_qm_dev_err_uninit(qm);
862 hisi_qm_uninit(qm);
863 hisi_qm_del_from_list(qm, &zip_devices);
864 }
865
866 static const struct pci_error_handlers hisi_zip_err_handler = {
867 .error_detected = hisi_qm_dev_err_detected,
868 };
869
870 static struct pci_driver hisi_zip_pci_driver = {
871 .name = "hisi_zip",
872 .id_table = hisi_zip_dev_ids,
873 .probe = hisi_zip_probe,
874 .remove = hisi_zip_remove,
875 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
876 hisi_zip_sriov_configure : NULL,
877 .err_handler = &hisi_zip_err_handler,
878 };
879
880 static void hisi_zip_register_debugfs(void)
881 {
882 if (!debugfs_initialized())
883 return;
884
885 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL);
886 }
887
888 static void hisi_zip_unregister_debugfs(void)
889 {
890 debugfs_remove_recursive(hzip_debugfs_root);
891 }
892
893 static int __init hisi_zip_init(void)
894 {
895 int ret;
896
897 hisi_qm_init_list(&zip_devices);
898 hisi_zip_register_debugfs();
899
900 ret = pci_register_driver(&hisi_zip_pci_driver);
901 if (ret < 0) {
902 pr_err("Failed to register pci driver.\n");
903 goto err_pci;
904 }
905
906 ret = hisi_zip_register_to_crypto();
907 if (ret < 0) {
908 pr_err("Failed to register driver to crypto.\n");
909 goto err_crypto;
910 }
911
912 return 0;
913
914 err_crypto:
915 pci_unregister_driver(&hisi_zip_pci_driver);
916 err_pci:
917 hisi_zip_unregister_debugfs();
918
919 return ret;
920 }
921
922 static void __exit hisi_zip_exit(void)
923 {
924 hisi_zip_unregister_from_crypto();
925 pci_unregister_driver(&hisi_zip_pci_driver);
926 hisi_zip_unregister_debugfs();
927 }
928
929 module_init(hisi_zip_init);
930 module_exit(hisi_zip_exit);
931
932 MODULE_LICENSE("GPL v2");
933 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
934 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator");
Linux with added FPC-III support