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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / crypto / omap-sham.c
bloba82a3596dca34f4b93ba85aa88ca8e7c7e3da2ac
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cryptographic API.
4 *
5 * Support for OMAP SHA1/MD5 HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 *
11 * Some ideas are from old omap-sha1-md5.c driver.
12 */
13
14 #define pr_fmt(fmt) "%s: " fmt, __func__
15
16 #include <linux/err.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/irq.h>
24 #include <linux/io.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <linux/cryptohash.h>
37 #include <crypto/scatterwalk.h>
38 #include <crypto/algapi.h>
39 #include <crypto/sha.h>
40 #include <crypto/hash.h>
41 #include <crypto/hmac.h>
42 #include <crypto/internal/hash.h>
43
44 #define MD5_DIGEST_SIZE 16
45
46 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
47 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
48 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
49
50 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
51
52 #define SHA_REG_CTRL 0x18
53 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
54 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
55 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
56 #define SHA_REG_CTRL_ALGO (1 << 2)
57 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
58 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
59
60 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
61
62 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
63 #define SHA_REG_MASK_DMA_EN (1 << 3)
64 #define SHA_REG_MASK_IT_EN (1 << 2)
65 #define SHA_REG_MASK_SOFTRESET (1 << 1)
66 #define SHA_REG_AUTOIDLE (1 << 0)
67
68 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
69 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
70
71 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
72 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
73 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
74 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
75 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
76
77 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
78 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
79 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
80 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
81 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
83 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
84
85 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
86
87 #define SHA_REG_IRQSTATUS 0x118
88 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
90 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
92
93 #define SHA_REG_IRQENA 0x11C
94 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
95 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
96 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
97 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
98
99 #define DEFAULT_TIMEOUT_INTERVAL HZ
100
101 #define DEFAULT_AUTOSUSPEND_DELAY 1000
102
103 /* mostly device flags */
104 #define FLAGS_BUSY 0
105 #define FLAGS_FINAL 1
106 #define FLAGS_DMA_ACTIVE 2
107 #define FLAGS_OUTPUT_READY 3
108 #define FLAGS_INIT 4
109 #define FLAGS_CPU 5
110 #define FLAGS_DMA_READY 6
111 #define FLAGS_AUTO_XOR 7
112 #define FLAGS_BE32_SHA1 8
113 #define FLAGS_SGS_COPIED 9
114 #define FLAGS_SGS_ALLOCED 10
115 #define FLAGS_HUGE 11
116
117 /* context flags */
118 #define FLAGS_FINUP 16
119
120 #define FLAGS_MODE_SHIFT 18
121 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
128
129 #define FLAGS_HMAC 21
130 #define FLAGS_ERROR 22
131
132 #define OP_UPDATE 1
133 #define OP_FINAL 2
134
135 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
136 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
137
138 #define BUFLEN SHA512_BLOCK_SIZE
139 #define OMAP_SHA_DMA_THRESHOLD 256
140
141 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048)
142
143 struct omap_sham_dev;
144
145 struct omap_sham_reqctx {
146 struct omap_sham_dev *dd;
147 unsigned long flags;
148 unsigned long op;
149
150 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
151 size_t digcnt;
152 size_t bufcnt;
153 size_t buflen;
154
155 /* walk state */
156 struct scatterlist *sg;
157 struct scatterlist sgl[2];
158 int offset; /* offset in current sg */
159 int sg_len;
160 unsigned int total; /* total request */
161
162 u8 buffer[] OMAP_ALIGNED;
163 };
164
165 struct omap_sham_hmac_ctx {
166 struct crypto_shash *shash;
167 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
168 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
169 };
170
171 struct omap_sham_ctx {
172 unsigned long flags;
173
174 /* fallback stuff */
175 struct crypto_shash *fallback;
176
177 struct omap_sham_hmac_ctx base[];
178 };
179
180 #define OMAP_SHAM_QUEUE_LENGTH 10
181
182 struct omap_sham_algs_info {
183 struct ahash_alg *algs_list;
184 unsigned int size;
185 unsigned int registered;
186 };
187
188 struct omap_sham_pdata {
189 struct omap_sham_algs_info *algs_info;
190 unsigned int algs_info_size;
191 unsigned long flags;
192 int digest_size;
193
194 void (*copy_hash)(struct ahash_request *req, int out);
195 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
196 int final, int dma);
197 void (*trigger)(struct omap_sham_dev *dd, size_t length);
198 int (*poll_irq)(struct omap_sham_dev *dd);
199 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
200
201 u32 odigest_ofs;
202 u32 idigest_ofs;
203 u32 din_ofs;
204 u32 digcnt_ofs;
205 u32 rev_ofs;
206 u32 mask_ofs;
207 u32 sysstatus_ofs;
208 u32 mode_ofs;
209 u32 length_ofs;
210
211 u32 major_mask;
212 u32 major_shift;
213 u32 minor_mask;
214 u32 minor_shift;
215 };
216
217 struct omap_sham_dev {
218 struct list_head list;
219 unsigned long phys_base;
220 struct device *dev;
221 void __iomem *io_base;
222 int irq;
223 spinlock_t lock;
224 int err;
225 struct dma_chan *dma_lch;
226 struct tasklet_struct done_task;
227 u8 polling_mode;
228 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
229
230 unsigned long flags;
231 int fallback_sz;
232 struct crypto_queue queue;
233 struct ahash_request *req;
234
235 const struct omap_sham_pdata *pdata;
236 };
237
238 struct omap_sham_drv {
239 struct list_head dev_list;
240 spinlock_t lock;
241 unsigned long flags;
242 };
243
244 static struct omap_sham_drv sham = {
245 .dev_list = LIST_HEAD_INIT(sham.dev_list),
246 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
247 };
248
249 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
250 {
251 return __raw_readl(dd->io_base + offset);
252 }
253
254 static inline void omap_sham_write(struct omap_sham_dev *dd,
255 u32 offset, u32 value)
256 {
257 __raw_writel(value, dd->io_base + offset);
258 }
259
260 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
261 u32 value, u32 mask)
262 {
263 u32 val;
264
265 val = omap_sham_read(dd, address);
266 val &= ~mask;
267 val |= value;
268 omap_sham_write(dd, address, val);
269 }
270
271 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
272 {
273 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
274
275 while (!(omap_sham_read(dd, offset) & bit)) {
276 if (time_is_before_jiffies(timeout))
277 return -ETIMEDOUT;
278 }
279
280 return 0;
281 }
282
283 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
284 {
285 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
286 struct omap_sham_dev *dd = ctx->dd;
287 u32 *hash = (u32 *)ctx->digest;
288 int i;
289
290 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
291 if (out)
292 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
293 else
294 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
295 }
296 }
297
298 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
299 {
300 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
301 struct omap_sham_dev *dd = ctx->dd;
302 int i;
303
304 if (ctx->flags & BIT(FLAGS_HMAC)) {
305 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
306 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
307 struct omap_sham_hmac_ctx *bctx = tctx->base;
308 u32 *opad = (u32 *)bctx->opad;
309
310 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
311 if (out)
312 opad[i] = omap_sham_read(dd,
313 SHA_REG_ODIGEST(dd, i));
314 else
315 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
316 opad[i]);
317 }
318 }
319
320 omap_sham_copy_hash_omap2(req, out);
321 }
322
323 static void omap_sham_copy_ready_hash(struct ahash_request *req)
324 {
325 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
326 u32 *in = (u32 *)ctx->digest;
327 u32 *hash = (u32 *)req->result;
328 int i, d, big_endian = 0;
329
330 if (!hash)
331 return;
332
333 switch (ctx->flags & FLAGS_MODE_MASK) {
334 case FLAGS_MODE_MD5:
335 d = MD5_DIGEST_SIZE / sizeof(u32);
336 break;
337 case FLAGS_MODE_SHA1:
338 /* OMAP2 SHA1 is big endian */
339 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
340 big_endian = 1;
341 d = SHA1_DIGEST_SIZE / sizeof(u32);
342 break;
343 case FLAGS_MODE_SHA224:
344 d = SHA224_DIGEST_SIZE / sizeof(u32);
345 break;
346 case FLAGS_MODE_SHA256:
347 d = SHA256_DIGEST_SIZE / sizeof(u32);
348 break;
349 case FLAGS_MODE_SHA384:
350 d = SHA384_DIGEST_SIZE / sizeof(u32);
351 break;
352 case FLAGS_MODE_SHA512:
353 d = SHA512_DIGEST_SIZE / sizeof(u32);
354 break;
355 default:
356 d = 0;
357 }
358
359 if (big_endian)
360 for (i = 0; i < d; i++)
361 hash[i] = be32_to_cpu(in[i]);
362 else
363 for (i = 0; i < d; i++)
364 hash[i] = le32_to_cpu(in[i]);
365 }
366
367 static int omap_sham_hw_init(struct omap_sham_dev *dd)
368 {
369 int err;
370
371 err = pm_runtime_get_sync(dd->dev);
372 if (err < 0) {
373 dev_err(dd->dev, "failed to get sync: %d\n", err);
374 return err;
375 }
376
377 if (!test_bit(FLAGS_INIT, &dd->flags)) {
378 set_bit(FLAGS_INIT, &dd->flags);
379 dd->err = 0;
380 }
381
382 return 0;
383 }
384
385 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
386 int final, int dma)
387 {
388 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
389 u32 val = length << 5, mask;
390
391 if (likely(ctx->digcnt))
392 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
393
394 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
395 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
396 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
397 /*
398 * Setting ALGO_CONST only for the first iteration
399 * and CLOSE_HASH only for the last one.
400 */
401 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
402 val |= SHA_REG_CTRL_ALGO;
403 if (!ctx->digcnt)
404 val |= SHA_REG_CTRL_ALGO_CONST;
405 if (final)
406 val |= SHA_REG_CTRL_CLOSE_HASH;
407
408 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
409 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
410
411 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
412 }
413
414 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
415 {
416 }
417
418 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
419 {
420 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
421 }
422
423 static int get_block_size(struct omap_sham_reqctx *ctx)
424 {
425 int d;
426
427 switch (ctx->flags & FLAGS_MODE_MASK) {
428 case FLAGS_MODE_MD5:
429 case FLAGS_MODE_SHA1:
430 d = SHA1_BLOCK_SIZE;
431 break;
432 case FLAGS_MODE_SHA224:
433 case FLAGS_MODE_SHA256:
434 d = SHA256_BLOCK_SIZE;
435 break;
436 case FLAGS_MODE_SHA384:
437 case FLAGS_MODE_SHA512:
438 d = SHA512_BLOCK_SIZE;
439 break;
440 default:
441 d = 0;
442 }
443
444 return d;
445 }
446
447 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
448 u32 *value, int count)
449 {
450 for (; count--; value++, offset += 4)
451 omap_sham_write(dd, offset, *value);
452 }
453
454 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
455 int final, int dma)
456 {
457 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
458 u32 val, mask;
459
460 /*
461 * Setting ALGO_CONST only for the first iteration and
462 * CLOSE_HASH only for the last one. Note that flags mode bits
463 * correspond to algorithm encoding in mode register.
464 */
465 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
466 if (!ctx->digcnt) {
467 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
468 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
469 struct omap_sham_hmac_ctx *bctx = tctx->base;
470 int bs, nr_dr;
471
472 val |= SHA_REG_MODE_ALGO_CONSTANT;
473
474 if (ctx->flags & BIT(FLAGS_HMAC)) {
475 bs = get_block_size(ctx);
476 nr_dr = bs / (2 * sizeof(u32));
477 val |= SHA_REG_MODE_HMAC_KEY_PROC;
478 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
479 (u32 *)bctx->ipad, nr_dr);
480 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
481 (u32 *)bctx->ipad + nr_dr, nr_dr);
482 ctx->digcnt += bs;
483 }
484 }
485
486 if (final) {
487 val |= SHA_REG_MODE_CLOSE_HASH;
488
489 if (ctx->flags & BIT(FLAGS_HMAC))
490 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
491 }
492
493 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
494 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
495 SHA_REG_MODE_HMAC_KEY_PROC;
496
497 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
498 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
499 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
500 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
501 SHA_REG_MASK_IT_EN |
502 (dma ? SHA_REG_MASK_DMA_EN : 0),
503 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
504 }
505
506 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
507 {
508 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
509 }
510
511 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
512 {
513 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
514 SHA_REG_IRQSTATUS_INPUT_RDY);
515 }
516
517 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
518 int final)
519 {
520 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
521 int count, len32, bs32, offset = 0;
522 const u32 *buffer;
523 int mlen;
524 struct sg_mapping_iter mi;
525
526 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
527 ctx->digcnt, length, final);
528
529 dd->pdata->write_ctrl(dd, length, final, 0);
530 dd->pdata->trigger(dd, length);
531
532 /* should be non-zero before next lines to disable clocks later */
533 ctx->digcnt += length;
534 ctx->total -= length;
535
536 if (final)
537 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
538
539 set_bit(FLAGS_CPU, &dd->flags);
540
541 len32 = DIV_ROUND_UP(length, sizeof(u32));
542 bs32 = get_block_size(ctx) / sizeof(u32);
543
544 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
545 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
546
547 mlen = 0;
548
549 while (len32) {
550 if (dd->pdata->poll_irq(dd))
551 return -ETIMEDOUT;
552
553 for (count = 0; count < min(len32, bs32); count++, offset++) {
554 if (!mlen) {
555 sg_miter_next(&mi);
556 mlen = mi.length;
557 if (!mlen) {
558 pr_err("sg miter failure.\n");
559 return -EINVAL;
560 }
561 offset = 0;
562 buffer = mi.addr;
563 }
564 omap_sham_write(dd, SHA_REG_DIN(dd, count),
565 buffer[offset]);
566 mlen -= 4;
567 }
568 len32 -= min(len32, bs32);
569 }
570
571 sg_miter_stop(&mi);
572
573 return -EINPROGRESS;
574 }
575
576 static void omap_sham_dma_callback(void *param)
577 {
578 struct omap_sham_dev *dd = param;
579
580 set_bit(FLAGS_DMA_READY, &dd->flags);
581 tasklet_schedule(&dd->done_task);
582 }
583
584 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
585 int final)
586 {
587 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
588 struct dma_async_tx_descriptor *tx;
589 struct dma_slave_config cfg;
590 int ret;
591
592 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
593 ctx->digcnt, length, final);
594
595 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
596 dev_err(dd->dev, "dma_map_sg error\n");
597 return -EINVAL;
598 }
599
600 memset(&cfg, 0, sizeof(cfg));
601
602 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
603 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
604 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
605
606 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
607 if (ret) {
608 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
609 return ret;
610 }
611
612 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
613 DMA_MEM_TO_DEV,
614 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
615
616 if (!tx) {
617 dev_err(dd->dev, "prep_slave_sg failed\n");
618 return -EINVAL;
619 }
620
621 tx->callback = omap_sham_dma_callback;
622 tx->callback_param = dd;
623
624 dd->pdata->write_ctrl(dd, length, final, 1);
625
626 ctx->digcnt += length;
627 ctx->total -= length;
628
629 if (final)
630 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
631
632 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
633
634 dmaengine_submit(tx);
635 dma_async_issue_pending(dd->dma_lch);
636
637 dd->pdata->trigger(dd, length);
638
639 return -EINPROGRESS;
640 }
641
642 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
643 struct scatterlist *sg, int bs, int new_len)
644 {
645 int n = sg_nents(sg);
646 struct scatterlist *tmp;
647 int offset = ctx->offset;
648
649 ctx->total = new_len;
650
651 if (ctx->bufcnt)
652 n++;
653
654 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
655 if (!ctx->sg)
656 return -ENOMEM;
657
658 sg_init_table(ctx->sg, n);
659
660 tmp = ctx->sg;
661
662 ctx->sg_len = 0;
663
664 if (ctx->bufcnt) {
665 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
666 tmp = sg_next(tmp);
667 ctx->sg_len++;
668 new_len -= ctx->bufcnt;
669 }
670
671 while (sg && new_len) {
672 int len = sg->length - offset;
673
674 if (len <= 0) {
675 offset -= sg->length;
676 sg = sg_next(sg);
677 continue;
678 }
679
680 if (new_len < len)
681 len = new_len;
682
683 if (len > 0) {
684 new_len -= len;
685 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
686 offset = 0;
687 ctx->offset = 0;
688 ctx->sg_len++;
689 if (new_len <= 0)
690 break;
691 tmp = sg_next(tmp);
692 }
693
694 sg = sg_next(sg);
695 }
696
697 if (tmp)
698 sg_mark_end(tmp);
699
700 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
701
702 ctx->offset += new_len - ctx->bufcnt;
703 ctx->bufcnt = 0;
704
705 return 0;
706 }
707
708 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
709 struct scatterlist *sg, int bs,
710 unsigned int new_len)
711 {
712 int pages;
713 void *buf;
714
715 pages = get_order(new_len);
716
717 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
718 if (!buf) {
719 pr_err("Couldn't allocate pages for unaligned cases.\n");
720 return -ENOMEM;
721 }
722
723 if (ctx->bufcnt)
724 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
725
726 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
727 min(new_len, ctx->total) - ctx->bufcnt, 0);
728 sg_init_table(ctx->sgl, 1);
729 sg_set_buf(ctx->sgl, buf, new_len);
730 ctx->sg = ctx->sgl;
731 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
732 ctx->sg_len = 1;
733 ctx->offset += new_len - ctx->bufcnt;
734 ctx->bufcnt = 0;
735 ctx->total = new_len;
736
737 return 0;
738 }
739
740 static int omap_sham_align_sgs(struct scatterlist *sg,
741 int nbytes, int bs, bool final,
742 struct omap_sham_reqctx *rctx)
743 {
744 int n = 0;
745 bool aligned = true;
746 bool list_ok = true;
747 struct scatterlist *sg_tmp = sg;
748 int new_len;
749 int offset = rctx->offset;
750 int bufcnt = rctx->bufcnt;
751
752 if (!sg || !sg->length || !nbytes) {
753 if (bufcnt) {
754 sg_init_table(rctx->sgl, 1);
755 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt);
756 rctx->sg = rctx->sgl;
757 }
758
759 return 0;
760 }
761
762 new_len = nbytes;
763
764 if (offset)
765 list_ok = false;
766
767 if (final)
768 new_len = DIV_ROUND_UP(new_len, bs) * bs;
769 else
770 new_len = (new_len - 1) / bs * bs;
771
772 if (!new_len)
773 return 0;
774
775 if (nbytes != new_len)
776 list_ok = false;
777
778 while (nbytes > 0 && sg_tmp) {
779 n++;
780
781 if (bufcnt) {
782 if (!IS_ALIGNED(bufcnt, bs)) {
783 aligned = false;
784 break;
785 }
786 nbytes -= bufcnt;
787 bufcnt = 0;
788 if (!nbytes)
789 list_ok = false;
790
791 continue;
792 }
793
794 #ifdef CONFIG_ZONE_DMA
795 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
796 aligned = false;
797 break;
798 }
799 #endif
800
801 if (offset < sg_tmp->length) {
802 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
803 aligned = false;
804 break;
805 }
806
807 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
808 aligned = false;
809 break;
810 }
811 }
812
813 if (offset) {
814 offset -= sg_tmp->length;
815 if (offset < 0) {
816 nbytes += offset;
817 offset = 0;
818 }
819 } else {
820 nbytes -= sg_tmp->length;
821 }
822
823 sg_tmp = sg_next(sg_tmp);
824
825 if (nbytes < 0) {
826 list_ok = false;
827 break;
828 }
829 }
830
831 if (new_len > OMAP_SHA_MAX_DMA_LEN) {
832 new_len = OMAP_SHA_MAX_DMA_LEN;
833 aligned = false;
834 }
835
836 if (!aligned)
837 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
838 else if (!list_ok)
839 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
840
841 rctx->total = new_len;
842 rctx->offset += new_len;
843 rctx->sg_len = n;
844 if (rctx->bufcnt) {
845 sg_init_table(rctx->sgl, 2);
846 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
847 sg_chain(rctx->sgl, 2, sg);
848 rctx->sg = rctx->sgl;
849 } else {
850 rctx->sg = sg;
851 }
852
853 return 0;
854 }
855
856 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
857 {
858 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
859 int bs;
860 int ret;
861 unsigned int nbytes;
862 bool final = rctx->flags & BIT(FLAGS_FINUP);
863 int hash_later;
864
865 bs = get_block_size(rctx);
866
867 nbytes = rctx->bufcnt;
868
869 if (update)
870 nbytes += req->nbytes - rctx->offset;
871
872 dev_dbg(rctx->dd->dev,
873 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n",
874 __func__, nbytes, bs, rctx->total, rctx->offset,
875 rctx->bufcnt);
876
877 if (!nbytes)
878 return 0;
879
880 rctx->total = nbytes;
881
882 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
883 int len = bs - rctx->bufcnt % bs;
884
885 if (len > req->nbytes)
886 len = req->nbytes;
887 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
888 0, len, 0);
889 rctx->bufcnt += len;
890 rctx->offset = len;
891 }
892
893 if (rctx->bufcnt)
894 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
895
896 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
897 if (ret)
898 return ret;
899
900 hash_later = nbytes - rctx->total;
901 if (hash_later < 0)
902 hash_later = 0;
903
904 if (hash_later && hash_later <= rctx->buflen) {
905 scatterwalk_map_and_copy(rctx->buffer,
906 req->src,
907 req->nbytes - hash_later,
908 hash_later, 0);
909
910 rctx->bufcnt = hash_later;
911 } else {
912 rctx->bufcnt = 0;
913 }
914
915 if (hash_later > rctx->buflen)
916 set_bit(FLAGS_HUGE, &rctx->dd->flags);
917
918 rctx->total = min(nbytes, rctx->total);
919
920 return 0;
921 }
922
923 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
924 {
925 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
926
927 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
928
929 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
930
931 return 0;
932 }
933
934 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
935 {
936 struct omap_sham_dev *dd;
937
938 if (ctx->dd)
939 return ctx->dd;
940
941 spin_lock_bh(&sham.lock);
942 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
943 list_move_tail(&dd->list, &sham.dev_list);
944 ctx->dd = dd;
945 spin_unlock_bh(&sham.lock);
946
947 return dd;
948 }
949
950 static int omap_sham_init(struct ahash_request *req)
951 {
952 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
953 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
954 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
955 struct omap_sham_dev *dd;
956 int bs = 0;
957
958 ctx->dd = NULL;
959
960 dd = omap_sham_find_dev(ctx);
961 if (!dd)
962 return -ENODEV;
963
964 ctx->flags = 0;
965
966 dev_dbg(dd->dev, "init: digest size: %d\n",
967 crypto_ahash_digestsize(tfm));
968
969 switch (crypto_ahash_digestsize(tfm)) {
970 case MD5_DIGEST_SIZE:
971 ctx->flags |= FLAGS_MODE_MD5;
972 bs = SHA1_BLOCK_SIZE;
973 break;
974 case SHA1_DIGEST_SIZE:
975 ctx->flags |= FLAGS_MODE_SHA1;
976 bs = SHA1_BLOCK_SIZE;
977 break;
978 case SHA224_DIGEST_SIZE:
979 ctx->flags |= FLAGS_MODE_SHA224;
980 bs = SHA224_BLOCK_SIZE;
981 break;
982 case SHA256_DIGEST_SIZE:
983 ctx->flags |= FLAGS_MODE_SHA256;
984 bs = SHA256_BLOCK_SIZE;
985 break;
986 case SHA384_DIGEST_SIZE:
987 ctx->flags |= FLAGS_MODE_SHA384;
988 bs = SHA384_BLOCK_SIZE;
989 break;
990 case SHA512_DIGEST_SIZE:
991 ctx->flags |= FLAGS_MODE_SHA512;
992 bs = SHA512_BLOCK_SIZE;
993 break;
994 }
995
996 ctx->bufcnt = 0;
997 ctx->digcnt = 0;
998 ctx->total = 0;
999 ctx->offset = 0;
1000 ctx->buflen = BUFLEN;
1001
1002 if (tctx->flags & BIT(FLAGS_HMAC)) {
1003 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1004 struct omap_sham_hmac_ctx *bctx = tctx->base;
1005
1006 memcpy(ctx->buffer, bctx->ipad, bs);
1007 ctx->bufcnt = bs;
1008 }
1009
1010 ctx->flags |= BIT(FLAGS_HMAC);
1011 }
1012
1013 return 0;
1014
1015 }
1016
1017 static int omap_sham_update_req(struct omap_sham_dev *dd)
1018 {
1019 struct ahash_request *req = dd->req;
1020 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1021 int err;
1022 bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1023 !(dd->flags & BIT(FLAGS_HUGE));
1024
1025 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d",
1026 ctx->total, ctx->digcnt, final);
1027
1028 if (ctx->total < get_block_size(ctx) ||
1029 ctx->total < dd->fallback_sz)
1030 ctx->flags |= BIT(FLAGS_CPU);
1031
1032 if (ctx->flags & BIT(FLAGS_CPU))
1033 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1034 else
1035 err = omap_sham_xmit_dma(dd, ctx->total, final);
1036
1037 /* wait for dma completion before can take more data */
1038 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1039
1040 return err;
1041 }
1042
1043 static int omap_sham_final_req(struct omap_sham_dev *dd)
1044 {
1045 struct ahash_request *req = dd->req;
1046 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1047 int err = 0, use_dma = 1;
1048
1049 if (dd->flags & BIT(FLAGS_HUGE))
1050 return 0;
1051
1052 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1053 /*
1054 * faster to handle last block with cpu or
1055 * use cpu when dma is not present.
1056 */
1057 use_dma = 0;
1058
1059 if (use_dma)
1060 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1061 else
1062 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1063
1064 ctx->bufcnt = 0;
1065
1066 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1067
1068 return err;
1069 }
1070
1071 static int omap_sham_finish_hmac(struct ahash_request *req)
1072 {
1073 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1074 struct omap_sham_hmac_ctx *bctx = tctx->base;
1075 int bs = crypto_shash_blocksize(bctx->shash);
1076 int ds = crypto_shash_digestsize(bctx->shash);
1077 SHASH_DESC_ON_STACK(shash, bctx->shash);
1078
1079 shash->tfm = bctx->shash;
1080
1081 return crypto_shash_init(shash) ?:
1082 crypto_shash_update(shash, bctx->opad, bs) ?:
1083 crypto_shash_finup(shash, req->result, ds, req->result);
1084 }
1085
1086 static int omap_sham_finish(struct ahash_request *req)
1087 {
1088 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1089 struct omap_sham_dev *dd = ctx->dd;
1090 int err = 0;
1091
1092 if (ctx->digcnt) {
1093 omap_sham_copy_ready_hash(req);
1094 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1095 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1096 err = omap_sham_finish_hmac(req);
1097 }
1098
1099 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1100
1101 return err;
1102 }
1103
1104 static void omap_sham_finish_req(struct ahash_request *req, int err)
1105 {
1106 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1107 struct omap_sham_dev *dd = ctx->dd;
1108
1109 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1110 free_pages((unsigned long)sg_virt(ctx->sg),
1111 get_order(ctx->sg->length));
1112
1113 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1114 kfree(ctx->sg);
1115
1116 ctx->sg = NULL;
1117
1118 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1119
1120 if (dd->flags & BIT(FLAGS_HUGE)) {
1121 dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1122 BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE));
1123 omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1124 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1125 err = omap_sham_update_req(dd);
1126 if (err != -EINPROGRESS &&
1127 (ctx->flags & BIT(FLAGS_FINUP)))
1128 err = omap_sham_final_req(dd);
1129 } else if (ctx->op == OP_FINAL) {
1130 omap_sham_final_req(dd);
1131 }
1132 return;
1133 }
1134
1135 if (!err) {
1136 dd->pdata->copy_hash(req, 1);
1137 if (test_bit(FLAGS_FINAL, &dd->flags))
1138 err = omap_sham_finish(req);
1139 } else {
1140 ctx->flags |= BIT(FLAGS_ERROR);
1141 }
1142
1143 /* atomic operation is not needed here */
1144 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1145 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1146
1147 pm_runtime_mark_last_busy(dd->dev);
1148 pm_runtime_put_autosuspend(dd->dev);
1149
1150 ctx->offset = 0;
1151
1152 if (req->base.complete)
1153 req->base.complete(&req->base, err);
1154 }
1155
1156 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1157 struct ahash_request *req)
1158 {
1159 struct crypto_async_request *async_req, *backlog;
1160 struct omap_sham_reqctx *ctx;
1161 unsigned long flags;
1162 int err = 0, ret = 0;
1163
1164 retry:
1165 spin_lock_irqsave(&dd->lock, flags);
1166 if (req)
1167 ret = ahash_enqueue_request(&dd->queue, req);
1168 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1169 spin_unlock_irqrestore(&dd->lock, flags);
1170 return ret;
1171 }
1172 backlog = crypto_get_backlog(&dd->queue);
1173 async_req = crypto_dequeue_request(&dd->queue);
1174 if (async_req)
1175 set_bit(FLAGS_BUSY, &dd->flags);
1176 spin_unlock_irqrestore(&dd->lock, flags);
1177
1178 if (!async_req)
1179 return ret;
1180
1181 if (backlog)
1182 backlog->complete(backlog, -EINPROGRESS);
1183
1184 req = ahash_request_cast(async_req);
1185 dd->req = req;
1186 ctx = ahash_request_ctx(req);
1187
1188 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1189 if (err || !ctx->total)
1190 goto err1;
1191
1192 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1193 ctx->op, req->nbytes);
1194
1195 err = omap_sham_hw_init(dd);
1196 if (err)
1197 goto err1;
1198
1199 if (ctx->digcnt)
1200 /* request has changed - restore hash */
1201 dd->pdata->copy_hash(req, 0);
1202
1203 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) {
1204 err = omap_sham_update_req(dd);
1205 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1206 /* no final() after finup() */
1207 err = omap_sham_final_req(dd);
1208 } else if (ctx->op == OP_FINAL) {
1209 err = omap_sham_final_req(dd);
1210 }
1211 err1:
1212 dev_dbg(dd->dev, "exit, err: %d\n", err);
1213
1214 if (err != -EINPROGRESS) {
1215 /* done_task will not finish it, so do it here */
1216 omap_sham_finish_req(req, err);
1217 req = NULL;
1218
1219 /*
1220 * Execute next request immediately if there is anything
1221 * in queue.
1222 */
1223 goto retry;
1224 }
1225
1226 return ret;
1227 }
1228
1229 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1230 {
1231 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1232 struct omap_sham_dev *dd = ctx->dd;
1233
1234 ctx->op = op;
1235
1236 return omap_sham_handle_queue(dd, req);
1237 }
1238
1239 static int omap_sham_update(struct ahash_request *req)
1240 {
1241 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1242 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1243
1244 if (!req->nbytes)
1245 return 0;
1246
1247 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1248 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1249 0, req->nbytes, 0);
1250 ctx->bufcnt += req->nbytes;
1251 return 0;
1252 }
1253
1254 if (dd->polling_mode)
1255 ctx->flags |= BIT(FLAGS_CPU);
1256
1257 return omap_sham_enqueue(req, OP_UPDATE);
1258 }
1259
1260 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1261 const u8 *data, unsigned int len, u8 *out)
1262 {
1263 SHASH_DESC_ON_STACK(shash, tfm);
1264
1265 shash->tfm = tfm;
1266
1267 return crypto_shash_digest(shash, data, len, out);
1268 }
1269
1270 static int omap_sham_final_shash(struct ahash_request *req)
1271 {
1272 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1273 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1274 int offset = 0;
1275
1276 /*
1277 * If we are running HMAC on limited hardware support, skip
1278 * the ipad in the beginning of the buffer if we are going for
1279 * software fallback algorithm.
1280 */
1281 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1282 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1283 offset = get_block_size(ctx);
1284
1285 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1286 ctx->buffer + offset,
1287 ctx->bufcnt - offset, req->result);
1288 }
1289
1290 static int omap_sham_final(struct ahash_request *req)
1291 {
1292 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1293
1294 ctx->flags |= BIT(FLAGS_FINUP);
1295
1296 if (ctx->flags & BIT(FLAGS_ERROR))
1297 return 0; /* uncompleted hash is not needed */
1298
1299 /*
1300 * OMAP HW accel works only with buffers >= 9.
1301 * HMAC is always >= 9 because ipad == block size.
1302 * If buffersize is less than fallback_sz, we use fallback
1303 * SW encoding, as using DMA + HW in this case doesn't provide
1304 * any benefit.
1305 */
1306 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1307 return omap_sham_final_shash(req);
1308 else if (ctx->bufcnt)
1309 return omap_sham_enqueue(req, OP_FINAL);
1310
1311 /* copy ready hash (+ finalize hmac) */
1312 return omap_sham_finish(req);
1313 }
1314
1315 static int omap_sham_finup(struct ahash_request *req)
1316 {
1317 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1318 int err1, err2;
1319
1320 ctx->flags |= BIT(FLAGS_FINUP);
1321
1322 err1 = omap_sham_update(req);
1323 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1324 return err1;
1325 /*
1326 * final() has to be always called to cleanup resources
1327 * even if udpate() failed, except EINPROGRESS
1328 */
1329 err2 = omap_sham_final(req);
1330
1331 return err1 ?: err2;
1332 }
1333
1334 static int omap_sham_digest(struct ahash_request *req)
1335 {
1336 return omap_sham_init(req) ?: omap_sham_finup(req);
1337 }
1338
1339 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1340 unsigned int keylen)
1341 {
1342 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1343 struct omap_sham_hmac_ctx *bctx = tctx->base;
1344 int bs = crypto_shash_blocksize(bctx->shash);
1345 int ds = crypto_shash_digestsize(bctx->shash);
1346 int err, i;
1347
1348 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1349 if (err)
1350 return err;
1351
1352 if (keylen > bs) {
1353 err = omap_sham_shash_digest(bctx->shash,
1354 crypto_shash_get_flags(bctx->shash),
1355 key, keylen, bctx->ipad);
1356 if (err)
1357 return err;
1358 keylen = ds;
1359 } else {
1360 memcpy(bctx->ipad, key, keylen);
1361 }
1362
1363 memset(bctx->ipad + keylen, 0, bs - keylen);
1364
1365 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1366 memcpy(bctx->opad, bctx->ipad, bs);
1367
1368 for (i = 0; i < bs; i++) {
1369 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1370 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1371 }
1372 }
1373
1374 return err;
1375 }
1376
1377 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1378 {
1379 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1380 const char *alg_name = crypto_tfm_alg_name(tfm);
1381
1382 /* Allocate a fallback and abort if it failed. */
1383 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1384 CRYPTO_ALG_NEED_FALLBACK);
1385 if (IS_ERR(tctx->fallback)) {
1386 pr_err("omap-sham: fallback driver '%s' "
1387 "could not be loaded.\n", alg_name);
1388 return PTR_ERR(tctx->fallback);
1389 }
1390
1391 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1392 sizeof(struct omap_sham_reqctx) + BUFLEN);
1393
1394 if (alg_base) {
1395 struct omap_sham_hmac_ctx *bctx = tctx->base;
1396 tctx->flags |= BIT(FLAGS_HMAC);
1397 bctx->shash = crypto_alloc_shash(alg_base, 0,
1398 CRYPTO_ALG_NEED_FALLBACK);
1399 if (IS_ERR(bctx->shash)) {
1400 pr_err("omap-sham: base driver '%s' "
1401 "could not be loaded.\n", alg_base);
1402 crypto_free_shash(tctx->fallback);
1403 return PTR_ERR(bctx->shash);
1404 }
1405
1406 }
1407
1408 return 0;
1409 }
1410
1411 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1412 {
1413 return omap_sham_cra_init_alg(tfm, NULL);
1414 }
1415
1416 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1417 {
1418 return omap_sham_cra_init_alg(tfm, "sha1");
1419 }
1420
1421 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1422 {
1423 return omap_sham_cra_init_alg(tfm, "sha224");
1424 }
1425
1426 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1427 {
1428 return omap_sham_cra_init_alg(tfm, "sha256");
1429 }
1430
1431 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1432 {
1433 return omap_sham_cra_init_alg(tfm, "md5");
1434 }
1435
1436 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1437 {
1438 return omap_sham_cra_init_alg(tfm, "sha384");
1439 }
1440
1441 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1442 {
1443 return omap_sham_cra_init_alg(tfm, "sha512");
1444 }
1445
1446 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1447 {
1448 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1449
1450 crypto_free_shash(tctx->fallback);
1451 tctx->fallback = NULL;
1452
1453 if (tctx->flags & BIT(FLAGS_HMAC)) {
1454 struct omap_sham_hmac_ctx *bctx = tctx->base;
1455 crypto_free_shash(bctx->shash);
1456 }
1457 }
1458
1459 static int omap_sham_export(struct ahash_request *req, void *out)
1460 {
1461 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1462
1463 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1464
1465 return 0;
1466 }
1467
1468 static int omap_sham_import(struct ahash_request *req, const void *in)
1469 {
1470 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1471 const struct omap_sham_reqctx *ctx_in = in;
1472
1473 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1474
1475 return 0;
1476 }
1477
1478 static struct ahash_alg algs_sha1_md5[] = {
1479 {
1480 .init = omap_sham_init,
1481 .update = omap_sham_update,
1482 .final = omap_sham_final,
1483 .finup = omap_sham_finup,
1484 .digest = omap_sham_digest,
1485 .halg.digestsize = SHA1_DIGEST_SIZE,
1486 .halg.base = {
1487 .cra_name = "sha1",
1488 .cra_driver_name = "omap-sha1",
1489 .cra_priority = 400,
1490 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1491 CRYPTO_ALG_ASYNC |
1492 CRYPTO_ALG_NEED_FALLBACK,
1493 .cra_blocksize = SHA1_BLOCK_SIZE,
1494 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1495 .cra_alignmask = OMAP_ALIGN_MASK,
1496 .cra_module = THIS_MODULE,
1497 .cra_init = omap_sham_cra_init,
1498 .cra_exit = omap_sham_cra_exit,
1499 }
1500 },
1501 {
1502 .init = omap_sham_init,
1503 .update = omap_sham_update,
1504 .final = omap_sham_final,
1505 .finup = omap_sham_finup,
1506 .digest = omap_sham_digest,
1507 .halg.digestsize = MD5_DIGEST_SIZE,
1508 .halg.base = {
1509 .cra_name = "md5",
1510 .cra_driver_name = "omap-md5",
1511 .cra_priority = 400,
1512 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1513 CRYPTO_ALG_ASYNC |
1514 CRYPTO_ALG_NEED_FALLBACK,
1515 .cra_blocksize = SHA1_BLOCK_SIZE,
1516 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1517 .cra_alignmask = OMAP_ALIGN_MASK,
1518 .cra_module = THIS_MODULE,
1519 .cra_init = omap_sham_cra_init,
1520 .cra_exit = omap_sham_cra_exit,
1521 }
1522 },
1523 {
1524 .init = omap_sham_init,
1525 .update = omap_sham_update,
1526 .final = omap_sham_final,
1527 .finup = omap_sham_finup,
1528 .digest = omap_sham_digest,
1529 .setkey = omap_sham_setkey,
1530 .halg.digestsize = SHA1_DIGEST_SIZE,
1531 .halg.base = {
1532 .cra_name = "hmac(sha1)",
1533 .cra_driver_name = "omap-hmac-sha1",
1534 .cra_priority = 400,
1535 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1536 CRYPTO_ALG_ASYNC |
1537 CRYPTO_ALG_NEED_FALLBACK,
1538 .cra_blocksize = SHA1_BLOCK_SIZE,
1539 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1540 sizeof(struct omap_sham_hmac_ctx),
1541 .cra_alignmask = OMAP_ALIGN_MASK,
1542 .cra_module = THIS_MODULE,
1543 .cra_init = omap_sham_cra_sha1_init,
1544 .cra_exit = omap_sham_cra_exit,
1545 }
1546 },
1547 {
1548 .init = omap_sham_init,
1549 .update = omap_sham_update,
1550 .final = omap_sham_final,
1551 .finup = omap_sham_finup,
1552 .digest = omap_sham_digest,
1553 .setkey = omap_sham_setkey,
1554 .halg.digestsize = MD5_DIGEST_SIZE,
1555 .halg.base = {
1556 .cra_name = "hmac(md5)",
1557 .cra_driver_name = "omap-hmac-md5",
1558 .cra_priority = 400,
1559 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1560 CRYPTO_ALG_ASYNC |
1561 CRYPTO_ALG_NEED_FALLBACK,
1562 .cra_blocksize = SHA1_BLOCK_SIZE,
1563 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1564 sizeof(struct omap_sham_hmac_ctx),
1565 .cra_alignmask = OMAP_ALIGN_MASK,
1566 .cra_module = THIS_MODULE,
1567 .cra_init = omap_sham_cra_md5_init,
1568 .cra_exit = omap_sham_cra_exit,
1569 }
1570 }
1571 };
1572
1573 /* OMAP4 has some algs in addition to what OMAP2 has */
1574 static struct ahash_alg algs_sha224_sha256[] = {
1575 {
1576 .init = omap_sham_init,
1577 .update = omap_sham_update,
1578 .final = omap_sham_final,
1579 .finup = omap_sham_finup,
1580 .digest = omap_sham_digest,
1581 .halg.digestsize = SHA224_DIGEST_SIZE,
1582 .halg.base = {
1583 .cra_name = "sha224",
1584 .cra_driver_name = "omap-sha224",
1585 .cra_priority = 400,
1586 .cra_flags = CRYPTO_ALG_ASYNC |
1587 CRYPTO_ALG_NEED_FALLBACK,
1588 .cra_blocksize = SHA224_BLOCK_SIZE,
1589 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1590 .cra_alignmask = OMAP_ALIGN_MASK,
1591 .cra_module = THIS_MODULE,
1592 .cra_init = omap_sham_cra_init,
1593 .cra_exit = omap_sham_cra_exit,
1594 }
1595 },
1596 {
1597 .init = omap_sham_init,
1598 .update = omap_sham_update,
1599 .final = omap_sham_final,
1600 .finup = omap_sham_finup,
1601 .digest = omap_sham_digest,
1602 .halg.digestsize = SHA256_DIGEST_SIZE,
1603 .halg.base = {
1604 .cra_name = "sha256",
1605 .cra_driver_name = "omap-sha256",
1606 .cra_priority = 400,
1607 .cra_flags = CRYPTO_ALG_ASYNC |
1608 CRYPTO_ALG_NEED_FALLBACK,
1609 .cra_blocksize = SHA256_BLOCK_SIZE,
1610 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1611 .cra_alignmask = OMAP_ALIGN_MASK,
1612 .cra_module = THIS_MODULE,
1613 .cra_init = omap_sham_cra_init,
1614 .cra_exit = omap_sham_cra_exit,
1615 }
1616 },
1617 {
1618 .init = omap_sham_init,
1619 .update = omap_sham_update,
1620 .final = omap_sham_final,
1621 .finup = omap_sham_finup,
1622 .digest = omap_sham_digest,
1623 .setkey = omap_sham_setkey,
1624 .halg.digestsize = SHA224_DIGEST_SIZE,
1625 .halg.base = {
1626 .cra_name = "hmac(sha224)",
1627 .cra_driver_name = "omap-hmac-sha224",
1628 .cra_priority = 400,
1629 .cra_flags = CRYPTO_ALG_ASYNC |
1630 CRYPTO_ALG_NEED_FALLBACK,
1631 .cra_blocksize = SHA224_BLOCK_SIZE,
1632 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1633 sizeof(struct omap_sham_hmac_ctx),
1634 .cra_alignmask = OMAP_ALIGN_MASK,
1635 .cra_module = THIS_MODULE,
1636 .cra_init = omap_sham_cra_sha224_init,
1637 .cra_exit = omap_sham_cra_exit,
1638 }
1639 },
1640 {
1641 .init = omap_sham_init,
1642 .update = omap_sham_update,
1643 .final = omap_sham_final,
1644 .finup = omap_sham_finup,
1645 .digest = omap_sham_digest,
1646 .setkey = omap_sham_setkey,
1647 .halg.digestsize = SHA256_DIGEST_SIZE,
1648 .halg.base = {
1649 .cra_name = "hmac(sha256)",
1650 .cra_driver_name = "omap-hmac-sha256",
1651 .cra_priority = 400,
1652 .cra_flags = CRYPTO_ALG_ASYNC |
1653 CRYPTO_ALG_NEED_FALLBACK,
1654 .cra_blocksize = SHA256_BLOCK_SIZE,
1655 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1656 sizeof(struct omap_sham_hmac_ctx),
1657 .cra_alignmask = OMAP_ALIGN_MASK,
1658 .cra_module = THIS_MODULE,
1659 .cra_init = omap_sham_cra_sha256_init,
1660 .cra_exit = omap_sham_cra_exit,
1661 }
1662 },
1663 };
1664
1665 static struct ahash_alg algs_sha384_sha512[] = {
1666 {
1667 .init = omap_sham_init,
1668 .update = omap_sham_update,
1669 .final = omap_sham_final,
1670 .finup = omap_sham_finup,
1671 .digest = omap_sham_digest,
1672 .halg.digestsize = SHA384_DIGEST_SIZE,
1673 .halg.base = {
1674 .cra_name = "sha384",
1675 .cra_driver_name = "omap-sha384",
1676 .cra_priority = 400,
1677 .cra_flags = CRYPTO_ALG_ASYNC |
1678 CRYPTO_ALG_NEED_FALLBACK,
1679 .cra_blocksize = SHA384_BLOCK_SIZE,
1680 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1681 .cra_alignmask = OMAP_ALIGN_MASK,
1682 .cra_module = THIS_MODULE,
1683 .cra_init = omap_sham_cra_init,
1684 .cra_exit = omap_sham_cra_exit,
1685 }
1686 },
1687 {
1688 .init = omap_sham_init,
1689 .update = omap_sham_update,
1690 .final = omap_sham_final,
1691 .finup = omap_sham_finup,
1692 .digest = omap_sham_digest,
1693 .halg.digestsize = SHA512_DIGEST_SIZE,
1694 .halg.base = {
1695 .cra_name = "sha512",
1696 .cra_driver_name = "omap-sha512",
1697 .cra_priority = 400,
1698 .cra_flags = CRYPTO_ALG_ASYNC |
1699 CRYPTO_ALG_NEED_FALLBACK,
1700 .cra_blocksize = SHA512_BLOCK_SIZE,
1701 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1702 .cra_alignmask = OMAP_ALIGN_MASK,
1703 .cra_module = THIS_MODULE,
1704 .cra_init = omap_sham_cra_init,
1705 .cra_exit = omap_sham_cra_exit,
1706 }
1707 },
1708 {
1709 .init = omap_sham_init,
1710 .update = omap_sham_update,
1711 .final = omap_sham_final,
1712 .finup = omap_sham_finup,
1713 .digest = omap_sham_digest,
1714 .setkey = omap_sham_setkey,
1715 .halg.digestsize = SHA384_DIGEST_SIZE,
1716 .halg.base = {
1717 .cra_name = "hmac(sha384)",
1718 .cra_driver_name = "omap-hmac-sha384",
1719 .cra_priority = 400,
1720 .cra_flags = CRYPTO_ALG_ASYNC |
1721 CRYPTO_ALG_NEED_FALLBACK,
1722 .cra_blocksize = SHA384_BLOCK_SIZE,
1723 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1724 sizeof(struct omap_sham_hmac_ctx),
1725 .cra_alignmask = OMAP_ALIGN_MASK,
1726 .cra_module = THIS_MODULE,
1727 .cra_init = omap_sham_cra_sha384_init,
1728 .cra_exit = omap_sham_cra_exit,
1729 }
1730 },
1731 {
1732 .init = omap_sham_init,
1733 .update = omap_sham_update,
1734 .final = omap_sham_final,
1735 .finup = omap_sham_finup,
1736 .digest = omap_sham_digest,
1737 .setkey = omap_sham_setkey,
1738 .halg.digestsize = SHA512_DIGEST_SIZE,
1739 .halg.base = {
1740 .cra_name = "hmac(sha512)",
1741 .cra_driver_name = "omap-hmac-sha512",
1742 .cra_priority = 400,
1743 .cra_flags = CRYPTO_ALG_ASYNC |
1744 CRYPTO_ALG_NEED_FALLBACK,
1745 .cra_blocksize = SHA512_BLOCK_SIZE,
1746 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1747 sizeof(struct omap_sham_hmac_ctx),
1748 .cra_alignmask = OMAP_ALIGN_MASK,
1749 .cra_module = THIS_MODULE,
1750 .cra_init = omap_sham_cra_sha512_init,
1751 .cra_exit = omap_sham_cra_exit,
1752 }
1753 },
1754 };
1755
1756 static void omap_sham_done_task(unsigned long data)
1757 {
1758 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1759 int err = 0;
1760
1761 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1762
1763 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1764 omap_sham_handle_queue(dd, NULL);
1765 return;
1766 }
1767
1768 if (test_bit(FLAGS_CPU, &dd->flags)) {
1769 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1770 goto finish;
1771 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1772 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1773 omap_sham_update_dma_stop(dd);
1774 if (dd->err) {
1775 err = dd->err;
1776 goto finish;
1777 }
1778 }
1779 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1780 /* hash or semi-hash ready */
1781 clear_bit(FLAGS_DMA_READY, &dd->flags);
1782 goto finish;
1783 }
1784 }
1785
1786 return;
1787
1788 finish:
1789 dev_dbg(dd->dev, "update done: err: %d\n", err);
1790 /* finish curent request */
1791 omap_sham_finish_req(dd->req, err);
1792
1793 /* If we are not busy, process next req */
1794 if (!test_bit(FLAGS_BUSY, &dd->flags))
1795 omap_sham_handle_queue(dd, NULL);
1796 }
1797
1798 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1799 {
1800 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1801 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1802 } else {
1803 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1804 tasklet_schedule(&dd->done_task);
1805 }
1806
1807 return IRQ_HANDLED;
1808 }
1809
1810 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1811 {
1812 struct omap_sham_dev *dd = dev_id;
1813
1814 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1815 /* final -> allow device to go to power-saving mode */
1816 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1817
1818 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1819 SHA_REG_CTRL_OUTPUT_READY);
1820 omap_sham_read(dd, SHA_REG_CTRL);
1821
1822 return omap_sham_irq_common(dd);
1823 }
1824
1825 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1826 {
1827 struct omap_sham_dev *dd = dev_id;
1828
1829 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1830
1831 return omap_sham_irq_common(dd);
1832 }
1833
1834 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1835 {
1836 .algs_list = algs_sha1_md5,
1837 .size = ARRAY_SIZE(algs_sha1_md5),
1838 },
1839 };
1840
1841 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1842 .algs_info = omap_sham_algs_info_omap2,
1843 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1844 .flags = BIT(FLAGS_BE32_SHA1),
1845 .digest_size = SHA1_DIGEST_SIZE,
1846 .copy_hash = omap_sham_copy_hash_omap2,
1847 .write_ctrl = omap_sham_write_ctrl_omap2,
1848 .trigger = omap_sham_trigger_omap2,
1849 .poll_irq = omap_sham_poll_irq_omap2,
1850 .intr_hdlr = omap_sham_irq_omap2,
1851 .idigest_ofs = 0x00,
1852 .din_ofs = 0x1c,
1853 .digcnt_ofs = 0x14,
1854 .rev_ofs = 0x5c,
1855 .mask_ofs = 0x60,
1856 .sysstatus_ofs = 0x64,
1857 .major_mask = 0xf0,
1858 .major_shift = 4,
1859 .minor_mask = 0x0f,
1860 .minor_shift = 0,
1861 };
1862
1863 #ifdef CONFIG_OF
1864 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1865 {
1866 .algs_list = algs_sha1_md5,
1867 .size = ARRAY_SIZE(algs_sha1_md5),
1868 },
1869 {
1870 .algs_list = algs_sha224_sha256,
1871 .size = ARRAY_SIZE(algs_sha224_sha256),
1872 },
1873 };
1874
1875 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1876 .algs_info = omap_sham_algs_info_omap4,
1877 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1878 .flags = BIT(FLAGS_AUTO_XOR),
1879 .digest_size = SHA256_DIGEST_SIZE,
1880 .copy_hash = omap_sham_copy_hash_omap4,
1881 .write_ctrl = omap_sham_write_ctrl_omap4,
1882 .trigger = omap_sham_trigger_omap4,
1883 .poll_irq = omap_sham_poll_irq_omap4,
1884 .intr_hdlr = omap_sham_irq_omap4,
1885 .idigest_ofs = 0x020,
1886 .odigest_ofs = 0x0,
1887 .din_ofs = 0x080,
1888 .digcnt_ofs = 0x040,
1889 .rev_ofs = 0x100,
1890 .mask_ofs = 0x110,
1891 .sysstatus_ofs = 0x114,
1892 .mode_ofs = 0x44,
1893 .length_ofs = 0x48,
1894 .major_mask = 0x0700,
1895 .major_shift = 8,
1896 .minor_mask = 0x003f,
1897 .minor_shift = 0,
1898 };
1899
1900 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1901 {
1902 .algs_list = algs_sha1_md5,
1903 .size = ARRAY_SIZE(algs_sha1_md5),
1904 },
1905 {
1906 .algs_list = algs_sha224_sha256,
1907 .size = ARRAY_SIZE(algs_sha224_sha256),
1908 },
1909 {
1910 .algs_list = algs_sha384_sha512,
1911 .size = ARRAY_SIZE(algs_sha384_sha512),
1912 },
1913 };
1914
1915 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1916 .algs_info = omap_sham_algs_info_omap5,
1917 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1918 .flags = BIT(FLAGS_AUTO_XOR),
1919 .digest_size = SHA512_DIGEST_SIZE,
1920 .copy_hash = omap_sham_copy_hash_omap4,
1921 .write_ctrl = omap_sham_write_ctrl_omap4,
1922 .trigger = omap_sham_trigger_omap4,
1923 .poll_irq = omap_sham_poll_irq_omap4,
1924 .intr_hdlr = omap_sham_irq_omap4,
1925 .idigest_ofs = 0x240,
1926 .odigest_ofs = 0x200,
1927 .din_ofs = 0x080,
1928 .digcnt_ofs = 0x280,
1929 .rev_ofs = 0x100,
1930 .mask_ofs = 0x110,
1931 .sysstatus_ofs = 0x114,
1932 .mode_ofs = 0x284,
1933 .length_ofs = 0x288,
1934 .major_mask = 0x0700,
1935 .major_shift = 8,
1936 .minor_mask = 0x003f,
1937 .minor_shift = 0,
1938 };
1939
1940 static const struct of_device_id omap_sham_of_match[] = {
1941 {
1942 .compatible = "ti,omap2-sham",
1943 .data = &omap_sham_pdata_omap2,
1944 },
1945 {
1946 .compatible = "ti,omap3-sham",
1947 .data = &omap_sham_pdata_omap2,
1948 },
1949 {
1950 .compatible = "ti,omap4-sham",
1951 .data = &omap_sham_pdata_omap4,
1952 },
1953 {
1954 .compatible = "ti,omap5-sham",
1955 .data = &omap_sham_pdata_omap5,
1956 },
1957 {},
1958 };
1959 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1960
1961 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1962 struct device *dev, struct resource *res)
1963 {
1964 struct device_node *node = dev->of_node;
1965 int err = 0;
1966
1967 dd->pdata = of_device_get_match_data(dev);
1968 if (!dd->pdata) {
1969 dev_err(dev, "no compatible OF match\n");
1970 err = -EINVAL;
1971 goto err;
1972 }
1973
1974 err = of_address_to_resource(node, 0, res);
1975 if (err < 0) {
1976 dev_err(dev, "can't translate OF node address\n");
1977 err = -EINVAL;
1978 goto err;
1979 }
1980
1981 dd->irq = irq_of_parse_and_map(node, 0);
1982 if (!dd->irq) {
1983 dev_err(dev, "can't translate OF irq value\n");
1984 err = -EINVAL;
1985 goto err;
1986 }
1987
1988 err:
1989 return err;
1990 }
1991 #else
1992 static const struct of_device_id omap_sham_of_match[] = {
1993 {},
1994 };
1995
1996 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1997 struct device *dev, struct resource *res)
1998 {
1999 return -EINVAL;
2000 }
2001 #endif
2002
2003 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
2004 struct platform_device *pdev, struct resource *res)
2005 {
2006 struct device *dev = &pdev->dev;
2007 struct resource *r;
2008 int err = 0;
2009
2010 /* Get the base address */
2011 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2012 if (!r) {
2013 dev_err(dev, "no MEM resource info\n");
2014 err = -ENODEV;
2015 goto err;
2016 }
2017 memcpy(res, r, sizeof(*res));
2018
2019 /* Get the IRQ */
2020 dd->irq = platform_get_irq(pdev, 0);
2021 if (dd->irq < 0) {
2022 err = dd->irq;
2023 goto err;
2024 }
2025
2026 /* Only OMAP2/3 can be non-DT */
2027 dd->pdata = &omap_sham_pdata_omap2;
2028
2029 err:
2030 return err;
2031 }
2032
2033 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2034 char *buf)
2035 {
2036 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2037
2038 return sprintf(buf, "%d\n", dd->fallback_sz);
2039 }
2040
2041 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2042 const char *buf, size_t size)
2043 {
2044 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2045 ssize_t status;
2046 long value;
2047
2048 status = kstrtol(buf, 0, &value);
2049 if (status)
2050 return status;
2051
2052 /* HW accelerator only works with buffers > 9 */
2053 if (value < 9) {
2054 dev_err(dev, "minimum fallback size 9\n");
2055 return -EINVAL;
2056 }
2057
2058 dd->fallback_sz = value;
2059
2060 return size;
2061 }
2062
2063 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2064 char *buf)
2065 {
2066 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2067
2068 return sprintf(buf, "%d\n", dd->queue.max_qlen);
2069 }
2070
2071 static ssize_t queue_len_store(struct device *dev,
2072 struct device_attribute *attr, const char *buf,
2073 size_t size)
2074 {
2075 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2076 ssize_t status;
2077 long value;
2078 unsigned long flags;
2079
2080 status = kstrtol(buf, 0, &value);
2081 if (status)
2082 return status;
2083
2084 if (value < 1)
2085 return -EINVAL;
2086
2087 /*
2088 * Changing the queue size in fly is safe, if size becomes smaller
2089 * than current size, it will just not accept new entries until
2090 * it has shrank enough.
2091 */
2092 spin_lock_irqsave(&dd->lock, flags);
2093 dd->queue.max_qlen = value;
2094 spin_unlock_irqrestore(&dd->lock, flags);
2095
2096 return size;
2097 }
2098
2099 static DEVICE_ATTR_RW(queue_len);
2100 static DEVICE_ATTR_RW(fallback);
2101
2102 static struct attribute *omap_sham_attrs[] = {
2103 &dev_attr_queue_len.attr,
2104 &dev_attr_fallback.attr,
2105 NULL,
2106 };
2107
2108 static struct attribute_group omap_sham_attr_group = {
2109 .attrs = omap_sham_attrs,
2110 };
2111
2112 static int omap_sham_probe(struct platform_device *pdev)
2113 {
2114 struct omap_sham_dev *dd;
2115 struct device *dev = &pdev->dev;
2116 struct resource res;
2117 dma_cap_mask_t mask;
2118 int err, i, j;
2119 u32 rev;
2120
2121 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2122 if (dd == NULL) {
2123 dev_err(dev, "unable to alloc data struct.\n");
2124 err = -ENOMEM;
2125 goto data_err;
2126 }
2127 dd->dev = dev;
2128 platform_set_drvdata(pdev, dd);
2129
2130 INIT_LIST_HEAD(&dd->list);
2131 spin_lock_init(&dd->lock);
2132 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2133 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2134
2135 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2136 omap_sham_get_res_pdev(dd, pdev, &res);
2137 if (err)
2138 goto data_err;
2139
2140 dd->io_base = devm_ioremap_resource(dev, &res);
2141 if (IS_ERR(dd->io_base)) {
2142 err = PTR_ERR(dd->io_base);
2143 goto data_err;
2144 }
2145 dd->phys_base = res.start;
2146
2147 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2148 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2149 if (err) {
2150 dev_err(dev, "unable to request irq %d, err = %d\n",
2151 dd->irq, err);
2152 goto data_err;
2153 }
2154
2155 dma_cap_zero(mask);
2156 dma_cap_set(DMA_SLAVE, mask);
2157
2158 dd->dma_lch = dma_request_chan(dev, "rx");
2159 if (IS_ERR(dd->dma_lch)) {
2160 err = PTR_ERR(dd->dma_lch);
2161 if (err == -EPROBE_DEFER)
2162 goto data_err;
2163
2164 dd->polling_mode = 1;
2165 dev_dbg(dev, "using polling mode instead of dma\n");
2166 }
2167
2168 dd->flags |= dd->pdata->flags;
2169 sham.flags |= dd->pdata->flags;
2170
2171 pm_runtime_use_autosuspend(dev);
2172 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2173
2174 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2175
2176 pm_runtime_enable(dev);
2177 pm_runtime_irq_safe(dev);
2178
2179 err = pm_runtime_get_sync(dev);
2180 if (err < 0) {
2181 dev_err(dev, "failed to get sync: %d\n", err);
2182 goto err_pm;
2183 }
2184
2185 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2186 pm_runtime_put_sync(&pdev->dev);
2187
2188 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2189 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2190 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2191
2192 spin_lock(&sham.lock);
2193 list_add_tail(&dd->list, &sham.dev_list);
2194 spin_unlock(&sham.lock);
2195
2196 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2197 if (dd->pdata->algs_info[i].registered)
2198 break;
2199
2200 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2201 struct ahash_alg *alg;
2202
2203 alg = &dd->pdata->algs_info[i].algs_list[j];
2204 alg->export = omap_sham_export;
2205 alg->import = omap_sham_import;
2206 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2207 BUFLEN;
2208 err = crypto_register_ahash(alg);
2209 if (err)
2210 goto err_algs;
2211
2212 dd->pdata->algs_info[i].registered++;
2213 }
2214 }
2215
2216 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2217 if (err) {
2218 dev_err(dev, "could not create sysfs device attrs\n");
2219 goto err_algs;
2220 }
2221
2222 return 0;
2223
2224 err_algs:
2225 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2226 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2227 crypto_unregister_ahash(
2228 &dd->pdata->algs_info[i].algs_list[j]);
2229 err_pm:
2230 pm_runtime_disable(dev);
2231 if (!dd->polling_mode)
2232 dma_release_channel(dd->dma_lch);
2233 data_err:
2234 dev_err(dev, "initialization failed.\n");
2235
2236 return err;
2237 }
2238
2239 static int omap_sham_remove(struct platform_device *pdev)
2240 {
2241 struct omap_sham_dev *dd;
2242 int i, j;
2243
2244 dd = platform_get_drvdata(pdev);
2245 if (!dd)
2246 return -ENODEV;
2247 spin_lock(&sham.lock);
2248 list_del(&dd->list);
2249 spin_unlock(&sham.lock);
2250 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2251 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2252 crypto_unregister_ahash(
2253 &dd->pdata->algs_info[i].algs_list[j]);
2254 dd->pdata->algs_info[i].registered--;
2255 }
2256 tasklet_kill(&dd->done_task);
2257 pm_runtime_disable(&pdev->dev);
2258
2259 if (!dd->polling_mode)
2260 dma_release_channel(dd->dma_lch);
2261
2262 sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group);
2263
2264 return 0;
2265 }
2266
2267 #ifdef CONFIG_PM_SLEEP
2268 static int omap_sham_suspend(struct device *dev)
2269 {
2270 pm_runtime_put_sync(dev);
2271 return 0;
2272 }
2273
2274 static int omap_sham_resume(struct device *dev)
2275 {
2276 int err = pm_runtime_get_sync(dev);
2277 if (err < 0) {
2278 dev_err(dev, "failed to get sync: %d\n", err);
2279 return err;
2280 }
2281 return 0;
2282 }
2283 #endif
2284
2285 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2286
2287 static struct platform_driver omap_sham_driver = {
2288 .probe = omap_sham_probe,
2289 .remove = omap_sham_remove,
2290 .driver = {
2291 .name = "omap-sham",
2292 .pm = &omap_sham_pm_ops,
2293 .of_match_table = omap_sham_of_match,
2294 },
2295 };
2296
2297 module_platform_driver(omap_sham_driver);
2298
2299 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2300 MODULE_LICENSE("GPL v2");
2301 MODULE_AUTHOR("Dmitry Kasatkin");
2302 MODULE_ALIAS("platform:omap-sham");
Linux with added FPC-III support