?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / edac / skx_base.c
bloba51954bc488ce88405391571d302005e9f187089
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * EDAC driver for Intel(R) Xeon(R) Skylake processors
4 * Copyright (c) 2016, Intel Corporation.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/processor.h>
9 #include <asm/cpu_device_id.h>
10 #include <asm/intel-family.h>
11 #include <asm/mce.h>
12
13 #include "edac_module.h"
14 #include "skx_common.h"
15
16 #define EDAC_MOD_STR "skx_edac"
17
18 /*
19 * Debug macros
20 */
21 #define skx_printk(level, fmt, arg...) \
22 edac_printk(level, "skx", fmt, ##arg)
23
24 #define skx_mc_printk(mci, level, fmt, arg...) \
25 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
26
27 static struct list_head *skx_edac_list;
28
29 static u64 skx_tolm, skx_tohm;
30 static int skx_num_sockets;
31 static unsigned int nvdimm_count;
32
33 #define MASK26 0x3FFFFFF /* Mask for 2^26 */
34 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
35
36 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
37 {
38 struct skx_dev *d;
39
40 list_for_each_entry(d, skx_edac_list, list) {
41 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
42 return d;
43 }
44
45 return NULL;
46 }
47
48 enum munittype {
49 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD,
50 ERRCHAN0, ERRCHAN1, ERRCHAN2,
51 };
52
53 struct munit {
54 u16 did;
55 u16 devfn[SKX_NUM_IMC];
56 u8 busidx;
57 u8 per_socket;
58 enum munittype mtype;
59 };
60
61 /*
62 * List of PCI device ids that we need together with some device
63 * number and function numbers to tell which memory controller the
64 * device belongs to.
65 */
66 static const struct munit skx_all_munits[] = {
67 { 0x2054, { }, 1, 1, SAD_ALL },
68 { 0x2055, { }, 1, 1, UTIL_ALL },
69 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
70 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
71 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
72 { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 },
73 { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 },
74 { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 },
75 { 0x208e, { }, 1, 0, SAD },
76 { }
77 };
78
79 static int get_all_munits(const struct munit *m)
80 {
81 struct pci_dev *pdev, *prev;
82 struct skx_dev *d;
83 u32 reg;
84 int i = 0, ndev = 0;
85
86 prev = NULL;
87 for (;;) {
88 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
89 if (!pdev)
90 break;
91 ndev++;
92 if (m->per_socket == SKX_NUM_IMC) {
93 for (i = 0; i < SKX_NUM_IMC; i++)
94 if (m->devfn[i] == pdev->devfn)
95 break;
96 if (i == SKX_NUM_IMC)
97 goto fail;
98 }
99 d = get_skx_dev(pdev->bus, m->busidx);
100 if (!d)
101 goto fail;
102
103 /* Be sure that the device is enabled */
104 if (unlikely(pci_enable_device(pdev) < 0)) {
105 skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n",
106 PCI_VENDOR_ID_INTEL, m->did);
107 goto fail;
108 }
109
110 switch (m->mtype) {
111 case CHAN0:
112 case CHAN1:
113 case CHAN2:
114 pci_dev_get(pdev);
115 d->imc[i].chan[m->mtype].cdev = pdev;
116 break;
117 case ERRCHAN0:
118 case ERRCHAN1:
119 case ERRCHAN2:
120 pci_dev_get(pdev);
121 d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev;
122 break;
123 case SAD_ALL:
124 pci_dev_get(pdev);
125 d->sad_all = pdev;
126 break;
127 case UTIL_ALL:
128 pci_dev_get(pdev);
129 d->util_all = pdev;
130 break;
131 case SAD:
132 /*
133 * one of these devices per core, including cores
134 * that don't exist on this SKU. Ignore any that
135 * read a route table of zero, make sure all the
136 * non-zero values match.
137 */
138 pci_read_config_dword(pdev, 0xB4, &reg);
139 if (reg != 0) {
140 if (d->mcroute == 0) {
141 d->mcroute = reg;
142 } else if (d->mcroute != reg) {
143 skx_printk(KERN_ERR, "mcroute mismatch\n");
144 goto fail;
145 }
146 }
147 ndev--;
148 break;
149 }
150
151 prev = pdev;
152 }
153
154 return ndev;
155 fail:
156 pci_dev_put(pdev);
157 return -ENODEV;
158 }
159
160 static const struct x86_cpu_id skx_cpuids[] = {
161 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
162 { }
163 };
164 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
165
166 static bool skx_check_ecc(u32 mcmtr)
167 {
168 return !!GET_BITFIELD(mcmtr, 2, 2);
169 }
170
171 static int skx_get_dimm_config(struct mem_ctl_info *mci)
172 {
173 struct skx_pvt *pvt = mci->pvt_info;
174 u32 mtr, mcmtr, amap, mcddrtcfg;
175 struct skx_imc *imc = pvt->imc;
176 struct dimm_info *dimm;
177 int i, j;
178 int ndimms;
179
180 /* Only the mcmtr on the first channel is effective */
181 pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr);
182
183 for (i = 0; i < SKX_NUM_CHANNELS; i++) {
184 ndimms = 0;
185 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
186 pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
187 for (j = 0; j < SKX_NUM_DIMMS; j++) {
188 dimm = edac_get_dimm(mci, i, j, 0);
189 pci_read_config_dword(imc->chan[i].cdev,
190 0x80 + 4 * j, &mtr);
191 if (IS_DIMM_PRESENT(mtr)) {
192 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j);
193 } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
194 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
195 EDAC_MOD_STR);
196 nvdimm_count++;
197 }
198 }
199 if (ndimms && !skx_check_ecc(mcmtr)) {
200 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
201 return -ENODEV;
202 }
203 }
204
205 return 0;
206 }
207
208 #define SKX_MAX_SAD 24
209
210 #define SKX_GET_SAD(d, i, reg) \
211 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg))
212 #define SKX_GET_ILV(d, i, reg) \
213 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg))
214
215 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
216 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
217 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
218 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
219 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
220 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
221 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
222
223 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
224 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
225
226 static void skx_show_retry_rd_err_log(struct decoded_addr *res,
227 char *msg, int len)
228 {
229 u32 log0, log1, log2, log3, log4;
230 u32 corr0, corr1, corr2, corr3;
231 struct pci_dev *edev;
232 int n;
233
234 edev = res->dev->imc[res->imc].chan[res->channel].edev;
235
236 pci_read_config_dword(edev, 0x154, &log0);
237 pci_read_config_dword(edev, 0x148, &log1);
238 pci_read_config_dword(edev, 0x150, &log2);
239 pci_read_config_dword(edev, 0x15c, &log3);
240 pci_read_config_dword(edev, 0x114, &log4);
241
242 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]",
243 log0, log1, log2, log3, log4);
244
245 pci_read_config_dword(edev, 0x104, &corr0);
246 pci_read_config_dword(edev, 0x108, &corr1);
247 pci_read_config_dword(edev, 0x10c, &corr2);
248 pci_read_config_dword(edev, 0x110, &corr3);
249
250 if (len - n > 0)
251 snprintf(msg + n, len - n,
252 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
253 corr0 & 0xffff, corr0 >> 16,
254 corr1 & 0xffff, corr1 >> 16,
255 corr2 & 0xffff, corr2 >> 16,
256 corr3 & 0xffff, corr3 >> 16);
257 }
258
259 static bool skx_sad_decode(struct decoded_addr *res)
260 {
261 struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list);
262 u64 addr = res->addr;
263 int i, idx, tgt, lchan, shift;
264 u32 sad, ilv;
265 u64 limit, prev_limit;
266 int remote = 0;
267
268 /* Simple sanity check for I/O space or out of range */
269 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
270 edac_dbg(0, "Address 0x%llx out of range\n", addr);
271 return false;
272 }
273
274 restart:
275 prev_limit = 0;
276 for (i = 0; i < SKX_MAX_SAD; i++) {
277 SKX_GET_SAD(d, i, sad);
278 limit = SKX_SAD_LIMIT(sad);
279 if (SKX_SAD_ENABLE(sad)) {
280 if (addr >= prev_limit && addr <= limit)
281 goto sad_found;
282 }
283 prev_limit = limit + 1;
284 }
285 edac_dbg(0, "No SAD entry for 0x%llx\n", addr);
286 return false;
287
288 sad_found:
289 SKX_GET_ILV(d, i, ilv);
290
291 switch (SKX_SAD_INTERLEAVE(sad)) {
292 case 0:
293 idx = GET_BITFIELD(addr, 6, 8);
294 break;
295 case 1:
296 idx = GET_BITFIELD(addr, 8, 10);
297 break;
298 case 2:
299 idx = GET_BITFIELD(addr, 12, 14);
300 break;
301 case 3:
302 idx = GET_BITFIELD(addr, 30, 32);
303 break;
304 }
305
306 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
307
308 /* If point to another node, find it and start over */
309 if (SKX_ILV_REMOTE(tgt)) {
310 if (remote) {
311 edac_dbg(0, "Double remote!\n");
312 return false;
313 }
314 remote = 1;
315 list_for_each_entry(d, skx_edac_list, list) {
316 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
317 goto restart;
318 }
319 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
320 return false;
321 }
322
323 if (SKX_SAD_MOD3(sad) == 0) {
324 lchan = SKX_ILV_TARGET(tgt);
325 } else {
326 switch (SKX_SAD_MOD3MODE(sad)) {
327 case 0:
328 shift = 6;
329 break;
330 case 1:
331 shift = 8;
332 break;
333 case 2:
334 shift = 12;
335 break;
336 default:
337 edac_dbg(0, "illegal mod3mode\n");
338 return false;
339 }
340 switch (SKX_SAD_MOD3ASMOD2(sad)) {
341 case 0:
342 lchan = (addr >> shift) % 3;
343 break;
344 case 1:
345 lchan = (addr >> shift) % 2;
346 break;
347 case 2:
348 lchan = (addr >> shift) % 2;
349 lchan = (lchan << 1) | !lchan;
350 break;
351 case 3:
352 lchan = ((addr >> shift) % 2) << 1;
353 break;
354 }
355 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
356 }
357
358 res->dev = d;
359 res->socket = d->imc[0].src_id;
360 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
361 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
362
363 edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n",
364 res->addr, res->socket, res->imc, res->channel);
365 return true;
366 }
367
368 #define SKX_MAX_TAD 8
369
370 #define SKX_GET_TADBASE(d, mc, i, reg) \
371 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg))
372 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
373 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg))
374 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
375 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg))
376
377 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
378 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
379 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
380 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
381 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
382 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
383 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
384
385 /* which bit used for both socket and channel interleave */
386 static int skx_granularity[] = { 6, 8, 12, 30 };
387
388 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
389 {
390 addr >>= shift;
391 addr /= ways;
392 addr <<= shift;
393
394 return addr | (lowbits & ((1ull << shift) - 1));
395 }
396
397 static bool skx_tad_decode(struct decoded_addr *res)
398 {
399 int i;
400 u32 base, wayness, chnilvoffset;
401 int skt_interleave_bit, chn_interleave_bit;
402 u64 channel_addr;
403
404 for (i = 0; i < SKX_MAX_TAD; i++) {
405 SKX_GET_TADBASE(res->dev, res->imc, i, base);
406 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
407 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
408 goto tad_found;
409 }
410 edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr);
411 return false;
412
413 tad_found:
414 res->sktways = SKX_TAD_SKTWAYS(wayness);
415 res->chanways = SKX_TAD_CHNWAYS(wayness);
416 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
417 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
418
419 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
420 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
421
422 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
423 /* Must handle channel first, then socket */
424 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
425 res->chanways, channel_addr);
426 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
427 res->sktways, channel_addr);
428 } else {
429 /* Handle socket then channel. Preserve low bits from original address */
430 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
431 res->sktways, res->addr);
432 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
433 res->chanways, res->addr);
434 }
435
436 res->chan_addr = channel_addr;
437
438 edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n",
439 res->addr, res->chan_addr, res->sktways, res->chanways);
440 return true;
441 }
442
443 #define SKX_MAX_RIR 4
444
445 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
446 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
447 0x108 + 4 * (i), &(reg))
448 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
449 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
450 0x120 + 16 * (idx) + 4 * (i), &(reg))
451
452 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
453 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
454 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
455 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
456 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
457
458 static bool skx_rir_decode(struct decoded_addr *res)
459 {
460 int i, idx, chan_rank;
461 int shift;
462 u32 rirway, rirlv;
463 u64 rank_addr, prev_limit = 0, limit;
464
465 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
466 shift = 6;
467 else
468 shift = 13;
469
470 for (i = 0; i < SKX_MAX_RIR; i++) {
471 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
472 limit = SKX_RIR_LIMIT(rirway);
473 if (SKX_RIR_VALID(rirway)) {
474 if (prev_limit <= res->chan_addr &&
475 res->chan_addr <= limit)
476 goto rir_found;
477 }
478 prev_limit = limit;
479 }
480 edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr);
481 return false;
482
483 rir_found:
484 rank_addr = res->chan_addr >> shift;
485 rank_addr /= SKX_RIR_WAYS(rirway);
486 rank_addr <<= shift;
487 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
488
489 res->rank_address = rank_addr;
490 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
491
492 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
493 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
494 chan_rank = SKX_RIR_CHAN_RANK(rirlv);
495 res->channel_rank = chan_rank;
496 res->dimm = chan_rank / 4;
497 res->rank = chan_rank % 4;
498
499 edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n",
500 res->addr, res->dimm, res->rank,
501 res->channel_rank, res->rank_address);
502 return true;
503 }
504
505 static u8 skx_close_row[] = {
506 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
507 };
508
509 static u8 skx_close_column[] = {
510 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
511 };
512
513 static u8 skx_open_row[] = {
514 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
515 };
516
517 static u8 skx_open_column[] = {
518 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
519 };
520
521 static u8 skx_open_fine_column[] = {
522 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
523 };
524
525 static int skx_bits(u64 addr, int nbits, u8 *bits)
526 {
527 int i, res = 0;
528
529 for (i = 0; i < nbits; i++)
530 res |= ((addr >> bits[i]) & 1) << i;
531 return res;
532 }
533
534 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
535 {
536 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
537
538 if (do_xor)
539 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
540
541 return ret;
542 }
543
544 static bool skx_mad_decode(struct decoded_addr *r)
545 {
546 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
547 int bg0 = dimm->fine_grain_bank ? 6 : 13;
548
549 if (dimm->close_pg) {
550 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
551 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
552 r->column |= 0x400; /* C10 is autoprecharge, always set */
553 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
554 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
555 } else {
556 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
557 if (dimm->fine_grain_bank)
558 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
559 else
560 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
561 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
562 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
563 }
564 r->row &= (1u << dimm->rowbits) - 1;
565
566 edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n",
567 r->addr, r->row, r->column, r->bank_address,
568 r->bank_group);
569 return true;
570 }
571
572 static bool skx_decode(struct decoded_addr *res)
573 {
574 return skx_sad_decode(res) && skx_tad_decode(res) &&
575 skx_rir_decode(res) && skx_mad_decode(res);
576 }
577
578 static struct notifier_block skx_mce_dec = {
579 .notifier_call = skx_mce_check_error,
580 .priority = MCE_PRIO_EDAC,
581 };
582
583 #ifdef CONFIG_EDAC_DEBUG
584 /*
585 * Debug feature.
586 * Exercise the address decode logic by writing an address to
587 * /sys/kernel/debug/edac/skx_test/addr.
588 */
589 static struct dentry *skx_test;
590
591 static int debugfs_u64_set(void *data, u64 val)
592 {
593 struct mce m;
594
595 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
596
597 memset(&m, 0, sizeof(m));
598 /* ADDRV + MemRd + Unknown channel */
599 m.status = MCI_STATUS_ADDRV + 0x90;
600 /* One corrected error */
601 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
602 m.addr = val;
603 skx_mce_check_error(NULL, 0, &m);
604
605 return 0;
606 }
607 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
608
609 static void setup_skx_debug(void)
610 {
611 skx_test = edac_debugfs_create_dir("skx_test");
612 if (!skx_test)
613 return;
614
615 if (!edac_debugfs_create_file("addr", 0200, skx_test,
616 NULL, &fops_u64_wo)) {
617 debugfs_remove(skx_test);
618 skx_test = NULL;
619 }
620 }
621
622 static void teardown_skx_debug(void)
623 {
624 debugfs_remove_recursive(skx_test);
625 }
626 #else
627 static inline void setup_skx_debug(void) {}
628 static inline void teardown_skx_debug(void) {}
629 #endif /*CONFIG_EDAC_DEBUG*/
630
631 /*
632 * skx_init:
633 * make sure we are running on the correct cpu model
634 * search for all the devices we need
635 * check which DIMMs are present.
636 */
637 static int __init skx_init(void)
638 {
639 const struct x86_cpu_id *id;
640 const struct munit *m;
641 const char *owner;
642 int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
643 u8 mc = 0, src_id, node_id;
644 struct skx_dev *d;
645
646 edac_dbg(2, "\n");
647
648 owner = edac_get_owner();
649 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
650 return -EBUSY;
651
652 id = x86_match_cpu(skx_cpuids);
653 if (!id)
654 return -ENODEV;
655
656 rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm);
657 if (rc)
658 return rc;
659
660 rc = skx_get_all_bus_mappings(0x2016, 0xcc, SKX, &skx_edac_list);
661 if (rc < 0)
662 goto fail;
663 if (rc == 0) {
664 edac_dbg(2, "No memory controllers found\n");
665 return -ENODEV;
666 }
667 skx_num_sockets = rc;
668
669 for (m = skx_all_munits; m->did; m++) {
670 rc = get_all_munits(m);
671 if (rc < 0)
672 goto fail;
673 if (rc != m->per_socket * skx_num_sockets) {
674 edac_dbg(2, "Expected %d, got %d of 0x%x\n",
675 m->per_socket * skx_num_sockets, rc, m->did);
676 rc = -ENODEV;
677 goto fail;
678 }
679 }
680
681 list_for_each_entry(d, skx_edac_list, list) {
682 rc = skx_get_src_id(d, 0xf0, &src_id);
683 if (rc < 0)
684 goto fail;
685 rc = skx_get_node_id(d, &node_id);
686 if (rc < 0)
687 goto fail;
688 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
689 for (i = 0; i < SKX_NUM_IMC; i++) {
690 d->imc[i].mc = mc++;
691 d->imc[i].lmc = i;
692 d->imc[i].src_id = src_id;
693 d->imc[i].node_id = node_id;
694 rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
695 "Skylake Socket", EDAC_MOD_STR,
696 skx_get_dimm_config);
697 if (rc < 0)
698 goto fail;
699 }
700 }
701
702 skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
703
704 if (nvdimm_count && skx_adxl_get() == -ENODEV)
705 skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n");
706
707 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
708 opstate_init();
709
710 setup_skx_debug();
711
712 mce_register_decode_chain(&skx_mce_dec);
713
714 return 0;
715 fail:
716 skx_remove();
717 return rc;
718 }
719
720 static void __exit skx_exit(void)
721 {
722 edac_dbg(2, "\n");
723 mce_unregister_decode_chain(&skx_mce_dec);
724 teardown_skx_debug();
725 if (nvdimm_count)
726 skx_adxl_put();
727 skx_remove();
728 }
729
730 module_init(skx_init);
731 module_exit(skx_exit);
732
733 module_param(edac_op_state, int, 0444);
734 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
735
736 MODULE_LICENSE("GPL v2");
737 MODULE_AUTHOR("Tony Luck");
738 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
Linux with added FPC-III support