drivers/iio/adc/ad7124.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7124 SPI ADC driver
   4  *
   5  * Copyright 2018 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/spi/spi.h>
  17
  18 #include <linux/iio/iio.h>
  19 #include <linux/iio/adc/ad_sigma_delta.h>
  20 #include <linux/iio/sysfs.h>
  21
  22 /* AD7124 registers */
  23 #define AD7124_COMMS                    0x00
  24 #define AD7124_STATUS                   0x00
  25 #define AD7124_ADC_CONTROL              0x01
  26 #define AD7124_DATA                     0x02
  27 #define AD7124_IO_CONTROL_1             0x03
  28 #define AD7124_IO_CONTROL_2             0x04
  29 #define AD7124_ID                       0x05
  30 #define AD7124_ERROR                    0x06
  31 #define AD7124_ERROR_EN         0x07
  32 #define AD7124_MCLK_COUNT               0x08
  33 #define AD7124_CHANNEL(x)               (0x09 + (x))
  34 #define AD7124_CONFIG(x)                (0x19 + (x))
  35 #define AD7124_FILTER(x)                (0x21 + (x))
  36 #define AD7124_OFFSET(x)                (0x29 + (x))
  37 #define AD7124_GAIN(x)                  (0x31 + (x))
  38
  39 /* AD7124_STATUS */
  40 #define AD7124_STATUS_POR_FLAG_MSK      BIT(4)
  41
  42 /* AD7124_ADC_CONTROL */
  43 #define AD7124_ADC_CTRL_REF_EN_MSK      BIT(8)
  44 #define AD7124_ADC_CTRL_REF_EN(x)       FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
  45 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  46 #define AD7124_ADC_CTRL_PWR(x)          FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  47 #define AD7124_ADC_CTRL_MODE_MSK        GENMASK(5, 2)
  48 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  49
  50 /* AD7124_CHANNEL_X */
  51 #define AD7124_CHANNEL_EN_MSK           BIT(15)
  52 #define AD7124_CHANNEL_EN(x)            FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  53 #define AD7124_CHANNEL_SETUP_MSK        GENMASK(14, 12)
  54 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  55 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  56 #define AD7124_CHANNEL_AINP(x)          FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  57 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  58 #define AD7124_CHANNEL_AINM(x)          FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  59
  60 /* AD7124_CONFIG_X */
  61 #define AD7124_CONFIG_BIPOLAR_MSK       BIT(11)
  62 #define AD7124_CONFIG_BIPOLAR(x)        FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  63 #define AD7124_CONFIG_REF_SEL_MSK       GENMASK(4, 3)
  64 #define AD7124_CONFIG_REF_SEL(x)        FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  65 #define AD7124_CONFIG_PGA_MSK           GENMASK(2, 0)
  66 #define AD7124_CONFIG_PGA(x)            FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  67 #define AD7124_CONFIG_IN_BUFF_MSK       GENMASK(7, 6)
  68 #define AD7124_CONFIG_IN_BUFF(x)        FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
  69
  70 /* AD7124_FILTER_X */
  71 #define AD7124_FILTER_FS_MSK            GENMASK(10, 0)
  72 #define AD7124_FILTER_FS(x)             FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  73 #define AD7124_FILTER_TYPE_MSK          GENMASK(23, 21)
  74 #define AD7124_FILTER_TYPE_SEL(x)       FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
  75
  76 #define AD7124_SINC3_FILTER 2
  77 #define AD7124_SINC4_FILTER 0
  78
  79 enum ad7124_ids {
  80         ID_AD7124_4,
  81         ID_AD7124_8,
  82 };
  83
  84 enum ad7124_ref_sel {
  85         AD7124_REFIN1,
  86         AD7124_REFIN2,
  87         AD7124_INT_REF,
  88         AD7124_AVDD_REF,
  89 };
  90
  91 enum ad7124_power_mode {
  92         AD7124_LOW_POWER,
  93         AD7124_MID_POWER,
  94         AD7124_FULL_POWER,
  95 };
  96
  97 static const unsigned int ad7124_gain[8] = {
  98         1, 2, 4, 8, 16, 32, 64, 128
  99 };
 100
 101 static const unsigned int ad7124_reg_size[] = {
 102         1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
 103         2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
 104         2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
 105         3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
 106         3, 3, 3, 3, 3
 107 };
 108
 109 static const int ad7124_master_clk_freq_hz[3] = {
 110         [AD7124_LOW_POWER] = 76800,
 111         [AD7124_MID_POWER] = 153600,
 112         [AD7124_FULL_POWER] = 614400,
 113 };
 114
 115 static const char * const ad7124_ref_names[] = {
 116         [AD7124_REFIN1] = "refin1",
 117         [AD7124_REFIN2] = "refin2",
 118         [AD7124_INT_REF] = "int",
 119         [AD7124_AVDD_REF] = "avdd",
 120 };
 121
 122 struct ad7124_chip_info {
 123         unsigned int num_inputs;
 124 };
 125
 126 struct ad7124_channel_config {
 127         enum ad7124_ref_sel refsel;
 128         bool bipolar;
 129         bool buf_positive;
 130         bool buf_negative;
 131         unsigned int ain;
 132         unsigned int vref_mv;
 133         unsigned int pga_bits;
 134         unsigned int odr;
 135         unsigned int filter_type;
 136 };
 137
 138 struct ad7124_state {
 139         const struct ad7124_chip_info *chip_info;
 140         struct ad_sigma_delta sd;
 141         struct ad7124_channel_config *channel_config;
 142         struct regulator *vref[4];
 143         struct clk *mclk;
 144         unsigned int adc_control;
 145         unsigned int num_channels;
 146 };
 147
 148 static const struct iio_chan_spec ad7124_channel_template = {
 149         .type = IIO_VOLTAGE,
 150         .indexed = 1,
 151         .differential = 1,
 152         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 153                 BIT(IIO_CHAN_INFO_SCALE) |
 154                 BIT(IIO_CHAN_INFO_OFFSET) |
 155                 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
 156                 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
 157         .scan_type = {
 158                 .sign = 'u',
 159                 .realbits = 24,
 160                 .storagebits = 32,
 161                 .shift = 8,
 162                 .endianness = IIO_BE,
 163         },
 164 };
 165
 166 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
 167         [ID_AD7124_4] = {
 168                 .num_inputs = 8,
 169         },
 170         [ID_AD7124_8] = {
 171                 .num_inputs = 16,
 172         },
 173 };
 174
 175 static int ad7124_find_closest_match(const int *array,
 176                                      unsigned int size, int val)
 177 {
 178         int i, idx;
 179         unsigned int diff_new, diff_old;
 180
 181         diff_old = U32_MAX;
 182         idx = 0;
 183
 184         for (i = 0; i < size; i++) {
 185                 diff_new = abs(val - array[i]);
 186                 if (diff_new < diff_old) {
 187                         diff_old = diff_new;
 188                         idx = i;
 189                 }
 190         }
 191
 192         return idx;
 193 }
 194
 195 static int ad7124_spi_write_mask(struct ad7124_state *st,
 196                                  unsigned int addr,
 197                                  unsigned long mask,
 198                                  unsigned int val,
 199                                  unsigned int bytes)
 200 {
 201         unsigned int readval;
 202         int ret;
 203
 204         ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
 205         if (ret < 0)
 206                 return ret;
 207
 208         readval &= ~mask;
 209         readval |= val;
 210
 211         return ad_sd_write_reg(&st->sd, addr, bytes, readval);
 212 }
 213
 214 static int ad7124_set_mode(struct ad_sigma_delta *sd,
 215                            enum ad_sigma_delta_mode mode)
 216 {
 217         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 218
 219         st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
 220         st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
 221
 222         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 223 }
 224
 225 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 226 {
 227         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 228         unsigned int val;
 229
 230         val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
 231               AD7124_CHANNEL_SETUP(channel);
 232
 233         return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
 234 }
 235
 236 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
 237         .set_channel = ad7124_set_channel,
 238         .set_mode = ad7124_set_mode,
 239         .has_registers = true,
 240         .addr_shift = 0,
 241         .read_mask = BIT(6),
 242         .data_reg = AD7124_DATA,
 243         .irq_flags = IRQF_TRIGGER_FALLING,
 244 };
 245
 246 static int ad7124_set_channel_odr(struct ad7124_state *st,
 247                                   unsigned int channel,
 248                                   unsigned int odr)
 249 {
 250         unsigned int fclk, odr_sel_bits;
 251         int ret;
 252
 253         fclk = clk_get_rate(st->mclk);
 254         /*
 255          * FS[10:0] = fCLK / (fADC x 32) where:
 256          * fADC is the output data rate
 257          * fCLK is the master clock frequency
 258          * FS[10:0] are the bits in the filter register
 259          * FS[10:0] can have a value from 1 to 2047
 260          */
 261         odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
 262         if (odr_sel_bits < 1)
 263                 odr_sel_bits = 1;
 264         else if (odr_sel_bits > 2047)
 265                 odr_sel_bits = 2047;
 266
 267         ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 268                                     AD7124_FILTER_FS_MSK,
 269                                     AD7124_FILTER_FS(odr_sel_bits), 3);
 270         if (ret < 0)
 271                 return ret;
 272         /* fADC = fCLK / (FS[10:0] x 32) */
 273         st->channel_config[channel].odr =
 274                 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
 275
 276         return 0;
 277 }
 278
 279 static int ad7124_set_channel_gain(struct ad7124_state *st,
 280                                    unsigned int channel,
 281                                    unsigned int gain)
 282 {
 283         unsigned int res;
 284         int ret;
 285
 286         res = ad7124_find_closest_match(ad7124_gain,
 287                                         ARRAY_SIZE(ad7124_gain), gain);
 288         ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
 289                                     AD7124_CONFIG_PGA_MSK,
 290                                     AD7124_CONFIG_PGA(res), 2);
 291         if (ret < 0)
 292                 return ret;
 293
 294         st->channel_config[channel].pga_bits = res;
 295
 296         return 0;
 297 }
 298
 299 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
 300                                       unsigned int channel)
 301 {
 302         unsigned int fadc;
 303
 304         fadc = st->channel_config[channel].odr;
 305
 306         switch (st->channel_config[channel].filter_type) {
 307         case AD7124_SINC3_FILTER:
 308                 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
 309         case AD7124_SINC4_FILTER:
 310                 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
 311         default:
 312                 return -EINVAL;
 313         }
 314 }
 315
 316 static int ad7124_set_3db_filter_freq(struct ad7124_state *st,
 317                                       unsigned int channel,
 318                                       unsigned int freq)
 319 {
 320         unsigned int sinc4_3db_odr;
 321         unsigned int sinc3_3db_odr;
 322         unsigned int new_filter;
 323         unsigned int new_odr;
 324
 325         sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
 326         sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
 327
 328         if (sinc4_3db_odr > sinc3_3db_odr) {
 329                 new_filter = AD7124_SINC3_FILTER;
 330                 new_odr = sinc4_3db_odr;
 331         } else {
 332                 new_filter = AD7124_SINC4_FILTER;
 333                 new_odr = sinc3_3db_odr;
 334         }
 335
 336         if (st->channel_config[channel].filter_type != new_filter) {
 337                 int ret;
 338
 339                 st->channel_config[channel].filter_type = new_filter;
 340                 ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 341                                             AD7124_FILTER_TYPE_MSK,
 342                                             AD7124_FILTER_TYPE_SEL(new_filter),
 343                                             3);
 344                 if (ret < 0)
 345                         return ret;
 346         }
 347
 348         return ad7124_set_channel_odr(st, channel, new_odr);
 349 }
 350
 351 static int ad7124_read_raw(struct iio_dev *indio_dev,
 352                            struct iio_chan_spec const *chan,
 353                            int *val, int *val2, long info)
 354 {
 355         struct ad7124_state *st = iio_priv(indio_dev);
 356         int idx, ret;
 357
 358         switch (info) {
 359         case IIO_CHAN_INFO_RAW:
 360                 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
 361                 if (ret < 0)
 362                         return ret;
 363
 364                 /* After the conversion is performed, disable the channel */
 365                 ret = ad_sd_write_reg(&st->sd,
 366                                       AD7124_CHANNEL(chan->address), 2,
 367                                       st->channel_config[chan->address].ain |
 368                                       AD7124_CHANNEL_EN(0));
 369                 if (ret < 0)
 370                         return ret;
 371
 372                 return IIO_VAL_INT;
 373         case IIO_CHAN_INFO_SCALE:
 374                 idx = st->channel_config[chan->address].pga_bits;
 375                 *val = st->channel_config[chan->address].vref_mv;
 376                 if (st->channel_config[chan->address].bipolar)
 377                         *val2 = chan->scan_type.realbits - 1 + idx;
 378                 else
 379                         *val2 = chan->scan_type.realbits + idx;
 380
 381                 return IIO_VAL_FRACTIONAL_LOG2;
 382         case IIO_CHAN_INFO_OFFSET:
 383                 if (st->channel_config[chan->address].bipolar)
 384                         *val = -(1 << (chan->scan_type.realbits - 1));
 385                 else
 386                         *val = 0;
 387
 388                 return IIO_VAL_INT;
 389         case IIO_CHAN_INFO_SAMP_FREQ:
 390                 *val = st->channel_config[chan->address].odr;
 391
 392                 return IIO_VAL_INT;
 393         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 394                 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
 395                 return IIO_VAL_INT;
 396         default:
 397                 return -EINVAL;
 398         }
 399 }
 400
 401 static int ad7124_write_raw(struct iio_dev *indio_dev,
 402                             struct iio_chan_spec const *chan,
 403                             int val, int val2, long info)
 404 {
 405         struct ad7124_state *st = iio_priv(indio_dev);
 406         unsigned int res, gain, full_scale, vref;
 407
 408         switch (info) {
 409         case IIO_CHAN_INFO_SAMP_FREQ:
 410                 if (val2 != 0)
 411                         return -EINVAL;
 412
 413                 return ad7124_set_channel_odr(st, chan->address, val);
 414         case IIO_CHAN_INFO_SCALE:
 415                 if (val != 0)
 416                         return -EINVAL;
 417
 418                 if (st->channel_config[chan->address].bipolar)
 419                         full_scale = 1 << (chan->scan_type.realbits - 1);
 420                 else
 421                         full_scale = 1 << chan->scan_type.realbits;
 422
 423                 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
 424                 res = DIV_ROUND_CLOSEST(vref, full_scale);
 425                 gain = DIV_ROUND_CLOSEST(res, val2);
 426
 427                 return ad7124_set_channel_gain(st, chan->address, gain);
 428         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 429                 if (val2 != 0)
 430                         return -EINVAL;
 431
 432                 return ad7124_set_3db_filter_freq(st, chan->address, val);
 433         default:
 434                 return -EINVAL;
 435         }
 436 }
 437
 438 static int ad7124_reg_access(struct iio_dev *indio_dev,
 439                              unsigned int reg,
 440                              unsigned int writeval,
 441                              unsigned int *readval)
 442 {
 443         struct ad7124_state *st = iio_priv(indio_dev);
 444         int ret;
 445
 446         if (reg >= ARRAY_SIZE(ad7124_reg_size))
 447                 return -EINVAL;
 448
 449         if (readval)
 450                 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
 451                                      readval);
 452         else
 453                 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
 454                                       writeval);
 455
 456         return ret;
 457 }
 458
 459 static IIO_CONST_ATTR(in_voltage_scale_available,
 460         "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
 461
 462 static struct attribute *ad7124_attributes[] = {
 463         &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
 464         NULL,
 465 };
 466
 467 static const struct attribute_group ad7124_attrs_group = {
 468         .attrs = ad7124_attributes,
 469 };
 470
 471 static const struct iio_info ad7124_info = {
 472         .read_raw = ad7124_read_raw,
 473         .write_raw = ad7124_write_raw,
 474         .debugfs_reg_access = &ad7124_reg_access,
 475         .validate_trigger = ad_sd_validate_trigger,
 476         .attrs = &ad7124_attrs_group,
 477 };
 478
 479 static int ad7124_soft_reset(struct ad7124_state *st)
 480 {
 481         unsigned int readval, timeout;
 482         int ret;
 483
 484         ret = ad_sd_reset(&st->sd, 64);
 485         if (ret < 0)
 486                 return ret;
 487
 488         timeout = 100;
 489         do {
 490                 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
 491                 if (ret < 0)
 492                         return ret;
 493
 494                 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
 495                         return 0;
 496
 497                 /* The AD7124 requires typically 2ms to power up and settle */
 498                 usleep_range(100, 2000);
 499         } while (--timeout);
 500
 501         dev_err(&st->sd.spi->dev, "Soft reset failed\n");
 502
 503         return -EIO;
 504 }
 505
 506 static int ad7124_init_channel_vref(struct ad7124_state *st,
 507                                     unsigned int channel_number)
 508 {
 509         unsigned int refsel = st->channel_config[channel_number].refsel;
 510
 511         switch (refsel) {
 512         case AD7124_REFIN1:
 513         case AD7124_REFIN2:
 514         case AD7124_AVDD_REF:
 515                 if (IS_ERR(st->vref[refsel])) {
 516                         dev_err(&st->sd.spi->dev,
 517                                 "Error, trying to use external voltage reference without a %s regulator.\n",
 518                                 ad7124_ref_names[refsel]);
 519                         return PTR_ERR(st->vref[refsel]);
 520                 }
 521                 st->channel_config[channel_number].vref_mv =
 522                         regulator_get_voltage(st->vref[refsel]);
 523                 /* Conversion from uV to mV */
 524                 st->channel_config[channel_number].vref_mv /= 1000;
 525                 break;
 526         case AD7124_INT_REF:
 527                 st->channel_config[channel_number].vref_mv = 2500;
 528                 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
 529                 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
 530                 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
 531                                       2, st->adc_control);
 532         default:
 533                 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
 534                 return -EINVAL;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
 541                                           struct device_node *np)
 542 {
 543         struct ad7124_state *st = iio_priv(indio_dev);
 544         struct device_node *child;
 545         struct iio_chan_spec *chan;
 546         struct ad7124_channel_config *chan_config;
 547         unsigned int ain[2], channel = 0, tmp;
 548         int ret;
 549
 550         st->num_channels = of_get_available_child_count(np);
 551         if (!st->num_channels) {
 552                 dev_err(indio_dev->dev.parent, "no channel children\n");
 553                 return -ENODEV;
 554         }
 555
 556         chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 557                             sizeof(*chan), GFP_KERNEL);
 558         if (!chan)
 559                 return -ENOMEM;
 560
 561         chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 562                                    sizeof(*chan_config), GFP_KERNEL);
 563         if (!chan_config)
 564                 return -ENOMEM;
 565
 566         indio_dev->channels = chan;
 567         indio_dev->num_channels = st->num_channels;
 568         st->channel_config = chan_config;
 569
 570         for_each_available_child_of_node(np, child) {
 571                 ret = of_property_read_u32(child, "reg", &channel);
 572                 if (ret)
 573                         goto err;
 574
 575                 ret = of_property_read_u32_array(child, "diff-channels",
 576                                                  ain, 2);
 577                 if (ret)
 578                         goto err;
 579
 580                 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
 581                                                   AD7124_CHANNEL_AINM(ain[1]);
 582                 st->channel_config[channel].bipolar =
 583                         of_property_read_bool(child, "bipolar");
 584
 585                 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
 586                 if (ret)
 587                         st->channel_config[channel].refsel = AD7124_INT_REF;
 588                 else
 589                         st->channel_config[channel].refsel = tmp;
 590
 591                 st->channel_config[channel].buf_positive =
 592                         of_property_read_bool(child, "adi,buffered-positive");
 593                 st->channel_config[channel].buf_negative =
 594                         of_property_read_bool(child, "adi,buffered-negative");
 595
 596                 chan[channel] = ad7124_channel_template;
 597                 chan[channel].address = channel;
 598                 chan[channel].scan_index = channel;
 599                 chan[channel].channel = ain[0];
 600                 chan[channel].channel2 = ain[1];
 601         }
 602
 603         return 0;
 604 err:
 605         of_node_put(child);
 606
 607         return ret;
 608 }
 609
 610 static int ad7124_setup(struct ad7124_state *st)
 611 {
 612         unsigned int val, fclk, power_mode;
 613         int i, ret, tmp;
 614
 615         fclk = clk_get_rate(st->mclk);
 616         if (!fclk)
 617                 return -EINVAL;
 618
 619         /* The power mode changes the master clock frequency */
 620         power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
 621                                         ARRAY_SIZE(ad7124_master_clk_freq_hz),
 622                                         fclk);
 623         if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
 624                 ret = clk_set_rate(st->mclk, fclk);
 625                 if (ret)
 626                         return ret;
 627         }
 628
 629         /* Set the power mode */
 630         st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
 631         st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
 632         ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 633         if (ret < 0)
 634                 return ret;
 635
 636         for (i = 0; i < st->num_channels; i++) {
 637                 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
 638                 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
 639                 if (ret < 0)
 640                         return ret;
 641
 642                 ret = ad7124_init_channel_vref(st, i);
 643                 if (ret < 0)
 644                         return ret;
 645
 646                 tmp = (st->channel_config[i].buf_positive << 1)  +
 647                         st->channel_config[i].buf_negative;
 648
 649                 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
 650                       AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
 651                       AD7124_CONFIG_IN_BUFF(tmp);
 652                 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
 653                 if (ret < 0)
 654                         return ret;
 655                 /*
 656                  * 9.38 SPS is the minimum output data rate supported
 657                  * regardless of the selected power mode. Round it up to 10 and
 658                  * set all the enabled channels to this default value.
 659                  */
 660                 ret = ad7124_set_channel_odr(st, i, 10);
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int ad7124_probe(struct spi_device *spi)
 667 {
 668         const struct spi_device_id *id;
 669         struct ad7124_state *st;
 670         struct iio_dev *indio_dev;
 671         int i, ret;
 672
 673         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 674         if (!indio_dev)
 675                 return -ENOMEM;
 676
 677         st = iio_priv(indio_dev);
 678
 679         id = spi_get_device_id(spi);
 680         st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
 681
 682         ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
 683
 684         spi_set_drvdata(spi, indio_dev);
 685
 686         indio_dev->dev.parent = &spi->dev;
 687         indio_dev->name = spi_get_device_id(spi)->name;
 688         indio_dev->modes = INDIO_DIRECT_MODE;
 689         indio_dev->info = &ad7124_info;
 690
 691         ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
 692         if (ret < 0)
 693                 return ret;
 694
 695         for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
 696                 if (i == AD7124_INT_REF)
 697                         continue;
 698
 699                 st->vref[i] = devm_regulator_get_optional(&spi->dev,
 700                                                 ad7124_ref_names[i]);
 701                 if (PTR_ERR(st->vref[i]) == -ENODEV)
 702                         continue;
 703                 else if (IS_ERR(st->vref[i]))
 704                         return PTR_ERR(st->vref[i]);
 705
 706                 ret = regulator_enable(st->vref[i]);
 707                 if (ret)
 708                         return ret;
 709         }
 710
 711         st->mclk = devm_clk_get(&spi->dev, "mclk");
 712         if (IS_ERR(st->mclk)) {
 713                 ret = PTR_ERR(st->mclk);
 714                 goto error_regulator_disable;
 715         }
 716
 717         ret = clk_prepare_enable(st->mclk);
 718         if (ret < 0)
 719                 goto error_regulator_disable;
 720
 721         ret = ad7124_soft_reset(st);
 722         if (ret < 0)
 723                 goto error_clk_disable_unprepare;
 724
 725         ret = ad7124_setup(st);
 726         if (ret < 0)
 727                 goto error_clk_disable_unprepare;
 728
 729         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 730         if (ret < 0)
 731                 goto error_clk_disable_unprepare;
 732
 733         ret = iio_device_register(indio_dev);
 734         if (ret < 0) {
 735                 dev_err(&spi->dev, "Failed to register iio device\n");
 736                 goto error_remove_trigger;
 737         }
 738
 739         return 0;
 740
 741 error_remove_trigger:
 742         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 743 error_clk_disable_unprepare:
 744         clk_disable_unprepare(st->mclk);
 745 error_regulator_disable:
 746         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 747                 if (!IS_ERR_OR_NULL(st->vref[i]))
 748                         regulator_disable(st->vref[i]);
 749         }
 750
 751         return ret;
 752 }
 753
 754 static int ad7124_remove(struct spi_device *spi)
 755 {
 756         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 757         struct ad7124_state *st = iio_priv(indio_dev);
 758         int i;
 759
 760         iio_device_unregister(indio_dev);
 761         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 762         clk_disable_unprepare(st->mclk);
 763
 764         for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
 765                 if (!IS_ERR_OR_NULL(st->vref[i]))
 766                         regulator_disable(st->vref[i]);
 767         }
 768
 769         return 0;
 770 }
 771
 772 static const struct spi_device_id ad7124_id_table[] = {
 773         { "ad7124-4", ID_AD7124_4 },
 774         { "ad7124-8", ID_AD7124_8 },
 775         {}
 776 };
 777 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
 778
 779 static const struct of_device_id ad7124_of_match[] = {
 780         { .compatible = "adi,ad7124-4" },
 781         { .compatible = "adi,ad7124-8" },
 782         { },
 783 };
 784 MODULE_DEVICE_TABLE(of, ad7124_of_match);
 785
 786 static struct spi_driver ad71124_driver = {
 787         .driver = {
 788                 .name = "ad7124",
 789                 .of_match_table = ad7124_of_match,
 790         },
 791         .probe = ad7124_probe,
 792         .remove = ad7124_remove,
 793         .id_table = ad7124_id_table,
 794 };
 795 module_spi_driver(ad71124_driver);
 796
 797 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 798 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
 799 MODULE_LICENSE("GPL");