drivers/iio/adc/ad7768-1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Analog Devices AD7768-1 SPI ADC driver
   4  *
   5  * Copyright 2017 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/sysfs.h>
  17 #include <linux/spi/spi.h>
  18
  19 #include <linux/iio/buffer.h>
  20 #include <linux/iio/iio.h>
  21 #include <linux/iio/sysfs.h>
  22 #include <linux/iio/trigger.h>
  23 #include <linux/iio/triggered_buffer.h>
  24 #include <linux/iio/trigger_consumer.h>
  25
  26 /* AD7768 registers definition */
  27 #define AD7768_REG_CHIP_TYPE            0x3
  28 #define AD7768_REG_PROD_ID_L            0x4
  29 #define AD7768_REG_PROD_ID_H            0x5
  30 #define AD7768_REG_CHIP_GRADE           0x6
  31 #define AD7768_REG_SCRATCH_PAD          0x0A
  32 #define AD7768_REG_VENDOR_L             0x0C
  33 #define AD7768_REG_VENDOR_H             0x0D
  34 #define AD7768_REG_INTERFACE_FORMAT     0x14
  35 #define AD7768_REG_POWER_CLOCK          0x15
  36 #define AD7768_REG_ANALOG               0x16
  37 #define AD7768_REG_ANALOG2              0x17
  38 #define AD7768_REG_CONVERSION           0x18
  39 #define AD7768_REG_DIGITAL_FILTER       0x19
  40 #define AD7768_REG_SINC3_DEC_RATE_MSB   0x1A
  41 #define AD7768_REG_SINC3_DEC_RATE_LSB   0x1B
  42 #define AD7768_REG_DUTY_CYCLE_RATIO     0x1C
  43 #define AD7768_REG_SYNC_RESET           0x1D
  44 #define AD7768_REG_GPIO_CONTROL         0x1E
  45 #define AD7768_REG_GPIO_WRITE           0x1F
  46 #define AD7768_REG_GPIO_READ            0x20
  47 #define AD7768_REG_OFFSET_HI            0x21
  48 #define AD7768_REG_OFFSET_MID           0x22
  49 #define AD7768_REG_OFFSET_LO            0x23
  50 #define AD7768_REG_GAIN_HI              0x24
  51 #define AD7768_REG_GAIN_MID             0x25
  52 #define AD7768_REG_GAIN_LO              0x26
  53 #define AD7768_REG_SPI_DIAG_ENABLE      0x28
  54 #define AD7768_REG_ADC_DIAG_ENABLE      0x29
  55 #define AD7768_REG_DIG_DIAG_ENABLE      0x2A
  56 #define AD7768_REG_ADC_DATA             0x2C
  57 #define AD7768_REG_MASTER_STATUS        0x2D
  58 #define AD7768_REG_SPI_DIAG_STATUS      0x2E
  59 #define AD7768_REG_ADC_DIAG_STATUS      0x2F
  60 #define AD7768_REG_DIG_DIAG_STATUS      0x30
  61 #define AD7768_REG_MCLK_COUNTER         0x31
  62
  63 /* AD7768_REG_POWER_CLOCK */
  64 #define AD7768_PWR_MCLK_DIV_MSK         GENMASK(5, 4)
  65 #define AD7768_PWR_MCLK_DIV(x)          FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
  66 #define AD7768_PWR_PWRMODE_MSK          GENMASK(1, 0)
  67 #define AD7768_PWR_PWRMODE(x)           FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
  68
  69 /* AD7768_REG_DIGITAL_FILTER */
  70 #define AD7768_DIG_FIL_FIL_MSK          GENMASK(6, 4)
  71 #define AD7768_DIG_FIL_FIL(x)           FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
  72 #define AD7768_DIG_FIL_DEC_MSK          GENMASK(2, 0)
  73 #define AD7768_DIG_FIL_DEC_RATE(x)      FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
  74
  75 /* AD7768_REG_CONVERSION */
  76 #define AD7768_CONV_MODE_MSK            GENMASK(2, 0)
  77 #define AD7768_CONV_MODE(x)             FIELD_PREP(AD7768_CONV_MODE_MSK, x)
  78
  79 #define AD7768_RD_FLAG_MSK(x)           (BIT(6) | ((x) & 0x3F))
  80 #define AD7768_WR_FLAG_MSK(x)           ((x) & 0x3F)
  81
  82 enum ad7768_conv_mode {
  83         AD7768_CONTINUOUS,
  84         AD7768_ONE_SHOT,
  85         AD7768_SINGLE,
  86         AD7768_PERIODIC,
  87         AD7768_STANDBY
  88 };
  89
  90 enum ad7768_pwrmode {
  91         AD7768_ECO_MODE = 0,
  92         AD7768_MED_MODE = 2,
  93         AD7768_FAST_MODE = 3
  94 };
  95
  96 enum ad7768_mclk_div {
  97         AD7768_MCLK_DIV_16,
  98         AD7768_MCLK_DIV_8,
  99         AD7768_MCLK_DIV_4,
 100         AD7768_MCLK_DIV_2
 101 };
 102
 103 enum ad7768_dec_rate {
 104         AD7768_DEC_RATE_32 = 0,
 105         AD7768_DEC_RATE_64 = 1,
 106         AD7768_DEC_RATE_128 = 2,
 107         AD7768_DEC_RATE_256 = 3,
 108         AD7768_DEC_RATE_512 = 4,
 109         AD7768_DEC_RATE_1024 = 5,
 110         AD7768_DEC_RATE_8 = 9,
 111         AD7768_DEC_RATE_16 = 10
 112 };
 113
 114 struct ad7768_clk_configuration {
 115         enum ad7768_mclk_div mclk_div;
 116         enum ad7768_dec_rate dec_rate;
 117         unsigned int clk_div;
 118         enum ad7768_pwrmode pwrmode;
 119 };
 120
 121 static const struct ad7768_clk_configuration ad7768_clk_config[] = {
 122         { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16,  AD7768_FAST_MODE },
 123         { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32,  AD7768_FAST_MODE },
 124         { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
 125         { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
 126         { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
 127         { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
 128         { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
 129         { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
 130         { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
 131         { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
 132         { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
 133 };
 134
 135 static const struct iio_chan_spec ad7768_channels[] = {
 136         {
 137                 .type = IIO_VOLTAGE,
 138                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
 139                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
 140                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 141                 .indexed = 1,
 142                 .channel = 0,
 143                 .scan_index = 0,
 144                 .scan_type = {
 145                         .sign = 'u',
 146                         .realbits = 24,
 147                         .storagebits = 32,
 148                         .shift = 8,
 149                         .endianness = IIO_BE,
 150                 },
 151         },
 152 };
 153
 154 struct ad7768_state {
 155         struct spi_device *spi;
 156         struct regulator *vref;
 157         struct mutex lock;
 158         struct clk *mclk;
 159         unsigned int mclk_freq;
 160         unsigned int samp_freq;
 161         struct completion completion;
 162         struct iio_trigger *trig;
 163         struct gpio_desc *gpio_sync_in;
 164         /*
 165          * DMA (thus cache coherency maintenance) requires the
 166          * transfer buffers to live in their own cache lines.
 167          */
 168         union {
 169                 __be32 d32;
 170                 u8 d8[2];
 171         } data ____cacheline_aligned;
 172 };
 173
 174 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
 175                                unsigned int len)
 176 {
 177         unsigned int shift;
 178         int ret;
 179
 180         shift = 32 - (8 * len);
 181         st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
 182
 183         ret = spi_write_then_read(st->spi, st->data.d8, 1,
 184                                   &st->data.d32, len);
 185         if (ret < 0)
 186                 return ret;
 187
 188         return (be32_to_cpu(st->data.d32) >> shift);
 189 }
 190
 191 static int ad7768_spi_reg_write(struct ad7768_state *st,
 192                                 unsigned int addr,
 193                                 unsigned int val)
 194 {
 195         st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
 196         st->data.d8[1] = val & 0xFF;
 197
 198         return spi_write(st->spi, st->data.d8, 2);
 199 }
 200
 201 static int ad7768_set_mode(struct ad7768_state *st,
 202                            enum ad7768_conv_mode mode)
 203 {
 204         int regval;
 205
 206         regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
 207         if (regval < 0)
 208                 return regval;
 209
 210         regval &= ~AD7768_CONV_MODE_MSK;
 211         regval |= AD7768_CONV_MODE(mode);
 212
 213         return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
 214 }
 215
 216 static int ad7768_scan_direct(struct iio_dev *indio_dev)
 217 {
 218         struct ad7768_state *st = iio_priv(indio_dev);
 219         int readval, ret;
 220
 221         reinit_completion(&st->completion);
 222
 223         ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
 224         if (ret < 0)
 225                 return ret;
 226
 227         ret = wait_for_completion_timeout(&st->completion,
 228                                           msecs_to_jiffies(1000));
 229         if (!ret)
 230                 return -ETIMEDOUT;
 231
 232         readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
 233         if (readval < 0)
 234                 return readval;
 235         /*
 236          * Any SPI configuration of the AD7768-1 can only be
 237          * performed in continuous conversion mode.
 238          */
 239         ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
 240         if (ret < 0)
 241                 return ret;
 242
 243         return readval;
 244 }
 245
 246 static int ad7768_reg_access(struct iio_dev *indio_dev,
 247                              unsigned int reg,
 248                              unsigned int writeval,
 249                              unsigned int *readval)
 250 {
 251         struct ad7768_state *st = iio_priv(indio_dev);
 252         int ret;
 253
 254         mutex_lock(&st->lock);
 255         if (readval) {
 256                 ret = ad7768_spi_reg_read(st, reg, 1);
 257                 if (ret < 0)
 258                         goto err_unlock;
 259                 *readval = ret;
 260                 ret = 0;
 261         } else {
 262                 ret = ad7768_spi_reg_write(st, reg, writeval);
 263         }
 264 err_unlock:
 265         mutex_unlock(&st->lock);
 266
 267         return ret;
 268 }
 269
 270 static int ad7768_set_dig_fil(struct ad7768_state *st,
 271                               enum ad7768_dec_rate dec_rate)
 272 {
 273         unsigned int mode;
 274         int ret;
 275
 276         if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
 277                 mode = AD7768_DIG_FIL_FIL(dec_rate);
 278         else
 279                 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
 280
 281         ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
 282         if (ret < 0)
 283                 return ret;
 284
 285         /* A sync-in pulse is required every time the filter dec rate changes */
 286         gpiod_set_value(st->gpio_sync_in, 1);
 287         gpiod_set_value(st->gpio_sync_in, 0);
 288
 289         return 0;
 290 }
 291
 292 static int ad7768_set_freq(struct ad7768_state *st,
 293                            unsigned int freq)
 294 {
 295         unsigned int diff_new, diff_old, pwr_mode, i, idx;
 296         int res, ret;
 297
 298         diff_old = U32_MAX;
 299         idx = 0;
 300
 301         res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
 302
 303         /* Find the closest match for the desired sampling frequency */
 304         for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
 305                 diff_new = abs(res - ad7768_clk_config[i].clk_div);
 306                 if (diff_new < diff_old) {
 307                         diff_old = diff_new;
 308                         idx = i;
 309                 }
 310         }
 311
 312         /*
 313          * Set both the mclk_div and pwrmode with a single write to the
 314          * POWER_CLOCK register
 315          */
 316         pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
 317                    AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
 318         ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
 319         if (ret < 0)
 320                 return ret;
 321
 322         ret =  ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
 323         if (ret < 0)
 324                 return ret;
 325
 326         st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
 327                                           ad7768_clk_config[idx].clk_div);
 328
 329         return 0;
 330 }
 331
 332 static ssize_t ad7768_sampling_freq_avail(struct device *dev,
 333                                           struct device_attribute *attr,
 334                                           char *buf)
 335 {
 336         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 337         struct ad7768_state *st = iio_priv(indio_dev);
 338         unsigned int freq;
 339         int i, len = 0;
 340
 341         for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
 342                 freq = DIV_ROUND_CLOSEST(st->mclk_freq,
 343                                          ad7768_clk_config[i].clk_div);
 344                 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
 345         }
 346
 347         buf[len - 1] = '\n';
 348
 349         return len;
 350 }
 351
 352 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
 353
 354 static int ad7768_read_raw(struct iio_dev *indio_dev,
 355                            struct iio_chan_spec const *chan,
 356                            int *val, int *val2, long info)
 357 {
 358         struct ad7768_state *st = iio_priv(indio_dev);
 359         int scale_uv, ret;
 360
 361         switch (info) {
 362         case IIO_CHAN_INFO_RAW:
 363                 ret = iio_device_claim_direct_mode(indio_dev);
 364                 if (ret)
 365                         return ret;
 366
 367                 ret = ad7768_scan_direct(indio_dev);
 368                 if (ret >= 0)
 369                         *val = ret;
 370
 371                 iio_device_release_direct_mode(indio_dev);
 372                 if (ret < 0)
 373                         return ret;
 374
 375                 return IIO_VAL_INT;
 376
 377         case IIO_CHAN_INFO_SCALE:
 378                 scale_uv = regulator_get_voltage(st->vref);
 379                 if (scale_uv < 0)
 380                         return scale_uv;
 381
 382                 *val = (scale_uv * 2) / 1000;
 383                 *val2 = chan->scan_type.realbits;
 384
 385                 return IIO_VAL_FRACTIONAL_LOG2;
 386
 387         case IIO_CHAN_INFO_SAMP_FREQ:
 388                 *val = st->samp_freq;
 389
 390                 return IIO_VAL_INT;
 391         }
 392
 393         return -EINVAL;
 394 }
 395
 396 static int ad7768_write_raw(struct iio_dev *indio_dev,
 397                             struct iio_chan_spec const *chan,
 398                             int val, int val2, long info)
 399 {
 400         struct ad7768_state *st = iio_priv(indio_dev);
 401
 402         switch (info) {
 403         case IIO_CHAN_INFO_SAMP_FREQ:
 404                 return ad7768_set_freq(st, val);
 405         default:
 406                 return -EINVAL;
 407         }
 408 }
 409
 410 static struct attribute *ad7768_attributes[] = {
 411         &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 412         NULL
 413 };
 414
 415 static const struct attribute_group ad7768_group = {
 416         .attrs = ad7768_attributes,
 417 };
 418
 419 static const struct iio_info ad7768_info = {
 420         .attrs = &ad7768_group,
 421         .read_raw = &ad7768_read_raw,
 422         .write_raw = &ad7768_write_raw,
 423         .debugfs_reg_access = &ad7768_reg_access,
 424 };
 425
 426 static int ad7768_setup(struct ad7768_state *st)
 427 {
 428         int ret;
 429
 430         /*
 431          * Two writes to the SPI_RESET[1:0] bits are required to initiate
 432          * a software reset. The bits must first be set to 11, and then
 433          * to 10. When the sequence is detected, the reset occurs.
 434          * See the datasheet, page 70.
 435          */
 436         ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
 437         if (ret)
 438                 return ret;
 439
 440         ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
 441         if (ret)
 442                 return ret;
 443
 444         st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
 445                                           GPIOD_OUT_LOW);
 446         if (IS_ERR(st->gpio_sync_in))
 447                 return PTR_ERR(st->gpio_sync_in);
 448
 449         /* Set the default sampling frequency to 32000 kSPS */
 450         return ad7768_set_freq(st, 32000);
 451 }
 452
 453 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
 454 {
 455         struct iio_poll_func *pf = p;
 456         struct iio_dev *indio_dev = pf->indio_dev;
 457         struct ad7768_state *st = iio_priv(indio_dev);
 458         int ret;
 459
 460         mutex_lock(&st->lock);
 461
 462         ret = spi_read(st->spi, &st->data.d32, 3);
 463         if (ret < 0)
 464                 goto err_unlock;
 465
 466         iio_push_to_buffers_with_timestamp(indio_dev, &st->data.d32,
 467                                            iio_get_time_ns(indio_dev));
 468
 469         iio_trigger_notify_done(indio_dev->trig);
 470 err_unlock:
 471         mutex_unlock(&st->lock);
 472
 473         return IRQ_HANDLED;
 474 }
 475
 476 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
 477 {
 478         struct iio_dev *indio_dev = dev_id;
 479         struct ad7768_state *st = iio_priv(indio_dev);
 480
 481         if (iio_buffer_enabled(indio_dev))
 482                 iio_trigger_poll(st->trig);
 483         else
 484                 complete(&st->completion);
 485
 486         return IRQ_HANDLED;
 487 };
 488
 489 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
 490 {
 491         struct ad7768_state *st = iio_priv(indio_dev);
 492
 493         iio_triggered_buffer_postenable(indio_dev);
 494         /*
 495          * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
 496          * continuous read mode. Subsequent data reads do not require an
 497          * initial 8-bit write to query the ADC_DATA register.
 498          */
 499         return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
 500 }
 501
 502 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
 503 {
 504         struct ad7768_state *st = iio_priv(indio_dev);
 505         int ret;
 506
 507         /*
 508          * To exit continuous read mode, perform a single read of the ADC_DATA
 509          * reg (0x2C), which allows further configuration of the device.
 510          */
 511         ret = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
 512         if (ret < 0)
 513                 return ret;
 514
 515         return iio_triggered_buffer_predisable(indio_dev);
 516 }
 517
 518 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
 519         .postenable = &ad7768_buffer_postenable,
 520         .predisable = &ad7768_buffer_predisable,
 521 };
 522
 523 static const struct iio_trigger_ops ad7768_trigger_ops = {
 524         .validate_device = iio_trigger_validate_own_device,
 525 };
 526
 527 static void ad7768_regulator_disable(void *data)
 528 {
 529         struct ad7768_state *st = data;
 530
 531         regulator_disable(st->vref);
 532 }
 533
 534 static void ad7768_clk_disable(void *data)
 535 {
 536         struct ad7768_state *st = data;
 537
 538         clk_disable_unprepare(st->mclk);
 539 }
 540
 541 static int ad7768_probe(struct spi_device *spi)
 542 {
 543         struct ad7768_state *st;
 544         struct iio_dev *indio_dev;
 545         int ret;
 546
 547         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 548         if (!indio_dev)
 549                 return -ENOMEM;
 550
 551         st = iio_priv(indio_dev);
 552         st->spi = spi;
 553
 554         st->vref = devm_regulator_get(&spi->dev, "vref");
 555         if (IS_ERR(st->vref))
 556                 return PTR_ERR(st->vref);
 557
 558         ret = regulator_enable(st->vref);
 559         if (ret) {
 560                 dev_err(&spi->dev, "Failed to enable specified vref supply\n");
 561                 return ret;
 562         }
 563
 564         ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
 565         if (ret)
 566                 return ret;
 567
 568         st->mclk = devm_clk_get(&spi->dev, "mclk");
 569         if (IS_ERR(st->mclk))
 570                 return PTR_ERR(st->mclk);
 571
 572         ret = clk_prepare_enable(st->mclk);
 573         if (ret < 0)
 574                 return ret;
 575
 576         ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
 577         if (ret)
 578                 return ret;
 579
 580         st->mclk_freq = clk_get_rate(st->mclk);
 581
 582         spi_set_drvdata(spi, indio_dev);
 583         mutex_init(&st->lock);
 584
 585         indio_dev->channels = ad7768_channels;
 586         indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
 587         indio_dev->dev.parent = &spi->dev;
 588         indio_dev->name = spi_get_device_id(spi)->name;
 589         indio_dev->info = &ad7768_info;
 590         indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
 591
 592         ret = ad7768_setup(st);
 593         if (ret < 0) {
 594                 dev_err(&spi->dev, "AD7768 setup failed\n");
 595                 return ret;
 596         }
 597
 598         st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
 599                                           indio_dev->name, indio_dev->id);
 600         if (!st->trig)
 601                 return -ENOMEM;
 602
 603         st->trig->ops = &ad7768_trigger_ops;
 604         st->trig->dev.parent = &spi->dev;
 605         iio_trigger_set_drvdata(st->trig, indio_dev);
 606         ret = devm_iio_trigger_register(&spi->dev, st->trig);
 607         if (ret)
 608                 return ret;
 609
 610         indio_dev->trig = iio_trigger_get(st->trig);
 611
 612         init_completion(&st->completion);
 613
 614         ret = devm_request_irq(&spi->dev, spi->irq,
 615                                &ad7768_interrupt,
 616                                IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 617                                indio_dev->name, indio_dev);
 618         if (ret)
 619                 return ret;
 620
 621         ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
 622                                               &iio_pollfunc_store_time,
 623                                               &ad7768_trigger_handler,
 624                                               &ad7768_buffer_ops);
 625         if (ret)
 626                 return ret;
 627
 628         return devm_iio_device_register(&spi->dev, indio_dev);
 629 }
 630
 631 static const struct spi_device_id ad7768_id_table[] = {
 632         { "ad7768-1", 0 },
 633         {}
 634 };
 635 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
 636
 637 static const struct of_device_id ad7768_of_match[] = {
 638         { .compatible = "adi,ad7768-1" },
 639         { },
 640 };
 641 MODULE_DEVICE_TABLE(of, ad7768_of_match);
 642
 643 static struct spi_driver ad7768_driver = {
 644         .driver = {
 645                 .name = "ad7768-1",
 646                 .of_match_table = ad7768_of_match,
 647         },
 648         .probe = ad7768_probe,
 649         .id_table = ad7768_id_table,
 650 };
 651 module_spi_driver(ad7768_driver);
 652
 653 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 654 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
 655 MODULE_LICENSE("GPL v2");