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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / iio / frequency / adf4350.c
blob1c2dc9b00f319ee2f2e49c8b39117ee42232dd96
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
4 *
5 * Copyright 2012-2013 Analog Devices Inc.
6 */
7
8 #include <linux/device.h>
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/sysfs.h>
12 #include <linux/spi/spi.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/gcd.h>
17 #include <linux/gpio/consumer.h>
18 #include <asm/div64.h>
19 #include <linux/clk.h>
20 #include <linux/of.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/frequency/adf4350.h>
25
26 enum {
27 ADF4350_FREQ,
28 ADF4350_FREQ_REFIN,
29 ADF4350_FREQ_RESOLUTION,
30 ADF4350_PWRDOWN,
31 };
32
33 struct adf4350_state {
34 struct spi_device *spi;
35 struct regulator *reg;
36 struct gpio_desc *lock_detect_gpiod;
37 struct adf4350_platform_data *pdata;
38 struct clk *clk;
39 unsigned long clkin;
40 unsigned long chspc; /* Channel Spacing */
41 unsigned long fpfd; /* Phase Frequency Detector */
42 unsigned long min_out_freq;
43 unsigned r0_fract;
44 unsigned r0_int;
45 unsigned r1_mod;
46 unsigned r4_rf_div_sel;
47 unsigned long regs[6];
48 unsigned long regs_hw[6];
49 unsigned long long freq_req;
50 /*
51 * DMA (thus cache coherency maintenance) requires the
52 * transfer buffers to live in their own cache lines.
53 */
54 __be32 val ____cacheline_aligned;
55 };
56
57 static struct adf4350_platform_data default_pdata = {
58 .channel_spacing = 10000,
59 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
60 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
61 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
62 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
63 ADF4350_REG4_MUTE_TILL_LOCK_EN,
64 };
65
66 static int adf4350_sync_config(struct adf4350_state *st)
67 {
68 int ret, i, doublebuf = 0;
69
70 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
71 if ((st->regs_hw[i] != st->regs[i]) ||
72 ((i == ADF4350_REG0) && doublebuf)) {
73 switch (i) {
74 case ADF4350_REG1:
75 case ADF4350_REG4:
76 doublebuf = 1;
77 break;
78 }
79
80 st->val = cpu_to_be32(st->regs[i] | i);
81 ret = spi_write(st->spi, &st->val, 4);
82 if (ret < 0)
83 return ret;
84 st->regs_hw[i] = st->regs[i];
85 dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
86 i, (u32)st->regs[i] | i);
87 }
88 }
89 return 0;
90 }
91
92 static int adf4350_reg_access(struct iio_dev *indio_dev,
93 unsigned reg, unsigned writeval,
94 unsigned *readval)
95 {
96 struct adf4350_state *st = iio_priv(indio_dev);
97 int ret;
98
99 if (reg > ADF4350_REG5)
100 return -EINVAL;
101
102 mutex_lock(&indio_dev->mlock);
103 if (readval == NULL) {
104 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
105 ret = adf4350_sync_config(st);
106 } else {
107 *readval = st->regs_hw[reg];
108 ret = 0;
109 }
110 mutex_unlock(&indio_dev->mlock);
111
112 return ret;
113 }
114
115 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
116 {
117 struct adf4350_platform_data *pdata = st->pdata;
118
119 do {
120 r_cnt++;
121 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
122 (r_cnt * (pdata->ref_div2_en ? 2 : 1));
123 } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
124
125 return r_cnt;
126 }
127
128 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
129 {
130 struct adf4350_platform_data *pdata = st->pdata;
131 u64 tmp;
132 u32 div_gcd, prescaler, chspc;
133 u16 mdiv, r_cnt = 0;
134 u8 band_sel_div;
135
136 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
137 return -EINVAL;
138
139 if (freq > ADF4350_MAX_FREQ_45_PRESC) {
140 prescaler = ADF4350_REG1_PRESCALER;
141 mdiv = 75;
142 } else {
143 prescaler = 0;
144 mdiv = 23;
145 }
146
147 st->r4_rf_div_sel = 0;
148
149 while (freq < ADF4350_MIN_VCO_FREQ) {
150 freq <<= 1;
151 st->r4_rf_div_sel++;
152 }
153
154 /*
155 * Allow a predefined reference division factor
156 * if not set, compute our own
157 */
158 if (pdata->ref_div_factor)
159 r_cnt = pdata->ref_div_factor - 1;
160
161 chspc = st->chspc;
162
163 do {
164 do {
165 do {
166 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
167 st->r1_mod = st->fpfd / chspc;
168 if (r_cnt > ADF4350_MAX_R_CNT) {
169 /* try higher spacing values */
170 chspc++;
171 r_cnt = 0;
172 }
173 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
174 } while (r_cnt == 0);
175
176 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
177 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
178 st->r0_fract = do_div(tmp, st->r1_mod);
179 st->r0_int = tmp;
180 } while (mdiv > st->r0_int);
181
182 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
183
184 if (st->r0_fract && st->r1_mod) {
185 div_gcd = gcd(st->r1_mod, st->r0_fract);
186 st->r1_mod /= div_gcd;
187 st->r0_fract /= div_gcd;
188 } else {
189 st->r0_fract = 0;
190 st->r1_mod = 1;
191 }
192
193 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
194 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
195 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
196 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
197 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
198 band_sel_div);
199
200 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
201 ADF4350_REG0_FRACT(st->r0_fract);
202
203 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
204 ADF4350_REG1_MOD(st->r1_mod) |
205 prescaler;
206
207 st->regs[ADF4350_REG2] =
208 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
209 ADF4350_REG2_DOUBLE_BUFF_EN |
210 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
211 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
212 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
213 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
214 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
215 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
216
217 st->regs[ADF4350_REG3] = pdata->r3_user_settings &
218 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
219 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
220 ADF4350_REG3_12BIT_CSR_EN |
221 ADF4351_REG3_CHARGE_CANCELLATION_EN |
222 ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
223 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
224
225 st->regs[ADF4350_REG4] =
226 ADF4350_REG4_FEEDBACK_FUND |
227 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
228 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
229 ADF4350_REG4_RF_OUT_EN |
230 (pdata->r4_user_settings &
231 (ADF4350_REG4_OUTPUT_PWR(0x3) |
232 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
233 ADF4350_REG4_AUX_OUTPUT_EN |
234 ADF4350_REG4_AUX_OUTPUT_FUND |
235 ADF4350_REG4_MUTE_TILL_LOCK_EN));
236
237 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
238 st->freq_req = freq;
239
240 return adf4350_sync_config(st);
241 }
242
243 static ssize_t adf4350_write(struct iio_dev *indio_dev,
244 uintptr_t private,
245 const struct iio_chan_spec *chan,
246 const char *buf, size_t len)
247 {
248 struct adf4350_state *st = iio_priv(indio_dev);
249 unsigned long long readin;
250 unsigned long tmp;
251 int ret;
252
253 ret = kstrtoull(buf, 10, &readin);
254 if (ret)
255 return ret;
256
257 mutex_lock(&indio_dev->mlock);
258 switch ((u32)private) {
259 case ADF4350_FREQ:
260 ret = adf4350_set_freq(st, readin);
261 break;
262 case ADF4350_FREQ_REFIN:
263 if (readin > ADF4350_MAX_FREQ_REFIN) {
264 ret = -EINVAL;
265 break;
266 }
267
268 if (st->clk) {
269 tmp = clk_round_rate(st->clk, readin);
270 if (tmp != readin) {
271 ret = -EINVAL;
272 break;
273 }
274 ret = clk_set_rate(st->clk, tmp);
275 if (ret < 0)
276 break;
277 }
278 st->clkin = readin;
279 ret = adf4350_set_freq(st, st->freq_req);
280 break;
281 case ADF4350_FREQ_RESOLUTION:
282 if (readin == 0)
283 ret = -EINVAL;
284 else
285 st->chspc = readin;
286 break;
287 case ADF4350_PWRDOWN:
288 if (readin)
289 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
290 else
291 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
292
293 adf4350_sync_config(st);
294 break;
295 default:
296 ret = -EINVAL;
297 }
298 mutex_unlock(&indio_dev->mlock);
299
300 return ret ? ret : len;
301 }
302
303 static ssize_t adf4350_read(struct iio_dev *indio_dev,
304 uintptr_t private,
305 const struct iio_chan_spec *chan,
306 char *buf)
307 {
308 struct adf4350_state *st = iio_priv(indio_dev);
309 unsigned long long val;
310 int ret = 0;
311
312 mutex_lock(&indio_dev->mlock);
313 switch ((u32)private) {
314 case ADF4350_FREQ:
315 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
316 (u64)st->fpfd;
317 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
318 /* PLL unlocked? return error */
319 if (st->lock_detect_gpiod)
320 if (!gpiod_get_value(st->lock_detect_gpiod)) {
321 dev_dbg(&st->spi->dev, "PLL un-locked\n");
322 ret = -EBUSY;
323 }
324 break;
325 case ADF4350_FREQ_REFIN:
326 if (st->clk)
327 st->clkin = clk_get_rate(st->clk);
328
329 val = st->clkin;
330 break;
331 case ADF4350_FREQ_RESOLUTION:
332 val = st->chspc;
333 break;
334 case ADF4350_PWRDOWN:
335 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
336 break;
337 default:
338 ret = -EINVAL;
339 val = 0;
340 }
341 mutex_unlock(&indio_dev->mlock);
342
343 return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
344 }
345
346 #define _ADF4350_EXT_INFO(_name, _ident) { \
347 .name = _name, \
348 .read = adf4350_read, \
349 .write = adf4350_write, \
350 .private = _ident, \
351 .shared = IIO_SEPARATE, \
352 }
353
354 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
355 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
356 * values > 2^32 in order to support the entire frequency range
357 * in Hz. Using scale is a bit ugly.
358 */
359 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
360 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
361 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
362 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
363 { },
364 };
365
366 static const struct iio_chan_spec adf4350_chan = {
367 .type = IIO_ALTVOLTAGE,
368 .indexed = 1,
369 .output = 1,
370 .ext_info = adf4350_ext_info,
371 };
372
373 static const struct iio_info adf4350_info = {
374 .debugfs_reg_access = &adf4350_reg_access,
375 };
376
377 #ifdef CONFIG_OF
378 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
379 {
380 struct device_node *np = dev->of_node;
381 struct adf4350_platform_data *pdata;
382 unsigned int tmp;
383
384 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
385 if (!pdata)
386 return NULL;
387
388 snprintf(&pdata->name[0], SPI_NAME_SIZE - 1, "%pOFn", np);
389
390 tmp = 10000;
391 of_property_read_u32(np, "adi,channel-spacing", &tmp);
392 pdata->channel_spacing = tmp;
393
394 tmp = 0;
395 of_property_read_u32(np, "adi,power-up-frequency", &tmp);
396 pdata->power_up_frequency = tmp;
397
398 tmp = 0;
399 of_property_read_u32(np, "adi,reference-div-factor", &tmp);
400 pdata->ref_div_factor = tmp;
401
402 pdata->ref_doubler_en = of_property_read_bool(np,
403 "adi,reference-doubler-enable");
404 pdata->ref_div2_en = of_property_read_bool(np,
405 "adi,reference-div2-enable");
406
407 /* r2_user_settings */
408 pdata->r2_user_settings = of_property_read_bool(np,
409 "adi,phase-detector-polarity-positive-enable") ?
410 ADF4350_REG2_PD_POLARITY_POS : 0;
411 pdata->r2_user_settings |= of_property_read_bool(np,
412 "adi,lock-detect-precision-6ns-enable") ?
413 ADF4350_REG2_LDP_6ns : 0;
414 pdata->r2_user_settings |= of_property_read_bool(np,
415 "adi,lock-detect-function-integer-n-enable") ?
416 ADF4350_REG2_LDF_INT_N : 0;
417
418 tmp = 2500;
419 of_property_read_u32(np, "adi,charge-pump-current", &tmp);
420 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
421
422 tmp = 0;
423 of_property_read_u32(np, "adi,muxout-select", &tmp);
424 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
425
426 pdata->r2_user_settings |= of_property_read_bool(np,
427 "adi,low-spur-mode-enable") ?
428 ADF4350_REG2_NOISE_MODE(0x3) : 0;
429
430 /* r3_user_settings */
431
432 pdata->r3_user_settings = of_property_read_bool(np,
433 "adi,cycle-slip-reduction-enable") ?
434 ADF4350_REG3_12BIT_CSR_EN : 0;
435 pdata->r3_user_settings |= of_property_read_bool(np,
436 "adi,charge-cancellation-enable") ?
437 ADF4351_REG3_CHARGE_CANCELLATION_EN : 0;
438
439 pdata->r3_user_settings |= of_property_read_bool(np,
440 "adi,anti-backlash-3ns-enable") ?
441 ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0;
442 pdata->r3_user_settings |= of_property_read_bool(np,
443 "adi,band-select-clock-mode-high-enable") ?
444 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0;
445
446 tmp = 0;
447 of_property_read_u32(np, "adi,12bit-clk-divider", &tmp);
448 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
449
450 tmp = 0;
451 of_property_read_u32(np, "adi,clk-divider-mode", &tmp);
452 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
453
454 /* r4_user_settings */
455
456 pdata->r4_user_settings = of_property_read_bool(np,
457 "adi,aux-output-enable") ?
458 ADF4350_REG4_AUX_OUTPUT_EN : 0;
459 pdata->r4_user_settings |= of_property_read_bool(np,
460 "adi,aux-output-fundamental-enable") ?
461 ADF4350_REG4_AUX_OUTPUT_FUND : 0;
462 pdata->r4_user_settings |= of_property_read_bool(np,
463 "adi,mute-till-lock-enable") ?
464 ADF4350_REG4_MUTE_TILL_LOCK_EN : 0;
465
466 tmp = 0;
467 of_property_read_u32(np, "adi,output-power", &tmp);
468 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
469
470 tmp = 0;
471 of_property_read_u32(np, "adi,aux-output-power", &tmp);
472 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
473
474 return pdata;
475 }
476 #else
477 static
478 struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
479 {
480 return NULL;
481 }
482 #endif
483
484 static int adf4350_probe(struct spi_device *spi)
485 {
486 struct adf4350_platform_data *pdata;
487 struct iio_dev *indio_dev;
488 struct adf4350_state *st;
489 struct clk *clk = NULL;
490 int ret;
491
492 if (spi->dev.of_node) {
493 pdata = adf4350_parse_dt(&spi->dev);
494 if (pdata == NULL)
495 return -EINVAL;
496 } else {
497 pdata = spi->dev.platform_data;
498 }
499
500 if (!pdata) {
501 dev_warn(&spi->dev, "no platform data? using default\n");
502 pdata = &default_pdata;
503 }
504
505 if (!pdata->clkin) {
506 clk = devm_clk_get(&spi->dev, "clkin");
507 if (IS_ERR(clk))
508 return -EPROBE_DEFER;
509
510 ret = clk_prepare_enable(clk);
511 if (ret < 0)
512 return ret;
513 }
514
515 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
516 if (indio_dev == NULL) {
517 ret = -ENOMEM;
518 goto error_disable_clk;
519 }
520
521 st = iio_priv(indio_dev);
522
523 st->reg = devm_regulator_get(&spi->dev, "vcc");
524 if (!IS_ERR(st->reg)) {
525 ret = regulator_enable(st->reg);
526 if (ret)
527 goto error_disable_clk;
528 }
529
530 spi_set_drvdata(spi, indio_dev);
531 st->spi = spi;
532 st->pdata = pdata;
533
534 indio_dev->dev.parent = &spi->dev;
535 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
536 spi_get_device_id(spi)->name;
537
538 indio_dev->info = &adf4350_info;
539 indio_dev->modes = INDIO_DIRECT_MODE;
540 indio_dev->channels = &adf4350_chan;
541 indio_dev->num_channels = 1;
542
543 st->chspc = pdata->channel_spacing;
544 if (clk) {
545 st->clk = clk;
546 st->clkin = clk_get_rate(clk);
547 } else {
548 st->clkin = pdata->clkin;
549 }
550
551 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
552 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
553
554 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
555
556 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
557 GPIOD_IN);
558 if (IS_ERR(st->lock_detect_gpiod))
559 return PTR_ERR(st->lock_detect_gpiod);
560
561 if (pdata->power_up_frequency) {
562 ret = adf4350_set_freq(st, pdata->power_up_frequency);
563 if (ret)
564 goto error_disable_reg;
565 }
566
567 ret = iio_device_register(indio_dev);
568 if (ret)
569 goto error_disable_reg;
570
571 return 0;
572
573 error_disable_reg:
574 if (!IS_ERR(st->reg))
575 regulator_disable(st->reg);
576 error_disable_clk:
577 if (clk)
578 clk_disable_unprepare(clk);
579
580 return ret;
581 }
582
583 static int adf4350_remove(struct spi_device *spi)
584 {
585 struct iio_dev *indio_dev = spi_get_drvdata(spi);
586 struct adf4350_state *st = iio_priv(indio_dev);
587 struct regulator *reg = st->reg;
588
589 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
590 adf4350_sync_config(st);
591
592 iio_device_unregister(indio_dev);
593
594 if (st->clk)
595 clk_disable_unprepare(st->clk);
596
597 if (!IS_ERR(reg))
598 regulator_disable(reg);
599
600 return 0;
601 }
602
603 static const struct of_device_id adf4350_of_match[] = {
604 { .compatible = "adi,adf4350", },
605 { .compatible = "adi,adf4351", },
606 { /* sentinel */ },
607 };
608 MODULE_DEVICE_TABLE(of, adf4350_of_match);
609
610 static const struct spi_device_id adf4350_id[] = {
611 {"adf4350", 4350},
612 {"adf4351", 4351},
613 {}
614 };
615 MODULE_DEVICE_TABLE(spi, adf4350_id);
616
617 static struct spi_driver adf4350_driver = {
618 .driver = {
619 .name = "adf4350",
620 .of_match_table = of_match_ptr(adf4350_of_match),
621 },
622 .probe = adf4350_probe,
623 .remove = adf4350_remove,
624 .id_table = adf4350_id,
625 };
626 module_spi_driver(adf4350_driver);
627
628 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
629 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
630 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support