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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / infiniband / hw / hns / hns_roce_qp.c
blob6317901c4b4fe378427fad4a62a403418b01c31b
1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/pci.h>
35 #include <linux/platform_device.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_umem.h>
38 #include <rdma/uverbs_ioctl.h>
39 #include "hns_roce_common.h"
40 #include "hns_roce_device.h"
41 #include "hns_roce_hem.h"
42 #include <rdma/hns-abi.h>
43
44 #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
45
46 static void flush_work_handle(struct work_struct *work)
47 {
48 struct hns_roce_work *flush_work = container_of(work,
49 struct hns_roce_work, work);
50 struct hns_roce_qp *hr_qp = container_of(flush_work,
51 struct hns_roce_qp, flush_work);
52 struct device *dev = flush_work->hr_dev->dev;
53 struct ib_qp_attr attr;
54 int attr_mask;
55 int ret;
56
57 attr_mask = IB_QP_STATE;
58 attr.qp_state = IB_QPS_ERR;
59
60 if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) {
61 ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL);
62 if (ret)
63 dev_err(dev, "Modify QP to error state failed(%d) during CQE flush\n",
64 ret);
65 }
66
67 /*
68 * make sure we signal QP destroy leg that flush QP was completed
69 * so that it can safely proceed ahead now and destroy QP
70 */
71 if (atomic_dec_and_test(&hr_qp->refcount))
72 complete(&hr_qp->free);
73 }
74
75 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
76 {
77 struct hns_roce_work *flush_work = &hr_qp->flush_work;
78
79 flush_work->hr_dev = hr_dev;
80 INIT_WORK(&flush_work->work, flush_work_handle);
81 atomic_inc(&hr_qp->refcount);
82 queue_work(hr_dev->irq_workq, &flush_work->work);
83 }
84
85 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
86 {
87 struct device *dev = hr_dev->dev;
88 struct hns_roce_qp *qp;
89
90 xa_lock(&hr_dev->qp_table_xa);
91 qp = __hns_roce_qp_lookup(hr_dev, qpn);
92 if (qp)
93 atomic_inc(&qp->refcount);
94 xa_unlock(&hr_dev->qp_table_xa);
95
96 if (!qp) {
97 dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
98 return;
99 }
100
101 if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 &&
102 (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR ||
103 event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR ||
104 event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)) {
105 qp->state = IB_QPS_ERR;
106 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
107 init_flush_work(hr_dev, qp);
108 }
109
110 qp->event(qp, (enum hns_roce_event)event_type);
111
112 if (atomic_dec_and_test(&qp->refcount))
113 complete(&qp->free);
114 }
115
116 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
117 enum hns_roce_event type)
118 {
119 struct ib_event event;
120 struct ib_qp *ibqp = &hr_qp->ibqp;
121
122 if (ibqp->event_handler) {
123 event.device = ibqp->device;
124 event.element.qp = ibqp;
125 switch (type) {
126 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
127 event.event = IB_EVENT_PATH_MIG;
128 break;
129 case HNS_ROCE_EVENT_TYPE_COMM_EST:
130 event.event = IB_EVENT_COMM_EST;
131 break;
132 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
133 event.event = IB_EVENT_SQ_DRAINED;
134 break;
135 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
136 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
137 break;
138 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
139 event.event = IB_EVENT_QP_FATAL;
140 break;
141 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
142 event.event = IB_EVENT_PATH_MIG_ERR;
143 break;
144 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
145 event.event = IB_EVENT_QP_REQ_ERR;
146 break;
147 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
148 event.event = IB_EVENT_QP_ACCESS_ERR;
149 break;
150 default:
151 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
152 type, hr_qp->qpn);
153 return;
154 }
155 ibqp->event_handler(&event, ibqp->qp_context);
156 }
157 }
158
159 static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
160 {
161 unsigned long num = 0;
162 int ret;
163
164 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) {
165 /* when hw version is v1, the sqpn is allocated */
166 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1)
167 num = HNS_ROCE_MAX_PORTS +
168 hr_dev->iboe.phy_port[hr_qp->port];
169 else
170 num = 1;
171
172 hr_qp->doorbell_qpn = 1;
173 } else {
174 ret = hns_roce_bitmap_alloc_range(&hr_dev->qp_table.bitmap,
175 1, 1, &num);
176 if (ret) {
177 ibdev_err(&hr_dev->ib_dev, "Failed to alloc bitmap\n");
178 return -ENOMEM;
179 }
180
181 hr_qp->doorbell_qpn = (u32)num;
182 }
183
184 hr_qp->qpn = num;
185
186 return 0;
187 }
188
189 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
190 {
191 switch (state) {
192 case IB_QPS_RESET:
193 return HNS_ROCE_QP_STATE_RST;
194 case IB_QPS_INIT:
195 return HNS_ROCE_QP_STATE_INIT;
196 case IB_QPS_RTR:
197 return HNS_ROCE_QP_STATE_RTR;
198 case IB_QPS_RTS:
199 return HNS_ROCE_QP_STATE_RTS;
200 case IB_QPS_SQD:
201 return HNS_ROCE_QP_STATE_SQD;
202 case IB_QPS_ERR:
203 return HNS_ROCE_QP_STATE_ERR;
204 default:
205 return HNS_ROCE_QP_NUM_STATE;
206 }
207 }
208
209 static void add_qp_to_list(struct hns_roce_dev *hr_dev,
210 struct hns_roce_qp *hr_qp,
211 struct ib_cq *send_cq, struct ib_cq *recv_cq)
212 {
213 struct hns_roce_cq *hr_send_cq, *hr_recv_cq;
214 unsigned long flags;
215
216 hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL;
217 hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL;
218
219 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
220 hns_roce_lock_cqs(hr_send_cq, hr_recv_cq);
221
222 list_add_tail(&hr_qp->node, &hr_dev->qp_list);
223 if (hr_send_cq)
224 list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list);
225 if (hr_recv_cq)
226 list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list);
227
228 hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq);
229 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
230 }
231
232 static int hns_roce_qp_store(struct hns_roce_dev *hr_dev,
233 struct hns_roce_qp *hr_qp,
234 struct ib_qp_init_attr *init_attr)
235 {
236 struct xarray *xa = &hr_dev->qp_table_xa;
237 int ret;
238
239 if (!hr_qp->qpn)
240 return -EINVAL;
241
242 ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL));
243 if (ret)
244 dev_err(hr_dev->dev, "Failed to xa store for QPC\n");
245 else
246 /* add QP to device's QP list for softwc */
247 add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq,
248 init_attr->recv_cq);
249
250 return ret;
251 }
252
253 static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
254 {
255 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
256 struct device *dev = hr_dev->dev;
257 int ret;
258
259 if (!hr_qp->qpn)
260 return -EINVAL;
261
262 /* In v1 engine, GSI QP context is saved in the RoCE hw's register */
263 if (hr_qp->ibqp.qp_type == IB_QPT_GSI &&
264 hr_dev->hw_rev == HNS_ROCE_HW_VER1)
265 return 0;
266
267 /* Alloc memory for QPC */
268 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
269 if (ret) {
270 dev_err(dev, "Failed to get QPC table\n");
271 goto err_out;
272 }
273
274 /* Alloc memory for IRRL */
275 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
276 if (ret) {
277 dev_err(dev, "Failed to get IRRL table\n");
278 goto err_put_qp;
279 }
280
281 if (hr_dev->caps.trrl_entry_sz) {
282 /* Alloc memory for TRRL */
283 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
284 hr_qp->qpn);
285 if (ret) {
286 dev_err(dev, "Failed to get TRRL table\n");
287 goto err_put_irrl;
288 }
289 }
290
291 if (hr_dev->caps.sccc_entry_sz) {
292 /* Alloc memory for SCC CTX */
293 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table,
294 hr_qp->qpn);
295 if (ret) {
296 dev_err(dev, "Failed to get SCC CTX table\n");
297 goto err_put_trrl;
298 }
299 }
300
301 return 0;
302
303 err_put_trrl:
304 if (hr_dev->caps.trrl_entry_sz)
305 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
306
307 err_put_irrl:
308 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
309
310 err_put_qp:
311 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
312
313 err_out:
314 return ret;
315 }
316
317 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
318 {
319 struct xarray *xa = &hr_dev->qp_table_xa;
320 unsigned long flags;
321
322 list_del(&hr_qp->node);
323 list_del(&hr_qp->sq_node);
324 list_del(&hr_qp->rq_node);
325
326 xa_lock_irqsave(xa, flags);
327 __xa_erase(xa, hr_qp->qpn & (hr_dev->caps.num_qps - 1));
328 xa_unlock_irqrestore(xa, flags);
329 }
330
331 static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
332 {
333 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
334
335 /* In v1 engine, GSI QP context is saved in the RoCE hw's register */
336 if (hr_qp->ibqp.qp_type == IB_QPT_GSI &&
337 hr_dev->hw_rev == HNS_ROCE_HW_VER1)
338 return;
339
340 if (hr_dev->caps.trrl_entry_sz)
341 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
342 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
343 }
344
345 static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
346 {
347 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
348
349 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
350 return;
351
352 if (hr_qp->qpn < hr_dev->caps.reserved_qps)
353 return;
354
355 hns_roce_bitmap_free_range(&qp_table->bitmap, hr_qp->qpn, 1, BITMAP_RR);
356 }
357
358 static int set_rq_size(struct hns_roce_dev *hr_dev,
359 struct ib_qp_cap *cap, bool is_user, int has_rq,
360 struct hns_roce_qp *hr_qp)
361 {
362 u32 max_cnt;
363
364 /* If srq exist, set zero for relative number of rq */
365 if (!has_rq) {
366 hr_qp->rq.wqe_cnt = 0;
367 hr_qp->rq.max_gs = 0;
368 cap->max_recv_wr = 0;
369 cap->max_recv_sge = 0;
370
371 return 0;
372 }
373
374 /* Check the validity of QP support capacity */
375 if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes ||
376 cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
377 ibdev_err(&hr_dev->ib_dev, "RQ config error, depth=%u, sge=%d\n",
378 cap->max_recv_wr, cap->max_recv_sge);
379 return -EINVAL;
380 }
381
382 max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
383
384 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
385 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
386 ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n",
387 cap->max_recv_wr);
388 return -EINVAL;
389 }
390
391 max_cnt = max(1U, cap->max_recv_sge);
392 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
393
394 if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE)
395 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz);
396 else
397 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz *
398 hr_qp->rq.max_gs);
399
400 cap->max_recv_wr = hr_qp->rq.wqe_cnt;
401 cap->max_recv_sge = hr_qp->rq.max_gs;
402
403 return 0;
404 }
405
406 static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev,
407 struct ib_qp_cap *cap,
408 struct hns_roce_ib_create_qp *ucmd)
409 {
410 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
411 u8 max_sq_stride = ilog2(roundup_sq_stride);
412
413 /* Sanity check SQ size before proceeding */
414 if (ucmd->log_sq_stride > max_sq_stride ||
415 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
416 ibdev_err(&hr_dev->ib_dev, "Failed to check SQ stride size\n");
417 return -EINVAL;
418 }
419
420 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
421 ibdev_err(&hr_dev->ib_dev, "Failed to check SQ SGE size %d\n",
422 cap->max_send_sge);
423 return -EINVAL;
424 }
425
426 return 0;
427 }
428
429 static int set_user_sq_size(struct hns_roce_dev *hr_dev,
430 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp,
431 struct hns_roce_ib_create_qp *ucmd)
432 {
433 u32 ex_sge_num;
434 u32 page_size;
435 u32 max_cnt;
436 int ret;
437
438 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &hr_qp->sq.wqe_cnt) ||
439 hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes)
440 return -EINVAL;
441
442 ret = check_sq_size_with_integrity(hr_dev, cap, ucmd);
443 if (ret) {
444 ibdev_err(&hr_dev->ib_dev, "Failed to check user SQ size limit\n");
445 return ret;
446 }
447
448 hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
449
450 max_cnt = max(1U, cap->max_send_sge);
451 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1)
452 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
453 else
454 hr_qp->sq.max_gs = max_cnt;
455
456 if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE)
457 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
458 (hr_qp->sq.max_gs - 2));
459
460 if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE &&
461 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) {
462 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
463 ibdev_err(&hr_dev->ib_dev,
464 "Failed to check extended SGE size limit %d\n",
465 hr_qp->sge.sge_cnt);
466 return -EINVAL;
467 }
468 }
469
470 hr_qp->sge.sge_shift = 4;
471 ex_sge_num = hr_qp->sge.sge_cnt;
472
473 /* Get buf size, SQ and RQ are aligned to page_szie */
474 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
475 hr_qp->buff_size = round_up((hr_qp->rq.wqe_cnt <<
476 hr_qp->rq.wqe_shift), PAGE_SIZE) +
477 round_up((hr_qp->sq.wqe_cnt <<
478 hr_qp->sq.wqe_shift), PAGE_SIZE);
479
480 hr_qp->sq.offset = 0;
481 hr_qp->rq.offset = round_up((hr_qp->sq.wqe_cnt <<
482 hr_qp->sq.wqe_shift), PAGE_SIZE);
483 } else {
484 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
485 hr_qp->sge.sge_cnt = ex_sge_num ?
486 max(page_size / (1 << hr_qp->sge.sge_shift), ex_sge_num) : 0;
487 hr_qp->buff_size = round_up((hr_qp->rq.wqe_cnt <<
488 hr_qp->rq.wqe_shift), page_size) +
489 round_up((hr_qp->sge.sge_cnt <<
490 hr_qp->sge.sge_shift), page_size) +
491 round_up((hr_qp->sq.wqe_cnt <<
492 hr_qp->sq.wqe_shift), page_size);
493
494 hr_qp->sq.offset = 0;
495 if (ex_sge_num) {
496 hr_qp->sge.offset = round_up((hr_qp->sq.wqe_cnt <<
497 hr_qp->sq.wqe_shift),
498 page_size);
499 hr_qp->rq.offset = hr_qp->sge.offset +
500 round_up((hr_qp->sge.sge_cnt <<
501 hr_qp->sge.sge_shift),
502 page_size);
503 } else {
504 hr_qp->rq.offset = round_up((hr_qp->sq.wqe_cnt <<
505 hr_qp->sq.wqe_shift),
506 page_size);
507 }
508 }
509
510 return 0;
511 }
512
513 static int split_wqe_buf_region(struct hns_roce_dev *hr_dev,
514 struct hns_roce_qp *hr_qp,
515 struct hns_roce_buf_region *regions,
516 int region_max, int page_shift)
517 {
518 int page_size = 1 << page_shift;
519 bool is_extend_sge;
520 int region_cnt = 0;
521 int buf_size;
522 int buf_cnt;
523
524 if (hr_qp->buff_size < 1 || region_max < 1)
525 return region_cnt;
526
527 if (hr_qp->sge.sge_cnt > 0)
528 is_extend_sge = true;
529 else
530 is_extend_sge = false;
531
532 /* sq region */
533 if (is_extend_sge)
534 buf_size = hr_qp->sge.offset - hr_qp->sq.offset;
535 else
536 buf_size = hr_qp->rq.offset - hr_qp->sq.offset;
537
538 if (buf_size > 0 && region_cnt < region_max) {
539 buf_cnt = DIV_ROUND_UP(buf_size, page_size);
540 hns_roce_init_buf_region(&regions[region_cnt],
541 hr_dev->caps.wqe_sq_hop_num,
542 hr_qp->sq.offset / page_size,
543 buf_cnt);
544 region_cnt++;
545 }
546
547 /* sge region */
548 if (is_extend_sge) {
549 buf_size = hr_qp->rq.offset - hr_qp->sge.offset;
550 if (buf_size > 0 && region_cnt < region_max) {
551 buf_cnt = DIV_ROUND_UP(buf_size, page_size);
552 hns_roce_init_buf_region(&regions[region_cnt],
553 hr_dev->caps.wqe_sge_hop_num,
554 hr_qp->sge.offset / page_size,
555 buf_cnt);
556 region_cnt++;
557 }
558 }
559
560 /* rq region */
561 buf_size = hr_qp->buff_size - hr_qp->rq.offset;
562 if (buf_size > 0) {
563 buf_cnt = DIV_ROUND_UP(buf_size, page_size);
564 hns_roce_init_buf_region(&regions[region_cnt],
565 hr_dev->caps.wqe_rq_hop_num,
566 hr_qp->rq.offset / page_size,
567 buf_cnt);
568 region_cnt++;
569 }
570
571 return region_cnt;
572 }
573
574 static int set_extend_sge_param(struct hns_roce_dev *hr_dev,
575 struct hns_roce_qp *hr_qp)
576 {
577 struct device *dev = hr_dev->dev;
578
579 if (hr_qp->sq.max_gs > 2) {
580 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
581 (hr_qp->sq.max_gs - 2));
582 hr_qp->sge.sge_shift = 4;
583 }
584
585 /* ud sqwqe's sge use extend sge */
586 if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 &&
587 hr_qp->ibqp.qp_type == IB_QPT_GSI) {
588 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
589 hr_qp->sq.max_gs);
590 hr_qp->sge.sge_shift = 4;
591 }
592
593 if (hr_qp->sq.max_gs > 2 &&
594 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) {
595 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
596 dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n",
597 hr_qp->sge.sge_cnt);
598 return -EINVAL;
599 }
600 }
601
602 return 0;
603 }
604
605 static int set_kernel_sq_size(struct hns_roce_dev *hr_dev,
606 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp)
607 {
608 u32 page_size;
609 u32 max_cnt;
610 int size;
611 int ret;
612
613 if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes ||
614 cap->max_send_sge > hr_dev->caps.max_sq_sg ||
615 cap->max_inline_data > hr_dev->caps.max_sq_inline) {
616 ibdev_err(&hr_dev->ib_dev,
617 "SQ WR or sge or inline data error!\n");
618 return -EINVAL;
619 }
620
621 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
622
623 max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
624
625 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
626 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
627 ibdev_err(&hr_dev->ib_dev,
628 "while setting kernel sq size, sq.wqe_cnt too large\n");
629 return -EINVAL;
630 }
631
632 /* Get data_seg numbers */
633 max_cnt = max(1U, cap->max_send_sge);
634 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1)
635 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
636 else
637 hr_qp->sq.max_gs = max_cnt;
638
639 ret = set_extend_sge_param(hr_dev, hr_qp);
640 if (ret) {
641 ibdev_err(&hr_dev->ib_dev, "set extend sge parameters fail\n");
642 return ret;
643 }
644
645 /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
646 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
647 hr_qp->sq.offset = 0;
648 size = round_up(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift, page_size);
649
650 if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && hr_qp->sge.sge_cnt) {
651 hr_qp->sge.sge_cnt = max(page_size/(1 << hr_qp->sge.sge_shift),
652 (u32)hr_qp->sge.sge_cnt);
653 hr_qp->sge.offset = size;
654 size += round_up(hr_qp->sge.sge_cnt << hr_qp->sge.sge_shift,
655 page_size);
656 }
657
658 hr_qp->rq.offset = size;
659 size += round_up((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift), page_size);
660 hr_qp->buff_size = size;
661
662 /* Get wr and sge number which send */
663 cap->max_send_wr = hr_qp->sq.wqe_cnt;
664 cap->max_send_sge = hr_qp->sq.max_gs;
665
666 /* We don't support inline sends for kernel QPs (yet) */
667 cap->max_inline_data = 0;
668
669 return 0;
670 }
671
672 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
673 {
674 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr)
675 return 0;
676
677 return 1;
678 }
679
680 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
681 {
682 if (attr->qp_type == IB_QPT_XRC_INI ||
683 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
684 !attr->cap.max_recv_wr)
685 return 0;
686
687 return 1;
688 }
689
690 static int alloc_rq_inline_buf(struct hns_roce_qp *hr_qp,
691 struct ib_qp_init_attr *init_attr)
692 {
693 u32 max_recv_sge = init_attr->cap.max_recv_sge;
694 struct hns_roce_rinl_wqe *wqe_list;
695 u32 wqe_cnt = hr_qp->rq.wqe_cnt;
696 int i;
697
698 /* allocate recv inline buf */
699 wqe_list = kcalloc(wqe_cnt, sizeof(struct hns_roce_rinl_wqe),
700 GFP_KERNEL);
701
702 if (!wqe_list)
703 goto err;
704
705 /* Allocate a continuous buffer for all inline sge we need */
706 wqe_list[0].sg_list = kcalloc(wqe_cnt, (max_recv_sge *
707 sizeof(struct hns_roce_rinl_sge)),
708 GFP_KERNEL);
709 if (!wqe_list[0].sg_list)
710 goto err_wqe_list;
711
712 /* Assign buffers of sg_list to each inline wqe */
713 for (i = 1; i < wqe_cnt; i++)
714 wqe_list[i].sg_list = &wqe_list[0].sg_list[i * max_recv_sge];
715
716 hr_qp->rq_inl_buf.wqe_list = wqe_list;
717 hr_qp->rq_inl_buf.wqe_cnt = wqe_cnt;
718
719 return 0;
720
721 err_wqe_list:
722 kfree(wqe_list);
723
724 err:
725 return -ENOMEM;
726 }
727
728 static void free_rq_inline_buf(struct hns_roce_qp *hr_qp)
729 {
730 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
731 kfree(hr_qp->rq_inl_buf.wqe_list);
732 }
733
734 static int map_wqe_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
735 u32 page_shift, bool is_user)
736 {
737 /* WQE buffer include 3 parts: SQ, extend SGE and RQ. */
738 #define HNS_ROCE_WQE_REGION_MAX 3
739 struct hns_roce_buf_region regions[HNS_ROCE_WQE_REGION_MAX] = {};
740 dma_addr_t *buf_list[HNS_ROCE_WQE_REGION_MAX] = {};
741 struct ib_device *ibdev = &hr_dev->ib_dev;
742 struct hns_roce_buf_region *r;
743 int region_count;
744 int buf_count;
745 int ret;
746 int i;
747
748 region_count = split_wqe_buf_region(hr_dev, hr_qp, regions,
749 ARRAY_SIZE(regions), page_shift);
750
751 /* alloc a tmp list to store WQE buffers address */
752 ret = hns_roce_alloc_buf_list(regions, buf_list, region_count);
753 if (ret) {
754 ibdev_err(ibdev, "Failed to alloc WQE buffer list\n");
755 return ret;
756 }
757
758 for (i = 0; i < region_count; i++) {
759 r = &regions[i];
760 if (is_user)
761 buf_count = hns_roce_get_umem_bufs(hr_dev, buf_list[i],
762 r->count, r->offset, hr_qp->umem,
763 page_shift);
764 else
765 buf_count = hns_roce_get_kmem_bufs(hr_dev, buf_list[i],
766 r->count, r->offset, &hr_qp->hr_buf);
767
768 if (buf_count != r->count) {
769 ibdev_err(ibdev, "Failed to get %s WQE buf, expect %d = %d.\n",
770 is_user ? "user" : "kernel",
771 r->count, buf_count);
772 ret = -ENOBUFS;
773 goto done;
774 }
775 }
776
777 hr_qp->wqe_bt_pg_shift = hr_dev->caps.mtt_ba_pg_sz;
778 hns_roce_mtr_init(&hr_qp->mtr, PAGE_SHIFT + hr_qp->wqe_bt_pg_shift,
779 page_shift);
780 ret = hns_roce_mtr_attach(hr_dev, &hr_qp->mtr, buf_list, regions,
781 region_count);
782 if (ret)
783 ibdev_err(ibdev, "Failed to attach WQE's mtr\n");
784
785 goto done;
786
787 hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr);
788 done:
789 hns_roce_free_buf_list(buf_list, region_count);
790
791 return ret;
792 }
793
794 static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
795 struct ib_qp_init_attr *init_attr,
796 struct ib_udata *udata, unsigned long addr)
797 {
798 u32 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
799 struct ib_device *ibdev = &hr_dev->ib_dev;
800 bool is_rq_buf_inline;
801 int ret;
802
803 is_rq_buf_inline = (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) &&
804 hns_roce_qp_has_rq(init_attr);
805 if (is_rq_buf_inline) {
806 ret = alloc_rq_inline_buf(hr_qp, init_attr);
807 if (ret) {
808 ibdev_err(ibdev, "Failed to alloc inline RQ buffer\n");
809 return ret;
810 }
811 }
812
813 if (udata) {
814 hr_qp->umem = ib_umem_get(ibdev, addr, hr_qp->buff_size, 0);
815 if (IS_ERR(hr_qp->umem)) {
816 ret = PTR_ERR(hr_qp->umem);
817 goto err_inline;
818 }
819 } else {
820 ret = hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
821 (1 << page_shift) * 2,
822 &hr_qp->hr_buf, page_shift);
823 if (ret)
824 goto err_inline;
825 }
826
827 ret = map_wqe_buf(hr_dev, hr_qp, page_shift, udata);
828 if (ret)
829 goto err_alloc;
830
831 return 0;
832
833 err_inline:
834 if (is_rq_buf_inline)
835 free_rq_inline_buf(hr_qp);
836
837 err_alloc:
838 if (udata) {
839 ib_umem_release(hr_qp->umem);
840 hr_qp->umem = NULL;
841 } else {
842 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
843 }
844
845 ibdev_err(ibdev, "Failed to alloc WQE buffer, ret %d.\n", ret);
846
847 return ret;
848 }
849
850 static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
851 {
852 hns_roce_mtr_cleanup(hr_dev, &hr_qp->mtr);
853 if (hr_qp->umem) {
854 ib_umem_release(hr_qp->umem);
855 hr_qp->umem = NULL;
856 }
857
858 if (hr_qp->hr_buf.nbufs > 0)
859 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
860
861 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) &&
862 hr_qp->rq.wqe_cnt)
863 free_rq_inline_buf(hr_qp);
864 }
865
866 static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev,
867 struct ib_qp_init_attr *init_attr,
868 struct ib_udata *udata,
869 struct hns_roce_ib_create_qp_resp *resp,
870 struct hns_roce_ib_create_qp *ucmd)
871 {
872 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
873 udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
874 hns_roce_qp_has_sq(init_attr) &&
875 udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr));
876 }
877
878 static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev,
879 struct ib_qp_init_attr *init_attr,
880 struct ib_udata *udata,
881 struct hns_roce_ib_create_qp_resp *resp)
882 {
883 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
884 udata->outlen >= offsetofend(typeof(*resp), cap_flags) &&
885 hns_roce_qp_has_rq(init_attr));
886 }
887
888 static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev,
889 struct ib_qp_init_attr *init_attr)
890 {
891 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
892 hns_roce_qp_has_rq(init_attr));
893 }
894
895 static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
896 struct ib_qp_init_attr *init_attr,
897 struct ib_udata *udata,
898 struct hns_roce_ib_create_qp *ucmd,
899 struct hns_roce_ib_create_qp_resp *resp)
900 {
901 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(
902 udata, struct hns_roce_ucontext, ibucontext);
903 struct ib_device *ibdev = &hr_dev->ib_dev;
904 int ret;
905
906 if (udata) {
907 if (user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd)) {
908 ret = hns_roce_db_map_user(uctx, udata, ucmd->sdb_addr,
909 &hr_qp->sdb);
910 if (ret) {
911 ibdev_err(ibdev,
912 "Failed to map user SQ doorbell\n");
913 goto err_out;
914 }
915 hr_qp->sdb_en = 1;
916 resp->cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB;
917 }
918
919 if (user_qp_has_rdb(hr_dev, init_attr, udata, resp)) {
920 ret = hns_roce_db_map_user(uctx, udata, ucmd->db_addr,
921 &hr_qp->rdb);
922 if (ret) {
923 ibdev_err(ibdev,
924 "Failed to map user RQ doorbell\n");
925 goto err_sdb;
926 }
927 hr_qp->rdb_en = 1;
928 resp->cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB;
929 }
930 } else {
931 /* QP doorbell register address */
932 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
933 DB_REG_OFFSET * hr_dev->priv_uar.index;
934 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
935 DB_REG_OFFSET * hr_dev->priv_uar.index;
936
937 if (kernel_qp_has_rdb(hr_dev, init_attr)) {
938 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
939 if (ret) {
940 ibdev_err(ibdev,
941 "Failed to alloc kernel RQ doorbell\n");
942 goto err_out;
943 }
944 *hr_qp->rdb.db_record = 0;
945 hr_qp->rdb_en = 1;
946 }
947 }
948
949 return 0;
950 err_sdb:
951 if (udata && hr_qp->sdb_en)
952 hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
953 err_out:
954 return ret;
955 }
956
957 static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
958 struct ib_udata *udata)
959 {
960 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(
961 udata, struct hns_roce_ucontext, ibucontext);
962
963 if (udata) {
964 if (hr_qp->rdb_en)
965 hns_roce_db_unmap_user(uctx, &hr_qp->rdb);
966 if (hr_qp->sdb_en)
967 hns_roce_db_unmap_user(uctx, &hr_qp->sdb);
968 } else {
969 if (hr_qp->rdb_en)
970 hns_roce_free_db(hr_dev, &hr_qp->rdb);
971 }
972 }
973
974 static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev,
975 struct hns_roce_qp *hr_qp)
976 {
977 struct ib_device *ibdev = &hr_dev->ib_dev;
978 u64 *sq_wrid = NULL;
979 u64 *rq_wrid = NULL;
980 int ret;
981
982 sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL);
983 if (ZERO_OR_NULL_PTR(sq_wrid)) {
984 ibdev_err(ibdev, "Failed to alloc SQ wrid\n");
985 return -ENOMEM;
986 }
987
988 if (hr_qp->rq.wqe_cnt) {
989 rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL);
990 if (ZERO_OR_NULL_PTR(rq_wrid)) {
991 ibdev_err(ibdev, "Failed to alloc RQ wrid\n");
992 ret = -ENOMEM;
993 goto err_sq;
994 }
995 }
996
997 hr_qp->sq.wrid = sq_wrid;
998 hr_qp->rq.wrid = rq_wrid;
999 return 0;
1000 err_sq:
1001 kfree(sq_wrid);
1002
1003 return ret;
1004 }
1005
1006 static void free_kernel_wrid(struct hns_roce_dev *hr_dev,
1007 struct hns_roce_qp *hr_qp)
1008 {
1009 kfree(hr_qp->rq.wrid);
1010 kfree(hr_qp->sq.wrid);
1011 }
1012
1013 static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1014 struct ib_qp_init_attr *init_attr,
1015 struct ib_udata *udata,
1016 struct hns_roce_ib_create_qp *ucmd)
1017 {
1018 struct ib_device *ibdev = &hr_dev->ib_dev;
1019 int ret;
1020
1021 hr_qp->ibqp.qp_type = init_attr->qp_type;
1022
1023 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1024 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR;
1025 else
1026 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR;
1027
1028 ret = set_rq_size(hr_dev, &init_attr->cap, udata,
1029 hns_roce_qp_has_rq(init_attr), hr_qp);
1030 if (ret) {
1031 ibdev_err(ibdev, "Failed to set user RQ size\n");
1032 return ret;
1033 }
1034
1035 if (udata) {
1036 if (ib_copy_from_udata(ucmd, udata, sizeof(*ucmd))) {
1037 ibdev_err(ibdev, "Failed to copy QP ucmd\n");
1038 return -EFAULT;
1039 }
1040
1041 ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd);
1042 if (ret)
1043 ibdev_err(ibdev, "Failed to set user SQ size\n");
1044 } else {
1045 if (init_attr->create_flags &
1046 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1047 ibdev_err(ibdev, "Failed to check multicast loopback\n");
1048 return -EINVAL;
1049 }
1050
1051 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
1052 ibdev_err(ibdev, "Failed to check ipoib ud lso\n");
1053 return -EINVAL;
1054 }
1055
1056 ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp);
1057 if (ret)
1058 ibdev_err(ibdev, "Failed to set kernel SQ size\n");
1059 }
1060
1061 return ret;
1062 }
1063
1064 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
1065 struct ib_pd *ib_pd,
1066 struct ib_qp_init_attr *init_attr,
1067 struct ib_udata *udata,
1068 struct hns_roce_qp *hr_qp)
1069 {
1070 struct hns_roce_ib_create_qp_resp resp = {};
1071 struct ib_device *ibdev = &hr_dev->ib_dev;
1072 struct hns_roce_ib_create_qp ucmd;
1073 int ret;
1074
1075 mutex_init(&hr_qp->mutex);
1076 spin_lock_init(&hr_qp->sq.lock);
1077 spin_lock_init(&hr_qp->rq.lock);
1078
1079 hr_qp->state = IB_QPS_RESET;
1080 hr_qp->flush_flag = 0;
1081
1082 ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd);
1083 if (ret) {
1084 ibdev_err(ibdev, "Failed to set QP param\n");
1085 return ret;
1086 }
1087
1088 if (!udata) {
1089 ret = alloc_kernel_wrid(hr_dev, hr_qp);
1090 if (ret) {
1091 ibdev_err(ibdev, "Failed to alloc wrid\n");
1092 return ret;
1093 }
1094 }
1095
1096 ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp);
1097 if (ret) {
1098 ibdev_err(ibdev, "Failed to alloc QP doorbell\n");
1099 goto err_wrid;
1100 }
1101
1102 ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr);
1103 if (ret) {
1104 ibdev_err(ibdev, "Failed to alloc QP buffer\n");
1105 goto err_db;
1106 }
1107
1108 ret = alloc_qpn(hr_dev, hr_qp);
1109 if (ret) {
1110 ibdev_err(ibdev, "Failed to alloc QPN\n");
1111 goto err_buf;
1112 }
1113
1114 ret = alloc_qpc(hr_dev, hr_qp);
1115 if (ret) {
1116 ibdev_err(ibdev, "Failed to alloc QP context\n");
1117 goto err_qpn;
1118 }
1119
1120 ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr);
1121 if (ret) {
1122 ibdev_err(ibdev, "Failed to store QP\n");
1123 goto err_qpc;
1124 }
1125
1126 if (udata) {
1127 ret = ib_copy_to_udata(udata, &resp,
1128 min(udata->outlen, sizeof(resp)));
1129 if (ret) {
1130 ibdev_err(ibdev, "copy qp resp failed!\n");
1131 goto err_store;
1132 }
1133 }
1134
1135 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
1136 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp);
1137 if (ret)
1138 goto err_store;
1139 }
1140
1141 hr_qp->ibqp.qp_num = hr_qp->qpn;
1142 hr_qp->event = hns_roce_ib_qp_event;
1143 atomic_set(&hr_qp->refcount, 1);
1144 init_completion(&hr_qp->free);
1145
1146 return 0;
1147
1148 err_store:
1149 hns_roce_qp_remove(hr_dev, hr_qp);
1150 err_qpc:
1151 free_qpc(hr_dev, hr_qp);
1152 err_qpn:
1153 free_qpn(hr_dev, hr_qp);
1154 err_buf:
1155 free_qp_buf(hr_dev, hr_qp);
1156 err_db:
1157 free_qp_db(hr_dev, hr_qp, udata);
1158 err_wrid:
1159 free_kernel_wrid(hr_dev, hr_qp);
1160 return ret;
1161 }
1162
1163 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1164 struct ib_udata *udata)
1165 {
1166 if (atomic_dec_and_test(&hr_qp->refcount))
1167 complete(&hr_qp->free);
1168 wait_for_completion(&hr_qp->free);
1169
1170 free_qpc(hr_dev, hr_qp);
1171 free_qpn(hr_dev, hr_qp);
1172 free_qp_buf(hr_dev, hr_qp);
1173 free_kernel_wrid(hr_dev, hr_qp);
1174 free_qp_db(hr_dev, hr_qp, udata);
1175
1176 kfree(hr_qp);
1177 }
1178
1179 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
1180 struct ib_qp_init_attr *init_attr,
1181 struct ib_udata *udata)
1182 {
1183 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
1184 struct ib_device *ibdev = &hr_dev->ib_dev;
1185 struct hns_roce_qp *hr_qp;
1186 int ret;
1187
1188 switch (init_attr->qp_type) {
1189 case IB_QPT_RC: {
1190 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
1191 if (!hr_qp)
1192 return ERR_PTR(-ENOMEM);
1193
1194 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
1195 hr_qp);
1196 if (ret) {
1197 ibdev_err(ibdev, "Create QP 0x%06lx failed(%d)\n",
1198 hr_qp->qpn, ret);
1199 kfree(hr_qp);
1200 return ERR_PTR(ret);
1201 }
1202
1203 break;
1204 }
1205 case IB_QPT_GSI: {
1206 /* Userspace is not allowed to create special QPs: */
1207 if (udata) {
1208 ibdev_err(ibdev, "not support usr space GSI\n");
1209 return ERR_PTR(-EINVAL);
1210 }
1211
1212 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
1213 if (!hr_qp)
1214 return ERR_PTR(-ENOMEM);
1215
1216 hr_qp->port = init_attr->port_num - 1;
1217 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
1218
1219 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
1220 hr_qp);
1221 if (ret) {
1222 ibdev_err(ibdev, "Create GSI QP failed!\n");
1223 kfree(hr_qp);
1224 return ERR_PTR(ret);
1225 }
1226
1227 break;
1228 }
1229 default:{
1230 ibdev_err(ibdev, "not support QP type %d\n",
1231 init_attr->qp_type);
1232 return ERR_PTR(-EOPNOTSUPP);
1233 }
1234 }
1235
1236 return &hr_qp->ibqp;
1237 }
1238
1239 int to_hr_qp_type(int qp_type)
1240 {
1241 int transport_type;
1242
1243 if (qp_type == IB_QPT_RC)
1244 transport_type = SERV_TYPE_RC;
1245 else if (qp_type == IB_QPT_UC)
1246 transport_type = SERV_TYPE_UC;
1247 else if (qp_type == IB_QPT_UD)
1248 transport_type = SERV_TYPE_UD;
1249 else if (qp_type == IB_QPT_GSI)
1250 transport_type = SERV_TYPE_UD;
1251 else
1252 transport_type = -1;
1253
1254 return transport_type;
1255 }
1256
1257 static int check_mtu_validate(struct hns_roce_dev *hr_dev,
1258 struct hns_roce_qp *hr_qp,
1259 struct ib_qp_attr *attr, int attr_mask)
1260 {
1261 enum ib_mtu active_mtu;
1262 int p;
1263
1264 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1265 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
1266
1267 if ((hr_dev->caps.max_mtu >= IB_MTU_2048 &&
1268 attr->path_mtu > hr_dev->caps.max_mtu) ||
1269 attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) {
1270 ibdev_err(&hr_dev->ib_dev,
1271 "attr path_mtu(%d)invalid while modify qp",
1272 attr->path_mtu);
1273 return -EINVAL;
1274 }
1275
1276 return 0;
1277 }
1278
1279 static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1280 int attr_mask)
1281 {
1282 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1283 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1284 int p;
1285
1286 if ((attr_mask & IB_QP_PORT) &&
1287 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
1288 ibdev_err(&hr_dev->ib_dev,
1289 "attr port_num invalid.attr->port_num=%d\n",
1290 attr->port_num);
1291 return -EINVAL;
1292 }
1293
1294 if (attr_mask & IB_QP_PKEY_INDEX) {
1295 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
1296 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
1297 ibdev_err(&hr_dev->ib_dev,
1298 "attr pkey_index invalid.attr->pkey_index=%d\n",
1299 attr->pkey_index);
1300 return -EINVAL;
1301 }
1302 }
1303
1304 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1305 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
1306 ibdev_err(&hr_dev->ib_dev,
1307 "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
1308 attr->max_rd_atomic);
1309 return -EINVAL;
1310 }
1311
1312 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1313 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
1314 ibdev_err(&hr_dev->ib_dev,
1315 "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
1316 attr->max_dest_rd_atomic);
1317 return -EINVAL;
1318 }
1319
1320 if (attr_mask & IB_QP_PATH_MTU)
1321 return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask);
1322
1323 return 0;
1324 }
1325
1326 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1327 int attr_mask, struct ib_udata *udata)
1328 {
1329 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1330 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1331 enum ib_qp_state cur_state, new_state;
1332 int ret = -EINVAL;
1333
1334 mutex_lock(&hr_qp->mutex);
1335
1336 cur_state = attr_mask & IB_QP_CUR_STATE ?
1337 attr->cur_qp_state : (enum ib_qp_state)hr_qp->state;
1338 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1339
1340 if (ibqp->uobject &&
1341 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
1342 if (hr_qp->sdb_en == 1) {
1343 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
1344
1345 if (hr_qp->rdb_en == 1)
1346 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
1347 } else {
1348 ibdev_warn(&hr_dev->ib_dev,
1349 "flush cqe is not supported in userspace!\n");
1350 goto out;
1351 }
1352 }
1353
1354 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1355 attr_mask)) {
1356 ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n");
1357 goto out;
1358 }
1359
1360 ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask);
1361 if (ret)
1362 goto out;
1363
1364 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1365 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
1366 ret = -EPERM;
1367 ibdev_err(&hr_dev->ib_dev,
1368 "RST2RST state is not supported\n");
1369 } else {
1370 ret = 0;
1371 }
1372
1373 goto out;
1374 }
1375
1376 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
1377 new_state);
1378
1379 out:
1380 mutex_unlock(&hr_qp->mutex);
1381
1382 return ret;
1383 }
1384
1385 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
1386 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1387 {
1388 if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1389 __acquire(&send_cq->lock);
1390 __acquire(&recv_cq->lock);
1391 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1392 spin_lock_irq(&send_cq->lock);
1393 __acquire(&recv_cq->lock);
1394 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1395 spin_lock_irq(&recv_cq->lock);
1396 __acquire(&send_cq->lock);
1397 } else if (send_cq == recv_cq) {
1398 spin_lock_irq(&send_cq->lock);
1399 __acquire(&recv_cq->lock);
1400 } else if (send_cq->cqn < recv_cq->cqn) {
1401 spin_lock_irq(&send_cq->lock);
1402 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1403 } else {
1404 spin_lock_irq(&recv_cq->lock);
1405 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1406 }
1407 }
1408
1409 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1410 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
1411 __releases(&recv_cq->lock)
1412 {
1413 if (unlikely(send_cq == NULL && recv_cq == NULL)) {
1414 __release(&recv_cq->lock);
1415 __release(&send_cq->lock);
1416 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) {
1417 __release(&recv_cq->lock);
1418 spin_unlock(&send_cq->lock);
1419 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) {
1420 __release(&send_cq->lock);
1421 spin_unlock(&recv_cq->lock);
1422 } else if (send_cq == recv_cq) {
1423 __release(&recv_cq->lock);
1424 spin_unlock_irq(&send_cq->lock);
1425 } else if (send_cq->cqn < recv_cq->cqn) {
1426 spin_unlock(&recv_cq->lock);
1427 spin_unlock_irq(&send_cq->lock);
1428 } else {
1429 spin_unlock(&send_cq->lock);
1430 spin_unlock_irq(&recv_cq->lock);
1431 }
1432 }
1433
1434 static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
1435 {
1436
1437 return hns_roce_buf_offset(&hr_qp->hr_buf, offset);
1438 }
1439
1440 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
1441 {
1442 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
1443 }
1444
1445 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n)
1446 {
1447 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
1448 }
1449
1450 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n)
1451 {
1452 return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
1453 (n << hr_qp->sge.sge_shift));
1454 }
1455
1456 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1457 struct ib_cq *ib_cq)
1458 {
1459 struct hns_roce_cq *hr_cq;
1460 u32 cur;
1461
1462 cur = hr_wq->head - hr_wq->tail;
1463 if (likely(cur + nreq < hr_wq->wqe_cnt))
1464 return false;
1465
1466 hr_cq = to_hr_cq(ib_cq);
1467 spin_lock(&hr_cq->lock);
1468 cur = hr_wq->head - hr_wq->tail;
1469 spin_unlock(&hr_cq->lock);
1470
1471 return cur + nreq >= hr_wq->wqe_cnt;
1472 }
1473
1474 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
1475 {
1476 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
1477 int reserved_from_top = 0;
1478 int reserved_from_bot;
1479 int ret;
1480
1481 mutex_init(&qp_table->scc_mutex);
1482 xa_init(&hr_dev->qp_table_xa);
1483
1484 reserved_from_bot = hr_dev->caps.reserved_qps;
1485
1486 ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps,
1487 hr_dev->caps.num_qps - 1, reserved_from_bot,
1488 reserved_from_top);
1489 if (ret) {
1490 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
1491 ret);
1492 return ret;
1493 }
1494
1495 return 0;
1496 }
1497
1498 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
1499 {
1500 hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap);
1501 }
Linux with added FPC-III support