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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / infiniband / hw / mlx5 / cq.c
blob146ba29667441eadcc3f4aac7443181cb9707142
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
37 #include "mlx5_ib.h"
38 #include "srq.h"
39
40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)
41 {
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
45 }
46
47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48 {
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
53
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
56 type, mcq->cqn);
57 return;
58 }
59
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
65 }
66 }
67
68 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
69 {
70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
71 }
72
73 static u8 sw_ownership_bit(int n, int nent)
74 {
75 return (n & nent) ? 1 : 0;
76 }
77
78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
79 {
80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
81 struct mlx5_cqe64 *cqe64;
82
83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
84
85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
87 return cqe;
88 } else {
89 return NULL;
90 }
91 }
92
93 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
94 {
95 return get_sw_cqe(cq, cq->mcq.cons_index);
96 }
97
98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
99 {
100 switch (wq->wr_data[idx]) {
101 case MLX5_IB_WR_UMR:
102 return 0;
103
104 case IB_WR_LOCAL_INV:
105 return IB_WC_LOCAL_INV;
106
107 case IB_WR_REG_MR:
108 return IB_WC_REG_MR;
109
110 default:
111 pr_warn("unknown completion status\n");
112 return 0;
113 }
114 }
115
116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
117 struct mlx5_ib_wq *wq, int idx)
118 {
119 wc->wc_flags = 0;
120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
121 case MLX5_OPCODE_RDMA_WRITE_IMM:
122 wc->wc_flags |= IB_WC_WITH_IMM;
123 /* fall through */
124 case MLX5_OPCODE_RDMA_WRITE:
125 wc->opcode = IB_WC_RDMA_WRITE;
126 break;
127 case MLX5_OPCODE_SEND_IMM:
128 wc->wc_flags |= IB_WC_WITH_IMM;
129 /* fall through */
130 case MLX5_OPCODE_SEND:
131 case MLX5_OPCODE_SEND_INVAL:
132 wc->opcode = IB_WC_SEND;
133 break;
134 case MLX5_OPCODE_RDMA_READ:
135 wc->opcode = IB_WC_RDMA_READ;
136 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
137 break;
138 case MLX5_OPCODE_ATOMIC_CS:
139 wc->opcode = IB_WC_COMP_SWAP;
140 wc->byte_len = 8;
141 break;
142 case MLX5_OPCODE_ATOMIC_FA:
143 wc->opcode = IB_WC_FETCH_ADD;
144 wc->byte_len = 8;
145 break;
146 case MLX5_OPCODE_ATOMIC_MASKED_CS:
147 wc->opcode = IB_WC_MASKED_COMP_SWAP;
148 wc->byte_len = 8;
149 break;
150 case MLX5_OPCODE_ATOMIC_MASKED_FA:
151 wc->opcode = IB_WC_MASKED_FETCH_ADD;
152 wc->byte_len = 8;
153 break;
154 case MLX5_OPCODE_UMR:
155 wc->opcode = get_umr_comp(wq, idx);
156 break;
157 }
158 }
159
160 enum {
161 MLX5_GRH_IN_BUFFER = 1,
162 MLX5_GRH_IN_CQE = 2,
163 };
164
165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
166 struct mlx5_ib_qp *qp)
167 {
168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
170 struct mlx5_ib_srq *srq;
171 struct mlx5_ib_wq *wq;
172 u16 wqe_ctr;
173 u8 roce_packet_type;
174 bool vlan_present;
175 u8 g;
176
177 if (qp->ibqp.srq || qp->ibqp.xrcd) {
178 struct mlx5_core_srq *msrq = NULL;
179
180 if (qp->ibqp.xrcd) {
181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
183 } else {
184 srq = to_msrq(qp->ibqp.srq);
185 }
186 if (srq) {
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
190 if (msrq)
191 mlx5_core_res_put(&msrq->common);
192 }
193 } else {
194 wq = &qp->rq;
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
196 ++wq->tail;
197 }
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
199
200 switch (get_cqe_opcode(cqe)) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
205 break;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
211 wc->wc_flags = 0;
212 break;
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
217 break;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
222 break;
223 }
224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
225 wc->dlid_path_bits = cqe->ml_path;
226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
227 wc->wc_flags |= g ? IB_WC_GRH : 0;
228 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
230
231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
232 &wc->pkey_index);
233 } else {
234 wc->pkey_index = 0;
235 }
236
237 if (ll != IB_LINK_LAYER_ETHERNET) {
238 wc->slid = be16_to_cpu(cqe->slid);
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
240 return;
241 }
242
243 wc->slid = 0;
244 vlan_present = cqe->l4_l3_hdr_type & 0x1;
245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
246 if (vlan_present) {
247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
249 wc->wc_flags |= IB_WC_WITH_VLAN;
250 } else {
251 wc->sl = 0;
252 }
253
254 switch (roce_packet_type) {
255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
256 wc->network_hdr_type = RDMA_NETWORK_IB;
257 break;
258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
259 wc->network_hdr_type = RDMA_NETWORK_IPV6;
260 break;
261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
262 wc->network_hdr_type = RDMA_NETWORK_IPV4;
263 break;
264 }
265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
266 }
267
268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
269 {
270 mlx5_ib_warn(dev, "dump error cqe\n");
271 mlx5_dump_err_cqe(dev->mdev, cqe);
272 }
273
274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
275 struct mlx5_err_cqe *cqe,
276 struct ib_wc *wc)
277 {
278 int dump = 1;
279
280 switch (cqe->syndrome) {
281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
282 wc->status = IB_WC_LOC_LEN_ERR;
283 break;
284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
285 wc->status = IB_WC_LOC_QP_OP_ERR;
286 break;
287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
288 wc->status = IB_WC_LOC_PROT_ERR;
289 break;
290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
291 dump = 0;
292 wc->status = IB_WC_WR_FLUSH_ERR;
293 break;
294 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
295 wc->status = IB_WC_MW_BIND_ERR;
296 break;
297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
298 wc->status = IB_WC_BAD_RESP_ERR;
299 break;
300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
301 wc->status = IB_WC_LOC_ACCESS_ERR;
302 break;
303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
304 wc->status = IB_WC_REM_INV_REQ_ERR;
305 break;
306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
307 wc->status = IB_WC_REM_ACCESS_ERR;
308 break;
309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
310 wc->status = IB_WC_REM_OP_ERR;
311 break;
312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
313 wc->status = IB_WC_RETRY_EXC_ERR;
314 dump = 0;
315 break;
316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
317 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
318 dump = 0;
319 break;
320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
321 wc->status = IB_WC_REM_ABORT_ERR;
322 break;
323 default:
324 wc->status = IB_WC_GENERAL_ERR;
325 break;
326 }
327
328 wc->vendor_err = cqe->vendor_err_synd;
329 if (dump)
330 dump_cqe(dev, cqe);
331 }
332
333 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
334 u16 tail, u16 head)
335 {
336 u16 idx;
337
338 do {
339 idx = tail & (qp->sq.wqe_cnt - 1);
340 if (idx == head)
341 break;
342
343 tail = qp->sq.w_list[idx].next;
344 } while (1);
345 tail = qp->sq.w_list[idx].next;
346 qp->sq.last_poll = tail;
347 }
348
349 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
350 {
351 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
352 }
353
354 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
355 struct ib_sig_err *item)
356 {
357 u16 syndrome = be16_to_cpu(cqe->syndrome);
358
359 #define GUARD_ERR (1 << 13)
360 #define APPTAG_ERR (1 << 12)
361 #define REFTAG_ERR (1 << 11)
362
363 if (syndrome & GUARD_ERR) {
364 item->err_type = IB_SIG_BAD_GUARD;
365 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
366 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
367 } else
368 if (syndrome & REFTAG_ERR) {
369 item->err_type = IB_SIG_BAD_REFTAG;
370 item->expected = be32_to_cpu(cqe->expected_reftag);
371 item->actual = be32_to_cpu(cqe->actual_reftag);
372 } else
373 if (syndrome & APPTAG_ERR) {
374 item->err_type = IB_SIG_BAD_APPTAG;
375 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
376 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
377 } else {
378 pr_err("Got signature completion error with bad syndrome %04x\n",
379 syndrome);
380 }
381
382 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
383 item->key = be32_to_cpu(cqe->mkey);
384 }
385
386 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
387 int *npolled, bool is_send)
388 {
389 struct mlx5_ib_wq *wq;
390 unsigned int cur;
391 int np;
392 int i;
393
394 wq = (is_send) ? &qp->sq : &qp->rq;
395 cur = wq->head - wq->tail;
396 np = *npolled;
397
398 if (cur == 0)
399 return;
400
401 for (i = 0; i < cur && np < num_entries; i++) {
402 unsigned int idx;
403
404 idx = (is_send) ? wq->last_poll : wq->tail;
405 idx &= (wq->wqe_cnt - 1);
406 wc->wr_id = wq->wrid[idx];
407 wc->status = IB_WC_WR_FLUSH_ERR;
408 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
409 wq->tail++;
410 if (is_send)
411 wq->last_poll = wq->w_list[idx].next;
412 np++;
413 wc->qp = &qp->ibqp;
414 wc++;
415 }
416 *npolled = np;
417 }
418
419 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
420 struct ib_wc *wc, int *npolled)
421 {
422 struct mlx5_ib_qp *qp;
423
424 *npolled = 0;
425 /* Find uncompleted WQEs belonging to that cq and return mmics ones */
426 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
427 sw_comp(qp, num_entries, wc + *npolled, npolled, true);
428 if (*npolled >= num_entries)
429 return;
430 }
431
432 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
433 sw_comp(qp, num_entries, wc + *npolled, npolled, false);
434 if (*npolled >= num_entries)
435 return;
436 }
437 }
438
439 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
440 struct mlx5_ib_qp **cur_qp,
441 struct ib_wc *wc)
442 {
443 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
444 struct mlx5_err_cqe *err_cqe;
445 struct mlx5_cqe64 *cqe64;
446 struct mlx5_core_qp *mqp;
447 struct mlx5_ib_wq *wq;
448 uint8_t opcode;
449 uint32_t qpn;
450 u16 wqe_ctr;
451 void *cqe;
452 int idx;
453
454 repoll:
455 cqe = next_cqe_sw(cq);
456 if (!cqe)
457 return -EAGAIN;
458
459 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
460
461 ++cq->mcq.cons_index;
462
463 /* Make sure we read CQ entry contents after we've checked the
464 * ownership bit.
465 */
466 rmb();
467
468 opcode = get_cqe_opcode(cqe64);
469 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
470 if (likely(cq->resize_buf)) {
471 free_cq_buf(dev, &cq->buf);
472 cq->buf = *cq->resize_buf;
473 kfree(cq->resize_buf);
474 cq->resize_buf = NULL;
475 goto repoll;
476 } else {
477 mlx5_ib_warn(dev, "unexpected resize cqe\n");
478 }
479 }
480
481 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
482 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
483 /* We do not have to take the QP table lock here,
484 * because CQs will be locked while QPs are removed
485 * from the table.
486 */
487 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
488 *cur_qp = to_mibqp(mqp);
489 }
490
491 wc->qp = &(*cur_qp)->ibqp;
492 switch (opcode) {
493 case MLX5_CQE_REQ:
494 wq = &(*cur_qp)->sq;
495 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
496 idx = wqe_ctr & (wq->wqe_cnt - 1);
497 handle_good_req(wc, cqe64, wq, idx);
498 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
499 wc->wr_id = wq->wrid[idx];
500 wq->tail = wq->wqe_head[idx] + 1;
501 wc->status = IB_WC_SUCCESS;
502 break;
503 case MLX5_CQE_RESP_WR_IMM:
504 case MLX5_CQE_RESP_SEND:
505 case MLX5_CQE_RESP_SEND_IMM:
506 case MLX5_CQE_RESP_SEND_INV:
507 handle_responder(wc, cqe64, *cur_qp);
508 wc->status = IB_WC_SUCCESS;
509 break;
510 case MLX5_CQE_RESIZE_CQ:
511 break;
512 case MLX5_CQE_REQ_ERR:
513 case MLX5_CQE_RESP_ERR:
514 err_cqe = (struct mlx5_err_cqe *)cqe64;
515 mlx5_handle_error_cqe(dev, err_cqe, wc);
516 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
517 opcode == MLX5_CQE_REQ_ERR ?
518 "Requestor" : "Responder", cq->mcq.cqn);
519 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
520 err_cqe->syndrome, err_cqe->vendor_err_synd);
521 if (opcode == MLX5_CQE_REQ_ERR) {
522 wq = &(*cur_qp)->sq;
523 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
524 idx = wqe_ctr & (wq->wqe_cnt - 1);
525 wc->wr_id = wq->wrid[idx];
526 wq->tail = wq->wqe_head[idx] + 1;
527 } else {
528 struct mlx5_ib_srq *srq;
529
530 if ((*cur_qp)->ibqp.srq) {
531 srq = to_msrq((*cur_qp)->ibqp.srq);
532 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
533 wc->wr_id = srq->wrid[wqe_ctr];
534 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
535 } else {
536 wq = &(*cur_qp)->rq;
537 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
538 ++wq->tail;
539 }
540 }
541 break;
542 case MLX5_CQE_SIG_ERR: {
543 struct mlx5_sig_err_cqe *sig_err_cqe =
544 (struct mlx5_sig_err_cqe *)cqe64;
545 struct mlx5_core_sig_ctx *sig;
546
547 xa_lock(&dev->sig_mrs);
548 sig = xa_load(&dev->sig_mrs,
549 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
550 get_sig_err_item(sig_err_cqe, &sig->err_item);
551 sig->sig_err_exists = true;
552 sig->sigerr_count++;
553
554 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
555 cq->mcq.cqn, sig->err_item.key,
556 sig->err_item.err_type,
557 sig->err_item.sig_err_offset,
558 sig->err_item.expected,
559 sig->err_item.actual);
560
561 xa_unlock(&dev->sig_mrs);
562 goto repoll;
563 }
564 }
565
566 return 0;
567 }
568
569 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
570 struct ib_wc *wc, bool is_fatal_err)
571 {
572 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
573 struct mlx5_ib_wc *soft_wc, *next;
574 int npolled = 0;
575
576 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
577 if (npolled >= num_entries)
578 break;
579
580 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
581 cq->mcq.cqn);
582
583 if (unlikely(is_fatal_err)) {
584 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
585 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
586 }
587 wc[npolled++] = soft_wc->wc;
588 list_del(&soft_wc->list);
589 kfree(soft_wc);
590 }
591
592 return npolled;
593 }
594
595 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
596 {
597 struct mlx5_ib_cq *cq = to_mcq(ibcq);
598 struct mlx5_ib_qp *cur_qp = NULL;
599 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
600 struct mlx5_core_dev *mdev = dev->mdev;
601 unsigned long flags;
602 int soft_polled = 0;
603 int npolled;
604
605 spin_lock_irqsave(&cq->lock, flags);
606 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
607 /* make sure no soft wqe's are waiting */
608 if (unlikely(!list_empty(&cq->wc_list)))
609 soft_polled = poll_soft_wc(cq, num_entries, wc, true);
610
611 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
612 wc + soft_polled, &npolled);
613 goto out;
614 }
615
616 if (unlikely(!list_empty(&cq->wc_list)))
617 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
618
619 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
620 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
621 break;
622 }
623
624 if (npolled)
625 mlx5_cq_set_ci(&cq->mcq);
626 out:
627 spin_unlock_irqrestore(&cq->lock, flags);
628
629 return soft_polled + npolled;
630 }
631
632 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
633 {
634 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
635 struct mlx5_ib_cq *cq = to_mcq(ibcq);
636 void __iomem *uar_page = mdev->priv.uar->map;
637 unsigned long irq_flags;
638 int ret = 0;
639
640 spin_lock_irqsave(&cq->lock, irq_flags);
641 if (cq->notify_flags != IB_CQ_NEXT_COMP)
642 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
643
644 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
645 ret = 1;
646 spin_unlock_irqrestore(&cq->lock, irq_flags);
647
648 mlx5_cq_arm(&cq->mcq,
649 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
650 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
651 uar_page, to_mcq(ibcq)->mcq.cons_index);
652
653 return ret;
654 }
655
656 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
657 struct mlx5_ib_cq_buf *buf,
658 int nent,
659 int cqe_size)
660 {
661 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
662 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
663 u8 log_wq_sz = ilog2(cqe_size);
664 int err;
665
666 err = mlx5_frag_buf_alloc_node(dev->mdev,
667 nent * cqe_size,
668 frag_buf,
669 dev->mdev->priv.numa_node);
670 if (err)
671 return err;
672
673 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
674
675 buf->cqe_size = cqe_size;
676 buf->nent = nent;
677
678 return 0;
679 }
680
681 enum {
682 MLX5_CQE_RES_FORMAT_HASH = 0,
683 MLX5_CQE_RES_FORMAT_CSUM = 1,
684 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
685 };
686
687 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
688 {
689 switch (format) {
690 case MLX5_IB_CQE_RES_FORMAT_HASH:
691 return MLX5_CQE_RES_FORMAT_HASH;
692 case MLX5_IB_CQE_RES_FORMAT_CSUM:
693 return MLX5_CQE_RES_FORMAT_CSUM;
694 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
695 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
696 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
697 return -EOPNOTSUPP;
698 default:
699 return -EINVAL;
700 }
701 }
702
703 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
704 struct mlx5_ib_cq *cq, int entries, u32 **cqb,
705 int *cqe_size, int *index, int *inlen)
706 {
707 struct mlx5_ib_create_cq ucmd = {};
708 size_t ucmdlen;
709 int page_shift;
710 __be64 *pas;
711 int npages;
712 int ncont;
713 void *cqc;
714 int err;
715 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
716 udata, struct mlx5_ib_ucontext, ibucontext);
717
718 ucmdlen = min(udata->inlen, sizeof(ucmd));
719 if (ucmdlen < offsetof(struct mlx5_ib_create_cq, flags))
720 return -EINVAL;
721
722 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
723 return -EFAULT;
724
725 if ((ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD |
726 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX)))
727 return -EINVAL;
728
729 if ((ucmd.cqe_size != 64 && ucmd.cqe_size != 128) ||
730 ucmd.reserved0 || ucmd.reserved1)
731 return -EINVAL;
732
733 *cqe_size = ucmd.cqe_size;
734
735 cq->buf.umem =
736 ib_umem_get(&dev->ib_dev, ucmd.buf_addr,
737 entries * ucmd.cqe_size, IB_ACCESS_LOCAL_WRITE);
738 if (IS_ERR(cq->buf.umem)) {
739 err = PTR_ERR(cq->buf.umem);
740 return err;
741 }
742
743 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db);
744 if (err)
745 goto err_umem;
746
747 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
748 &ncont, NULL);
749 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
750 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
751
752 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
753 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
754 *cqb = kvzalloc(*inlen, GFP_KERNEL);
755 if (!*cqb) {
756 err = -ENOMEM;
757 goto err_db;
758 }
759
760 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
761 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
762
763 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
764 MLX5_SET(cqc, cqc, log_page_size,
765 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
766
767 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) {
768 *index = ucmd.uar_page_index;
769 } else if (context->bfregi.lib_uar_dyn) {
770 err = -EINVAL;
771 goto err_cqb;
772 } else {
773 *index = context->bfregi.sys_pages[0];
774 }
775
776 if (ucmd.cqe_comp_en == 1) {
777 int mini_cqe_format;
778
779 if (!((*cqe_size == 128 &&
780 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
781 (*cqe_size == 64 &&
782 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
783 err = -EOPNOTSUPP;
784 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
785 *cqe_size);
786 goto err_cqb;
787 }
788
789 mini_cqe_format =
790 mini_cqe_res_format_to_hw(dev,
791 ucmd.cqe_comp_res_format);
792 if (mini_cqe_format < 0) {
793 err = mini_cqe_format;
794 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
795 ucmd.cqe_comp_res_format, err);
796 goto err_cqb;
797 }
798
799 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
800 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
801 }
802
803 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
804 if (*cqe_size != 128 ||
805 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
806 err = -EOPNOTSUPP;
807 mlx5_ib_warn(dev,
808 "CQE padding is not supported for CQE size of %dB!\n",
809 *cqe_size);
810 goto err_cqb;
811 }
812
813 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
814 }
815
816 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid);
817 return 0;
818
819 err_cqb:
820 kvfree(*cqb);
821
822 err_db:
823 mlx5_ib_db_unmap_user(context, &cq->db);
824
825 err_umem:
826 ib_umem_release(cq->buf.umem);
827 return err;
828 }
829
830 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata)
831 {
832 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
833 udata, struct mlx5_ib_ucontext, ibucontext);
834
835 mlx5_ib_db_unmap_user(context, &cq->db);
836 ib_umem_release(cq->buf.umem);
837 }
838
839 static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
840 struct mlx5_ib_cq_buf *buf)
841 {
842 int i;
843 void *cqe;
844 struct mlx5_cqe64 *cqe64;
845
846 for (i = 0; i < buf->nent; i++) {
847 cqe = get_cqe(cq, i);
848 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
849 cqe64->op_own = MLX5_CQE_INVALID << 4;
850 }
851 }
852
853 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
854 int entries, int cqe_size,
855 u32 **cqb, int *index, int *inlen)
856 {
857 __be64 *pas;
858 void *cqc;
859 int err;
860
861 err = mlx5_db_alloc(dev->mdev, &cq->db);
862 if (err)
863 return err;
864
865 cq->mcq.set_ci_db = cq->db.db;
866 cq->mcq.arm_db = cq->db.db + 1;
867 cq->mcq.cqe_sz = cqe_size;
868
869 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
870 if (err)
871 goto err_db;
872
873 init_cq_frag_buf(cq, &cq->buf);
874
875 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
876 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
877 cq->buf.frag_buf.npages;
878 *cqb = kvzalloc(*inlen, GFP_KERNEL);
879 if (!*cqb) {
880 err = -ENOMEM;
881 goto err_buf;
882 }
883
884 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
885 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
886
887 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
888 MLX5_SET(cqc, cqc, log_page_size,
889 cq->buf.frag_buf.page_shift -
890 MLX5_ADAPTER_PAGE_SHIFT);
891
892 *index = dev->mdev->priv.uar->index;
893
894 return 0;
895
896 err_buf:
897 free_cq_buf(dev, &cq->buf);
898
899 err_db:
900 mlx5_db_free(dev->mdev, &cq->db);
901 return err;
902 }
903
904 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
905 {
906 free_cq_buf(dev, &cq->buf);
907 mlx5_db_free(dev->mdev, &cq->db);
908 }
909
910 static void notify_soft_wc_handler(struct work_struct *work)
911 {
912 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
913 notify_work);
914
915 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
916 }
917
918 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
919 struct ib_udata *udata)
920 {
921 struct ib_device *ibdev = ibcq->device;
922 int entries = attr->cqe;
923 int vector = attr->comp_vector;
924 struct mlx5_ib_dev *dev = to_mdev(ibdev);
925 struct mlx5_ib_cq *cq = to_mcq(ibcq);
926 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
927 int uninitialized_var(index);
928 int uninitialized_var(inlen);
929 u32 *cqb = NULL;
930 void *cqc;
931 int cqe_size;
932 unsigned int irqn;
933 int eqn;
934 int err;
935
936 if (entries < 0 ||
937 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
938 return -EINVAL;
939
940 if (check_cq_create_flags(attr->flags))
941 return -EOPNOTSUPP;
942
943 entries = roundup_pow_of_two(entries + 1);
944 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
945 return -EINVAL;
946
947 cq->ibcq.cqe = entries - 1;
948 mutex_init(&cq->resize_mutex);
949 spin_lock_init(&cq->lock);
950 cq->resize_buf = NULL;
951 cq->resize_umem = NULL;
952 cq->create_flags = attr->flags;
953 INIT_LIST_HEAD(&cq->list_send_qp);
954 INIT_LIST_HEAD(&cq->list_recv_qp);
955
956 if (udata) {
957 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size,
958 &index, &inlen);
959 if (err)
960 return err;
961 } else {
962 cqe_size = cache_line_size() == 128 ? 128 : 64;
963 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
964 &index, &inlen);
965 if (err)
966 return err;
967
968 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
969 }
970
971 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
972 if (err)
973 goto err_cqb;
974
975 cq->cqe_size = cqe_size;
976
977 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
978 MLX5_SET(cqc, cqc, cqe_sz,
979 cqe_sz_to_mlx_sz(cqe_size,
980 cq->private_flags &
981 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
982 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
983 MLX5_SET(cqc, cqc, uar_page, index);
984 MLX5_SET(cqc, cqc, c_eqn, eqn);
985 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
986 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
987 MLX5_SET(cqc, cqc, oi, 1);
988
989 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out));
990 if (err)
991 goto err_cqb;
992
993 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
994 cq->mcq.irqn = irqn;
995 if (udata)
996 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
997 else
998 cq->mcq.comp = mlx5_ib_cq_comp;
999 cq->mcq.event = mlx5_ib_cq_event;
1000
1001 INIT_LIST_HEAD(&cq->wc_list);
1002
1003 if (udata)
1004 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1005 err = -EFAULT;
1006 goto err_cmd;
1007 }
1008
1009
1010 kvfree(cqb);
1011 return 0;
1012
1013 err_cmd:
1014 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1015
1016 err_cqb:
1017 kvfree(cqb);
1018 if (udata)
1019 destroy_cq_user(cq, udata);
1020 else
1021 destroy_cq_kernel(dev, cq);
1022 return err;
1023 }
1024
1025 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata)
1026 {
1027 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1028 struct mlx5_ib_cq *mcq = to_mcq(cq);
1029
1030 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1031 if (udata)
1032 destroy_cq_user(mcq, udata);
1033 else
1034 destroy_cq_kernel(dev, mcq);
1035 }
1036
1037 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1038 {
1039 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1040 }
1041
1042 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1043 {
1044 struct mlx5_cqe64 *cqe64, *dest64;
1045 void *cqe, *dest;
1046 u32 prod_index;
1047 int nfreed = 0;
1048 u8 owner_bit;
1049
1050 if (!cq)
1051 return;
1052
1053 /* First we need to find the current producer index, so we
1054 * know where to start cleaning from. It doesn't matter if HW
1055 * adds new entries after this loop -- the QP we're worried
1056 * about is already in RESET, so the new entries won't come
1057 * from our QP and therefore don't need to be checked.
1058 */
1059 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1060 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1061 break;
1062
1063 /* Now sweep backwards through the CQ, removing CQ entries
1064 * that match our QP by copying older entries on top of them.
1065 */
1066 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1067 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1068 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1069 if (is_equal_rsn(cqe64, rsn)) {
1070 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1071 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1072 ++nfreed;
1073 } else if (nfreed) {
1074 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1075 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1076 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1077 memcpy(dest, cqe, cq->mcq.cqe_sz);
1078 dest64->op_own = owner_bit |
1079 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1080 }
1081 }
1082
1083 if (nfreed) {
1084 cq->mcq.cons_index += nfreed;
1085 /* Make sure update of buffer contents is done before
1086 * updating consumer index.
1087 */
1088 wmb();
1089 mlx5_cq_set_ci(&cq->mcq);
1090 }
1091 }
1092
1093 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1094 {
1095 if (!cq)
1096 return;
1097
1098 spin_lock_irq(&cq->lock);
1099 __mlx5_ib_cq_clean(cq, qpn, srq);
1100 spin_unlock_irq(&cq->lock);
1101 }
1102
1103 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1104 {
1105 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1106 struct mlx5_ib_cq *mcq = to_mcq(cq);
1107 int err;
1108
1109 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1110 return -EOPNOTSUPP;
1111
1112 if (cq_period > MLX5_MAX_CQ_PERIOD)
1113 return -EINVAL;
1114
1115 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1116 cq_period, cq_count);
1117 if (err)
1118 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1119
1120 return err;
1121 }
1122
1123 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1124 int entries, struct ib_udata *udata, int *npas,
1125 int *page_shift, int *cqe_size)
1126 {
1127 struct mlx5_ib_resize_cq ucmd;
1128 struct ib_umem *umem;
1129 int err;
1130 int npages;
1131
1132 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1133 if (err)
1134 return err;
1135
1136 if (ucmd.reserved0 || ucmd.reserved1)
1137 return -EINVAL;
1138
1139 /* check multiplication overflow */
1140 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1141 return -EINVAL;
1142
1143 umem = ib_umem_get(&dev->ib_dev, ucmd.buf_addr,
1144 (size_t)ucmd.cqe_size * entries,
1145 IB_ACCESS_LOCAL_WRITE);
1146 if (IS_ERR(umem)) {
1147 err = PTR_ERR(umem);
1148 return err;
1149 }
1150
1151 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1152 npas, NULL);
1153
1154 cq->resize_umem = umem;
1155 *cqe_size = ucmd.cqe_size;
1156
1157 return 0;
1158 }
1159
1160 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1161 int entries, int cqe_size)
1162 {
1163 int err;
1164
1165 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1166 if (!cq->resize_buf)
1167 return -ENOMEM;
1168
1169 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1170 if (err)
1171 goto ex;
1172
1173 init_cq_frag_buf(cq, cq->resize_buf);
1174
1175 return 0;
1176
1177 ex:
1178 kfree(cq->resize_buf);
1179 return err;
1180 }
1181
1182 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1183 {
1184 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1185 struct mlx5_cqe64 *scqe64;
1186 struct mlx5_cqe64 *dcqe64;
1187 void *start_cqe;
1188 void *scqe;
1189 void *dcqe;
1190 int ssize;
1191 int dsize;
1192 int i;
1193 u8 sw_own;
1194
1195 ssize = cq->buf.cqe_size;
1196 dsize = cq->resize_buf->cqe_size;
1197 if (ssize != dsize) {
1198 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1199 return -EINVAL;
1200 }
1201
1202 i = cq->mcq.cons_index;
1203 scqe = get_sw_cqe(cq, i);
1204 scqe64 = ssize == 64 ? scqe : scqe + 64;
1205 start_cqe = scqe;
1206 if (!scqe) {
1207 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1208 return -EINVAL;
1209 }
1210
1211 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) {
1212 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1213 (i + 1) & cq->resize_buf->nent);
1214 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1215 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1216 memcpy(dcqe, scqe, dsize);
1217 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1218
1219 ++i;
1220 scqe = get_sw_cqe(cq, i);
1221 scqe64 = ssize == 64 ? scqe : scqe + 64;
1222 if (!scqe) {
1223 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1224 return -EINVAL;
1225 }
1226
1227 if (scqe == start_cqe) {
1228 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1229 cq->mcq.cqn);
1230 return -ENOMEM;
1231 }
1232 }
1233 ++cq->mcq.cons_index;
1234 return 0;
1235 }
1236
1237 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1238 {
1239 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1240 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1241 void *cqc;
1242 u32 *in;
1243 int err;
1244 int npas;
1245 __be64 *pas;
1246 int page_shift;
1247 int inlen;
1248 int uninitialized_var(cqe_size);
1249 unsigned long flags;
1250
1251 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1252 pr_info("Firmware does not support resize CQ\n");
1253 return -ENOSYS;
1254 }
1255
1256 if (entries < 1 ||
1257 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1258 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1259 entries,
1260 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1261 return -EINVAL;
1262 }
1263
1264 entries = roundup_pow_of_two(entries + 1);
1265 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1266 return -EINVAL;
1267
1268 if (entries == ibcq->cqe + 1)
1269 return 0;
1270
1271 mutex_lock(&cq->resize_mutex);
1272 if (udata) {
1273 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1274 &cqe_size);
1275 } else {
1276 cqe_size = 64;
1277 err = resize_kernel(dev, cq, entries, cqe_size);
1278 if (!err) {
1279 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1280
1281 npas = frag_buf->npages;
1282 page_shift = frag_buf->page_shift;
1283 }
1284 }
1285
1286 if (err)
1287 goto ex;
1288
1289 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1290 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1291
1292 in = kvzalloc(inlen, GFP_KERNEL);
1293 if (!in) {
1294 err = -ENOMEM;
1295 goto ex_resize;
1296 }
1297
1298 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1299 if (udata)
1300 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1301 pas, 0);
1302 else
1303 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1304
1305 MLX5_SET(modify_cq_in, in,
1306 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1307 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1308 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1309 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1310
1311 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1312
1313 MLX5_SET(cqc, cqc, log_page_size,
1314 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1315 MLX5_SET(cqc, cqc, cqe_sz,
1316 cqe_sz_to_mlx_sz(cqe_size,
1317 cq->private_flags &
1318 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1319 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1320
1321 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1322 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1323
1324 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1325 if (err)
1326 goto ex_alloc;
1327
1328 if (udata) {
1329 cq->ibcq.cqe = entries - 1;
1330 ib_umem_release(cq->buf.umem);
1331 cq->buf.umem = cq->resize_umem;
1332 cq->resize_umem = NULL;
1333 } else {
1334 struct mlx5_ib_cq_buf tbuf;
1335 int resized = 0;
1336
1337 spin_lock_irqsave(&cq->lock, flags);
1338 if (cq->resize_buf) {
1339 err = copy_resize_cqes(cq);
1340 if (!err) {
1341 tbuf = cq->buf;
1342 cq->buf = *cq->resize_buf;
1343 kfree(cq->resize_buf);
1344 cq->resize_buf = NULL;
1345 resized = 1;
1346 }
1347 }
1348 cq->ibcq.cqe = entries - 1;
1349 spin_unlock_irqrestore(&cq->lock, flags);
1350 if (resized)
1351 free_cq_buf(dev, &tbuf);
1352 }
1353 mutex_unlock(&cq->resize_mutex);
1354
1355 kvfree(in);
1356 return 0;
1357
1358 ex_alloc:
1359 kvfree(in);
1360
1361 ex_resize:
1362 ib_umem_release(cq->resize_umem);
1363 if (!udata) {
1364 free_cq_buf(dev, cq->resize_buf);
1365 cq->resize_buf = NULL;
1366 }
1367 ex:
1368 mutex_unlock(&cq->resize_mutex);
1369 return err;
1370 }
1371
1372 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1373 {
1374 struct mlx5_ib_cq *cq;
1375
1376 if (!ibcq)
1377 return 128;
1378
1379 cq = to_mcq(ibcq);
1380 return cq->cqe_size;
1381 }
1382
1383 /* Called from atomic context */
1384 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1385 {
1386 struct mlx5_ib_wc *soft_wc;
1387 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1388 unsigned long flags;
1389
1390 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1391 if (!soft_wc)
1392 return -ENOMEM;
1393
1394 soft_wc->wc = *wc;
1395 spin_lock_irqsave(&cq->lock, flags);
1396 list_add_tail(&soft_wc->list, &cq->wc_list);
1397 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1398 wc->status != IB_WC_SUCCESS) {
1399 cq->notify_flags = 0;
1400 schedule_work(&cq->notify_work);
1401 }
1402 spin_unlock_irqrestore(&cq->lock, flags);
1403
1404 return 0;
1405 }
Linux with added FPC-III support