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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / infiniband / hw / mlx5 / main.c
blob6679756506e605d115c41f2b25b86b7caeae2d25
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #include <linux/sched.h>
43 #include <linux/sched/mm.h>
44 #include <linux/sched/task.h>
45 #include <linux/delay.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_addr.h>
48 #include <rdma/ib_cache.h>
49 #include <linux/mlx5/port.h>
50 #include <linux/mlx5/vport.h>
51 #include <linux/mlx5/fs.h>
52 #include <linux/mlx5/eswitch.h>
53 #include <linux/list.h>
54 #include <rdma/ib_smi.h>
55 #include <rdma/ib_umem.h>
56 #include <linux/in.h>
57 #include <linux/etherdevice.h>
58 #include "mlx5_ib.h"
59 #include "ib_rep.h"
60 #include "cmd.h"
61 #include "srq.h"
62 #include <linux/mlx5/fs_helpers.h>
63 #include <linux/mlx5/accel.h>
64 #include <rdma/uverbs_std_types.h>
65 #include <rdma/mlx5_user_ioctl_verbs.h>
66 #include <rdma/mlx5_user_ioctl_cmds.h>
67 #include <rdma/ib_umem_odp.h>
68
69 #define UVERBS_MODULE_NAME mlx5_ib
70 #include <rdma/uverbs_named_ioctl.h>
71
72 #define DRIVER_NAME "mlx5_ib"
73 #define DRIVER_VERSION "5.0-0"
74
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
81 DRIVER_VERSION "\n";
82
83 struct mlx5_ib_event_work {
84 struct work_struct work;
85 union {
86 struct mlx5_ib_dev *dev;
87 struct mlx5_ib_multiport_info *mpi;
88 };
89 bool is_slave;
90 unsigned int event;
91 void *param;
92 };
93
94 enum {
95 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
96 };
97
98 static struct workqueue_struct *mlx5_ib_event_wq;
99 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
100 static LIST_HEAD(mlx5_ib_dev_list);
101 /*
102 * This mutex should be held when accessing either of the above lists
103 */
104 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
105
106 /* We can't use an array for xlt_emergency_page because dma_map_single
107 * doesn't work on kernel modules memory
108 */
109 static unsigned long xlt_emergency_page;
110 static struct mutex xlt_emergency_page_mutex;
111
112 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
113 {
114 struct mlx5_ib_dev *dev;
115
116 mutex_lock(&mlx5_ib_multiport_mutex);
117 dev = mpi->ibdev;
118 mutex_unlock(&mlx5_ib_multiport_mutex);
119 return dev;
120 }
121
122 static enum rdma_link_layer
123 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
124 {
125 switch (port_type_cap) {
126 case MLX5_CAP_PORT_TYPE_IB:
127 return IB_LINK_LAYER_INFINIBAND;
128 case MLX5_CAP_PORT_TYPE_ETH:
129 return IB_LINK_LAYER_ETHERNET;
130 default:
131 return IB_LINK_LAYER_UNSPECIFIED;
132 }
133 }
134
135 static enum rdma_link_layer
136 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
137 {
138 struct mlx5_ib_dev *dev = to_mdev(device);
139 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
140
141 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
142 }
143
144 static int get_port_state(struct ib_device *ibdev,
145 u8 port_num,
146 enum ib_port_state *state)
147 {
148 struct ib_port_attr attr;
149 int ret;
150
151 memset(&attr, 0, sizeof(attr));
152 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
153 if (!ret)
154 *state = attr.state;
155 return ret;
156 }
157
158 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
159 struct net_device *ndev,
160 u8 *port_num)
161 {
162 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
163 struct net_device *rep_ndev;
164 struct mlx5_ib_port *port;
165 int i;
166
167 for (i = 0; i < dev->num_ports; i++) {
168 port = &dev->port[i];
169 if (!port->rep)
170 continue;
171
172 read_lock(&port->roce.netdev_lock);
173 rep_ndev = mlx5_ib_get_rep_netdev(esw,
174 port->rep->vport);
175 if (rep_ndev == ndev) {
176 read_unlock(&port->roce.netdev_lock);
177 *port_num = i + 1;
178 return &port->roce;
179 }
180 read_unlock(&port->roce.netdev_lock);
181 }
182
183 return NULL;
184 }
185
186 static int mlx5_netdev_event(struct notifier_block *this,
187 unsigned long event, void *ptr)
188 {
189 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
190 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
191 u8 port_num = roce->native_port_num;
192 struct mlx5_core_dev *mdev;
193 struct mlx5_ib_dev *ibdev;
194
195 ibdev = roce->dev;
196 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
197 if (!mdev)
198 return NOTIFY_DONE;
199
200 switch (event) {
201 case NETDEV_REGISTER:
202 /* Should already be registered during the load */
203 if (ibdev->is_rep)
204 break;
205 write_lock(&roce->netdev_lock);
206 if (ndev->dev.parent == mdev->device)
207 roce->netdev = ndev;
208 write_unlock(&roce->netdev_lock);
209 break;
210
211 case NETDEV_UNREGISTER:
212 /* In case of reps, ib device goes away before the netdevs */
213 write_lock(&roce->netdev_lock);
214 if (roce->netdev == ndev)
215 roce->netdev = NULL;
216 write_unlock(&roce->netdev_lock);
217 break;
218
219 case NETDEV_CHANGE:
220 case NETDEV_UP:
221 case NETDEV_DOWN: {
222 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
223 struct net_device *upper = NULL;
224
225 if (lag_ndev) {
226 upper = netdev_master_upper_dev_get(lag_ndev);
227 dev_put(lag_ndev);
228 }
229
230 if (ibdev->is_rep)
231 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
232 if (!roce)
233 return NOTIFY_DONE;
234 if ((upper == ndev || (!upper && ndev == roce->netdev))
235 && ibdev->ib_active) {
236 struct ib_event ibev = { };
237 enum ib_port_state port_state;
238
239 if (get_port_state(&ibdev->ib_dev, port_num,
240 &port_state))
241 goto done;
242
243 if (roce->last_port_state == port_state)
244 goto done;
245
246 roce->last_port_state = port_state;
247 ibev.device = &ibdev->ib_dev;
248 if (port_state == IB_PORT_DOWN)
249 ibev.event = IB_EVENT_PORT_ERR;
250 else if (port_state == IB_PORT_ACTIVE)
251 ibev.event = IB_EVENT_PORT_ACTIVE;
252 else
253 goto done;
254
255 ibev.element.port_num = port_num;
256 ib_dispatch_event(&ibev);
257 }
258 break;
259 }
260
261 default:
262 break;
263 }
264 done:
265 mlx5_ib_put_native_port_mdev(ibdev, port_num);
266 return NOTIFY_DONE;
267 }
268
269 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
270 u8 port_num)
271 {
272 struct mlx5_ib_dev *ibdev = to_mdev(device);
273 struct net_device *ndev;
274 struct mlx5_core_dev *mdev;
275
276 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
277 if (!mdev)
278 return NULL;
279
280 ndev = mlx5_lag_get_roce_netdev(mdev);
281 if (ndev)
282 goto out;
283
284 /* Ensure ndev does not disappear before we invoke dev_hold()
285 */
286 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
287 ndev = ibdev->port[port_num - 1].roce.netdev;
288 if (ndev)
289 dev_hold(ndev);
290 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
291
292 out:
293 mlx5_ib_put_native_port_mdev(ibdev, port_num);
294 return ndev;
295 }
296
297 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
298 u8 ib_port_num,
299 u8 *native_port_num)
300 {
301 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
302 ib_port_num);
303 struct mlx5_core_dev *mdev = NULL;
304 struct mlx5_ib_multiport_info *mpi;
305 struct mlx5_ib_port *port;
306
307 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
308 ll != IB_LINK_LAYER_ETHERNET) {
309 if (native_port_num)
310 *native_port_num = ib_port_num;
311 return ibdev->mdev;
312 }
313
314 if (native_port_num)
315 *native_port_num = 1;
316
317 port = &ibdev->port[ib_port_num - 1];
318 if (!port)
319 return NULL;
320
321 spin_lock(&port->mp.mpi_lock);
322 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
323 if (mpi && !mpi->unaffiliate) {
324 mdev = mpi->mdev;
325 /* If it's the master no need to refcount, it'll exist
326 * as long as the ib_dev exists.
327 */
328 if (!mpi->is_master)
329 mpi->mdev_refcnt++;
330 }
331 spin_unlock(&port->mp.mpi_lock);
332
333 return mdev;
334 }
335
336 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
337 {
338 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
339 port_num);
340 struct mlx5_ib_multiport_info *mpi;
341 struct mlx5_ib_port *port;
342
343 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
344 return;
345
346 port = &ibdev->port[port_num - 1];
347
348 spin_lock(&port->mp.mpi_lock);
349 mpi = ibdev->port[port_num - 1].mp.mpi;
350 if (mpi->is_master)
351 goto out;
352
353 mpi->mdev_refcnt--;
354 if (mpi->unaffiliate)
355 complete(&mpi->unref_comp);
356 out:
357 spin_unlock(&port->mp.mpi_lock);
358 }
359
360 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
361 u8 *active_width)
362 {
363 switch (eth_proto_oper) {
364 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
365 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
366 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
368 *active_width = IB_WIDTH_1X;
369 *active_speed = IB_SPEED_SDR;
370 break;
371 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
372 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
378 *active_width = IB_WIDTH_1X;
379 *active_speed = IB_SPEED_QDR;
380 break;
381 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
382 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
384 *active_width = IB_WIDTH_1X;
385 *active_speed = IB_SPEED_EDR;
386 break;
387 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
388 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
391 *active_width = IB_WIDTH_4X;
392 *active_speed = IB_SPEED_QDR;
393 break;
394 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
395 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_HDR;
399 break;
400 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_FDR;
403 break;
404 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
405 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
408 *active_width = IB_WIDTH_4X;
409 *active_speed = IB_SPEED_EDR;
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 return 0;
416 }
417
418 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
419 u8 *active_width)
420 {
421 switch (eth_proto_oper) {
422 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
423 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
424 *active_width = IB_WIDTH_1X;
425 *active_speed = IB_SPEED_SDR;
426 break;
427 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
428 *active_width = IB_WIDTH_1X;
429 *active_speed = IB_SPEED_DDR;
430 break;
431 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
432 *active_width = IB_WIDTH_1X;
433 *active_speed = IB_SPEED_QDR;
434 break;
435 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
436 *active_width = IB_WIDTH_4X;
437 *active_speed = IB_SPEED_QDR;
438 break;
439 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
440 *active_width = IB_WIDTH_1X;
441 *active_speed = IB_SPEED_EDR;
442 break;
443 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
444 *active_width = IB_WIDTH_2X;
445 *active_speed = IB_SPEED_EDR;
446 break;
447 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
448 *active_width = IB_WIDTH_1X;
449 *active_speed = IB_SPEED_HDR;
450 break;
451 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
452 *active_width = IB_WIDTH_4X;
453 *active_speed = IB_SPEED_EDR;
454 break;
455 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
456 *active_width = IB_WIDTH_2X;
457 *active_speed = IB_SPEED_HDR;
458 break;
459 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
460 *active_width = IB_WIDTH_4X;
461 *active_speed = IB_SPEED_HDR;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468 }
469
470 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
471 u8 *active_width, bool ext)
472 {
473 return ext ?
474 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
475 active_width) :
476 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
477 active_width);
478 }
479
480 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
481 struct ib_port_attr *props)
482 {
483 struct mlx5_ib_dev *dev = to_mdev(device);
484 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
485 struct mlx5_core_dev *mdev;
486 struct net_device *ndev, *upper;
487 enum ib_mtu ndev_ib_mtu;
488 bool put_mdev = true;
489 u16 qkey_viol_cntr;
490 u32 eth_prot_oper;
491 u8 mdev_port_num;
492 bool ext;
493 int err;
494
495 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
496 if (!mdev) {
497 /* This means the port isn't affiliated yet. Get the
498 * info for the master port instead.
499 */
500 put_mdev = false;
501 mdev = dev->mdev;
502 mdev_port_num = 1;
503 port_num = 1;
504 }
505
506 /* Possible bad flows are checked before filling out props so in case
507 * of an error it will still be zeroed out.
508 * Use native port in case of reps
509 */
510 if (dev->is_rep)
511 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
512 1);
513 else
514 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
515 mdev_port_num);
516 if (err)
517 goto out;
518 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
519 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
520
521 props->active_width = IB_WIDTH_4X;
522 props->active_speed = IB_SPEED_QDR;
523
524 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
525 &props->active_width, ext);
526
527 props->port_cap_flags |= IB_PORT_CM_SUP;
528 props->ip_gids = true;
529
530 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
531 roce_address_table_size);
532 props->max_mtu = IB_MTU_4096;
533 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
534 props->pkey_tbl_len = 1;
535 props->state = IB_PORT_DOWN;
536 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
537
538 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
539 props->qkey_viol_cntr = qkey_viol_cntr;
540
541 /* If this is a stub query for an unaffiliated port stop here */
542 if (!put_mdev)
543 goto out;
544
545 ndev = mlx5_ib_get_netdev(device, port_num);
546 if (!ndev)
547 goto out;
548
549 if (dev->lag_active) {
550 rcu_read_lock();
551 upper = netdev_master_upper_dev_get_rcu(ndev);
552 if (upper) {
553 dev_put(ndev);
554 ndev = upper;
555 dev_hold(ndev);
556 }
557 rcu_read_unlock();
558 }
559
560 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
561 props->state = IB_PORT_ACTIVE;
562 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
563 }
564
565 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
566
567 dev_put(ndev);
568
569 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
570 out:
571 if (put_mdev)
572 mlx5_ib_put_native_port_mdev(dev, port_num);
573 return err;
574 }
575
576 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
577 unsigned int index, const union ib_gid *gid,
578 const struct ib_gid_attr *attr)
579 {
580 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
581 u16 vlan_id = 0xffff;
582 u8 roce_version = 0;
583 u8 roce_l3_type = 0;
584 u8 mac[ETH_ALEN];
585 int ret;
586
587 if (gid) {
588 gid_type = attr->gid_type;
589 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
590 if (ret)
591 return ret;
592 }
593
594 switch (gid_type) {
595 case IB_GID_TYPE_IB:
596 roce_version = MLX5_ROCE_VERSION_1;
597 break;
598 case IB_GID_TYPE_ROCE_UDP_ENCAP:
599 roce_version = MLX5_ROCE_VERSION_2;
600 if (ipv6_addr_v4mapped((void *)gid))
601 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
602 else
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
604 break;
605
606 default:
607 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
608 }
609
610 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
611 roce_l3_type, gid->raw, mac,
612 vlan_id < VLAN_CFI_MASK, vlan_id,
613 port_num);
614 }
615
616 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
617 __always_unused void **context)
618 {
619 return set_roce_addr(to_mdev(attr->device), attr->port_num,
620 attr->index, &attr->gid, attr);
621 }
622
623 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
624 __always_unused void **context)
625 {
626 return set_roce_addr(to_mdev(attr->device), attr->port_num,
627 attr->index, NULL, NULL);
628 }
629
630 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
631 const struct ib_gid_attr *attr)
632 {
633 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
634 return 0;
635
636 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
637 }
638
639 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
640 {
641 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
642 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
643 return 0;
644 }
645
646 enum {
647 MLX5_VPORT_ACCESS_METHOD_MAD,
648 MLX5_VPORT_ACCESS_METHOD_HCA,
649 MLX5_VPORT_ACCESS_METHOD_NIC,
650 };
651
652 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
653 {
654 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
655 return MLX5_VPORT_ACCESS_METHOD_MAD;
656
657 if (mlx5_ib_port_link_layer(ibdev, 1) ==
658 IB_LINK_LAYER_ETHERNET)
659 return MLX5_VPORT_ACCESS_METHOD_NIC;
660
661 return MLX5_VPORT_ACCESS_METHOD_HCA;
662 }
663
664 static void get_atomic_caps(struct mlx5_ib_dev *dev,
665 u8 atomic_size_qp,
666 struct ib_device_attr *props)
667 {
668 u8 tmp;
669 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
670 u8 atomic_req_8B_endianness_mode =
671 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
672
673 /* Check if HW supports 8 bytes standard atomic operations and capable
674 * of host endianness respond
675 */
676 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
677 if (((atomic_operations & tmp) == tmp) &&
678 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
679 (atomic_req_8B_endianness_mode)) {
680 props->atomic_cap = IB_ATOMIC_HCA;
681 } else {
682 props->atomic_cap = IB_ATOMIC_NONE;
683 }
684 }
685
686 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
687 struct ib_device_attr *props)
688 {
689 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
690
691 get_atomic_caps(dev, atomic_size_qp, props);
692 }
693
694 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
695 __be64 *sys_image_guid)
696 {
697 struct mlx5_ib_dev *dev = to_mdev(ibdev);
698 struct mlx5_core_dev *mdev = dev->mdev;
699 u64 tmp;
700 int err;
701
702 switch (mlx5_get_vport_access_method(ibdev)) {
703 case MLX5_VPORT_ACCESS_METHOD_MAD:
704 return mlx5_query_mad_ifc_system_image_guid(ibdev,
705 sys_image_guid);
706
707 case MLX5_VPORT_ACCESS_METHOD_HCA:
708 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
709 break;
710
711 case MLX5_VPORT_ACCESS_METHOD_NIC:
712 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
713 break;
714
715 default:
716 return -EINVAL;
717 }
718
719 if (!err)
720 *sys_image_guid = cpu_to_be64(tmp);
721
722 return err;
723
724 }
725
726 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
727 u16 *max_pkeys)
728 {
729 struct mlx5_ib_dev *dev = to_mdev(ibdev);
730 struct mlx5_core_dev *mdev = dev->mdev;
731
732 switch (mlx5_get_vport_access_method(ibdev)) {
733 case MLX5_VPORT_ACCESS_METHOD_MAD:
734 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
735
736 case MLX5_VPORT_ACCESS_METHOD_HCA:
737 case MLX5_VPORT_ACCESS_METHOD_NIC:
738 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
739 pkey_table_size));
740 return 0;
741
742 default:
743 return -EINVAL;
744 }
745 }
746
747 static int mlx5_query_vendor_id(struct ib_device *ibdev,
748 u32 *vendor_id)
749 {
750 struct mlx5_ib_dev *dev = to_mdev(ibdev);
751
752 switch (mlx5_get_vport_access_method(ibdev)) {
753 case MLX5_VPORT_ACCESS_METHOD_MAD:
754 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
755
756 case MLX5_VPORT_ACCESS_METHOD_HCA:
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
759
760 default:
761 return -EINVAL;
762 }
763 }
764
765 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
766 __be64 *node_guid)
767 {
768 u64 tmp;
769 int err;
770
771 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
772 case MLX5_VPORT_ACCESS_METHOD_MAD:
773 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
774
775 case MLX5_VPORT_ACCESS_METHOD_HCA:
776 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
777 break;
778
779 case MLX5_VPORT_ACCESS_METHOD_NIC:
780 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
781 break;
782
783 default:
784 return -EINVAL;
785 }
786
787 if (!err)
788 *node_guid = cpu_to_be64(tmp);
789
790 return err;
791 }
792
793 struct mlx5_reg_node_desc {
794 u8 desc[IB_DEVICE_NODE_DESC_MAX];
795 };
796
797 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
798 {
799 struct mlx5_reg_node_desc in;
800
801 if (mlx5_use_mad_ifc(dev))
802 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
803
804 memset(&in, 0, sizeof(in));
805
806 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
807 sizeof(struct mlx5_reg_node_desc),
808 MLX5_REG_NODE_DESC, 0, 0);
809 }
810
811 static int mlx5_ib_query_device(struct ib_device *ibdev,
812 struct ib_device_attr *props,
813 struct ib_udata *uhw)
814 {
815 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
816 struct mlx5_ib_dev *dev = to_mdev(ibdev);
817 struct mlx5_core_dev *mdev = dev->mdev;
818 int err = -ENOMEM;
819 int max_sq_desc;
820 int max_rq_sg;
821 int max_sq_sg;
822 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
823 bool raw_support = !mlx5_core_mp_enabled(mdev);
824 struct mlx5_ib_query_device_resp resp = {};
825 size_t resp_len;
826 u64 max_tso;
827
828 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
829 if (uhw_outlen && uhw_outlen < resp_len)
830 return -EINVAL;
831
832 resp.response_length = resp_len;
833
834 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
835 return -EINVAL;
836
837 memset(props, 0, sizeof(*props));
838 err = mlx5_query_system_image_guid(ibdev,
839 &props->sys_image_guid);
840 if (err)
841 return err;
842
843 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
844 if (err)
845 return err;
846
847 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
848 if (err)
849 return err;
850
851 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
852 (fw_rev_min(dev->mdev) << 16) |
853 fw_rev_sub(dev->mdev);
854 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
855 IB_DEVICE_PORT_ACTIVE_EVENT |
856 IB_DEVICE_SYS_IMAGE_GUID |
857 IB_DEVICE_RC_RNR_NAK_GEN;
858
859 if (MLX5_CAP_GEN(mdev, pkv))
860 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
861 if (MLX5_CAP_GEN(mdev, qkv))
862 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
863 if (MLX5_CAP_GEN(mdev, apm))
864 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
865 if (MLX5_CAP_GEN(mdev, xrc))
866 props->device_cap_flags |= IB_DEVICE_XRC;
867 if (MLX5_CAP_GEN(mdev, imaicl)) {
868 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
869 IB_DEVICE_MEM_WINDOW_TYPE_2B;
870 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
871 /* We support 'Gappy' memory registration too */
872 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
873 }
874 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
875 if (MLX5_CAP_GEN(mdev, sho)) {
876 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
877 /* At this stage no support for signature handover */
878 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
879 IB_PROT_T10DIF_TYPE_2 |
880 IB_PROT_T10DIF_TYPE_3;
881 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
882 IB_GUARD_T10DIF_CSUM;
883 }
884 if (MLX5_CAP_GEN(mdev, block_lb_mc))
885 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
886
887 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
888 if (MLX5_CAP_ETH(mdev, csum_cap)) {
889 /* Legacy bit to support old userspace libraries */
890 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
891 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
892 }
893
894 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
895 props->raw_packet_caps |=
896 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
897
898 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
899 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
900 if (max_tso) {
901 resp.tso_caps.max_tso = 1 << max_tso;
902 resp.tso_caps.supported_qpts |=
903 1 << IB_QPT_RAW_PACKET;
904 resp.response_length += sizeof(resp.tso_caps);
905 }
906 }
907
908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
909 resp.rss_caps.rx_hash_function =
910 MLX5_RX_HASH_FUNC_TOEPLITZ;
911 resp.rss_caps.rx_hash_fields_mask =
912 MLX5_RX_HASH_SRC_IPV4 |
913 MLX5_RX_HASH_DST_IPV4 |
914 MLX5_RX_HASH_SRC_IPV6 |
915 MLX5_RX_HASH_DST_IPV6 |
916 MLX5_RX_HASH_SRC_PORT_TCP |
917 MLX5_RX_HASH_DST_PORT_TCP |
918 MLX5_RX_HASH_SRC_PORT_UDP |
919 MLX5_RX_HASH_DST_PORT_UDP |
920 MLX5_RX_HASH_INNER;
921 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
922 MLX5_ACCEL_IPSEC_CAP_DEVICE)
923 resp.rss_caps.rx_hash_fields_mask |=
924 MLX5_RX_HASH_IPSEC_SPI;
925 resp.response_length += sizeof(resp.rss_caps);
926 }
927 } else {
928 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
929 resp.response_length += sizeof(resp.tso_caps);
930 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
931 resp.response_length += sizeof(resp.rss_caps);
932 }
933
934 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
935 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
936 props->device_cap_flags |= IB_DEVICE_UD_TSO;
937 }
938
939 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
940 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
941 raw_support)
942 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
943
944 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
945 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
946 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
947
948 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
949 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
950 raw_support) {
951 /* Legacy bit to support old userspace libraries */
952 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
953 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
954 }
955
956 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
957 props->max_dm_size =
958 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
959 }
960
961 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
962 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
963
964 if (MLX5_CAP_GEN(mdev, end_pad))
965 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
966
967 props->vendor_part_id = mdev->pdev->device;
968 props->hw_ver = mdev->pdev->revision;
969
970 props->max_mr_size = ~0ull;
971 props->page_size_cap = ~(min_page_size - 1);
972 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
973 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
974 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
975 sizeof(struct mlx5_wqe_data_seg);
976 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
977 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
978 sizeof(struct mlx5_wqe_raddr_seg)) /
979 sizeof(struct mlx5_wqe_data_seg);
980 props->max_send_sge = max_sq_sg;
981 props->max_recv_sge = max_rq_sg;
982 props->max_sge_rd = MLX5_MAX_SGE_RD;
983 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
984 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
985 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
986 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
987 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
988 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
989 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
990 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
991 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
992 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
993 props->max_srq_sge = max_rq_sg - 1;
994 props->max_fast_reg_page_list_len =
995 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
996 props->max_pi_fast_reg_page_list_len =
997 props->max_fast_reg_page_list_len / 2;
998 props->max_sgl_rd =
999 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
1000 get_atomic_caps_qp(dev, props);
1001 props->masked_atomic_cap = IB_ATOMIC_NONE;
1002 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1003 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1004 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1005 props->max_mcast_grp;
1006 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1007 props->max_ah = INT_MAX;
1008 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1009 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1010
1011 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1012 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1013 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1014 props->odp_caps = dev->odp_caps;
1015 if (!uhw) {
1016 /* ODP for kernel QPs is not implemented for receive
1017 * WQEs and SRQ WQEs
1018 */
1019 props->odp_caps.per_transport_caps.rc_odp_caps &=
1020 ~(IB_ODP_SUPPORT_READ |
1021 IB_ODP_SUPPORT_SRQ_RECV);
1022 props->odp_caps.per_transport_caps.uc_odp_caps &=
1023 ~(IB_ODP_SUPPORT_READ |
1024 IB_ODP_SUPPORT_SRQ_RECV);
1025 props->odp_caps.per_transport_caps.ud_odp_caps &=
1026 ~(IB_ODP_SUPPORT_READ |
1027 IB_ODP_SUPPORT_SRQ_RECV);
1028 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1029 ~(IB_ODP_SUPPORT_READ |
1030 IB_ODP_SUPPORT_SRQ_RECV);
1031 }
1032 }
1033
1034 if (MLX5_CAP_GEN(mdev, cd))
1035 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1036
1037 if (mlx5_core_is_vf(mdev))
1038 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1039
1040 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1041 IB_LINK_LAYER_ETHERNET && raw_support) {
1042 props->rss_caps.max_rwq_indirection_tables =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1044 props->rss_caps.max_rwq_indirection_table_size =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1046 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1047 props->max_wq_type_rq =
1048 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1049 }
1050
1051 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1052 props->tm_caps.max_num_tags =
1053 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1054 props->tm_caps.max_ops =
1055 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1056 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1057 }
1058
1059 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1060 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1061 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1062 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1063 }
1064
1065 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1066 props->cq_caps.max_cq_moderation_count =
1067 MLX5_MAX_CQ_COUNT;
1068 props->cq_caps.max_cq_moderation_period =
1069 MLX5_MAX_CQ_PERIOD;
1070 }
1071
1072 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1073 resp.response_length += sizeof(resp.cqe_comp_caps);
1074
1075 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1076 resp.cqe_comp_caps.max_num =
1077 MLX5_CAP_GEN(dev->mdev,
1078 cqe_compression_max_num);
1079
1080 resp.cqe_comp_caps.supported_format =
1081 MLX5_IB_CQE_RES_FORMAT_HASH |
1082 MLX5_IB_CQE_RES_FORMAT_CSUM;
1083
1084 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1085 resp.cqe_comp_caps.supported_format |=
1086 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1087 }
1088 }
1089
1090 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1091 raw_support) {
1092 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1093 MLX5_CAP_GEN(mdev, qos)) {
1094 resp.packet_pacing_caps.qp_rate_limit_max =
1095 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1096 resp.packet_pacing_caps.qp_rate_limit_min =
1097 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1098 resp.packet_pacing_caps.supported_qpts |=
1099 1 << IB_QPT_RAW_PACKET;
1100 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1101 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1102 resp.packet_pacing_caps.cap_flags |=
1103 MLX5_IB_PP_SUPPORT_BURST;
1104 }
1105 resp.response_length += sizeof(resp.packet_pacing_caps);
1106 }
1107
1108 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1109 uhw_outlen) {
1110 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1111 resp.mlx5_ib_support_multi_pkt_send_wqes =
1112 MLX5_IB_ALLOW_MPW;
1113
1114 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1115 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1116 MLX5_IB_SUPPORT_EMPW;
1117
1118 resp.response_length +=
1119 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1120 }
1121
1122 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1123 resp.response_length += sizeof(resp.flags);
1124
1125 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1126 resp.flags |=
1127 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1128
1129 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1130 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1131 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1132 resp.flags |=
1133 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1134
1135 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1136 }
1137
1138 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1139 resp.response_length += sizeof(resp.sw_parsing_caps);
1140 if (MLX5_CAP_ETH(mdev, swp)) {
1141 resp.sw_parsing_caps.sw_parsing_offloads |=
1142 MLX5_IB_SW_PARSING;
1143
1144 if (MLX5_CAP_ETH(mdev, swp_csum))
1145 resp.sw_parsing_caps.sw_parsing_offloads |=
1146 MLX5_IB_SW_PARSING_CSUM;
1147
1148 if (MLX5_CAP_ETH(mdev, swp_lso))
1149 resp.sw_parsing_caps.sw_parsing_offloads |=
1150 MLX5_IB_SW_PARSING_LSO;
1151
1152 if (resp.sw_parsing_caps.sw_parsing_offloads)
1153 resp.sw_parsing_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
1158 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1159 raw_support) {
1160 resp.response_length += sizeof(resp.striding_rq_caps);
1161 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1162 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1163 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1165 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1166 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1167 resp.striding_rq_caps
1168 .min_single_wqe_log_num_of_strides =
1169 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1170 else
1171 resp.striding_rq_caps
1172 .min_single_wqe_log_num_of_strides =
1173 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1174 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1175 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1176 resp.striding_rq_caps.supported_qpts =
1177 BIT(IB_QPT_RAW_PACKET);
1178 }
1179 }
1180
1181 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1182 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1183 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1184 resp.tunnel_offloads_caps |=
1185 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1186 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1189 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1190 resp.tunnel_offloads_caps |=
1191 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1192 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1193 resp.tunnel_offloads_caps |=
1194 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1195 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1196 resp.tunnel_offloads_caps |=
1197 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1198 }
1199
1200 if (uhw_outlen) {
1201 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1202
1203 if (err)
1204 return err;
1205 }
1206
1207 return 0;
1208 }
1209
1210 enum mlx5_ib_width {
1211 MLX5_IB_WIDTH_1X = 1 << 0,
1212 MLX5_IB_WIDTH_2X = 1 << 1,
1213 MLX5_IB_WIDTH_4X = 1 << 2,
1214 MLX5_IB_WIDTH_8X = 1 << 3,
1215 MLX5_IB_WIDTH_12X = 1 << 4
1216 };
1217
1218 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1219 u8 *ib_width)
1220 {
1221 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1222
1223 if (active_width & MLX5_IB_WIDTH_1X)
1224 *ib_width = IB_WIDTH_1X;
1225 else if (active_width & MLX5_IB_WIDTH_2X)
1226 *ib_width = IB_WIDTH_2X;
1227 else if (active_width & MLX5_IB_WIDTH_4X)
1228 *ib_width = IB_WIDTH_4X;
1229 else if (active_width & MLX5_IB_WIDTH_8X)
1230 *ib_width = IB_WIDTH_8X;
1231 else if (active_width & MLX5_IB_WIDTH_12X)
1232 *ib_width = IB_WIDTH_12X;
1233 else {
1234 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1235 (int)active_width);
1236 *ib_width = IB_WIDTH_4X;
1237 }
1238
1239 return;
1240 }
1241
1242 static int mlx5_mtu_to_ib_mtu(int mtu)
1243 {
1244 switch (mtu) {
1245 case 256: return 1;
1246 case 512: return 2;
1247 case 1024: return 3;
1248 case 2048: return 4;
1249 case 4096: return 5;
1250 default:
1251 pr_warn("invalid mtu\n");
1252 return -1;
1253 }
1254 }
1255
1256 enum ib_max_vl_num {
1257 __IB_MAX_VL_0 = 1,
1258 __IB_MAX_VL_0_1 = 2,
1259 __IB_MAX_VL_0_3 = 3,
1260 __IB_MAX_VL_0_7 = 4,
1261 __IB_MAX_VL_0_14 = 5,
1262 };
1263
1264 enum mlx5_vl_hw_cap {
1265 MLX5_VL_HW_0 = 1,
1266 MLX5_VL_HW_0_1 = 2,
1267 MLX5_VL_HW_0_2 = 3,
1268 MLX5_VL_HW_0_3 = 4,
1269 MLX5_VL_HW_0_4 = 5,
1270 MLX5_VL_HW_0_5 = 6,
1271 MLX5_VL_HW_0_6 = 7,
1272 MLX5_VL_HW_0_7 = 8,
1273 MLX5_VL_HW_0_14 = 15
1274 };
1275
1276 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1277 u8 *max_vl_num)
1278 {
1279 switch (vl_hw_cap) {
1280 case MLX5_VL_HW_0:
1281 *max_vl_num = __IB_MAX_VL_0;
1282 break;
1283 case MLX5_VL_HW_0_1:
1284 *max_vl_num = __IB_MAX_VL_0_1;
1285 break;
1286 case MLX5_VL_HW_0_3:
1287 *max_vl_num = __IB_MAX_VL_0_3;
1288 break;
1289 case MLX5_VL_HW_0_7:
1290 *max_vl_num = __IB_MAX_VL_0_7;
1291 break;
1292 case MLX5_VL_HW_0_14:
1293 *max_vl_num = __IB_MAX_VL_0_14;
1294 break;
1295
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 return 0;
1301 }
1302
1303 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1304 struct ib_port_attr *props)
1305 {
1306 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1307 struct mlx5_core_dev *mdev = dev->mdev;
1308 struct mlx5_hca_vport_context *rep;
1309 u16 max_mtu;
1310 u16 oper_mtu;
1311 int err;
1312 u8 ib_link_width_oper;
1313 u8 vl_hw_cap;
1314
1315 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1316 if (!rep) {
1317 err = -ENOMEM;
1318 goto out;
1319 }
1320
1321 /* props being zeroed by the caller, avoid zeroing it here */
1322
1323 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1324 if (err)
1325 goto out;
1326
1327 props->lid = rep->lid;
1328 props->lmc = rep->lmc;
1329 props->sm_lid = rep->sm_lid;
1330 props->sm_sl = rep->sm_sl;
1331 props->state = rep->vport_state;
1332 props->phys_state = rep->port_physical_state;
1333 props->port_cap_flags = rep->cap_mask1;
1334 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1335 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1336 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1337 props->bad_pkey_cntr = rep->pkey_violation_counter;
1338 props->qkey_viol_cntr = rep->qkey_violation_counter;
1339 props->subnet_timeout = rep->subnet_timeout;
1340 props->init_type_reply = rep->init_type_reply;
1341
1342 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1343 props->port_cap_flags2 = rep->cap_mask2;
1344
1345 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1346 if (err)
1347 goto out;
1348
1349 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1350
1351 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1352 if (err)
1353 goto out;
1354
1355 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1356
1357 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1358
1359 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1360
1361 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1362
1363 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1364 if (err)
1365 goto out;
1366
1367 err = translate_max_vl_num(ibdev, vl_hw_cap,
1368 &props->max_vl_num);
1369 out:
1370 kfree(rep);
1371 return err;
1372 }
1373
1374 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1375 struct ib_port_attr *props)
1376 {
1377 unsigned int count;
1378 int ret;
1379
1380 switch (mlx5_get_vport_access_method(ibdev)) {
1381 case MLX5_VPORT_ACCESS_METHOD_MAD:
1382 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1383 break;
1384
1385 case MLX5_VPORT_ACCESS_METHOD_HCA:
1386 ret = mlx5_query_hca_port(ibdev, port, props);
1387 break;
1388
1389 case MLX5_VPORT_ACCESS_METHOD_NIC:
1390 ret = mlx5_query_port_roce(ibdev, port, props);
1391 break;
1392
1393 default:
1394 ret = -EINVAL;
1395 }
1396
1397 if (!ret && props) {
1398 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1399 struct mlx5_core_dev *mdev;
1400 bool put_mdev = true;
1401
1402 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1403 if (!mdev) {
1404 /* If the port isn't affiliated yet query the master.
1405 * The master and slave will have the same values.
1406 */
1407 mdev = dev->mdev;
1408 port = 1;
1409 put_mdev = false;
1410 }
1411 count = mlx5_core_reserved_gids_count(mdev);
1412 if (put_mdev)
1413 mlx5_ib_put_native_port_mdev(dev, port);
1414 props->gid_tbl_len -= count;
1415 }
1416 return ret;
1417 }
1418
1419 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1420 struct ib_port_attr *props)
1421 {
1422 int ret;
1423
1424 /* Only link layer == ethernet is valid for representors
1425 * and we always use port 1
1426 */
1427 ret = mlx5_query_port_roce(ibdev, port, props);
1428 if (ret || !props)
1429 return ret;
1430
1431 /* We don't support GIDS */
1432 props->gid_tbl_len = 0;
1433
1434 return ret;
1435 }
1436
1437 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1438 union ib_gid *gid)
1439 {
1440 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1441 struct mlx5_core_dev *mdev = dev->mdev;
1442
1443 switch (mlx5_get_vport_access_method(ibdev)) {
1444 case MLX5_VPORT_ACCESS_METHOD_MAD:
1445 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1446
1447 case MLX5_VPORT_ACCESS_METHOD_HCA:
1448 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1449
1450 default:
1451 return -EINVAL;
1452 }
1453
1454 }
1455
1456 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1457 u16 index, u16 *pkey)
1458 {
1459 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1460 struct mlx5_core_dev *mdev;
1461 bool put_mdev = true;
1462 u8 mdev_port_num;
1463 int err;
1464
1465 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1466 if (!mdev) {
1467 /* The port isn't affiliated yet, get the PKey from the master
1468 * port. For RoCE the PKey tables will be the same.
1469 */
1470 put_mdev = false;
1471 mdev = dev->mdev;
1472 mdev_port_num = 1;
1473 }
1474
1475 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1476 index, pkey);
1477 if (put_mdev)
1478 mlx5_ib_put_native_port_mdev(dev, port);
1479
1480 return err;
1481 }
1482
1483 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1484 u16 *pkey)
1485 {
1486 switch (mlx5_get_vport_access_method(ibdev)) {
1487 case MLX5_VPORT_ACCESS_METHOD_MAD:
1488 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1489
1490 case MLX5_VPORT_ACCESS_METHOD_HCA:
1491 case MLX5_VPORT_ACCESS_METHOD_NIC:
1492 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1493 default:
1494 return -EINVAL;
1495 }
1496 }
1497
1498 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1499 struct ib_device_modify *props)
1500 {
1501 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1502 struct mlx5_reg_node_desc in;
1503 struct mlx5_reg_node_desc out;
1504 int err;
1505
1506 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1507 return -EOPNOTSUPP;
1508
1509 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1510 return 0;
1511
1512 /*
1513 * If possible, pass node desc to FW, so it can generate
1514 * a 144 trap. If cmd fails, just ignore.
1515 */
1516 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1517 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1518 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1519 if (err)
1520 return err;
1521
1522 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1523
1524 return err;
1525 }
1526
1527 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1528 u32 value)
1529 {
1530 struct mlx5_hca_vport_context ctx = {};
1531 struct mlx5_core_dev *mdev;
1532 u8 mdev_port_num;
1533 int err;
1534
1535 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1536 if (!mdev)
1537 return -ENODEV;
1538
1539 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1540 if (err)
1541 goto out;
1542
1543 if (~ctx.cap_mask1_perm & mask) {
1544 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1545 mask, ctx.cap_mask1_perm);
1546 err = -EINVAL;
1547 goto out;
1548 }
1549
1550 ctx.cap_mask1 = value;
1551 ctx.cap_mask1_perm = mask;
1552 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1553 0, &ctx);
1554
1555 out:
1556 mlx5_ib_put_native_port_mdev(dev, port_num);
1557
1558 return err;
1559 }
1560
1561 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1562 struct ib_port_modify *props)
1563 {
1564 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1565 struct ib_port_attr attr;
1566 u32 tmp;
1567 int err;
1568 u32 change_mask;
1569 u32 value;
1570 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1571 IB_LINK_LAYER_INFINIBAND);
1572
1573 /* CM layer calls ib_modify_port() regardless of the link layer. For
1574 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1575 */
1576 if (!is_ib)
1577 return 0;
1578
1579 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1580 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1581 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1582 return set_port_caps_atomic(dev, port, change_mask, value);
1583 }
1584
1585 mutex_lock(&dev->cap_mask_mutex);
1586
1587 err = ib_query_port(ibdev, port, &attr);
1588 if (err)
1589 goto out;
1590
1591 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1592 ~props->clr_port_cap_mask;
1593
1594 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1595
1596 out:
1597 mutex_unlock(&dev->cap_mask_mutex);
1598 return err;
1599 }
1600
1601 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1602 {
1603 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1604 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1605 }
1606
1607 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1608 {
1609 /* Large page with non 4k uar support might limit the dynamic size */
1610 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1611 return MLX5_MIN_DYN_BFREGS;
1612
1613 return MLX5_MAX_DYN_BFREGS;
1614 }
1615
1616 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1617 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1618 struct mlx5_bfreg_info *bfregi)
1619 {
1620 int uars_per_sys_page;
1621 int bfregs_per_sys_page;
1622 int ref_bfregs = req->total_num_bfregs;
1623
1624 if (req->total_num_bfregs == 0)
1625 return -EINVAL;
1626
1627 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1628 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1629
1630 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1631 return -ENOMEM;
1632
1633 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1634 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1635 /* This holds the required static allocation asked by the user */
1636 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1637 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1638 return -EINVAL;
1639
1640 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1641 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1642 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1643 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1644
1645 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1646 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1647 lib_uar_4k ? "yes" : "no", ref_bfregs,
1648 req->total_num_bfregs, bfregi->total_num_bfregs,
1649 bfregi->num_sys_pages);
1650
1651 return 0;
1652 }
1653
1654 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1655 {
1656 struct mlx5_bfreg_info *bfregi;
1657 int err;
1658 int i;
1659
1660 bfregi = &context->bfregi;
1661 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1662 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1663 if (err)
1664 goto error;
1665
1666 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1667 }
1668
1669 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1670 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1671
1672 return 0;
1673
1674 error:
1675 for (--i; i >= 0; i--)
1676 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1677 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1678
1679 return err;
1680 }
1681
1682 static void deallocate_uars(struct mlx5_ib_dev *dev,
1683 struct mlx5_ib_ucontext *context)
1684 {
1685 struct mlx5_bfreg_info *bfregi;
1686 int i;
1687
1688 bfregi = &context->bfregi;
1689 for (i = 0; i < bfregi->num_sys_pages; i++)
1690 if (i < bfregi->num_static_sys_pages ||
1691 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1692 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1693 }
1694
1695 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1696 {
1697 int err = 0;
1698
1699 mutex_lock(&dev->lb.mutex);
1700 if (td)
1701 dev->lb.user_td++;
1702 if (qp)
1703 dev->lb.qps++;
1704
1705 if (dev->lb.user_td == 2 ||
1706 dev->lb.qps == 1) {
1707 if (!dev->lb.enabled) {
1708 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1709 dev->lb.enabled = true;
1710 }
1711 }
1712
1713 mutex_unlock(&dev->lb.mutex);
1714
1715 return err;
1716 }
1717
1718 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1719 {
1720 mutex_lock(&dev->lb.mutex);
1721 if (td)
1722 dev->lb.user_td--;
1723 if (qp)
1724 dev->lb.qps--;
1725
1726 if (dev->lb.user_td == 1 &&
1727 dev->lb.qps == 0) {
1728 if (dev->lb.enabled) {
1729 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1730 dev->lb.enabled = false;
1731 }
1732 }
1733
1734 mutex_unlock(&dev->lb.mutex);
1735 }
1736
1737 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1738 u16 uid)
1739 {
1740 int err;
1741
1742 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1743 return 0;
1744
1745 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1746 if (err)
1747 return err;
1748
1749 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1750 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1751 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1752 return err;
1753
1754 return mlx5_ib_enable_lb(dev, true, false);
1755 }
1756
1757 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1758 u16 uid)
1759 {
1760 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1761 return;
1762
1763 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1764
1765 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1766 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1767 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1768 return;
1769
1770 mlx5_ib_disable_lb(dev, true, false);
1771 }
1772
1773 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1774 struct ib_udata *udata)
1775 {
1776 struct ib_device *ibdev = uctx->device;
1777 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1778 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1779 struct mlx5_ib_alloc_ucontext_resp resp = {};
1780 struct mlx5_core_dev *mdev = dev->mdev;
1781 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1782 struct mlx5_bfreg_info *bfregi;
1783 int ver;
1784 int err;
1785 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1786 max_cqe_version);
1787 u32 dump_fill_mkey;
1788 bool lib_uar_4k;
1789 bool lib_uar_dyn;
1790
1791 if (!dev->ib_active)
1792 return -EAGAIN;
1793
1794 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1795 ver = 0;
1796 else if (udata->inlen >= min_req_v2)
1797 ver = 2;
1798 else
1799 return -EINVAL;
1800
1801 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1802 if (err)
1803 return err;
1804
1805 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1806 return -EOPNOTSUPP;
1807
1808 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1809 return -EOPNOTSUPP;
1810
1811 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1812 MLX5_NON_FP_BFREGS_PER_UAR);
1813 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1814 return -EINVAL;
1815
1816 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1817 if (dev->wc_support)
1818 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1819 resp.cache_line_size = cache_line_size();
1820 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1821 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1822 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1823 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1824 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1825 resp.cqe_version = min_t(__u8,
1826 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1827 req.max_cqe_version);
1828 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1829 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1830 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1831 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1832 resp.response_length = min(offsetof(typeof(resp), response_length) +
1833 sizeof(resp.response_length), udata->outlen);
1834
1835 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1836 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1837 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1838 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1839 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1840 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1841 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1842 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1843 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1844 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1845 }
1846
1847 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1848 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1849 bfregi = &context->bfregi;
1850
1851 if (lib_uar_dyn) {
1852 bfregi->lib_uar_dyn = lib_uar_dyn;
1853 goto uar_done;
1854 }
1855
1856 /* updates req->total_num_bfregs */
1857 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1858 if (err)
1859 goto out_ctx;
1860
1861 mutex_init(&bfregi->lock);
1862 bfregi->lib_uar_4k = lib_uar_4k;
1863 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1864 GFP_KERNEL);
1865 if (!bfregi->count) {
1866 err = -ENOMEM;
1867 goto out_ctx;
1868 }
1869
1870 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1871 sizeof(*bfregi->sys_pages),
1872 GFP_KERNEL);
1873 if (!bfregi->sys_pages) {
1874 err = -ENOMEM;
1875 goto out_count;
1876 }
1877
1878 err = allocate_uars(dev, context);
1879 if (err)
1880 goto out_sys_pages;
1881
1882 uar_done:
1883 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1884 err = mlx5_ib_devx_create(dev, true);
1885 if (err < 0)
1886 goto out_uars;
1887 context->devx_uid = err;
1888 }
1889
1890 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1891 context->devx_uid);
1892 if (err)
1893 goto out_devx;
1894
1895 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1896 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1897 if (err)
1898 goto out_mdev;
1899 }
1900
1901 INIT_LIST_HEAD(&context->db_page_list);
1902 mutex_init(&context->db_page_mutex);
1903
1904 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs;
1905 resp.num_ports = dev->num_ports;
1906
1907 if (offsetofend(typeof(resp), cqe_version) <= udata->outlen)
1908 resp.response_length += sizeof(resp.cqe_version);
1909
1910 if (offsetofend(typeof(resp), cmds_supp_uhw) <= udata->outlen) {
1911 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1912 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1913 resp.response_length += sizeof(resp.cmds_supp_uhw);
1914 }
1915
1916 if (offsetofend(typeof(resp), eth_min_inline) <= udata->outlen) {
1917 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1918 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1919 resp.eth_min_inline++;
1920 }
1921 resp.response_length += sizeof(resp.eth_min_inline);
1922 }
1923
1924 if (offsetofend(typeof(resp), clock_info_versions) <= udata->outlen) {
1925 if (mdev->clock_info)
1926 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1927 resp.response_length += sizeof(resp.clock_info_versions);
1928 }
1929
1930 /*
1931 * We don't want to expose information from the PCI bar that is located
1932 * after 4096 bytes, so if the arch only supports larger pages, let's
1933 * pretend we don't support reading the HCA's core clock. This is also
1934 * forced by mmap function.
1935 */
1936 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
1937 if (PAGE_SIZE <= 4096) {
1938 resp.comp_mask |=
1939 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1940 resp.hca_core_clock_offset =
1941 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1942 }
1943 resp.response_length += sizeof(resp.hca_core_clock_offset);
1944 }
1945
1946 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
1947 resp.response_length += sizeof(resp.log_uar_size);
1948
1949 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
1950 resp.response_length += sizeof(resp.num_uars_per_page);
1951
1952 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
1953 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1954 resp.response_length += sizeof(resp.num_dyn_bfregs);
1955 }
1956
1957 if (offsetofend(typeof(resp), dump_fill_mkey) <= udata->outlen) {
1958 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1959 resp.dump_fill_mkey = dump_fill_mkey;
1960 resp.comp_mask |=
1961 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1962 }
1963 resp.response_length += sizeof(resp.dump_fill_mkey);
1964 }
1965
1966 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1967 if (err)
1968 goto out_mdev;
1969
1970 bfregi->ver = ver;
1971 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1972 context->cqe_version = resp.cqe_version;
1973 context->lib_caps = req.lib_caps;
1974 print_lib_caps(dev, context->lib_caps);
1975
1976 if (dev->lag_active) {
1977 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1978
1979 atomic_set(&context->tx_port_affinity,
1980 atomic_add_return(
1981 1, &dev->port[port].roce.tx_port_affinity));
1982 }
1983
1984 return 0;
1985
1986 out_mdev:
1987 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1988 out_devx:
1989 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1990 mlx5_ib_devx_destroy(dev, context->devx_uid);
1991
1992 out_uars:
1993 deallocate_uars(dev, context);
1994
1995 out_sys_pages:
1996 kfree(bfregi->sys_pages);
1997
1998 out_count:
1999 kfree(bfregi->count);
2000
2001 out_ctx:
2002 return err;
2003 }
2004
2005 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2006 {
2007 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2008 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2009 struct mlx5_bfreg_info *bfregi;
2010
2011 bfregi = &context->bfregi;
2012 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2013
2014 if (context->devx_uid)
2015 mlx5_ib_devx_destroy(dev, context->devx_uid);
2016
2017 deallocate_uars(dev, context);
2018 kfree(bfregi->sys_pages);
2019 kfree(bfregi->count);
2020 }
2021
2022 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2023 int uar_idx)
2024 {
2025 int fw_uars_per_page;
2026
2027 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2028
2029 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2030 }
2031
2032 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2033 int uar_idx)
2034 {
2035 unsigned int fw_uars_per_page;
2036
2037 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2038 MLX5_UARS_IN_PAGE : 1;
2039
2040 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2041 }
2042
2043 static int get_command(unsigned long offset)
2044 {
2045 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2046 }
2047
2048 static int get_arg(unsigned long offset)
2049 {
2050 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2051 }
2052
2053 static int get_index(unsigned long offset)
2054 {
2055 return get_arg(offset);
2056 }
2057
2058 /* Index resides in an extra byte to enable larger values than 255 */
2059 static int get_extended_index(unsigned long offset)
2060 {
2061 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2062 }
2063
2064
2065 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2066 {
2067 }
2068
2069 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2070 {
2071 switch (cmd) {
2072 case MLX5_IB_MMAP_WC_PAGE:
2073 return "WC";
2074 case MLX5_IB_MMAP_REGULAR_PAGE:
2075 return "best effort WC";
2076 case MLX5_IB_MMAP_NC_PAGE:
2077 return "NC";
2078 case MLX5_IB_MMAP_DEVICE_MEM:
2079 return "Device Memory";
2080 default:
2081 return NULL;
2082 }
2083 }
2084
2085 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2086 struct vm_area_struct *vma,
2087 struct mlx5_ib_ucontext *context)
2088 {
2089 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2090 !(vma->vm_flags & VM_SHARED))
2091 return -EINVAL;
2092
2093 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2094 return -EOPNOTSUPP;
2095
2096 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2097 return -EPERM;
2098 vma->vm_flags &= ~VM_MAYWRITE;
2099
2100 if (!dev->mdev->clock_info)
2101 return -EOPNOTSUPP;
2102
2103 return vm_insert_page(vma, vma->vm_start,
2104 virt_to_page(dev->mdev->clock_info));
2105 }
2106
2107 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2108 {
2109 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2110 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2111 struct mlx5_var_table *var_table = &dev->var_table;
2112 struct mlx5_ib_dm *mdm;
2113
2114 switch (mentry->mmap_flag) {
2115 case MLX5_IB_MMAP_TYPE_MEMIC:
2116 mdm = container_of(mentry, struct mlx5_ib_dm, mentry);
2117 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr,
2118 mdm->size);
2119 kfree(mdm);
2120 break;
2121 case MLX5_IB_MMAP_TYPE_VAR:
2122 mutex_lock(&var_table->bitmap_lock);
2123 clear_bit(mentry->page_idx, var_table->bitmap);
2124 mutex_unlock(&var_table->bitmap_lock);
2125 kfree(mentry);
2126 break;
2127 case MLX5_IB_MMAP_TYPE_UAR_WC:
2128 case MLX5_IB_MMAP_TYPE_UAR_NC:
2129 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2130 kfree(mentry);
2131 break;
2132 default:
2133 WARN_ON(true);
2134 }
2135 }
2136
2137 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2138 struct vm_area_struct *vma,
2139 struct mlx5_ib_ucontext *context)
2140 {
2141 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2142 int err;
2143 unsigned long idx;
2144 phys_addr_t pfn;
2145 pgprot_t prot;
2146 u32 bfreg_dyn_idx = 0;
2147 u32 uar_index;
2148 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2149 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2150 bfregi->num_static_sys_pages;
2151
2152 if (bfregi->lib_uar_dyn)
2153 return -EINVAL;
2154
2155 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2156 return -EINVAL;
2157
2158 if (dyn_uar)
2159 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2160 else
2161 idx = get_index(vma->vm_pgoff);
2162
2163 if (idx >= max_valid_idx) {
2164 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2165 idx, max_valid_idx);
2166 return -EINVAL;
2167 }
2168
2169 switch (cmd) {
2170 case MLX5_IB_MMAP_WC_PAGE:
2171 case MLX5_IB_MMAP_ALLOC_WC:
2172 case MLX5_IB_MMAP_REGULAR_PAGE:
2173 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2174 prot = pgprot_writecombine(vma->vm_page_prot);
2175 break;
2176 case MLX5_IB_MMAP_NC_PAGE:
2177 prot = pgprot_noncached(vma->vm_page_prot);
2178 break;
2179 default:
2180 return -EINVAL;
2181 }
2182
2183 if (dyn_uar) {
2184 int uars_per_page;
2185
2186 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2187 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2188 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2189 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2190 bfreg_dyn_idx, bfregi->total_num_bfregs);
2191 return -EINVAL;
2192 }
2193
2194 mutex_lock(&bfregi->lock);
2195 /* Fail if uar already allocated, first bfreg index of each
2196 * page holds its count.
2197 */
2198 if (bfregi->count[bfreg_dyn_idx]) {
2199 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2200 mutex_unlock(&bfregi->lock);
2201 return -EINVAL;
2202 }
2203
2204 bfregi->count[bfreg_dyn_idx]++;
2205 mutex_unlock(&bfregi->lock);
2206
2207 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2208 if (err) {
2209 mlx5_ib_warn(dev, "UAR alloc failed\n");
2210 goto free_bfreg;
2211 }
2212 } else {
2213 uar_index = bfregi->sys_pages[idx];
2214 }
2215
2216 pfn = uar_index2pfn(dev, uar_index);
2217 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2218
2219 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2220 prot, NULL);
2221 if (err) {
2222 mlx5_ib_err(dev,
2223 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2224 err, mmap_cmd2str(cmd));
2225 goto err;
2226 }
2227
2228 if (dyn_uar)
2229 bfregi->sys_pages[idx] = uar_index;
2230 return 0;
2231
2232 err:
2233 if (!dyn_uar)
2234 return err;
2235
2236 mlx5_cmd_free_uar(dev->mdev, idx);
2237
2238 free_bfreg:
2239 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2240
2241 return err;
2242 }
2243
2244 static int add_dm_mmap_entry(struct ib_ucontext *context,
2245 struct mlx5_ib_dm *mdm,
2246 u64 address)
2247 {
2248 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC;
2249 mdm->mentry.address = address;
2250 return rdma_user_mmap_entry_insert_range(
2251 context, &mdm->mentry.rdma_entry,
2252 mdm->size,
2253 MLX5_IB_MMAP_DEVICE_MEM << 16,
2254 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1);
2255 }
2256
2257 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2258 {
2259 unsigned long idx;
2260 u8 command;
2261
2262 command = get_command(vma->vm_pgoff);
2263 idx = get_extended_index(vma->vm_pgoff);
2264
2265 return (command << 16 | idx);
2266 }
2267
2268 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2269 struct vm_area_struct *vma,
2270 struct ib_ucontext *ucontext)
2271 {
2272 struct mlx5_user_mmap_entry *mentry;
2273 struct rdma_user_mmap_entry *entry;
2274 unsigned long pgoff;
2275 pgprot_t prot;
2276 phys_addr_t pfn;
2277 int ret;
2278
2279 pgoff = mlx5_vma_to_pgoff(vma);
2280 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2281 if (!entry)
2282 return -EINVAL;
2283
2284 mentry = to_mmmap(entry);
2285 pfn = (mentry->address >> PAGE_SHIFT);
2286 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2287 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2288 prot = pgprot_noncached(vma->vm_page_prot);
2289 else
2290 prot = pgprot_writecombine(vma->vm_page_prot);
2291 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2292 entry->npages * PAGE_SIZE,
2293 prot,
2294 entry);
2295 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2296 return ret;
2297 }
2298
2299 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2300 {
2301 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2302 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2303
2304 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2305 (index & 0xFF)) << PAGE_SHIFT;
2306 }
2307
2308 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2309 {
2310 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2311 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2312 unsigned long command;
2313 phys_addr_t pfn;
2314
2315 command = get_command(vma->vm_pgoff);
2316 switch (command) {
2317 case MLX5_IB_MMAP_WC_PAGE:
2318 case MLX5_IB_MMAP_ALLOC_WC:
2319 if (!dev->wc_support)
2320 return -EPERM;
2321 fallthrough;
2322 case MLX5_IB_MMAP_NC_PAGE:
2323 case MLX5_IB_MMAP_REGULAR_PAGE:
2324 return uar_mmap(dev, command, vma, context);
2325
2326 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2327 return -ENOSYS;
2328
2329 case MLX5_IB_MMAP_CORE_CLOCK:
2330 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2331 return -EINVAL;
2332
2333 if (vma->vm_flags & VM_WRITE)
2334 return -EPERM;
2335 vma->vm_flags &= ~VM_MAYWRITE;
2336
2337 /* Don't expose to user-space information it shouldn't have */
2338 if (PAGE_SIZE > 4096)
2339 return -EOPNOTSUPP;
2340
2341 pfn = (dev->mdev->iseg_base +
2342 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2343 PAGE_SHIFT;
2344 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2345 PAGE_SIZE,
2346 pgprot_noncached(vma->vm_page_prot),
2347 NULL);
2348 case MLX5_IB_MMAP_CLOCK_INFO:
2349 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2350
2351 default:
2352 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2353 }
2354
2355 return 0;
2356 }
2357
2358 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2359 u32 type)
2360 {
2361 switch (type) {
2362 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2363 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2364 return -EOPNOTSUPP;
2365 break;
2366 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2367 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2368 if (!capable(CAP_SYS_RAWIO) ||
2369 !capable(CAP_NET_RAW))
2370 return -EPERM;
2371
2372 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2373 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2374 return -EOPNOTSUPP;
2375 break;
2376 }
2377
2378 return 0;
2379 }
2380
2381 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2382 struct mlx5_ib_dm *dm,
2383 struct ib_dm_alloc_attr *attr,
2384 struct uverbs_attr_bundle *attrs)
2385 {
2386 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2387 u64 start_offset;
2388 u16 page_idx;
2389 int err;
2390 u64 address;
2391
2392 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2393
2394 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2395 dm->size, attr->alignment);
2396 if (err)
2397 return err;
2398
2399 address = dm->dev_addr & PAGE_MASK;
2400 err = add_dm_mmap_entry(ctx, dm, address);
2401 if (err)
2402 goto err_dealloc;
2403
2404 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF;
2405 err = uverbs_copy_to(attrs,
2406 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2407 &page_idx,
2408 sizeof(page_idx));
2409 if (err)
2410 goto err_copy;
2411
2412 start_offset = dm->dev_addr & ~PAGE_MASK;
2413 err = uverbs_copy_to(attrs,
2414 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2415 &start_offset, sizeof(start_offset));
2416 if (err)
2417 goto err_copy;
2418
2419 return 0;
2420
2421 err_copy:
2422 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2423 err_dealloc:
2424 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2425
2426 return err;
2427 }
2428
2429 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2430 struct mlx5_ib_dm *dm,
2431 struct ib_dm_alloc_attr *attr,
2432 struct uverbs_attr_bundle *attrs,
2433 int type)
2434 {
2435 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2436 u64 act_size;
2437 int err;
2438
2439 /* Allocation size must a multiple of the basic block size
2440 * and a power of 2.
2441 */
2442 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2443 act_size = roundup_pow_of_two(act_size);
2444
2445 dm->size = act_size;
2446 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2447 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2448 &dm->icm_dm.obj_id);
2449 if (err)
2450 return err;
2451
2452 err = uverbs_copy_to(attrs,
2453 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2454 &dm->dev_addr, sizeof(dm->dev_addr));
2455 if (err)
2456 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2457 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2458 dm->icm_dm.obj_id);
2459
2460 return err;
2461 }
2462
2463 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2464 struct ib_ucontext *context,
2465 struct ib_dm_alloc_attr *attr,
2466 struct uverbs_attr_bundle *attrs)
2467 {
2468 struct mlx5_ib_dm *dm;
2469 enum mlx5_ib_uapi_dm_type type;
2470 int err;
2471
2472 err = uverbs_get_const_default(&type, attrs,
2473 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2474 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2475 if (err)
2476 return ERR_PTR(err);
2477
2478 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2479 type, attr->length, attr->alignment);
2480
2481 err = check_dm_type_support(to_mdev(ibdev), type);
2482 if (err)
2483 return ERR_PTR(err);
2484
2485 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2486 if (!dm)
2487 return ERR_PTR(-ENOMEM);
2488
2489 dm->type = type;
2490
2491 switch (type) {
2492 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2493 err = handle_alloc_dm_memic(context, dm,
2494 attr,
2495 attrs);
2496 break;
2497 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2498 err = handle_alloc_dm_sw_icm(context, dm,
2499 attr, attrs,
2500 MLX5_SW_ICM_TYPE_STEERING);
2501 break;
2502 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2503 err = handle_alloc_dm_sw_icm(context, dm,
2504 attr, attrs,
2505 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2506 break;
2507 default:
2508 err = -EOPNOTSUPP;
2509 }
2510
2511 if (err)
2512 goto err_free;
2513
2514 return &dm->ibdm;
2515
2516 err_free:
2517 kfree(dm);
2518 return ERR_PTR(err);
2519 }
2520
2521 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2522 {
2523 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2524 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2525 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2526 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2527 int ret;
2528
2529 switch (dm->type) {
2530 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2531 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2532 return 0;
2533 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2534 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2535 dm->size, ctx->devx_uid, dm->dev_addr,
2536 dm->icm_dm.obj_id);
2537 if (ret)
2538 return ret;
2539 break;
2540 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2541 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2542 dm->size, ctx->devx_uid, dm->dev_addr,
2543 dm->icm_dm.obj_id);
2544 if (ret)
2545 return ret;
2546 break;
2547 default:
2548 return -EOPNOTSUPP;
2549 }
2550
2551 kfree(dm);
2552
2553 return 0;
2554 }
2555
2556 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2557 {
2558 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2559 struct ib_device *ibdev = ibpd->device;
2560 struct mlx5_ib_alloc_pd_resp resp;
2561 int err;
2562 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2563 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2564 u16 uid = 0;
2565 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2566 udata, struct mlx5_ib_ucontext, ibucontext);
2567
2568 uid = context ? context->devx_uid : 0;
2569 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2570 MLX5_SET(alloc_pd_in, in, uid, uid);
2571 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2572 out, sizeof(out));
2573 if (err)
2574 return err;
2575
2576 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2577 pd->uid = uid;
2578 if (udata) {
2579 resp.pdn = pd->pdn;
2580 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2581 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2582 return -EFAULT;
2583 }
2584 }
2585
2586 return 0;
2587 }
2588
2589 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2590 {
2591 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2592 struct mlx5_ib_pd *mpd = to_mpd(pd);
2593
2594 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2595 }
2596
2597 enum {
2598 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2599 MATCH_CRITERIA_ENABLE_MISC_BIT,
2600 MATCH_CRITERIA_ENABLE_INNER_BIT,
2601 MATCH_CRITERIA_ENABLE_MISC2_BIT
2602 };
2603
2604 #define HEADER_IS_ZERO(match_criteria, headers) \
2605 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2606 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2607
2608 static u8 get_match_criteria_enable(u32 *match_criteria)
2609 {
2610 u8 match_criteria_enable;
2611
2612 match_criteria_enable =
2613 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2614 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2615 match_criteria_enable |=
2616 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2617 MATCH_CRITERIA_ENABLE_MISC_BIT;
2618 match_criteria_enable |=
2619 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2620 MATCH_CRITERIA_ENABLE_INNER_BIT;
2621 match_criteria_enable |=
2622 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2623 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2624
2625 return match_criteria_enable;
2626 }
2627
2628 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2629 {
2630 u8 entry_mask;
2631 u8 entry_val;
2632 int err = 0;
2633
2634 if (!mask)
2635 goto out;
2636
2637 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2638 ip_protocol);
2639 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2640 ip_protocol);
2641 if (!entry_mask) {
2642 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2643 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2644 goto out;
2645 }
2646 /* Don't override existing ip protocol */
2647 if (mask != entry_mask || val != entry_val)
2648 err = -EINVAL;
2649 out:
2650 return err;
2651 }
2652
2653 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2654 bool inner)
2655 {
2656 if (inner) {
2657 MLX5_SET(fte_match_set_misc,
2658 misc_c, inner_ipv6_flow_label, mask);
2659 MLX5_SET(fte_match_set_misc,
2660 misc_v, inner_ipv6_flow_label, val);
2661 } else {
2662 MLX5_SET(fte_match_set_misc,
2663 misc_c, outer_ipv6_flow_label, mask);
2664 MLX5_SET(fte_match_set_misc,
2665 misc_v, outer_ipv6_flow_label, val);
2666 }
2667 }
2668
2669 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2670 {
2671 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2672 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2673 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2674 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2675 }
2676
2677 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2678 {
2679 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2680 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2681 return -EOPNOTSUPP;
2682
2683 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2684 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2685 return -EOPNOTSUPP;
2686
2687 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2688 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2689 return -EOPNOTSUPP;
2690
2691 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2692 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2693 return -EOPNOTSUPP;
2694
2695 return 0;
2696 }
2697
2698 #define LAST_ETH_FIELD vlan_tag
2699 #define LAST_IB_FIELD sl
2700 #define LAST_IPV4_FIELD tos
2701 #define LAST_IPV6_FIELD traffic_class
2702 #define LAST_TCP_UDP_FIELD src_port
2703 #define LAST_TUNNEL_FIELD tunnel_id
2704 #define LAST_FLOW_TAG_FIELD tag_id
2705 #define LAST_DROP_FIELD size
2706 #define LAST_COUNTERS_FIELD counters
2707
2708 /* Field is the last supported field */
2709 #define FIELDS_NOT_SUPPORTED(filter, field)\
2710 memchr_inv((void *)&filter.field +\
2711 sizeof(filter.field), 0,\
2712 sizeof(filter) -\
2713 offsetof(typeof(filter), field) -\
2714 sizeof(filter.field))
2715
2716 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2717 bool is_egress,
2718 struct mlx5_flow_act *action)
2719 {
2720
2721 switch (maction->ib_action.type) {
2722 case IB_FLOW_ACTION_ESP:
2723 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2724 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2725 return -EINVAL;
2726 /* Currently only AES_GCM keymat is supported by the driver */
2727 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2728 action->action |= is_egress ?
2729 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2730 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2731 return 0;
2732 case IB_FLOW_ACTION_UNSPECIFIED:
2733 if (maction->flow_action_raw.sub_type ==
2734 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2735 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2736 return -EINVAL;
2737 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2738 action->modify_hdr =
2739 maction->flow_action_raw.modify_hdr;
2740 return 0;
2741 }
2742 if (maction->flow_action_raw.sub_type ==
2743 MLX5_IB_FLOW_ACTION_DECAP) {
2744 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2745 return -EINVAL;
2746 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2747 return 0;
2748 }
2749 if (maction->flow_action_raw.sub_type ==
2750 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2751 if (action->action &
2752 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2753 return -EINVAL;
2754 action->action |=
2755 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2756 action->pkt_reformat =
2757 maction->flow_action_raw.pkt_reformat;
2758 return 0;
2759 }
2760 /* fall through */
2761 default:
2762 return -EOPNOTSUPP;
2763 }
2764 }
2765
2766 static int parse_flow_attr(struct mlx5_core_dev *mdev,
2767 struct mlx5_flow_spec *spec,
2768 const union ib_flow_spec *ib_spec,
2769 const struct ib_flow_attr *flow_attr,
2770 struct mlx5_flow_act *action, u32 prev_type)
2771 {
2772 struct mlx5_flow_context *flow_context = &spec->flow_context;
2773 u32 *match_c = spec->match_criteria;
2774 u32 *match_v = spec->match_value;
2775 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2776 misc_parameters);
2777 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2778 misc_parameters);
2779 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2780 misc_parameters_2);
2781 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2782 misc_parameters_2);
2783 void *headers_c;
2784 void *headers_v;
2785 int match_ipv;
2786 int ret;
2787
2788 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2789 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2790 inner_headers);
2791 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2792 inner_headers);
2793 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2794 ft_field_support.inner_ip_version);
2795 } else {
2796 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2797 outer_headers);
2798 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2799 outer_headers);
2800 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2801 ft_field_support.outer_ip_version);
2802 }
2803
2804 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2805 case IB_FLOW_SPEC_ETH:
2806 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2807 return -EOPNOTSUPP;
2808
2809 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2810 dmac_47_16),
2811 ib_spec->eth.mask.dst_mac);
2812 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2813 dmac_47_16),
2814 ib_spec->eth.val.dst_mac);
2815
2816 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2817 smac_47_16),
2818 ib_spec->eth.mask.src_mac);
2819 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2820 smac_47_16),
2821 ib_spec->eth.val.src_mac);
2822
2823 if (ib_spec->eth.mask.vlan_tag) {
2824 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2825 cvlan_tag, 1);
2826 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2827 cvlan_tag, 1);
2828
2829 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2830 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2831 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2832 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2833
2834 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2835 first_cfi,
2836 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2837 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2838 first_cfi,
2839 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2840
2841 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2842 first_prio,
2843 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2844 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2845 first_prio,
2846 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2847 }
2848 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2849 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2850 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2851 ethertype, ntohs(ib_spec->eth.val.ether_type));
2852 break;
2853 case IB_FLOW_SPEC_IPV4:
2854 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2855 return -EOPNOTSUPP;
2856
2857 if (match_ipv) {
2858 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2859 ip_version, 0xf);
2860 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2861 ip_version, MLX5_FS_IPV4_VERSION);
2862 } else {
2863 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2864 ethertype, 0xffff);
2865 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2866 ethertype, ETH_P_IP);
2867 }
2868
2869 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2870 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2871 &ib_spec->ipv4.mask.src_ip,
2872 sizeof(ib_spec->ipv4.mask.src_ip));
2873 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2874 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2875 &ib_spec->ipv4.val.src_ip,
2876 sizeof(ib_spec->ipv4.val.src_ip));
2877 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2878 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2879 &ib_spec->ipv4.mask.dst_ip,
2880 sizeof(ib_spec->ipv4.mask.dst_ip));
2881 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2882 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2883 &ib_spec->ipv4.val.dst_ip,
2884 sizeof(ib_spec->ipv4.val.dst_ip));
2885
2886 set_tos(headers_c, headers_v,
2887 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2888
2889 if (set_proto(headers_c, headers_v,
2890 ib_spec->ipv4.mask.proto,
2891 ib_spec->ipv4.val.proto))
2892 return -EINVAL;
2893 break;
2894 case IB_FLOW_SPEC_IPV6:
2895 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2896 return -EOPNOTSUPP;
2897
2898 if (match_ipv) {
2899 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2900 ip_version, 0xf);
2901 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2902 ip_version, MLX5_FS_IPV6_VERSION);
2903 } else {
2904 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2905 ethertype, 0xffff);
2906 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2907 ethertype, ETH_P_IPV6);
2908 }
2909
2910 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2911 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2912 &ib_spec->ipv6.mask.src_ip,
2913 sizeof(ib_spec->ipv6.mask.src_ip));
2914 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2915 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2916 &ib_spec->ipv6.val.src_ip,
2917 sizeof(ib_spec->ipv6.val.src_ip));
2918 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2919 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2920 &ib_spec->ipv6.mask.dst_ip,
2921 sizeof(ib_spec->ipv6.mask.dst_ip));
2922 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2923 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2924 &ib_spec->ipv6.val.dst_ip,
2925 sizeof(ib_spec->ipv6.val.dst_ip));
2926
2927 set_tos(headers_c, headers_v,
2928 ib_spec->ipv6.mask.traffic_class,
2929 ib_spec->ipv6.val.traffic_class);
2930
2931 if (set_proto(headers_c, headers_v,
2932 ib_spec->ipv6.mask.next_hdr,
2933 ib_spec->ipv6.val.next_hdr))
2934 return -EINVAL;
2935
2936 set_flow_label(misc_params_c, misc_params_v,
2937 ntohl(ib_spec->ipv6.mask.flow_label),
2938 ntohl(ib_spec->ipv6.val.flow_label),
2939 ib_spec->type & IB_FLOW_SPEC_INNER);
2940 break;
2941 case IB_FLOW_SPEC_ESP:
2942 if (ib_spec->esp.mask.seq)
2943 return -EOPNOTSUPP;
2944
2945 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2946 ntohl(ib_spec->esp.mask.spi));
2947 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2948 ntohl(ib_spec->esp.val.spi));
2949 break;
2950 case IB_FLOW_SPEC_TCP:
2951 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2952 LAST_TCP_UDP_FIELD))
2953 return -EOPNOTSUPP;
2954
2955 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2956 return -EINVAL;
2957
2958 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2959 ntohs(ib_spec->tcp_udp.mask.src_port));
2960 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2961 ntohs(ib_spec->tcp_udp.val.src_port));
2962
2963 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2964 ntohs(ib_spec->tcp_udp.mask.dst_port));
2965 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2966 ntohs(ib_spec->tcp_udp.val.dst_port));
2967 break;
2968 case IB_FLOW_SPEC_UDP:
2969 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2970 LAST_TCP_UDP_FIELD))
2971 return -EOPNOTSUPP;
2972
2973 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2974 return -EINVAL;
2975
2976 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2977 ntohs(ib_spec->tcp_udp.mask.src_port));
2978 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2979 ntohs(ib_spec->tcp_udp.val.src_port));
2980
2981 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2982 ntohs(ib_spec->tcp_udp.mask.dst_port));
2983 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2984 ntohs(ib_spec->tcp_udp.val.dst_port));
2985 break;
2986 case IB_FLOW_SPEC_GRE:
2987 if (ib_spec->gre.mask.c_ks_res0_ver)
2988 return -EOPNOTSUPP;
2989
2990 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2991 return -EINVAL;
2992
2993 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2994 0xff);
2995 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2996 IPPROTO_GRE);
2997
2998 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2999 ntohs(ib_spec->gre.mask.protocol));
3000 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
3001 ntohs(ib_spec->gre.val.protocol));
3002
3003 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
3004 gre_key.nvgre.hi),
3005 &ib_spec->gre.mask.key,
3006 sizeof(ib_spec->gre.mask.key));
3007 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
3008 gre_key.nvgre.hi),
3009 &ib_spec->gre.val.key,
3010 sizeof(ib_spec->gre.val.key));
3011 break;
3012 case IB_FLOW_SPEC_MPLS:
3013 switch (prev_type) {
3014 case IB_FLOW_SPEC_UDP:
3015 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3016 ft_field_support.outer_first_mpls_over_udp),
3017 &ib_spec->mpls.mask.tag))
3018 return -EOPNOTSUPP;
3019
3020 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3021 outer_first_mpls_over_udp),
3022 &ib_spec->mpls.val.tag,
3023 sizeof(ib_spec->mpls.val.tag));
3024 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3025 outer_first_mpls_over_udp),
3026 &ib_spec->mpls.mask.tag,
3027 sizeof(ib_spec->mpls.mask.tag));
3028 break;
3029 case IB_FLOW_SPEC_GRE:
3030 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3031 ft_field_support.outer_first_mpls_over_gre),
3032 &ib_spec->mpls.mask.tag))
3033 return -EOPNOTSUPP;
3034
3035 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3036 outer_first_mpls_over_gre),
3037 &ib_spec->mpls.val.tag,
3038 sizeof(ib_spec->mpls.val.tag));
3039 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3040 outer_first_mpls_over_gre),
3041 &ib_spec->mpls.mask.tag,
3042 sizeof(ib_spec->mpls.mask.tag));
3043 break;
3044 default:
3045 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
3046 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3047 ft_field_support.inner_first_mpls),
3048 &ib_spec->mpls.mask.tag))
3049 return -EOPNOTSUPP;
3050
3051 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3052 inner_first_mpls),
3053 &ib_spec->mpls.val.tag,
3054 sizeof(ib_spec->mpls.val.tag));
3055 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3056 inner_first_mpls),
3057 &ib_spec->mpls.mask.tag,
3058 sizeof(ib_spec->mpls.mask.tag));
3059 } else {
3060 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3061 ft_field_support.outer_first_mpls),
3062 &ib_spec->mpls.mask.tag))
3063 return -EOPNOTSUPP;
3064
3065 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
3066 outer_first_mpls),
3067 &ib_spec->mpls.val.tag,
3068 sizeof(ib_spec->mpls.val.tag));
3069 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
3070 outer_first_mpls),
3071 &ib_spec->mpls.mask.tag,
3072 sizeof(ib_spec->mpls.mask.tag));
3073 }
3074 }
3075 break;
3076 case IB_FLOW_SPEC_VXLAN_TUNNEL:
3077 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
3078 LAST_TUNNEL_FIELD))
3079 return -EOPNOTSUPP;
3080
3081 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
3082 ntohl(ib_spec->tunnel.mask.tunnel_id));
3083 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
3084 ntohl(ib_spec->tunnel.val.tunnel_id));
3085 break;
3086 case IB_FLOW_SPEC_ACTION_TAG:
3087 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3088 LAST_FLOW_TAG_FIELD))
3089 return -EOPNOTSUPP;
3090 if (ib_spec->flow_tag.tag_id >= BIT(24))
3091 return -EINVAL;
3092
3093 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3094 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
3095 break;
3096 case IB_FLOW_SPEC_ACTION_DROP:
3097 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3098 LAST_DROP_FIELD))
3099 return -EOPNOTSUPP;
3100 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3101 break;
3102 case IB_FLOW_SPEC_ACTION_HANDLE:
3103 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3104 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3105 if (ret)
3106 return ret;
3107 break;
3108 case IB_FLOW_SPEC_ACTION_COUNT:
3109 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3110 LAST_COUNTERS_FIELD))
3111 return -EOPNOTSUPP;
3112
3113 /* for now support only one counters spec per flow */
3114 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3115 return -EINVAL;
3116
3117 action->counters = ib_spec->flow_count.counters;
3118 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3119 break;
3120 default:
3121 return -EINVAL;
3122 }
3123
3124 return 0;
3125 }
3126
3127 /* If a flow could catch both multicast and unicast packets,
3128 * it won't fall into the multicast flow steering table and this rule
3129 * could steal other multicast packets.
3130 */
3131 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3132 {
3133 union ib_flow_spec *flow_spec;
3134
3135 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3136 ib_attr->num_of_specs < 1)
3137 return false;
3138
3139 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3140 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3141 struct ib_flow_spec_ipv4 *ipv4_spec;
3142
3143 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3144 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3145 return true;
3146
3147 return false;
3148 }
3149
3150 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3151 struct ib_flow_spec_eth *eth_spec;
3152
3153 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3154 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3155 is_multicast_ether_addr(eth_spec->val.dst_mac);
3156 }
3157
3158 return false;
3159 }
3160
3161 enum valid_spec {
3162 VALID_SPEC_INVALID,
3163 VALID_SPEC_VALID,
3164 VALID_SPEC_NA,
3165 };
3166
3167 static enum valid_spec
3168 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3169 const struct mlx5_flow_spec *spec,
3170 const struct mlx5_flow_act *flow_act,
3171 bool egress)
3172 {
3173 const u32 *match_c = spec->match_criteria;
3174 bool is_crypto =
3175 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3176 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3177 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3178 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3179
3180 /*
3181 * Currently only crypto is supported in egress, when regular egress
3182 * rules would be supported, always return VALID_SPEC_NA.
3183 */
3184 if (!is_crypto)
3185 return VALID_SPEC_NA;
3186
3187 return is_crypto && is_ipsec &&
3188 (!egress || (!is_drop &&
3189 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
3190 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3191 }
3192
3193 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3194 const struct mlx5_flow_spec *spec,
3195 const struct mlx5_flow_act *flow_act,
3196 bool egress)
3197 {
3198 /* We curretly only support ipsec egress flow */
3199 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3200 }
3201
3202 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3203 const struct ib_flow_attr *flow_attr,
3204 bool check_inner)
3205 {
3206 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3207 int match_ipv = check_inner ?
3208 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3209 ft_field_support.inner_ip_version) :
3210 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3211 ft_field_support.outer_ip_version);
3212 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3213 bool ipv4_spec_valid, ipv6_spec_valid;
3214 unsigned int ip_spec_type = 0;
3215 bool has_ethertype = false;
3216 unsigned int spec_index;
3217 bool mask_valid = true;
3218 u16 eth_type = 0;
3219 bool type_valid;
3220
3221 /* Validate that ethertype is correct */
3222 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3223 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3224 ib_spec->eth.mask.ether_type) {
3225 mask_valid = (ib_spec->eth.mask.ether_type ==
3226 htons(0xffff));
3227 has_ethertype = true;
3228 eth_type = ntohs(ib_spec->eth.val.ether_type);
3229 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3230 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3231 ip_spec_type = ib_spec->type;
3232 }
3233 ib_spec = (void *)ib_spec + ib_spec->size;
3234 }
3235
3236 type_valid = (!has_ethertype) || (!ip_spec_type);
3237 if (!type_valid && mask_valid) {
3238 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3239 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3240 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3241 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3242
3243 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3244 (((eth_type == ETH_P_MPLS_UC) ||
3245 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3246 }
3247
3248 return type_valid;
3249 }
3250
3251 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3252 const struct ib_flow_attr *flow_attr)
3253 {
3254 return is_valid_ethertype(mdev, flow_attr, false) &&
3255 is_valid_ethertype(mdev, flow_attr, true);
3256 }
3257
3258 static void put_flow_table(struct mlx5_ib_dev *dev,
3259 struct mlx5_ib_flow_prio *prio, bool ft_added)
3260 {
3261 prio->refcount -= !!ft_added;
3262 if (!prio->refcount) {
3263 mlx5_destroy_flow_table(prio->flow_table);
3264 prio->flow_table = NULL;
3265 }
3266 }
3267
3268 static void counters_clear_description(struct ib_counters *counters)
3269 {
3270 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3271
3272 mutex_lock(&mcounters->mcntrs_mutex);
3273 kfree(mcounters->counters_data);
3274 mcounters->counters_data = NULL;
3275 mcounters->cntrs_max_index = 0;
3276 mutex_unlock(&mcounters->mcntrs_mutex);
3277 }
3278
3279 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3280 {
3281 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3282 struct mlx5_ib_flow_handler,
3283 ibflow);
3284 struct mlx5_ib_flow_handler *iter, *tmp;
3285 struct mlx5_ib_dev *dev = handler->dev;
3286
3287 mutex_lock(&dev->flow_db->lock);
3288
3289 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3290 mlx5_del_flow_rules(iter->rule);
3291 put_flow_table(dev, iter->prio, true);
3292 list_del(&iter->list);
3293 kfree(iter);
3294 }
3295
3296 mlx5_del_flow_rules(handler->rule);
3297 put_flow_table(dev, handler->prio, true);
3298 if (handler->ibcounters &&
3299 atomic_read(&handler->ibcounters->usecnt) == 1)
3300 counters_clear_description(handler->ibcounters);
3301
3302 mutex_unlock(&dev->flow_db->lock);
3303 if (handler->flow_matcher)
3304 atomic_dec(&handler->flow_matcher->usecnt);
3305 kfree(handler);
3306
3307 return 0;
3308 }
3309
3310 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3311 {
3312 priority *= 2;
3313 if (!dont_trap)
3314 priority++;
3315 return priority;
3316 }
3317
3318 enum flow_table_type {
3319 MLX5_IB_FT_RX,
3320 MLX5_IB_FT_TX
3321 };
3322
3323 #define MLX5_FS_MAX_TYPES 6
3324 #define MLX5_FS_MAX_ENTRIES BIT(16)
3325
3326 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3327 struct mlx5_ib_flow_prio *prio,
3328 int priority,
3329 int num_entries, int num_groups,
3330 u32 flags)
3331 {
3332 struct mlx5_flow_table_attr ft_attr = {};
3333 struct mlx5_flow_table *ft;
3334
3335 ft_attr.prio = priority;
3336 ft_attr.max_fte = num_entries;
3337 ft_attr.flags = flags;
3338 ft_attr.autogroup.max_num_groups = num_groups;
3339 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
3340 if (IS_ERR(ft))
3341 return ERR_CAST(ft);
3342
3343 prio->flow_table = ft;
3344 prio->refcount = 0;
3345 return prio;
3346 }
3347
3348 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3349 struct ib_flow_attr *flow_attr,
3350 enum flow_table_type ft_type)
3351 {
3352 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3353 struct mlx5_flow_namespace *ns = NULL;
3354 struct mlx5_ib_flow_prio *prio;
3355 struct mlx5_flow_table *ft;
3356 int max_table_size;
3357 int num_entries;
3358 int num_groups;
3359 bool esw_encap;
3360 u32 flags = 0;
3361 int priority;
3362
3363 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3364 log_max_ft_size));
3365 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3366 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3367 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3368 enum mlx5_flow_namespace_type fn_type;
3369
3370 if (flow_is_multicast_only(flow_attr) &&
3371 !dont_trap)
3372 priority = MLX5_IB_FLOW_MCAST_PRIO;
3373 else
3374 priority = ib_prio_to_core_prio(flow_attr->priority,
3375 dont_trap);
3376 if (ft_type == MLX5_IB_FT_RX) {
3377 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3378 prio = &dev->flow_db->prios[priority];
3379 if (!dev->is_rep && !esw_encap &&
3380 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3381 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3382 if (!dev->is_rep && !esw_encap &&
3383 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3384 reformat_l3_tunnel_to_l2))
3385 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3386 } else {
3387 max_table_size =
3388 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3389 log_max_ft_size));
3390 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3391 prio = &dev->flow_db->egress_prios[priority];
3392 if (!dev->is_rep && !esw_encap &&
3393 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3394 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3395 }
3396 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3397 num_entries = MLX5_FS_MAX_ENTRIES;
3398 num_groups = MLX5_FS_MAX_TYPES;
3399 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3400 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3401 ns = mlx5_get_flow_namespace(dev->mdev,
3402 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3403 build_leftovers_ft_param(&priority,
3404 &num_entries,
3405 &num_groups);
3406 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3407 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3408 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3409 allow_sniffer_and_nic_rx_shared_tir))
3410 return ERR_PTR(-ENOTSUPP);
3411
3412 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3413 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3414 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3415
3416 prio = &dev->flow_db->sniffer[ft_type];
3417 priority = 0;
3418 num_entries = 1;
3419 num_groups = 1;
3420 }
3421
3422 if (!ns)
3423 return ERR_PTR(-ENOTSUPP);
3424
3425 max_table_size = min_t(int, num_entries, max_table_size);
3426
3427 ft = prio->flow_table;
3428 if (!ft)
3429 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3430 flags);
3431
3432 return prio;
3433 }
3434
3435 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3436 struct mlx5_flow_spec *spec,
3437 u32 underlay_qpn)
3438 {
3439 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3440 spec->match_criteria,
3441 misc_parameters);
3442 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3443 misc_parameters);
3444
3445 if (underlay_qpn &&
3446 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3447 ft_field_support.bth_dst_qp)) {
3448 MLX5_SET(fte_match_set_misc,
3449 misc_params_v, bth_dst_qp, underlay_qpn);
3450 MLX5_SET(fte_match_set_misc,
3451 misc_params_c, bth_dst_qp, 0xffffff);
3452 }
3453 }
3454
3455 static int read_flow_counters(struct ib_device *ibdev,
3456 struct mlx5_read_counters_attr *read_attr)
3457 {
3458 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3459 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3460
3461 return mlx5_fc_query(dev->mdev, fc,
3462 &read_attr->out[IB_COUNTER_PACKETS],
3463 &read_attr->out[IB_COUNTER_BYTES]);
3464 }
3465
3466 /* flow counters currently expose two counters packets and bytes */
3467 #define FLOW_COUNTERS_NUM 2
3468 static int counters_set_description(struct ib_counters *counters,
3469 enum mlx5_ib_counters_type counters_type,
3470 struct mlx5_ib_flow_counters_desc *desc_data,
3471 u32 ncounters)
3472 {
3473 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3474 u32 cntrs_max_index = 0;
3475 int i;
3476
3477 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3478 return -EINVAL;
3479
3480 /* init the fields for the object */
3481 mcounters->type = counters_type;
3482 mcounters->read_counters = read_flow_counters;
3483 mcounters->counters_num = FLOW_COUNTERS_NUM;
3484 mcounters->ncounters = ncounters;
3485 /* each counter entry have both description and index pair */
3486 for (i = 0; i < ncounters; i++) {
3487 if (desc_data[i].description > IB_COUNTER_BYTES)
3488 return -EINVAL;
3489
3490 if (cntrs_max_index <= desc_data[i].index)
3491 cntrs_max_index = desc_data[i].index + 1;
3492 }
3493
3494 mutex_lock(&mcounters->mcntrs_mutex);
3495 mcounters->counters_data = desc_data;
3496 mcounters->cntrs_max_index = cntrs_max_index;
3497 mutex_unlock(&mcounters->mcntrs_mutex);
3498
3499 return 0;
3500 }
3501
3502 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3503 static int flow_counters_set_data(struct ib_counters *ibcounters,
3504 struct mlx5_ib_create_flow *ucmd)
3505 {
3506 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3507 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3508 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3509 bool hw_hndl = false;
3510 int ret = 0;
3511
3512 if (ucmd && ucmd->ncounters_data != 0) {
3513 cntrs_data = ucmd->data;
3514 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3515 return -EINVAL;
3516
3517 desc_data = kcalloc(cntrs_data->ncounters,
3518 sizeof(*desc_data),
3519 GFP_KERNEL);
3520 if (!desc_data)
3521 return -ENOMEM;
3522
3523 if (copy_from_user(desc_data,
3524 u64_to_user_ptr(cntrs_data->counters_data),
3525 sizeof(*desc_data) * cntrs_data->ncounters)) {
3526 ret = -EFAULT;
3527 goto free;
3528 }
3529 }
3530
3531 if (!mcounters->hw_cntrs_hndl) {
3532 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3533 to_mdev(ibcounters->device)->mdev, false);
3534 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3535 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3536 goto free;
3537 }
3538 hw_hndl = true;
3539 }
3540
3541 if (desc_data) {
3542 /* counters already bound to at least one flow */
3543 if (mcounters->cntrs_max_index) {
3544 ret = -EINVAL;
3545 goto free_hndl;
3546 }
3547
3548 ret = counters_set_description(ibcounters,
3549 MLX5_IB_COUNTERS_FLOW,
3550 desc_data,
3551 cntrs_data->ncounters);
3552 if (ret)
3553 goto free_hndl;
3554
3555 } else if (!mcounters->cntrs_max_index) {
3556 /* counters not bound yet, must have udata passed */
3557 ret = -EINVAL;
3558 goto free_hndl;
3559 }
3560
3561 return 0;
3562
3563 free_hndl:
3564 if (hw_hndl) {
3565 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3566 mcounters->hw_cntrs_hndl);
3567 mcounters->hw_cntrs_hndl = NULL;
3568 }
3569 free:
3570 kfree(desc_data);
3571 return ret;
3572 }
3573
3574 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3575 struct mlx5_flow_spec *spec,
3576 struct mlx5_eswitch_rep *rep)
3577 {
3578 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3579 void *misc;
3580
3581 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3582 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3583 misc_parameters_2);
3584
3585 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3586 mlx5_eswitch_get_vport_metadata_for_match(esw,
3587 rep->vport));
3588 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3589 misc_parameters_2);
3590
3591 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3592 mlx5_eswitch_get_vport_metadata_mask());
3593 } else {
3594 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3595 misc_parameters);
3596
3597 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3598
3599 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3600 misc_parameters);
3601
3602 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3603 }
3604 }
3605
3606 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3607 struct mlx5_ib_flow_prio *ft_prio,
3608 const struct ib_flow_attr *flow_attr,
3609 struct mlx5_flow_destination *dst,
3610 u32 underlay_qpn,
3611 struct mlx5_ib_create_flow *ucmd)
3612 {
3613 struct mlx5_flow_table *ft = ft_prio->flow_table;
3614 struct mlx5_ib_flow_handler *handler;
3615 struct mlx5_flow_act flow_act = {};
3616 struct mlx5_flow_spec *spec;
3617 struct mlx5_flow_destination dest_arr[2] = {};
3618 struct mlx5_flow_destination *rule_dst = dest_arr;
3619 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3620 unsigned int spec_index;
3621 u32 prev_type = 0;
3622 int err = 0;
3623 int dest_num = 0;
3624 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3625
3626 if (!is_valid_attr(dev->mdev, flow_attr))
3627 return ERR_PTR(-EINVAL);
3628
3629 if (dev->is_rep && is_egress)
3630 return ERR_PTR(-EINVAL);
3631
3632 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3633 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3634 if (!handler || !spec) {
3635 err = -ENOMEM;
3636 goto free;
3637 }
3638
3639 INIT_LIST_HEAD(&handler->list);
3640
3641 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3642 err = parse_flow_attr(dev->mdev, spec,
3643 ib_flow, flow_attr, &flow_act,
3644 prev_type);
3645 if (err < 0)
3646 goto free;
3647
3648 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3649 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3650 }
3651
3652 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3653 memcpy(&dest_arr[0], dst, sizeof(*dst));
3654 dest_num++;
3655 }
3656
3657 if (!flow_is_multicast_only(flow_attr))
3658 set_underlay_qp(dev, spec, underlay_qpn);
3659
3660 if (dev->is_rep) {
3661 struct mlx5_eswitch_rep *rep;
3662
3663 rep = dev->port[flow_attr->port - 1].rep;
3664 if (!rep) {
3665 err = -EINVAL;
3666 goto free;
3667 }
3668
3669 mlx5_ib_set_rule_source_port(dev, spec, rep);
3670 }
3671
3672 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3673
3674 if (is_egress &&
3675 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3676 err = -EINVAL;
3677 goto free;
3678 }
3679
3680 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3681 struct mlx5_ib_mcounters *mcounters;
3682
3683 err = flow_counters_set_data(flow_act.counters, ucmd);
3684 if (err)
3685 goto free;
3686
3687 mcounters = to_mcounters(flow_act.counters);
3688 handler->ibcounters = flow_act.counters;
3689 dest_arr[dest_num].type =
3690 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3691 dest_arr[dest_num].counter_id =
3692 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3693 dest_num++;
3694 }
3695
3696 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3697 if (!dest_num)
3698 rule_dst = NULL;
3699 } else {
3700 if (is_egress)
3701 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3702 else
3703 flow_act.action |=
3704 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3705 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3706 }
3707
3708 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
3709 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3710 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3711 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3712 spec->flow_context.flow_tag, flow_attr->type);
3713 err = -EINVAL;
3714 goto free;
3715 }
3716 handler->rule = mlx5_add_flow_rules(ft, spec,
3717 &flow_act,
3718 rule_dst, dest_num);
3719
3720 if (IS_ERR(handler->rule)) {
3721 err = PTR_ERR(handler->rule);
3722 goto free;
3723 }
3724
3725 ft_prio->refcount++;
3726 handler->prio = ft_prio;
3727 handler->dev = dev;
3728
3729 ft_prio->flow_table = ft;
3730 free:
3731 if (err && handler) {
3732 if (handler->ibcounters &&
3733 atomic_read(&handler->ibcounters->usecnt) == 1)
3734 counters_clear_description(handler->ibcounters);
3735 kfree(handler);
3736 }
3737 kvfree(spec);
3738 return err ? ERR_PTR(err) : handler;
3739 }
3740
3741 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3742 struct mlx5_ib_flow_prio *ft_prio,
3743 const struct ib_flow_attr *flow_attr,
3744 struct mlx5_flow_destination *dst)
3745 {
3746 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3747 }
3748
3749 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3750 struct mlx5_ib_flow_prio *ft_prio,
3751 struct ib_flow_attr *flow_attr,
3752 struct mlx5_flow_destination *dst)
3753 {
3754 struct mlx5_ib_flow_handler *handler_dst = NULL;
3755 struct mlx5_ib_flow_handler *handler = NULL;
3756
3757 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3758 if (!IS_ERR(handler)) {
3759 handler_dst = create_flow_rule(dev, ft_prio,
3760 flow_attr, dst);
3761 if (IS_ERR(handler_dst)) {
3762 mlx5_del_flow_rules(handler->rule);
3763 ft_prio->refcount--;
3764 kfree(handler);
3765 handler = handler_dst;
3766 } else {
3767 list_add(&handler_dst->list, &handler->list);
3768 }
3769 }
3770
3771 return handler;
3772 }
3773 enum {
3774 LEFTOVERS_MC,
3775 LEFTOVERS_UC,
3776 };
3777
3778 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3779 struct mlx5_ib_flow_prio *ft_prio,
3780 struct ib_flow_attr *flow_attr,
3781 struct mlx5_flow_destination *dst)
3782 {
3783 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3784 struct mlx5_ib_flow_handler *handler = NULL;
3785
3786 static struct {
3787 struct ib_flow_attr flow_attr;
3788 struct ib_flow_spec_eth eth_flow;
3789 } leftovers_specs[] = {
3790 [LEFTOVERS_MC] = {
3791 .flow_attr = {
3792 .num_of_specs = 1,
3793 .size = sizeof(leftovers_specs[0])
3794 },
3795 .eth_flow = {
3796 .type = IB_FLOW_SPEC_ETH,
3797 .size = sizeof(struct ib_flow_spec_eth),
3798 .mask = {.dst_mac = {0x1} },
3799 .val = {.dst_mac = {0x1} }
3800 }
3801 },
3802 [LEFTOVERS_UC] = {
3803 .flow_attr = {
3804 .num_of_specs = 1,
3805 .size = sizeof(leftovers_specs[0])
3806 },
3807 .eth_flow = {
3808 .type = IB_FLOW_SPEC_ETH,
3809 .size = sizeof(struct ib_flow_spec_eth),
3810 .mask = {.dst_mac = {0x1} },
3811 .val = {.dst_mac = {} }
3812 }
3813 }
3814 };
3815
3816 handler = create_flow_rule(dev, ft_prio,
3817 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3818 dst);
3819 if (!IS_ERR(handler) &&
3820 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3821 handler_ucast = create_flow_rule(dev, ft_prio,
3822 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3823 dst);
3824 if (IS_ERR(handler_ucast)) {
3825 mlx5_del_flow_rules(handler->rule);
3826 ft_prio->refcount--;
3827 kfree(handler);
3828 handler = handler_ucast;
3829 } else {
3830 list_add(&handler_ucast->list, &handler->list);
3831 }
3832 }
3833
3834 return handler;
3835 }
3836
3837 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3838 struct mlx5_ib_flow_prio *ft_rx,
3839 struct mlx5_ib_flow_prio *ft_tx,
3840 struct mlx5_flow_destination *dst)
3841 {
3842 struct mlx5_ib_flow_handler *handler_rx;
3843 struct mlx5_ib_flow_handler *handler_tx;
3844 int err;
3845 static const struct ib_flow_attr flow_attr = {
3846 .num_of_specs = 0,
3847 .size = sizeof(flow_attr)
3848 };
3849
3850 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3851 if (IS_ERR(handler_rx)) {
3852 err = PTR_ERR(handler_rx);
3853 goto err;
3854 }
3855
3856 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3857 if (IS_ERR(handler_tx)) {
3858 err = PTR_ERR(handler_tx);
3859 goto err_tx;
3860 }
3861
3862 list_add(&handler_tx->list, &handler_rx->list);
3863
3864 return handler_rx;
3865
3866 err_tx:
3867 mlx5_del_flow_rules(handler_rx->rule);
3868 ft_rx->refcount--;
3869 kfree(handler_rx);
3870 err:
3871 return ERR_PTR(err);
3872 }
3873
3874 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3875 struct ib_flow_attr *flow_attr,
3876 int domain,
3877 struct ib_udata *udata)
3878 {
3879 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3880 struct mlx5_ib_qp *mqp = to_mqp(qp);
3881 struct mlx5_ib_flow_handler *handler = NULL;
3882 struct mlx5_flow_destination *dst = NULL;
3883 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3884 struct mlx5_ib_flow_prio *ft_prio;
3885 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3886 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3887 size_t min_ucmd_sz, required_ucmd_sz;
3888 int err;
3889 int underlay_qpn;
3890
3891 if (udata && udata->inlen) {
3892 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3893 sizeof(ucmd_hdr.reserved);
3894 if (udata->inlen < min_ucmd_sz)
3895 return ERR_PTR(-EOPNOTSUPP);
3896
3897 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3898 if (err)
3899 return ERR_PTR(err);
3900
3901 /* currently supports only one counters data */
3902 if (ucmd_hdr.ncounters_data > 1)
3903 return ERR_PTR(-EINVAL);
3904
3905 required_ucmd_sz = min_ucmd_sz +
3906 sizeof(struct mlx5_ib_flow_counters_data) *
3907 ucmd_hdr.ncounters_data;
3908 if (udata->inlen > required_ucmd_sz &&
3909 !ib_is_udata_cleared(udata, required_ucmd_sz,
3910 udata->inlen - required_ucmd_sz))
3911 return ERR_PTR(-EOPNOTSUPP);
3912
3913 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3914 if (!ucmd)
3915 return ERR_PTR(-ENOMEM);
3916
3917 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3918 if (err)
3919 goto free_ucmd;
3920 }
3921
3922 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3923 err = -ENOMEM;
3924 goto free_ucmd;
3925 }
3926
3927 if (domain != IB_FLOW_DOMAIN_USER ||
3928 flow_attr->port > dev->num_ports ||
3929 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3930 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3931 err = -EINVAL;
3932 goto free_ucmd;
3933 }
3934
3935 if (is_egress &&
3936 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3937 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3938 err = -EINVAL;
3939 goto free_ucmd;
3940 }
3941
3942 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3943 if (!dst) {
3944 err = -ENOMEM;
3945 goto free_ucmd;
3946 }
3947
3948 mutex_lock(&dev->flow_db->lock);
3949
3950 ft_prio = get_flow_table(dev, flow_attr,
3951 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3952 if (IS_ERR(ft_prio)) {
3953 err = PTR_ERR(ft_prio);
3954 goto unlock;
3955 }
3956 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3957 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3958 if (IS_ERR(ft_prio_tx)) {
3959 err = PTR_ERR(ft_prio_tx);
3960 ft_prio_tx = NULL;
3961 goto destroy_ft;
3962 }
3963 }
3964
3965 if (is_egress) {
3966 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3967 } else {
3968 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3969 if (mqp->flags & MLX5_IB_QP_RSS)
3970 dst->tir_num = mqp->rss_qp.tirn;
3971 else
3972 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3973 }
3974
3975 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3976 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3977 handler = create_dont_trap_rule(dev, ft_prio,
3978 flow_attr, dst);
3979 } else {
3980 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3981 mqp->underlay_qpn : 0;
3982 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3983 dst, underlay_qpn, ucmd);
3984 }
3985 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3986 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3987 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3988 dst);
3989 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3990 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3991 } else {
3992 err = -EINVAL;
3993 goto destroy_ft;
3994 }
3995
3996 if (IS_ERR(handler)) {
3997 err = PTR_ERR(handler);
3998 handler = NULL;
3999 goto destroy_ft;
4000 }
4001
4002 mutex_unlock(&dev->flow_db->lock);
4003 kfree(dst);
4004 kfree(ucmd);
4005
4006 return &handler->ibflow;
4007
4008 destroy_ft:
4009 put_flow_table(dev, ft_prio, false);
4010 if (ft_prio_tx)
4011 put_flow_table(dev, ft_prio_tx, false);
4012 unlock:
4013 mutex_unlock(&dev->flow_db->lock);
4014 kfree(dst);
4015 free_ucmd:
4016 kfree(ucmd);
4017 return ERR_PTR(err);
4018 }
4019
4020 static struct mlx5_ib_flow_prio *
4021 _get_flow_table(struct mlx5_ib_dev *dev,
4022 struct mlx5_ib_flow_matcher *fs_matcher,
4023 bool mcast)
4024 {
4025 struct mlx5_flow_namespace *ns = NULL;
4026 struct mlx5_ib_flow_prio *prio = NULL;
4027 int max_table_size = 0;
4028 bool esw_encap;
4029 u32 flags = 0;
4030 int priority;
4031
4032 if (mcast)
4033 priority = MLX5_IB_FLOW_MCAST_PRIO;
4034 else
4035 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
4036
4037 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
4038 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
4039 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
4040 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
4041 log_max_ft_size));
4042 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
4043 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4044 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
4045 reformat_l3_tunnel_to_l2) &&
4046 !esw_encap)
4047 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
4048 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
4049 max_table_size = BIT(
4050 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
4051 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
4052 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
4053 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
4054 max_table_size = BIT(
4055 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
4056 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
4057 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
4058 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
4059 esw_encap)
4060 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
4061 priority = FDB_BYPASS_PATH;
4062 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
4063 max_table_size =
4064 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
4065 log_max_ft_size));
4066 priority = fs_matcher->priority;
4067 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX) {
4068 max_table_size =
4069 BIT(MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev,
4070 log_max_ft_size));
4071 priority = fs_matcher->priority;
4072 }
4073
4074 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
4075
4076 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
4077 if (!ns)
4078 return ERR_PTR(-ENOTSUPP);
4079
4080 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
4081 prio = &dev->flow_db->prios[priority];
4082 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
4083 prio = &dev->flow_db->egress_prios[priority];
4084 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
4085 prio = &dev->flow_db->fdb;
4086 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
4087 prio = &dev->flow_db->rdma_rx[priority];
4088 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX)
4089 prio = &dev->flow_db->rdma_tx[priority];
4090
4091 if (!prio)
4092 return ERR_PTR(-EINVAL);
4093
4094 if (prio->flow_table)
4095 return prio;
4096
4097 return _get_prio(ns, prio, priority, max_table_size,
4098 MLX5_FS_MAX_TYPES, flags);
4099 }
4100
4101 static struct mlx5_ib_flow_handler *
4102 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
4103 struct mlx5_ib_flow_prio *ft_prio,
4104 struct mlx5_flow_destination *dst,
4105 struct mlx5_ib_flow_matcher *fs_matcher,
4106 struct mlx5_flow_context *flow_context,
4107 struct mlx5_flow_act *flow_act,
4108 void *cmd_in, int inlen,
4109 int dst_num)
4110 {
4111 struct mlx5_ib_flow_handler *handler;
4112 struct mlx5_flow_spec *spec;
4113 struct mlx5_flow_table *ft = ft_prio->flow_table;
4114 int err = 0;
4115
4116 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4117 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4118 if (!handler || !spec) {
4119 err = -ENOMEM;
4120 goto free;
4121 }
4122
4123 INIT_LIST_HEAD(&handler->list);
4124
4125 memcpy(spec->match_value, cmd_in, inlen);
4126 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4127 fs_matcher->mask_len);
4128 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
4129 spec->flow_context = *flow_context;
4130
4131 handler->rule = mlx5_add_flow_rules(ft, spec,
4132 flow_act, dst, dst_num);
4133
4134 if (IS_ERR(handler->rule)) {
4135 err = PTR_ERR(handler->rule);
4136 goto free;
4137 }
4138
4139 ft_prio->refcount++;
4140 handler->prio = ft_prio;
4141 handler->dev = dev;
4142 ft_prio->flow_table = ft;
4143
4144 free:
4145 if (err)
4146 kfree(handler);
4147 kvfree(spec);
4148 return err ? ERR_PTR(err) : handler;
4149 }
4150
4151 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4152 void *match_v)
4153 {
4154 void *match_c;
4155 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4156 void *dmac, *dmac_mask;
4157 void *ipv4, *ipv4_mask;
4158
4159 if (!(fs_matcher->match_criteria_enable &
4160 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4161 return false;
4162
4163 match_c = fs_matcher->matcher_mask.match_params;
4164 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4165 outer_headers);
4166 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4167 outer_headers);
4168
4169 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4170 dmac_47_16);
4171 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4172 dmac_47_16);
4173
4174 if (is_multicast_ether_addr(dmac) &&
4175 is_multicast_ether_addr(dmac_mask))
4176 return true;
4177
4178 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4179 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4180
4181 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4182 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4183
4184 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4185 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4186 return true;
4187
4188 return false;
4189 }
4190
4191 struct mlx5_ib_flow_handler *
4192 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4193 struct mlx5_ib_flow_matcher *fs_matcher,
4194 struct mlx5_flow_context *flow_context,
4195 struct mlx5_flow_act *flow_act,
4196 u32 counter_id,
4197 void *cmd_in, int inlen, int dest_id,
4198 int dest_type)
4199 {
4200 struct mlx5_flow_destination *dst;
4201 struct mlx5_ib_flow_prio *ft_prio;
4202 struct mlx5_ib_flow_handler *handler;
4203 int dst_num = 0;
4204 bool mcast;
4205 int err;
4206
4207 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4208 return ERR_PTR(-EOPNOTSUPP);
4209
4210 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4211 return ERR_PTR(-ENOMEM);
4212
4213 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4214 if (!dst)
4215 return ERR_PTR(-ENOMEM);
4216
4217 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4218 mutex_lock(&dev->flow_db->lock);
4219
4220 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4221 if (IS_ERR(ft_prio)) {
4222 err = PTR_ERR(ft_prio);
4223 goto unlock;
4224 }
4225
4226 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4227 dst[dst_num].type = dest_type;
4228 dst[dst_num].tir_num = dest_id;
4229 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4230 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4231 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4232 dst[dst_num].ft_num = dest_id;
4233 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4234 } else {
4235 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4236 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4237 }
4238
4239 dst_num++;
4240
4241 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4242 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4243 dst[dst_num].counter_id = counter_id;
4244 dst_num++;
4245 }
4246
4247 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4248 flow_context, flow_act,
4249 cmd_in, inlen, dst_num);
4250
4251 if (IS_ERR(handler)) {
4252 err = PTR_ERR(handler);
4253 goto destroy_ft;
4254 }
4255
4256 mutex_unlock(&dev->flow_db->lock);
4257 atomic_inc(&fs_matcher->usecnt);
4258 handler->flow_matcher = fs_matcher;
4259
4260 kfree(dst);
4261
4262 return handler;
4263
4264 destroy_ft:
4265 put_flow_table(dev, ft_prio, false);
4266 unlock:
4267 mutex_unlock(&dev->flow_db->lock);
4268 kfree(dst);
4269
4270 return ERR_PTR(err);
4271 }
4272
4273 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4274 {
4275 u32 flags = 0;
4276
4277 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4278 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4279
4280 return flags;
4281 }
4282
4283 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4284 static struct ib_flow_action *
4285 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4286 const struct ib_flow_action_attrs_esp *attr,
4287 struct uverbs_attr_bundle *attrs)
4288 {
4289 struct mlx5_ib_dev *mdev = to_mdev(device);
4290 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4291 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4292 struct mlx5_ib_flow_action *action;
4293 u64 action_flags;
4294 u64 flags;
4295 int err = 0;
4296
4297 err = uverbs_get_flags64(
4298 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4299 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4300 if (err)
4301 return ERR_PTR(err);
4302
4303 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4304
4305 /* We current only support a subset of the standard features. Only a
4306 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4307 * (with overlap). Full offload mode isn't supported.
4308 */
4309 if (!attr->keymat || attr->replay || attr->encap ||
4310 attr->spi || attr->seq || attr->tfc_pad ||
4311 attr->hard_limit_pkts ||
4312 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4313 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4314 return ERR_PTR(-EOPNOTSUPP);
4315
4316 if (attr->keymat->protocol !=
4317 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4318 return ERR_PTR(-EOPNOTSUPP);
4319
4320 aes_gcm = &attr->keymat->keymat.aes_gcm;
4321
4322 if (aes_gcm->icv_len != 16 ||
4323 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4324 return ERR_PTR(-EOPNOTSUPP);
4325
4326 action = kmalloc(sizeof(*action), GFP_KERNEL);
4327 if (!action)
4328 return ERR_PTR(-ENOMEM);
4329
4330 action->esp_aes_gcm.ib_flags = attr->flags;
4331 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4332 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4333 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4334 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4335 sizeof(accel_attrs.keymat.aes_gcm.salt));
4336 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4337 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4338 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4339 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4340 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4341
4342 accel_attrs.esn = attr->esn;
4343 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4344 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4345 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4346 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4347
4348 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4349 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4350
4351 action->esp_aes_gcm.ctx =
4352 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4353 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4354 err = PTR_ERR(action->esp_aes_gcm.ctx);
4355 goto err_parse;
4356 }
4357
4358 action->esp_aes_gcm.ib_flags = attr->flags;
4359
4360 return &action->ib_action;
4361
4362 err_parse:
4363 kfree(action);
4364 return ERR_PTR(err);
4365 }
4366
4367 static int
4368 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4369 const struct ib_flow_action_attrs_esp *attr,
4370 struct uverbs_attr_bundle *attrs)
4371 {
4372 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4373 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4374 int err = 0;
4375
4376 if (attr->keymat || attr->replay || attr->encap ||
4377 attr->spi || attr->seq || attr->tfc_pad ||
4378 attr->hard_limit_pkts ||
4379 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4380 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4381 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4382 return -EOPNOTSUPP;
4383
4384 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4385 * be modified.
4386 */
4387 if (!(maction->esp_aes_gcm.ib_flags &
4388 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4389 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4390 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4391 return -EINVAL;
4392
4393 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4394 sizeof(accel_attrs));
4395
4396 accel_attrs.esn = attr->esn;
4397 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4398 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4399 else
4400 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4401
4402 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4403 &accel_attrs);
4404 if (err)
4405 return err;
4406
4407 maction->esp_aes_gcm.ib_flags &=
4408 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4409 maction->esp_aes_gcm.ib_flags |=
4410 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4411
4412 return 0;
4413 }
4414
4415 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4416 {
4417 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4418
4419 switch (action->type) {
4420 case IB_FLOW_ACTION_ESP:
4421 /*
4422 * We only support aes_gcm by now, so we implicitly know this is
4423 * the underline crypto.
4424 */
4425 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4426 break;
4427 case IB_FLOW_ACTION_UNSPECIFIED:
4428 mlx5_ib_destroy_flow_action_raw(maction);
4429 break;
4430 default:
4431 WARN_ON(true);
4432 break;
4433 }
4434
4435 kfree(maction);
4436 return 0;
4437 }
4438
4439 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4440 {
4441 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4442 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4443 int err;
4444 u16 uid;
4445
4446 uid = ibqp->pd ?
4447 to_mpd(ibqp->pd)->uid : 0;
4448
4449 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4450 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4451 return -EOPNOTSUPP;
4452 }
4453
4454 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4455 if (err)
4456 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4457 ibqp->qp_num, gid->raw);
4458
4459 return err;
4460 }
4461
4462 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4463 {
4464 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4465 int err;
4466 u16 uid;
4467
4468 uid = ibqp->pd ?
4469 to_mpd(ibqp->pd)->uid : 0;
4470 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4471 if (err)
4472 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4473 ibqp->qp_num, gid->raw);
4474
4475 return err;
4476 }
4477
4478 static int init_node_data(struct mlx5_ib_dev *dev)
4479 {
4480 int err;
4481
4482 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4483 if (err)
4484 return err;
4485
4486 dev->mdev->rev_id = dev->mdev->pdev->revision;
4487
4488 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4489 }
4490
4491 static ssize_t fw_pages_show(struct device *device,
4492 struct device_attribute *attr, char *buf)
4493 {
4494 struct mlx5_ib_dev *dev =
4495 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4496
4497 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4498 }
4499 static DEVICE_ATTR_RO(fw_pages);
4500
4501 static ssize_t reg_pages_show(struct device *device,
4502 struct device_attribute *attr, char *buf)
4503 {
4504 struct mlx5_ib_dev *dev =
4505 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4506
4507 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4508 }
4509 static DEVICE_ATTR_RO(reg_pages);
4510
4511 static ssize_t hca_type_show(struct device *device,
4512 struct device_attribute *attr, char *buf)
4513 {
4514 struct mlx5_ib_dev *dev =
4515 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4516
4517 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4518 }
4519 static DEVICE_ATTR_RO(hca_type);
4520
4521 static ssize_t hw_rev_show(struct device *device,
4522 struct device_attribute *attr, char *buf)
4523 {
4524 struct mlx5_ib_dev *dev =
4525 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4526
4527 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4528 }
4529 static DEVICE_ATTR_RO(hw_rev);
4530
4531 static ssize_t board_id_show(struct device *device,
4532 struct device_attribute *attr, char *buf)
4533 {
4534 struct mlx5_ib_dev *dev =
4535 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4536
4537 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4538 dev->mdev->board_id);
4539 }
4540 static DEVICE_ATTR_RO(board_id);
4541
4542 static struct attribute *mlx5_class_attributes[] = {
4543 &dev_attr_hw_rev.attr,
4544 &dev_attr_hca_type.attr,
4545 &dev_attr_board_id.attr,
4546 &dev_attr_fw_pages.attr,
4547 &dev_attr_reg_pages.attr,
4548 NULL,
4549 };
4550
4551 static const struct attribute_group mlx5_attr_group = {
4552 .attrs = mlx5_class_attributes,
4553 };
4554
4555 static void pkey_change_handler(struct work_struct *work)
4556 {
4557 struct mlx5_ib_port_resources *ports =
4558 container_of(work, struct mlx5_ib_port_resources,
4559 pkey_change_work);
4560
4561 mutex_lock(&ports->devr->mutex);
4562 mlx5_ib_gsi_pkey_change(ports->gsi);
4563 mutex_unlock(&ports->devr->mutex);
4564 }
4565
4566 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4567 {
4568 struct mlx5_ib_qp *mqp;
4569 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4570 struct mlx5_core_cq *mcq;
4571 struct list_head cq_armed_list;
4572 unsigned long flags_qp;
4573 unsigned long flags_cq;
4574 unsigned long flags;
4575
4576 INIT_LIST_HEAD(&cq_armed_list);
4577
4578 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4579 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4580 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4581 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4582 if (mqp->sq.tail != mqp->sq.head) {
4583 send_mcq = to_mcq(mqp->ibqp.send_cq);
4584 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4585 if (send_mcq->mcq.comp &&
4586 mqp->ibqp.send_cq->comp_handler) {
4587 if (!send_mcq->mcq.reset_notify_added) {
4588 send_mcq->mcq.reset_notify_added = 1;
4589 list_add_tail(&send_mcq->mcq.reset_notify,
4590 &cq_armed_list);
4591 }
4592 }
4593 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4594 }
4595 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4596 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4597 /* no handling is needed for SRQ */
4598 if (!mqp->ibqp.srq) {
4599 if (mqp->rq.tail != mqp->rq.head) {
4600 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4601 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4602 if (recv_mcq->mcq.comp &&
4603 mqp->ibqp.recv_cq->comp_handler) {
4604 if (!recv_mcq->mcq.reset_notify_added) {
4605 recv_mcq->mcq.reset_notify_added = 1;
4606 list_add_tail(&recv_mcq->mcq.reset_notify,
4607 &cq_armed_list);
4608 }
4609 }
4610 spin_unlock_irqrestore(&recv_mcq->lock,
4611 flags_cq);
4612 }
4613 }
4614 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4615 }
4616 /*At that point all inflight post send were put to be executed as of we
4617 * lock/unlock above locks Now need to arm all involved CQs.
4618 */
4619 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4620 mcq->comp(mcq, NULL);
4621 }
4622 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4623 }
4624
4625 static void delay_drop_handler(struct work_struct *work)
4626 {
4627 int err;
4628 struct mlx5_ib_delay_drop *delay_drop =
4629 container_of(work, struct mlx5_ib_delay_drop,
4630 delay_drop_work);
4631
4632 atomic_inc(&delay_drop->events_cnt);
4633
4634 mutex_lock(&delay_drop->lock);
4635 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4636 delay_drop->timeout);
4637 if (err) {
4638 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4639 delay_drop->timeout);
4640 delay_drop->activate = false;
4641 }
4642 mutex_unlock(&delay_drop->lock);
4643 }
4644
4645 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4646 struct ib_event *ibev)
4647 {
4648 u8 port = (eqe->data.port.port >> 4) & 0xf;
4649
4650 switch (eqe->sub_type) {
4651 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4652 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4653 IB_LINK_LAYER_ETHERNET)
4654 schedule_work(&ibdev->delay_drop.delay_drop_work);
4655 break;
4656 default: /* do nothing */
4657 return;
4658 }
4659 }
4660
4661 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4662 struct ib_event *ibev)
4663 {
4664 u8 port = (eqe->data.port.port >> 4) & 0xf;
4665
4666 ibev->element.port_num = port;
4667
4668 switch (eqe->sub_type) {
4669 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4670 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4671 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4672 /* In RoCE, port up/down events are handled in
4673 * mlx5_netdev_event().
4674 */
4675 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4676 IB_LINK_LAYER_ETHERNET)
4677 return -EINVAL;
4678
4679 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4680 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4681 break;
4682
4683 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4684 ibev->event = IB_EVENT_LID_CHANGE;
4685 break;
4686
4687 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4688 ibev->event = IB_EVENT_PKEY_CHANGE;
4689 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4690 break;
4691
4692 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4693 ibev->event = IB_EVENT_GID_CHANGE;
4694 break;
4695
4696 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4697 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4698 break;
4699 default:
4700 return -EINVAL;
4701 }
4702
4703 return 0;
4704 }
4705
4706 static void mlx5_ib_handle_event(struct work_struct *_work)
4707 {
4708 struct mlx5_ib_event_work *work =
4709 container_of(_work, struct mlx5_ib_event_work, work);
4710 struct mlx5_ib_dev *ibdev;
4711 struct ib_event ibev;
4712 bool fatal = false;
4713
4714 if (work->is_slave) {
4715 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4716 if (!ibdev)
4717 goto out;
4718 } else {
4719 ibdev = work->dev;
4720 }
4721
4722 switch (work->event) {
4723 case MLX5_DEV_EVENT_SYS_ERROR:
4724 ibev.event = IB_EVENT_DEVICE_FATAL;
4725 mlx5_ib_handle_internal_error(ibdev);
4726 ibev.element.port_num = (u8)(unsigned long)work->param;
4727 fatal = true;
4728 break;
4729 case MLX5_EVENT_TYPE_PORT_CHANGE:
4730 if (handle_port_change(ibdev, work->param, &ibev))
4731 goto out;
4732 break;
4733 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4734 handle_general_event(ibdev, work->param, &ibev);
4735 /* fall through */
4736 default:
4737 goto out;
4738 }
4739
4740 ibev.device = &ibdev->ib_dev;
4741
4742 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4743 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
4744 goto out;
4745 }
4746
4747 if (ibdev->ib_active)
4748 ib_dispatch_event(&ibev);
4749
4750 if (fatal)
4751 ibdev->ib_active = false;
4752 out:
4753 kfree(work);
4754 }
4755
4756 static int mlx5_ib_event(struct notifier_block *nb,
4757 unsigned long event, void *param)
4758 {
4759 struct mlx5_ib_event_work *work;
4760
4761 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4762 if (!work)
4763 return NOTIFY_DONE;
4764
4765 INIT_WORK(&work->work, mlx5_ib_handle_event);
4766 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4767 work->is_slave = false;
4768 work->param = param;
4769 work->event = event;
4770
4771 queue_work(mlx5_ib_event_wq, &work->work);
4772
4773 return NOTIFY_OK;
4774 }
4775
4776 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4777 unsigned long event, void *param)
4778 {
4779 struct mlx5_ib_event_work *work;
4780
4781 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4782 if (!work)
4783 return NOTIFY_DONE;
4784
4785 INIT_WORK(&work->work, mlx5_ib_handle_event);
4786 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4787 work->is_slave = true;
4788 work->param = param;
4789 work->event = event;
4790 queue_work(mlx5_ib_event_wq, &work->work);
4791
4792 return NOTIFY_OK;
4793 }
4794
4795 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4796 {
4797 struct mlx5_hca_vport_context vport_ctx;
4798 int err;
4799 int port;
4800
4801 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4802 dev->mdev->port_caps[port - 1].has_smi = false;
4803 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4804 MLX5_CAP_PORT_TYPE_IB) {
4805 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4806 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4807 port, 0,
4808 &vport_ctx);
4809 if (err) {
4810 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4811 port, err);
4812 return err;
4813 }
4814 dev->mdev->port_caps[port - 1].has_smi =
4815 vport_ctx.has_smi;
4816 } else {
4817 dev->mdev->port_caps[port - 1].has_smi = true;
4818 }
4819 }
4820 }
4821 return 0;
4822 }
4823
4824 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4825 {
4826 int port;
4827
4828 for (port = 1; port <= dev->num_ports; port++)
4829 mlx5_query_ext_port_caps(dev, port);
4830 }
4831
4832 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4833 {
4834 struct ib_device_attr *dprops = NULL;
4835 struct ib_port_attr *pprops = NULL;
4836 int err = -ENOMEM;
4837
4838 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
4839 if (!pprops)
4840 goto out;
4841
4842 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4843 if (!dprops)
4844 goto out;
4845
4846 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
4847 if (err) {
4848 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4849 goto out;
4850 }
4851
4852 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4853 if (err) {
4854 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4855 port, err);
4856 goto out;
4857 }
4858
4859 dev->mdev->port_caps[port - 1].pkey_table_len =
4860 dprops->max_pkeys;
4861 dev->mdev->port_caps[port - 1].gid_table_len =
4862 pprops->gid_tbl_len;
4863 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4864 port, dprops->max_pkeys, pprops->gid_tbl_len);
4865
4866 out:
4867 kfree(pprops);
4868 kfree(dprops);
4869
4870 return err;
4871 }
4872
4873 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4874 {
4875 /* For representors use port 1, is this is the only native
4876 * port
4877 */
4878 if (dev->is_rep)
4879 return __get_port_caps(dev, 1);
4880 return __get_port_caps(dev, port);
4881 }
4882
4883 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4884 {
4885 int err;
4886
4887 err = mlx5_mr_cache_cleanup(dev);
4888 if (err)
4889 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4890
4891 if (dev->umrc.qp)
4892 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4893 if (dev->umrc.cq)
4894 ib_free_cq(dev->umrc.cq);
4895 if (dev->umrc.pd)
4896 ib_dealloc_pd(dev->umrc.pd);
4897 }
4898
4899 enum {
4900 MAX_UMR_WR = 128,
4901 };
4902
4903 static int create_umr_res(struct mlx5_ib_dev *dev)
4904 {
4905 struct ib_qp_init_attr *init_attr = NULL;
4906 struct ib_qp_attr *attr = NULL;
4907 struct ib_pd *pd;
4908 struct ib_cq *cq;
4909 struct ib_qp *qp;
4910 int ret;
4911
4912 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4913 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4914 if (!attr || !init_attr) {
4915 ret = -ENOMEM;
4916 goto error_0;
4917 }
4918
4919 pd = ib_alloc_pd(&dev->ib_dev, 0);
4920 if (IS_ERR(pd)) {
4921 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4922 ret = PTR_ERR(pd);
4923 goto error_0;
4924 }
4925
4926 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4927 if (IS_ERR(cq)) {
4928 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4929 ret = PTR_ERR(cq);
4930 goto error_2;
4931 }
4932
4933 init_attr->send_cq = cq;
4934 init_attr->recv_cq = cq;
4935 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4936 init_attr->cap.max_send_wr = MAX_UMR_WR;
4937 init_attr->cap.max_send_sge = 1;
4938 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4939 init_attr->port_num = 1;
4940 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4941 if (IS_ERR(qp)) {
4942 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4943 ret = PTR_ERR(qp);
4944 goto error_3;
4945 }
4946 qp->device = &dev->ib_dev;
4947 qp->real_qp = qp;
4948 qp->uobject = NULL;
4949 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4950 qp->send_cq = init_attr->send_cq;
4951 qp->recv_cq = init_attr->recv_cq;
4952
4953 attr->qp_state = IB_QPS_INIT;
4954 attr->port_num = 1;
4955 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4956 IB_QP_PORT, NULL);
4957 if (ret) {
4958 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4959 goto error_4;
4960 }
4961
4962 memset(attr, 0, sizeof(*attr));
4963 attr->qp_state = IB_QPS_RTR;
4964 attr->path_mtu = IB_MTU_256;
4965
4966 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4967 if (ret) {
4968 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4969 goto error_4;
4970 }
4971
4972 memset(attr, 0, sizeof(*attr));
4973 attr->qp_state = IB_QPS_RTS;
4974 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4975 if (ret) {
4976 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4977 goto error_4;
4978 }
4979
4980 dev->umrc.qp = qp;
4981 dev->umrc.cq = cq;
4982 dev->umrc.pd = pd;
4983
4984 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4985 ret = mlx5_mr_cache_init(dev);
4986 if (ret) {
4987 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4988 goto error_4;
4989 }
4990
4991 kfree(attr);
4992 kfree(init_attr);
4993
4994 return 0;
4995
4996 error_4:
4997 mlx5_ib_destroy_qp(qp, NULL);
4998 dev->umrc.qp = NULL;
4999
5000 error_3:
5001 ib_free_cq(cq);
5002 dev->umrc.cq = NULL;
5003
5004 error_2:
5005 ib_dealloc_pd(pd);
5006 dev->umrc.pd = NULL;
5007
5008 error_0:
5009 kfree(attr);
5010 kfree(init_attr);
5011 return ret;
5012 }
5013
5014 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
5015 {
5016 switch (umr_fence_cap) {
5017 case MLX5_CAP_UMR_FENCE_NONE:
5018 return MLX5_FENCE_MODE_NONE;
5019 case MLX5_CAP_UMR_FENCE_SMALL:
5020 return MLX5_FENCE_MODE_INITIATOR_SMALL;
5021 default:
5022 return MLX5_FENCE_MODE_STRONG_ORDERING;
5023 }
5024 }
5025
5026 static int create_dev_resources(struct mlx5_ib_resources *devr)
5027 {
5028 struct ib_srq_init_attr attr;
5029 struct mlx5_ib_dev *dev;
5030 struct ib_device *ibdev;
5031 struct ib_cq_init_attr cq_attr = {.cqe = 1};
5032 int port;
5033 int ret = 0;
5034
5035 dev = container_of(devr, struct mlx5_ib_dev, devr);
5036 ibdev = &dev->ib_dev;
5037
5038 mutex_init(&devr->mutex);
5039
5040 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
5041 if (!devr->p0)
5042 return -ENOMEM;
5043
5044 devr->p0->device = ibdev;
5045 devr->p0->uobject = NULL;
5046 atomic_set(&devr->p0->usecnt, 0);
5047
5048 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
5049 if (ret)
5050 goto error0;
5051
5052 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
5053 if (!devr->c0) {
5054 ret = -ENOMEM;
5055 goto error1;
5056 }
5057
5058 devr->c0->device = &dev->ib_dev;
5059 atomic_set(&devr->c0->usecnt, 0);
5060
5061 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
5062 if (ret)
5063 goto err_create_cq;
5064
5065 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
5066 if (IS_ERR(devr->x0)) {
5067 ret = PTR_ERR(devr->x0);
5068 goto error2;
5069 }
5070 devr->x0->device = &dev->ib_dev;
5071 devr->x0->inode = NULL;
5072 atomic_set(&devr->x0->usecnt, 0);
5073 mutex_init(&devr->x0->tgt_qp_mutex);
5074 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
5075
5076 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
5077 if (IS_ERR(devr->x1)) {
5078 ret = PTR_ERR(devr->x1);
5079 goto error3;
5080 }
5081 devr->x1->device = &dev->ib_dev;
5082 devr->x1->inode = NULL;
5083 atomic_set(&devr->x1->usecnt, 0);
5084 mutex_init(&devr->x1->tgt_qp_mutex);
5085 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
5086
5087 memset(&attr, 0, sizeof(attr));
5088 attr.attr.max_sge = 1;
5089 attr.attr.max_wr = 1;
5090 attr.srq_type = IB_SRQT_XRC;
5091 attr.ext.cq = devr->c0;
5092 attr.ext.xrc.xrcd = devr->x0;
5093
5094 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5095 if (!devr->s0) {
5096 ret = -ENOMEM;
5097 goto error4;
5098 }
5099
5100 devr->s0->device = &dev->ib_dev;
5101 devr->s0->pd = devr->p0;
5102 devr->s0->srq_type = IB_SRQT_XRC;
5103 devr->s0->ext.xrc.xrcd = devr->x0;
5104 devr->s0->ext.cq = devr->c0;
5105 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5106 if (ret)
5107 goto err_create;
5108
5109 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
5110 atomic_inc(&devr->s0->ext.cq->usecnt);
5111 atomic_inc(&devr->p0->usecnt);
5112 atomic_set(&devr->s0->usecnt, 0);
5113
5114 memset(&attr, 0, sizeof(attr));
5115 attr.attr.max_sge = 1;
5116 attr.attr.max_wr = 1;
5117 attr.srq_type = IB_SRQT_BASIC;
5118 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5119 if (!devr->s1) {
5120 ret = -ENOMEM;
5121 goto error5;
5122 }
5123
5124 devr->s1->device = &dev->ib_dev;
5125 devr->s1->pd = devr->p0;
5126 devr->s1->srq_type = IB_SRQT_BASIC;
5127 devr->s1->ext.cq = devr->c0;
5128
5129 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5130 if (ret)
5131 goto error6;
5132
5133 atomic_inc(&devr->p0->usecnt);
5134 atomic_set(&devr->s1->usecnt, 0);
5135
5136 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5137 INIT_WORK(&devr->ports[port].pkey_change_work,
5138 pkey_change_handler);
5139 devr->ports[port].devr = devr;
5140 }
5141
5142 return 0;
5143
5144 error6:
5145 kfree(devr->s1);
5146 error5:
5147 mlx5_ib_destroy_srq(devr->s0, NULL);
5148 err_create:
5149 kfree(devr->s0);
5150 error4:
5151 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5152 error3:
5153 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5154 error2:
5155 mlx5_ib_destroy_cq(devr->c0, NULL);
5156 err_create_cq:
5157 kfree(devr->c0);
5158 error1:
5159 mlx5_ib_dealloc_pd(devr->p0, NULL);
5160 error0:
5161 kfree(devr->p0);
5162 return ret;
5163 }
5164
5165 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5166 {
5167 int port;
5168
5169 mlx5_ib_destroy_srq(devr->s1, NULL);
5170 kfree(devr->s1);
5171 mlx5_ib_destroy_srq(devr->s0, NULL);
5172 kfree(devr->s0);
5173 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5174 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5175 mlx5_ib_destroy_cq(devr->c0, NULL);
5176 kfree(devr->c0);
5177 mlx5_ib_dealloc_pd(devr->p0, NULL);
5178 kfree(devr->p0);
5179
5180 /* Make sure no change P_Key work items are still executing */
5181 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5182 cancel_work_sync(&devr->ports[port].pkey_change_work);
5183 }
5184
5185 static u32 get_core_cap_flags(struct ib_device *ibdev,
5186 struct mlx5_hca_vport_context *rep)
5187 {
5188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5189 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5190 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5191 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5192 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5193 u32 ret = 0;
5194
5195 if (rep->grh_required)
5196 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5197
5198 if (ll == IB_LINK_LAYER_INFINIBAND)
5199 return ret | RDMA_CORE_PORT_IBA_IB;
5200
5201 if (raw_support)
5202 ret |= RDMA_CORE_PORT_RAW_PACKET;
5203
5204 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5205 return ret;
5206
5207 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5208 return ret;
5209
5210 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5211 ret |= RDMA_CORE_PORT_IBA_ROCE;
5212
5213 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5214 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5215
5216 return ret;
5217 }
5218
5219 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5220 struct ib_port_immutable *immutable)
5221 {
5222 struct ib_port_attr attr;
5223 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5224 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5225 struct mlx5_hca_vport_context rep = {0};
5226 int err;
5227
5228 err = ib_query_port(ibdev, port_num, &attr);
5229 if (err)
5230 return err;
5231
5232 if (ll == IB_LINK_LAYER_INFINIBAND) {
5233 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5234 &rep);
5235 if (err)
5236 return err;
5237 }
5238
5239 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5240 immutable->gid_tbl_len = attr.gid_tbl_len;
5241 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5242 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5243
5244 return 0;
5245 }
5246
5247 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5248 struct ib_port_immutable *immutable)
5249 {
5250 struct ib_port_attr attr;
5251 int err;
5252
5253 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5254
5255 err = ib_query_port(ibdev, port_num, &attr);
5256 if (err)
5257 return err;
5258
5259 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5260 immutable->gid_tbl_len = attr.gid_tbl_len;
5261 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5262
5263 return 0;
5264 }
5265
5266 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5267 {
5268 struct mlx5_ib_dev *dev =
5269 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5270 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5271 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5272 fw_rev_sub(dev->mdev));
5273 }
5274
5275 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5276 {
5277 struct mlx5_core_dev *mdev = dev->mdev;
5278 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5279 MLX5_FLOW_NAMESPACE_LAG);
5280 struct mlx5_flow_table *ft;
5281 int err;
5282
5283 if (!ns || !mlx5_lag_is_roce(mdev))
5284 return 0;
5285
5286 err = mlx5_cmd_create_vport_lag(mdev);
5287 if (err)
5288 return err;
5289
5290 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5291 if (IS_ERR(ft)) {
5292 err = PTR_ERR(ft);
5293 goto err_destroy_vport_lag;
5294 }
5295
5296 dev->flow_db->lag_demux_ft = ft;
5297 dev->lag_active = true;
5298 return 0;
5299
5300 err_destroy_vport_lag:
5301 mlx5_cmd_destroy_vport_lag(mdev);
5302 return err;
5303 }
5304
5305 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5306 {
5307 struct mlx5_core_dev *mdev = dev->mdev;
5308
5309 if (dev->lag_active) {
5310 dev->lag_active = false;
5311
5312 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5313 dev->flow_db->lag_demux_ft = NULL;
5314
5315 mlx5_cmd_destroy_vport_lag(mdev);
5316 }
5317 }
5318
5319 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5320 {
5321 int err;
5322
5323 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5324 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5325 if (err) {
5326 dev->port[port_num].roce.nb.notifier_call = NULL;
5327 return err;
5328 }
5329
5330 return 0;
5331 }
5332
5333 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5334 {
5335 if (dev->port[port_num].roce.nb.notifier_call) {
5336 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5337 dev->port[port_num].roce.nb.notifier_call = NULL;
5338 }
5339 }
5340
5341 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5342 {
5343 int err;
5344
5345 err = mlx5_nic_vport_enable_roce(dev->mdev);
5346 if (err)
5347 return err;
5348
5349 err = mlx5_eth_lag_init(dev);
5350 if (err)
5351 goto err_disable_roce;
5352
5353 return 0;
5354
5355 err_disable_roce:
5356 mlx5_nic_vport_disable_roce(dev->mdev);
5357
5358 return err;
5359 }
5360
5361 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5362 {
5363 mlx5_eth_lag_cleanup(dev);
5364 mlx5_nic_vport_disable_roce(dev->mdev);
5365 }
5366
5367 struct mlx5_ib_counter {
5368 const char *name;
5369 size_t offset;
5370 };
5371
5372 #define INIT_Q_COUNTER(_name) \
5373 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5374
5375 static const struct mlx5_ib_counter basic_q_cnts[] = {
5376 INIT_Q_COUNTER(rx_write_requests),
5377 INIT_Q_COUNTER(rx_read_requests),
5378 INIT_Q_COUNTER(rx_atomic_requests),
5379 INIT_Q_COUNTER(out_of_buffer),
5380 };
5381
5382 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5383 INIT_Q_COUNTER(out_of_sequence),
5384 };
5385
5386 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5387 INIT_Q_COUNTER(duplicate_request),
5388 INIT_Q_COUNTER(rnr_nak_retry_err),
5389 INIT_Q_COUNTER(packet_seq_err),
5390 INIT_Q_COUNTER(implied_nak_seq_err),
5391 INIT_Q_COUNTER(local_ack_timeout_err),
5392 };
5393
5394 #define INIT_CONG_COUNTER(_name) \
5395 { .name = #_name, .offset = \
5396 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5397
5398 static const struct mlx5_ib_counter cong_cnts[] = {
5399 INIT_CONG_COUNTER(rp_cnp_ignored),
5400 INIT_CONG_COUNTER(rp_cnp_handled),
5401 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5402 INIT_CONG_COUNTER(np_cnp_sent),
5403 };
5404
5405 static const struct mlx5_ib_counter extended_err_cnts[] = {
5406 INIT_Q_COUNTER(resp_local_length_error),
5407 INIT_Q_COUNTER(resp_cqe_error),
5408 INIT_Q_COUNTER(req_cqe_error),
5409 INIT_Q_COUNTER(req_remote_invalid_request),
5410 INIT_Q_COUNTER(req_remote_access_errors),
5411 INIT_Q_COUNTER(resp_remote_access_errors),
5412 INIT_Q_COUNTER(resp_cqe_flush_error),
5413 INIT_Q_COUNTER(req_cqe_flush_error),
5414 };
5415
5416 static const struct mlx5_ib_counter roce_accl_cnts[] = {
5417 INIT_Q_COUNTER(roce_adp_retrans),
5418 INIT_Q_COUNTER(roce_adp_retrans_to),
5419 INIT_Q_COUNTER(roce_slow_restart),
5420 INIT_Q_COUNTER(roce_slow_restart_cnps),
5421 INIT_Q_COUNTER(roce_slow_restart_trans),
5422 };
5423
5424 #define INIT_EXT_PPCNT_COUNTER(_name) \
5425 { .name = #_name, .offset = \
5426 MLX5_BYTE_OFF(ppcnt_reg, \
5427 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5428
5429 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5430 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5431 };
5432
5433 static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5434 {
5435 return MLX5_ESWITCH_MANAGER(mdev) &&
5436 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5437 MLX5_ESWITCH_OFFLOADS;
5438 }
5439
5440 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5441 {
5442 int num_cnt_ports;
5443 int i;
5444
5445 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5446
5447 for (i = 0; i < num_cnt_ports; i++) {
5448 if (dev->port[i].cnts.set_id_valid)
5449 mlx5_core_dealloc_q_counter(dev->mdev,
5450 dev->port[i].cnts.set_id);
5451 kfree(dev->port[i].cnts.names);
5452 kfree(dev->port[i].cnts.offsets);
5453 }
5454 }
5455
5456 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5457 struct mlx5_ib_counters *cnts)
5458 {
5459 u32 num_counters;
5460
5461 num_counters = ARRAY_SIZE(basic_q_cnts);
5462
5463 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5464 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5465
5466 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5467 num_counters += ARRAY_SIZE(retrans_q_cnts);
5468
5469 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5470 num_counters += ARRAY_SIZE(extended_err_cnts);
5471
5472 if (MLX5_CAP_GEN(dev->mdev, roce_accl))
5473 num_counters += ARRAY_SIZE(roce_accl_cnts);
5474
5475 cnts->num_q_counters = num_counters;
5476
5477 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5478 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5479 num_counters += ARRAY_SIZE(cong_cnts);
5480 }
5481 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5482 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5483 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5484 }
5485 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5486 if (!cnts->names)
5487 return -ENOMEM;
5488
5489 cnts->offsets = kcalloc(num_counters,
5490 sizeof(cnts->offsets), GFP_KERNEL);
5491 if (!cnts->offsets)
5492 goto err_names;
5493
5494 return 0;
5495
5496 err_names:
5497 kfree(cnts->names);
5498 cnts->names = NULL;
5499 return -ENOMEM;
5500 }
5501
5502 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5503 const char **names,
5504 size_t *offsets)
5505 {
5506 int i;
5507 int j = 0;
5508
5509 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5510 names[j] = basic_q_cnts[i].name;
5511 offsets[j] = basic_q_cnts[i].offset;
5512 }
5513
5514 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5515 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5516 names[j] = out_of_seq_q_cnts[i].name;
5517 offsets[j] = out_of_seq_q_cnts[i].offset;
5518 }
5519 }
5520
5521 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5522 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5523 names[j] = retrans_q_cnts[i].name;
5524 offsets[j] = retrans_q_cnts[i].offset;
5525 }
5526 }
5527
5528 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5529 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5530 names[j] = extended_err_cnts[i].name;
5531 offsets[j] = extended_err_cnts[i].offset;
5532 }
5533 }
5534
5535 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) {
5536 for (i = 0; i < ARRAY_SIZE(roce_accl_cnts); i++, j++) {
5537 names[j] = roce_accl_cnts[i].name;
5538 offsets[j] = roce_accl_cnts[i].offset;
5539 }
5540 }
5541
5542 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5543 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5544 names[j] = cong_cnts[i].name;
5545 offsets[j] = cong_cnts[i].offset;
5546 }
5547 }
5548
5549 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5550 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5551 names[j] = ext_ppcnt_cnts[i].name;
5552 offsets[j] = ext_ppcnt_cnts[i].offset;
5553 }
5554 }
5555 }
5556
5557 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5558 {
5559 int num_cnt_ports;
5560 int err = 0;
5561 int i;
5562 bool is_shared;
5563
5564 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5565 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5566
5567 for (i = 0; i < num_cnt_ports; i++) {
5568 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5569 if (err)
5570 goto err_alloc;
5571
5572 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5573 dev->port[i].cnts.offsets);
5574
5575 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5576 &dev->port[i].cnts.set_id,
5577 is_shared ?
5578 MLX5_SHARED_RESOURCE_UID : 0);
5579 if (err) {
5580 mlx5_ib_warn(dev,
5581 "couldn't allocate queue counter for port %d, err %d\n",
5582 i + 1, err);
5583 goto err_alloc;
5584 }
5585 dev->port[i].cnts.set_id_valid = true;
5586 }
5587 return 0;
5588
5589 err_alloc:
5590 mlx5_ib_dealloc_counters(dev);
5591 return err;
5592 }
5593
5594 static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5595 u8 port_num)
5596 {
5597 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5598 &dev->port[port_num].cnts;
5599 }
5600
5601 /**
5602 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5603 * @dev: Pointer to mlx5 IB device
5604 * @port_num: Zero based port number
5605 *
5606 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5607 * device port combination in switchdev and non switchdev mode of the
5608 * parent device.
5609 */
5610 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5611 {
5612 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5613
5614 return cnts->set_id;
5615 }
5616
5617 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5618 u8 port_num)
5619 {
5620 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5621 const struct mlx5_ib_counters *cnts;
5622 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
5623
5624 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
5625 return NULL;
5626
5627 cnts = get_counters(dev, port_num - 1);
5628
5629 return rdma_alloc_hw_stats_struct(cnts->names,
5630 cnts->num_q_counters +
5631 cnts->num_cong_counters +
5632 cnts->num_ext_ppcnt_counters,
5633 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5634 }
5635
5636 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5637 const struct mlx5_ib_counters *cnts,
5638 struct rdma_hw_stats *stats,
5639 u16 set_id)
5640 {
5641 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5642 void *out;
5643 __be32 val;
5644 int ret, i;
5645
5646 out = kvzalloc(outlen, GFP_KERNEL);
5647 if (!out)
5648 return -ENOMEM;
5649
5650 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
5651 if (ret)
5652 goto free;
5653
5654 for (i = 0; i < cnts->num_q_counters; i++) {
5655 val = *(__be32 *)(out + cnts->offsets[i]);
5656 stats->value[i] = (u64)be32_to_cpu(val);
5657 }
5658
5659 free:
5660 kvfree(out);
5661 return ret;
5662 }
5663
5664 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5665 const struct mlx5_ib_counters *cnts,
5666 struct rdma_hw_stats *stats)
5667 {
5668 int offset = cnts->num_q_counters + cnts->num_cong_counters;
5669 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5670 int ret, i;
5671 void *out;
5672
5673 out = kvzalloc(sz, GFP_KERNEL);
5674 if (!out)
5675 return -ENOMEM;
5676
5677 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5678 if (ret)
5679 goto free;
5680
5681 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
5682 stats->value[i + offset] =
5683 be64_to_cpup((__be64 *)(out +
5684 cnts->offsets[i + offset]));
5685 free:
5686 kvfree(out);
5687 return ret;
5688 }
5689
5690 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5691 struct rdma_hw_stats *stats,
5692 u8 port_num, int index)
5693 {
5694 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5695 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
5696 struct mlx5_core_dev *mdev;
5697 int ret, num_counters;
5698 u8 mdev_port_num;
5699
5700 if (!stats)
5701 return -EINVAL;
5702
5703 num_counters = cnts->num_q_counters +
5704 cnts->num_cong_counters +
5705 cnts->num_ext_ppcnt_counters;
5706
5707 /* q_counters are per IB device, query the master mdev */
5708 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
5709 if (ret)
5710 return ret;
5711
5712 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5713 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
5714 if (ret)
5715 return ret;
5716 }
5717
5718 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5719 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5720 &mdev_port_num);
5721 if (!mdev) {
5722 /* If port is not affiliated yet, its in down state
5723 * which doesn't have any counters yet, so it would be
5724 * zero. So no need to read from the HCA.
5725 */
5726 goto done;
5727 }
5728 ret = mlx5_lag_query_cong_counters(dev->mdev,
5729 stats->value +
5730 cnts->num_q_counters,
5731 cnts->num_cong_counters,
5732 cnts->offsets +
5733 cnts->num_q_counters);
5734
5735 mlx5_ib_put_native_port_mdev(dev, port_num);
5736 if (ret)
5737 return ret;
5738 }
5739
5740 done:
5741 return num_counters;
5742 }
5743
5744 static struct rdma_hw_stats *
5745 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5746 {
5747 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5748 const struct mlx5_ib_counters *cnts =
5749 get_counters(dev, counter->port - 1);
5750
5751 return rdma_alloc_hw_stats_struct(cnts->names,
5752 cnts->num_q_counters +
5753 cnts->num_cong_counters +
5754 cnts->num_ext_ppcnt_counters,
5755 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5756 }
5757
5758 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5759 {
5760 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5761 const struct mlx5_ib_counters *cnts =
5762 get_counters(dev, counter->port - 1);
5763
5764 return mlx5_ib_query_q_counters(dev->mdev, cnts,
5765 counter->stats, counter->id);
5766 }
5767
5768 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5769 struct ib_qp *qp)
5770 {
5771 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5772 u16 cnt_set_id = 0;
5773 int err;
5774
5775 if (!counter->id) {
5776 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5777 &cnt_set_id,
5778 MLX5_SHARED_RESOURCE_UID);
5779 if (err)
5780 return err;
5781 counter->id = cnt_set_id;
5782 }
5783
5784 err = mlx5_ib_qp_set_counter(qp, counter);
5785 if (err)
5786 goto fail_set_counter;
5787
5788 return 0;
5789
5790 fail_set_counter:
5791 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5792 counter->id = 0;
5793
5794 return err;
5795 }
5796
5797 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5798 {
5799 return mlx5_ib_qp_set_counter(qp, NULL);
5800 }
5801
5802 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5803 {
5804 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5805
5806 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5807 }
5808
5809 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5810 enum rdma_netdev_t type,
5811 struct rdma_netdev_alloc_params *params)
5812 {
5813 if (type != RDMA_NETDEV_IPOIB)
5814 return -EOPNOTSUPP;
5815
5816 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5817 }
5818
5819 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5820 {
5821 if (!dev->delay_drop.dir_debugfs)
5822 return;
5823 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
5824 dev->delay_drop.dir_debugfs = NULL;
5825 }
5826
5827 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5828 {
5829 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5830 return;
5831
5832 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5833 delay_drop_debugfs_cleanup(dev);
5834 }
5835
5836 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5837 size_t count, loff_t *pos)
5838 {
5839 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5840 char lbuf[20];
5841 int len;
5842
5843 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5844 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5845 }
5846
5847 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5848 size_t count, loff_t *pos)
5849 {
5850 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5851 u32 timeout;
5852 u32 var;
5853
5854 if (kstrtouint_from_user(buf, count, 0, &var))
5855 return -EFAULT;
5856
5857 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5858 1000);
5859 if (timeout != var)
5860 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5861 timeout);
5862
5863 delay_drop->timeout = timeout;
5864
5865 return count;
5866 }
5867
5868 static const struct file_operations fops_delay_drop_timeout = {
5869 .owner = THIS_MODULE,
5870 .open = simple_open,
5871 .write = delay_drop_timeout_write,
5872 .read = delay_drop_timeout_read,
5873 };
5874
5875 static void delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5876 {
5877 struct dentry *root;
5878
5879 if (!mlx5_debugfs_root)
5880 return;
5881
5882 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
5883 dev->delay_drop.dir_debugfs = root;
5884
5885 debugfs_create_atomic_t("num_timeout_events", 0400, root,
5886 &dev->delay_drop.events_cnt);
5887 debugfs_create_atomic_t("num_rqs", 0400, root,
5888 &dev->delay_drop.rqs_cnt);
5889 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
5890 &fops_delay_drop_timeout);
5891 }
5892
5893 static void init_delay_drop(struct mlx5_ib_dev *dev)
5894 {
5895 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5896 return;
5897
5898 mutex_init(&dev->delay_drop.lock);
5899 dev->delay_drop.dev = dev;
5900 dev->delay_drop.activate = false;
5901 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5902 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5903 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5904 atomic_set(&dev->delay_drop.events_cnt, 0);
5905
5906 delay_drop_debugfs_init(dev);
5907 }
5908
5909 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5910 struct mlx5_ib_multiport_info *mpi)
5911 {
5912 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5913 struct mlx5_ib_port *port = &ibdev->port[port_num];
5914 int comps;
5915 int err;
5916 int i;
5917
5918 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5919
5920 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5921
5922 spin_lock(&port->mp.mpi_lock);
5923 if (!mpi->ibdev) {
5924 spin_unlock(&port->mp.mpi_lock);
5925 return;
5926 }
5927
5928 mpi->ibdev = NULL;
5929
5930 spin_unlock(&port->mp.mpi_lock);
5931 if (mpi->mdev_events.notifier_call)
5932 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5933 mpi->mdev_events.notifier_call = NULL;
5934 mlx5_remove_netdev_notifier(ibdev, port_num);
5935 spin_lock(&port->mp.mpi_lock);
5936
5937 comps = mpi->mdev_refcnt;
5938 if (comps) {
5939 mpi->unaffiliate = true;
5940 init_completion(&mpi->unref_comp);
5941 spin_unlock(&port->mp.mpi_lock);
5942
5943 for (i = 0; i < comps; i++)
5944 wait_for_completion(&mpi->unref_comp);
5945
5946 spin_lock(&port->mp.mpi_lock);
5947 mpi->unaffiliate = false;
5948 }
5949
5950 port->mp.mpi = NULL;
5951
5952 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5953
5954 spin_unlock(&port->mp.mpi_lock);
5955
5956 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5957
5958 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5959 /* Log an error, still needed to cleanup the pointers and add
5960 * it back to the list.
5961 */
5962 if (err)
5963 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5964 port_num + 1);
5965
5966 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5967 }
5968
5969 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5970 struct mlx5_ib_multiport_info *mpi)
5971 {
5972 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5973 int err;
5974
5975 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5976
5977 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5978 if (ibdev->port[port_num].mp.mpi) {
5979 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5980 port_num + 1);
5981 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5982 return false;
5983 }
5984
5985 ibdev->port[port_num].mp.mpi = mpi;
5986 mpi->ibdev = ibdev;
5987 mpi->mdev_events.notifier_call = NULL;
5988 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5989
5990 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5991 if (err)
5992 goto unbind;
5993
5994 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5995 if (err)
5996 goto unbind;
5997
5998 err = mlx5_add_netdev_notifier(ibdev, port_num);
5999 if (err) {
6000 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
6001 port_num + 1);
6002 goto unbind;
6003 }
6004
6005 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
6006 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
6007
6008 mlx5_ib_init_cong_debugfs(ibdev, port_num);
6009
6010 return true;
6011
6012 unbind:
6013 mlx5_ib_unbind_slave_port(ibdev, mpi);
6014 return false;
6015 }
6016
6017 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
6018 {
6019 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6020 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6021 port_num + 1);
6022 struct mlx5_ib_multiport_info *mpi;
6023 int err;
6024 int i;
6025
6026 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6027 return 0;
6028
6029 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
6030 &dev->sys_image_guid);
6031 if (err)
6032 return err;
6033
6034 err = mlx5_nic_vport_enable_roce(dev->mdev);
6035 if (err)
6036 return err;
6037
6038 mutex_lock(&mlx5_ib_multiport_mutex);
6039 for (i = 0; i < dev->num_ports; i++) {
6040 bool bound = false;
6041
6042 /* build a stub multiport info struct for the native port. */
6043 if (i == port_num) {
6044 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6045 if (!mpi) {
6046 mutex_unlock(&mlx5_ib_multiport_mutex);
6047 mlx5_nic_vport_disable_roce(dev->mdev);
6048 return -ENOMEM;
6049 }
6050
6051 mpi->is_master = true;
6052 mpi->mdev = dev->mdev;
6053 mpi->sys_image_guid = dev->sys_image_guid;
6054 dev->port[i].mp.mpi = mpi;
6055 mpi->ibdev = dev;
6056 mpi = NULL;
6057 continue;
6058 }
6059
6060 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
6061 list) {
6062 if (dev->sys_image_guid == mpi->sys_image_guid &&
6063 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
6064 bound = mlx5_ib_bind_slave_port(dev, mpi);
6065 }
6066
6067 if (bound) {
6068 dev_dbg(mpi->mdev->device,
6069 "removing port from unaffiliated list.\n");
6070 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
6071 list_del(&mpi->list);
6072 break;
6073 }
6074 }
6075 if (!bound) {
6076 get_port_caps(dev, i + 1);
6077 mlx5_ib_dbg(dev, "no free port found for port %d\n",
6078 i + 1);
6079 }
6080 }
6081
6082 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6083 mutex_unlock(&mlx5_ib_multiport_mutex);
6084 return err;
6085 }
6086
6087 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6088 {
6089 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6090 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6091 port_num + 1);
6092 int i;
6093
6094 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6095 return;
6096
6097 mutex_lock(&mlx5_ib_multiport_mutex);
6098 for (i = 0; i < dev->num_ports; i++) {
6099 if (dev->port[i].mp.mpi) {
6100 /* Destroy the native port stub */
6101 if (i == port_num) {
6102 kfree(dev->port[i].mp.mpi);
6103 dev->port[i].mp.mpi = NULL;
6104 } else {
6105 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6106 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6107 }
6108 }
6109 }
6110
6111 mlx5_ib_dbg(dev, "removing from devlist\n");
6112 list_del(&dev->ib_dev_list);
6113 mutex_unlock(&mlx5_ib_multiport_mutex);
6114
6115 mlx5_nic_vport_disable_roce(dev->mdev);
6116 }
6117
6118 static int mmap_obj_cleanup(struct ib_uobject *uobject,
6119 enum rdma_remove_reason why,
6120 struct uverbs_attr_bundle *attrs)
6121 {
6122 struct mlx5_user_mmap_entry *obj = uobject->object;
6123
6124 rdma_user_mmap_entry_remove(&obj->rdma_entry);
6125 return 0;
6126 }
6127
6128 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
6129 struct mlx5_user_mmap_entry *entry,
6130 size_t length)
6131 {
6132 return rdma_user_mmap_entry_insert_range(
6133 &c->ibucontext, &entry->rdma_entry, length,
6134 (MLX5_IB_MMAP_OFFSET_START << 16),
6135 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
6136 }
6137
6138 static struct mlx5_user_mmap_entry *
6139 alloc_var_entry(struct mlx5_ib_ucontext *c)
6140 {
6141 struct mlx5_user_mmap_entry *entry;
6142 struct mlx5_var_table *var_table;
6143 u32 page_idx;
6144 int err;
6145
6146 var_table = &to_mdev(c->ibucontext.device)->var_table;
6147 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
6148 if (!entry)
6149 return ERR_PTR(-ENOMEM);
6150
6151 mutex_lock(&var_table->bitmap_lock);
6152 page_idx = find_first_zero_bit(var_table->bitmap,
6153 var_table->num_var_hw_entries);
6154 if (page_idx >= var_table->num_var_hw_entries) {
6155 err = -ENOSPC;
6156 mutex_unlock(&var_table->bitmap_lock);
6157 goto end;
6158 }
6159
6160 set_bit(page_idx, var_table->bitmap);
6161 mutex_unlock(&var_table->bitmap_lock);
6162
6163 entry->address = var_table->hw_start_addr +
6164 (page_idx * var_table->stride_size);
6165 entry->page_idx = page_idx;
6166 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
6167
6168 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
6169 var_table->stride_size);
6170 if (err)
6171 goto err_insert;
6172
6173 return entry;
6174
6175 err_insert:
6176 mutex_lock(&var_table->bitmap_lock);
6177 clear_bit(page_idx, var_table->bitmap);
6178 mutex_unlock(&var_table->bitmap_lock);
6179 end:
6180 kfree(entry);
6181 return ERR_PTR(err);
6182 }
6183
6184 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
6185 struct uverbs_attr_bundle *attrs)
6186 {
6187 struct ib_uobject *uobj = uverbs_attr_get_uobject(
6188 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
6189 struct mlx5_ib_ucontext *c;
6190 struct mlx5_user_mmap_entry *entry;
6191 u64 mmap_offset;
6192 u32 length;
6193 int err;
6194
6195 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
6196 if (IS_ERR(c))
6197 return PTR_ERR(c);
6198
6199 entry = alloc_var_entry(c);
6200 if (IS_ERR(entry))
6201 return PTR_ERR(entry);
6202
6203 mmap_offset = mlx5_entry_to_mmap_offset(entry);
6204 length = entry->rdma_entry.npages * PAGE_SIZE;
6205 uobj->object = entry;
6206
6207 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6208 &mmap_offset, sizeof(mmap_offset));
6209 if (err)
6210 goto err;
6211
6212 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6213 &entry->page_idx, sizeof(entry->page_idx));
6214 if (err)
6215 goto err;
6216
6217 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6218 &length, sizeof(length));
6219 if (err)
6220 goto err;
6221
6222 return 0;
6223
6224 err:
6225 rdma_user_mmap_entry_remove(&entry->rdma_entry);
6226 return err;
6227 }
6228
6229 DECLARE_UVERBS_NAMED_METHOD(
6230 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
6231 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
6232 MLX5_IB_OBJECT_VAR,
6233 UVERBS_ACCESS_NEW,
6234 UA_MANDATORY),
6235 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
6236 UVERBS_ATTR_TYPE(u32),
6237 UA_MANDATORY),
6238 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
6239 UVERBS_ATTR_TYPE(u32),
6240 UA_MANDATORY),
6241 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
6242 UVERBS_ATTR_TYPE(u64),
6243 UA_MANDATORY));
6244
6245 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
6246 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
6247 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
6248 MLX5_IB_OBJECT_VAR,
6249 UVERBS_ACCESS_DESTROY,
6250 UA_MANDATORY));
6251
6252 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
6253 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
6254 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
6255 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
6256
6257 static bool var_is_supported(struct ib_device *device)
6258 {
6259 struct mlx5_ib_dev *dev = to_mdev(device);
6260
6261 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6262 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
6263 }
6264
6265 static struct mlx5_user_mmap_entry *
6266 alloc_uar_entry(struct mlx5_ib_ucontext *c,
6267 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
6268 {
6269 struct mlx5_user_mmap_entry *entry;
6270 struct mlx5_ib_dev *dev;
6271 u32 uar_index;
6272 int err;
6273
6274 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
6275 if (!entry)
6276 return ERR_PTR(-ENOMEM);
6277
6278 dev = to_mdev(c->ibucontext.device);
6279 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
6280 if (err)
6281 goto end;
6282
6283 entry->page_idx = uar_index;
6284 entry->address = uar_index2paddress(dev, uar_index);
6285 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
6286 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
6287 else
6288 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
6289
6290 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
6291 if (err)
6292 goto err_insert;
6293
6294 return entry;
6295
6296 err_insert:
6297 mlx5_cmd_free_uar(dev->mdev, uar_index);
6298 end:
6299 kfree(entry);
6300 return ERR_PTR(err);
6301 }
6302
6303 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
6304 struct uverbs_attr_bundle *attrs)
6305 {
6306 struct ib_uobject *uobj = uverbs_attr_get_uobject(
6307 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
6308 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
6309 struct mlx5_ib_ucontext *c;
6310 struct mlx5_user_mmap_entry *entry;
6311 u64 mmap_offset;
6312 u32 length;
6313 int err;
6314
6315 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
6316 if (IS_ERR(c))
6317 return PTR_ERR(c);
6318
6319 err = uverbs_get_const(&alloc_type, attrs,
6320 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
6321 if (err)
6322 return err;
6323
6324 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
6325 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
6326 return -EOPNOTSUPP;
6327
6328 if (!to_mdev(c->ibucontext.device)->wc_support &&
6329 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
6330 return -EOPNOTSUPP;
6331
6332 entry = alloc_uar_entry(c, alloc_type);
6333 if (IS_ERR(entry))
6334 return PTR_ERR(entry);
6335
6336 mmap_offset = mlx5_entry_to_mmap_offset(entry);
6337 length = entry->rdma_entry.npages * PAGE_SIZE;
6338 uobj->object = entry;
6339
6340 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
6341 &mmap_offset, sizeof(mmap_offset));
6342 if (err)
6343 goto err;
6344
6345 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
6346 &entry->page_idx, sizeof(entry->page_idx));
6347 if (err)
6348 goto err;
6349
6350 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
6351 &length, sizeof(length));
6352 if (err)
6353 goto err;
6354
6355 return 0;
6356
6357 err:
6358 rdma_user_mmap_entry_remove(&entry->rdma_entry);
6359 return err;
6360 }
6361
6362 DECLARE_UVERBS_NAMED_METHOD(
6363 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
6364 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
6365 MLX5_IB_OBJECT_UAR,
6366 UVERBS_ACCESS_NEW,
6367 UA_MANDATORY),
6368 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
6369 enum mlx5_ib_uapi_uar_alloc_type,
6370 UA_MANDATORY),
6371 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
6372 UVERBS_ATTR_TYPE(u32),
6373 UA_MANDATORY),
6374 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
6375 UVERBS_ATTR_TYPE(u32),
6376 UA_MANDATORY),
6377 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
6378 UVERBS_ATTR_TYPE(u64),
6379 UA_MANDATORY));
6380
6381 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
6382 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
6383 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
6384 MLX5_IB_OBJECT_UAR,
6385 UVERBS_ACCESS_DESTROY,
6386 UA_MANDATORY));
6387
6388 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
6389 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
6390 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
6391 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
6392
6393 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6394 mlx5_ib_dm,
6395 UVERBS_OBJECT_DM,
6396 UVERBS_METHOD_DM_ALLOC,
6397 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6398 UVERBS_ATTR_TYPE(u64),
6399 UA_MANDATORY),
6400 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6401 UVERBS_ATTR_TYPE(u16),
6402 UA_OPTIONAL),
6403 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6404 enum mlx5_ib_uapi_dm_type,
6405 UA_OPTIONAL));
6406
6407 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6408 mlx5_ib_flow_action,
6409 UVERBS_OBJECT_FLOW_ACTION,
6410 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
6411 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6412 enum mlx5_ib_uapi_flow_action_flags));
6413
6414 static const struct uapi_definition mlx5_ib_defs[] = {
6415 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
6416 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6417 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
6418
6419 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6420 &mlx5_ib_flow_action),
6421 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6422 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
6423 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
6424 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
6425 {}
6426 };
6427
6428 static int mlx5_ib_read_counters(struct ib_counters *counters,
6429 struct ib_counters_read_attr *read_attr,
6430 struct uverbs_attr_bundle *attrs)
6431 {
6432 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6433 struct mlx5_read_counters_attr mread_attr = {};
6434 struct mlx5_ib_flow_counters_desc *desc;
6435 int ret, i;
6436
6437 mutex_lock(&mcounters->mcntrs_mutex);
6438 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6439 ret = -EINVAL;
6440 goto err_bound;
6441 }
6442
6443 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6444 GFP_KERNEL);
6445 if (!mread_attr.out) {
6446 ret = -ENOMEM;
6447 goto err_bound;
6448 }
6449
6450 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6451 mread_attr.flags = read_attr->flags;
6452 ret = mcounters->read_counters(counters->device, &mread_attr);
6453 if (ret)
6454 goto err_read;
6455
6456 /* do the pass over the counters data array to assign according to the
6457 * descriptions and indexing pairs
6458 */
6459 desc = mcounters->counters_data;
6460 for (i = 0; i < mcounters->ncounters; i++)
6461 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6462
6463 err_read:
6464 kfree(mread_attr.out);
6465 err_bound:
6466 mutex_unlock(&mcounters->mcntrs_mutex);
6467 return ret;
6468 }
6469
6470 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6471 {
6472 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6473
6474 counters_clear_description(counters);
6475 if (mcounters->hw_cntrs_hndl)
6476 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6477 mcounters->hw_cntrs_hndl);
6478
6479 kfree(mcounters);
6480
6481 return 0;
6482 }
6483
6484 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6485 struct uverbs_attr_bundle *attrs)
6486 {
6487 struct mlx5_ib_mcounters *mcounters;
6488
6489 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6490 if (!mcounters)
6491 return ERR_PTR(-ENOMEM);
6492
6493 mutex_init(&mcounters->mcntrs_mutex);
6494
6495 return &mcounters->ibcntrs;
6496 }
6497
6498 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
6499 {
6500 mlx5_ib_cleanup_multiport_master(dev);
6501 WARN_ON(!xa_empty(&dev->odp_mkeys));
6502 cleanup_srcu_struct(&dev->odp_srcu);
6503
6504 WARN_ON(!xa_empty(&dev->sig_mrs));
6505 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6506 }
6507
6508 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6509 {
6510 struct mlx5_core_dev *mdev = dev->mdev;
6511 int err;
6512 int i;
6513
6514 for (i = 0; i < dev->num_ports; i++) {
6515 spin_lock_init(&dev->port[i].mp.mpi_lock);
6516 rwlock_init(&dev->port[i].roce.netdev_lock);
6517 dev->port[i].roce.dev = dev;
6518 dev->port[i].roce.native_port_num = i + 1;
6519 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6520 }
6521
6522 mlx5_ib_internal_fill_odp_caps(dev);
6523
6524 err = mlx5_ib_init_multiport_master(dev);
6525 if (err)
6526 return err;
6527
6528 err = set_has_smi_cap(dev);
6529 if (err)
6530 return err;
6531
6532 if (!mlx5_core_mp_enabled(mdev)) {
6533 for (i = 1; i <= dev->num_ports; i++) {
6534 err = get_port_caps(dev, i);
6535 if (err)
6536 break;
6537 }
6538 } else {
6539 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6540 }
6541 if (err)
6542 goto err_mp;
6543
6544 if (mlx5_use_mad_ifc(dev))
6545 get_ext_port_caps(dev);
6546
6547 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
6548 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
6549 dev->ib_dev.phys_port_cnt = dev->num_ports;
6550 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
6551 dev->ib_dev.dev.parent = mdev->device;
6552
6553 mutex_init(&dev->cap_mask_mutex);
6554 INIT_LIST_HEAD(&dev->qp_list);
6555 spin_lock_init(&dev->reset_flow_resource_lock);
6556 xa_init(&dev->odp_mkeys);
6557 xa_init(&dev->sig_mrs);
6558 atomic_set(&dev->mkey_var, 0);
6559
6560 spin_lock_init(&dev->dm.lock);
6561 dev->dm.dev = mdev;
6562
6563 err = init_srcu_struct(&dev->odp_srcu);
6564 if (err)
6565 goto err_mp;
6566
6567 return 0;
6568
6569 err_mp:
6570 mlx5_ib_cleanup_multiport_master(dev);
6571
6572 return -ENOMEM;
6573 }
6574
6575 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6576 {
6577 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6578
6579 if (!dev->flow_db)
6580 return -ENOMEM;
6581
6582 mutex_init(&dev->flow_db->lock);
6583
6584 return 0;
6585 }
6586
6587 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6588 {
6589 kfree(dev->flow_db);
6590 }
6591
6592 static const struct ib_device_ops mlx5_ib_dev_ops = {
6593 .owner = THIS_MODULE,
6594 .driver_id = RDMA_DRIVER_MLX5,
6595 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6596
6597 .add_gid = mlx5_ib_add_gid,
6598 .alloc_mr = mlx5_ib_alloc_mr,
6599 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6600 .alloc_pd = mlx5_ib_alloc_pd,
6601 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6602 .attach_mcast = mlx5_ib_mcg_attach,
6603 .check_mr_status = mlx5_ib_check_mr_status,
6604 .create_ah = mlx5_ib_create_ah,
6605 .create_counters = mlx5_ib_create_counters,
6606 .create_cq = mlx5_ib_create_cq,
6607 .create_flow = mlx5_ib_create_flow,
6608 .create_qp = mlx5_ib_create_qp,
6609 .create_srq = mlx5_ib_create_srq,
6610 .dealloc_pd = mlx5_ib_dealloc_pd,
6611 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6612 .del_gid = mlx5_ib_del_gid,
6613 .dereg_mr = mlx5_ib_dereg_mr,
6614 .destroy_ah = mlx5_ib_destroy_ah,
6615 .destroy_counters = mlx5_ib_destroy_counters,
6616 .destroy_cq = mlx5_ib_destroy_cq,
6617 .destroy_flow = mlx5_ib_destroy_flow,
6618 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6619 .destroy_qp = mlx5_ib_destroy_qp,
6620 .destroy_srq = mlx5_ib_destroy_srq,
6621 .detach_mcast = mlx5_ib_mcg_detach,
6622 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6623 .drain_rq = mlx5_ib_drain_rq,
6624 .drain_sq = mlx5_ib_drain_sq,
6625 .enable_driver = mlx5_ib_enable_driver,
6626 .fill_res_entry = mlx5_ib_fill_res_entry,
6627 .fill_stat_entry = mlx5_ib_fill_stat_entry,
6628 .get_dev_fw_str = get_dev_fw_str,
6629 .get_dma_mr = mlx5_ib_get_dma_mr,
6630 .get_link_layer = mlx5_ib_port_link_layer,
6631 .map_mr_sg = mlx5_ib_map_mr_sg,
6632 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6633 .mmap = mlx5_ib_mmap,
6634 .mmap_free = mlx5_ib_mmap_free,
6635 .modify_cq = mlx5_ib_modify_cq,
6636 .modify_device = mlx5_ib_modify_device,
6637 .modify_port = mlx5_ib_modify_port,
6638 .modify_qp = mlx5_ib_modify_qp,
6639 .modify_srq = mlx5_ib_modify_srq,
6640 .poll_cq = mlx5_ib_poll_cq,
6641 .post_recv = mlx5_ib_post_recv,
6642 .post_send = mlx5_ib_post_send,
6643 .post_srq_recv = mlx5_ib_post_srq_recv,
6644 .process_mad = mlx5_ib_process_mad,
6645 .query_ah = mlx5_ib_query_ah,
6646 .query_device = mlx5_ib_query_device,
6647 .query_gid = mlx5_ib_query_gid,
6648 .query_pkey = mlx5_ib_query_pkey,
6649 .query_qp = mlx5_ib_query_qp,
6650 .query_srq = mlx5_ib_query_srq,
6651 .read_counters = mlx5_ib_read_counters,
6652 .reg_user_mr = mlx5_ib_reg_user_mr,
6653 .req_notify_cq = mlx5_ib_arm_cq,
6654 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6655 .resize_cq = mlx5_ib_resize_cq,
6656
6657 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6658 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6659 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6660 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6661 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6662 };
6663
6664 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6665 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6666 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6667 };
6668
6669 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6670 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6671 };
6672
6673 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6674 .get_vf_config = mlx5_ib_get_vf_config,
6675 .get_vf_guid = mlx5_ib_get_vf_guid,
6676 .get_vf_stats = mlx5_ib_get_vf_stats,
6677 .set_vf_guid = mlx5_ib_set_vf_guid,
6678 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6679 };
6680
6681 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6682 .alloc_mw = mlx5_ib_alloc_mw,
6683 .dealloc_mw = mlx5_ib_dealloc_mw,
6684 };
6685
6686 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6687 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6688 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6689 };
6690
6691 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6692 .alloc_dm = mlx5_ib_alloc_dm,
6693 .dealloc_dm = mlx5_ib_dealloc_dm,
6694 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6695 };
6696
6697 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
6698 {
6699 struct mlx5_core_dev *mdev = dev->mdev;
6700 struct mlx5_var_table *var_table = &dev->var_table;
6701 u8 log_doorbell_bar_size;
6702 u8 log_doorbell_stride;
6703 u64 bar_size;
6704
6705 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6706 log_doorbell_bar_size);
6707 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
6708 log_doorbell_stride);
6709 var_table->hw_start_addr = dev->mdev->bar_addr +
6710 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
6711 doorbell_bar_offset);
6712 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
6713 var_table->stride_size = 1ULL << log_doorbell_stride;
6714 var_table->num_var_hw_entries = div_u64(bar_size,
6715 var_table->stride_size);
6716 mutex_init(&var_table->bitmap_lock);
6717 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
6718 GFP_KERNEL);
6719 return (var_table->bitmap) ? 0 : -ENOMEM;
6720 }
6721
6722 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
6723 {
6724 bitmap_free(dev->var_table.bitmap);
6725 }
6726
6727 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6728 {
6729 struct mlx5_core_dev *mdev = dev->mdev;
6730 int err;
6731
6732 dev->ib_dev.uverbs_cmd_mask =
6733 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6734 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6735 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6736 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6737 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
6738 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6739 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
6740 (1ull << IB_USER_VERBS_CMD_REG_MR) |
6741 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
6742 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6743 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6744 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6745 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6746 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6747 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6748 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6749 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6750 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6751 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6752 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6753 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6754 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6755 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6756 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6757 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6758 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6759 dev->ib_dev.uverbs_ex_cmd_mask =
6760 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6761 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
6762 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
6763 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
6764 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6765 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6766 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6767
6768 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6769 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6770 ib_set_device_ops(&dev->ib_dev,
6771 &mlx5_ib_dev_ipoib_enhanced_ops);
6772
6773 if (mlx5_core_is_pf(mdev))
6774 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6775
6776 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6777
6778 if (MLX5_CAP_GEN(mdev, imaicl)) {
6779 dev->ib_dev.uverbs_cmd_mask |=
6780 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6781 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6782 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6783 }
6784
6785 if (MLX5_CAP_GEN(mdev, xrc)) {
6786 dev->ib_dev.uverbs_cmd_mask |=
6787 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6788 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6789 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6790 }
6791
6792 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6793 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6794 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6795 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6796
6797 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6798 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6799 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6800 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6801
6802 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6803 dev->ib_dev.driver_def = mlx5_ib_defs;
6804
6805 err = init_node_data(dev);
6806 if (err)
6807 return err;
6808
6809 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6810 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6811 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6812 mutex_init(&dev->lb.mutex);
6813
6814 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6815 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
6816 err = mlx5_ib_init_var_table(dev);
6817 if (err)
6818 return err;
6819 }
6820
6821 dev->ib_dev.use_cq_dim = true;
6822
6823 return 0;
6824 }
6825
6826 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6827 .get_port_immutable = mlx5_port_immutable,
6828 .query_port = mlx5_ib_query_port,
6829 };
6830
6831 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6832 {
6833 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6834 return 0;
6835 }
6836
6837 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6838 .get_port_immutable = mlx5_port_rep_immutable,
6839 .query_port = mlx5_ib_rep_query_port,
6840 };
6841
6842 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
6843 {
6844 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6845 return 0;
6846 }
6847
6848 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6849 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6850 .create_wq = mlx5_ib_create_wq,
6851 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6852 .destroy_wq = mlx5_ib_destroy_wq,
6853 .get_netdev = mlx5_ib_get_netdev,
6854 .modify_wq = mlx5_ib_modify_wq,
6855 };
6856
6857 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6858 {
6859 u8 port_num;
6860
6861 dev->ib_dev.uverbs_ex_cmd_mask |=
6862 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6863 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6864 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6865 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6866 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6867 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6868
6869 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6870
6871 /* Register only for native ports */
6872 return mlx5_add_netdev_notifier(dev, port_num);
6873 }
6874
6875 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6876 {
6877 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6878
6879 mlx5_remove_netdev_notifier(dev, port_num);
6880 }
6881
6882 static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev)
6883 {
6884 struct mlx5_core_dev *mdev = dev->mdev;
6885 enum rdma_link_layer ll;
6886 int port_type_cap;
6887 int err = 0;
6888
6889 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6890 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6891
6892 if (ll == IB_LINK_LAYER_ETHERNET)
6893 err = mlx5_ib_stage_common_roce_init(dev);
6894
6895 return err;
6896 }
6897
6898 static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev)
6899 {
6900 mlx5_ib_stage_common_roce_cleanup(dev);
6901 }
6902
6903 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6904 {
6905 struct mlx5_core_dev *mdev = dev->mdev;
6906 enum rdma_link_layer ll;
6907 int port_type_cap;
6908 int err;
6909
6910 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6911 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6912
6913 if (ll == IB_LINK_LAYER_ETHERNET) {
6914 err = mlx5_ib_stage_common_roce_init(dev);
6915 if (err)
6916 return err;
6917
6918 err = mlx5_enable_eth(dev);
6919 if (err)
6920 goto cleanup;
6921 }
6922
6923 return 0;
6924 cleanup:
6925 mlx5_ib_stage_common_roce_cleanup(dev);
6926
6927 return err;
6928 }
6929
6930 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6931 {
6932 struct mlx5_core_dev *mdev = dev->mdev;
6933 enum rdma_link_layer ll;
6934 int port_type_cap;
6935
6936 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6937 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6938
6939 if (ll == IB_LINK_LAYER_ETHERNET) {
6940 mlx5_disable_eth(dev);
6941 mlx5_ib_stage_common_roce_cleanup(dev);
6942 }
6943 }
6944
6945 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6946 {
6947 return create_dev_resources(&dev->devr);
6948 }
6949
6950 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6951 {
6952 destroy_dev_resources(&dev->devr);
6953 }
6954
6955 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6956 {
6957 return mlx5_ib_odp_init_one(dev);
6958 }
6959
6960 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6961 {
6962 mlx5_ib_odp_cleanup_one(dev);
6963 }
6964
6965 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6966 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6967 .get_hw_stats = mlx5_ib_get_hw_stats,
6968 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6969 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6970 .counter_dealloc = mlx5_ib_counter_dealloc,
6971 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6972 .counter_update_stats = mlx5_ib_counter_update_stats,
6973 };
6974
6975 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6976 {
6977 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6978 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6979
6980 return mlx5_ib_alloc_counters(dev);
6981 }
6982
6983 return 0;
6984 }
6985
6986 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6987 {
6988 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6989 mlx5_ib_dealloc_counters(dev);
6990 }
6991
6992 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6993 {
6994 mlx5_ib_init_cong_debugfs(dev,
6995 mlx5_core_native_port_num(dev->mdev) - 1);
6996 return 0;
6997 }
6998
6999 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
7000 {
7001 mlx5_ib_cleanup_cong_debugfs(dev,
7002 mlx5_core_native_port_num(dev->mdev) - 1);
7003 }
7004
7005 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
7006 {
7007 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
7008 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
7009 }
7010
7011 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
7012 {
7013 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
7014 }
7015
7016 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
7017 {
7018 int err;
7019
7020 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
7021 if (err)
7022 return err;
7023
7024 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
7025 if (err)
7026 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
7027
7028 return err;
7029 }
7030
7031 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
7032 {
7033 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
7034 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
7035 }
7036
7037 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
7038 {
7039 const char *name;
7040
7041 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7042 if (!mlx5_lag_is_roce(dev->mdev))
7043 name = "mlx5_%d";
7044 else
7045 name = "mlx5_bond_%d";
7046 return ib_register_device(&dev->ib_dev, name);
7047 }
7048
7049 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
7050 {
7051 destroy_umrc_res(dev);
7052 }
7053
7054 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
7055 {
7056 ib_unregister_device(&dev->ib_dev);
7057 }
7058
7059 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
7060 {
7061 return create_umr_res(dev);
7062 }
7063
7064 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
7065 {
7066 init_delay_drop(dev);
7067
7068 return 0;
7069 }
7070
7071 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
7072 {
7073 cancel_delay_drop(dev);
7074 }
7075
7076 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
7077 {
7078 dev->mdev_events.notifier_call = mlx5_ib_event;
7079 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
7080 return 0;
7081 }
7082
7083 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
7084 {
7085 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
7086 }
7087
7088 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
7089 {
7090 int uid;
7091
7092 uid = mlx5_ib_devx_create(dev, false);
7093 if (uid > 0) {
7094 dev->devx_whitelist_uid = uid;
7095 mlx5_ib_devx_init_event_table(dev);
7096 }
7097
7098 return 0;
7099 }
7100 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
7101 {
7102 if (dev->devx_whitelist_uid) {
7103 mlx5_ib_devx_cleanup_event_table(dev);
7104 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
7105 }
7106 }
7107
7108 int mlx5_ib_enable_driver(struct ib_device *dev)
7109 {
7110 struct mlx5_ib_dev *mdev = to_mdev(dev);
7111 int ret;
7112
7113 ret = mlx5_ib_test_wc(mdev);
7114 mlx5_ib_dbg(mdev, "Write-Combining %s",
7115 mdev->wc_support ? "supported" : "not supported");
7116
7117 return ret;
7118 }
7119
7120 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
7121 const struct mlx5_ib_profile *profile,
7122 int stage)
7123 {
7124 dev->ib_active = false;
7125
7126 /* Number of stages to cleanup */
7127 while (stage) {
7128 stage--;
7129 if (profile->stage[stage].cleanup)
7130 profile->stage[stage].cleanup(dev);
7131 }
7132
7133 kfree(dev->port);
7134 ib_dealloc_device(&dev->ib_dev);
7135 }
7136
7137 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
7138 const struct mlx5_ib_profile *profile)
7139 {
7140 int err;
7141 int i;
7142
7143 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
7144 if (profile->stage[i].init) {
7145 err = profile->stage[i].init(dev);
7146 if (err)
7147 goto err_out;
7148 }
7149 }
7150
7151 dev->profile = profile;
7152 dev->ib_active = true;
7153
7154 return dev;
7155
7156 err_out:
7157 __mlx5_ib_remove(dev, profile, i);
7158
7159 return NULL;
7160 }
7161
7162 static const struct mlx5_ib_profile pf_profile = {
7163 STAGE_CREATE(MLX5_IB_STAGE_INIT,
7164 mlx5_ib_stage_init_init,
7165 mlx5_ib_stage_init_cleanup),
7166 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
7167 mlx5_ib_stage_flow_db_init,
7168 mlx5_ib_stage_flow_db_cleanup),
7169 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
7170 mlx5_ib_stage_caps_init,
7171 mlx5_ib_stage_caps_cleanup),
7172 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
7173 mlx5_ib_stage_non_default_cb,
7174 NULL),
7175 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
7176 mlx5_ib_stage_roce_init,
7177 mlx5_ib_stage_roce_cleanup),
7178 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7179 mlx5_init_srq_table,
7180 mlx5_cleanup_srq_table),
7181 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7182 mlx5_ib_stage_dev_res_init,
7183 mlx5_ib_stage_dev_res_cleanup),
7184 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7185 mlx5_ib_stage_dev_notifier_init,
7186 mlx5_ib_stage_dev_notifier_cleanup),
7187 STAGE_CREATE(MLX5_IB_STAGE_ODP,
7188 mlx5_ib_stage_odp_init,
7189 mlx5_ib_stage_odp_cleanup),
7190 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7191 mlx5_ib_stage_counters_init,
7192 mlx5_ib_stage_counters_cleanup),
7193 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7194 mlx5_ib_stage_cong_debugfs_init,
7195 mlx5_ib_stage_cong_debugfs_cleanup),
7196 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7197 mlx5_ib_stage_uar_init,
7198 mlx5_ib_stage_uar_cleanup),
7199 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7200 mlx5_ib_stage_bfrag_init,
7201 mlx5_ib_stage_bfrag_cleanup),
7202 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7203 NULL,
7204 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7205 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7206 mlx5_ib_stage_devx_init,
7207 mlx5_ib_stage_devx_cleanup),
7208 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7209 mlx5_ib_stage_ib_reg_init,
7210 mlx5_ib_stage_ib_reg_cleanup),
7211 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7212 mlx5_ib_stage_post_ib_reg_umr_init,
7213 NULL),
7214 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
7215 mlx5_ib_stage_delay_drop_init,
7216 mlx5_ib_stage_delay_drop_cleanup),
7217 };
7218
7219 const struct mlx5_ib_profile raw_eth_profile = {
7220 STAGE_CREATE(MLX5_IB_STAGE_INIT,
7221 mlx5_ib_stage_init_init,
7222 mlx5_ib_stage_init_cleanup),
7223 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
7224 mlx5_ib_stage_flow_db_init,
7225 mlx5_ib_stage_flow_db_cleanup),
7226 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
7227 mlx5_ib_stage_caps_init,
7228 mlx5_ib_stage_caps_cleanup),
7229 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
7230 mlx5_ib_stage_raw_eth_non_default_cb,
7231 NULL),
7232 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
7233 mlx5_ib_stage_raw_eth_roce_init,
7234 mlx5_ib_stage_raw_eth_roce_cleanup),
7235 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
7236 mlx5_init_srq_table,
7237 mlx5_cleanup_srq_table),
7238 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
7239 mlx5_ib_stage_dev_res_init,
7240 mlx5_ib_stage_dev_res_cleanup),
7241 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
7242 mlx5_ib_stage_dev_notifier_init,
7243 mlx5_ib_stage_dev_notifier_cleanup),
7244 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
7245 mlx5_ib_stage_counters_init,
7246 mlx5_ib_stage_counters_cleanup),
7247 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
7248 mlx5_ib_stage_cong_debugfs_init,
7249 mlx5_ib_stage_cong_debugfs_cleanup),
7250 STAGE_CREATE(MLX5_IB_STAGE_UAR,
7251 mlx5_ib_stage_uar_init,
7252 mlx5_ib_stage_uar_cleanup),
7253 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
7254 mlx5_ib_stage_bfrag_init,
7255 mlx5_ib_stage_bfrag_cleanup),
7256 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
7257 NULL,
7258 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7259 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
7260 mlx5_ib_stage_devx_init,
7261 mlx5_ib_stage_devx_cleanup),
7262 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
7263 mlx5_ib_stage_ib_reg_init,
7264 mlx5_ib_stage_ib_reg_cleanup),
7265 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
7266 mlx5_ib_stage_post_ib_reg_umr_init,
7267 NULL),
7268 };
7269
7270 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
7271 {
7272 struct mlx5_ib_multiport_info *mpi;
7273 struct mlx5_ib_dev *dev;
7274 bool bound = false;
7275 int err;
7276
7277 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
7278 if (!mpi)
7279 return NULL;
7280
7281 mpi->mdev = mdev;
7282
7283 err = mlx5_query_nic_vport_system_image_guid(mdev,
7284 &mpi->sys_image_guid);
7285 if (err) {
7286 kfree(mpi);
7287 return NULL;
7288 }
7289
7290 mutex_lock(&mlx5_ib_multiport_mutex);
7291 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
7292 if (dev->sys_image_guid == mpi->sys_image_guid)
7293 bound = mlx5_ib_bind_slave_port(dev, mpi);
7294
7295 if (bound) {
7296 rdma_roce_rescan_device(&dev->ib_dev);
7297 break;
7298 }
7299 }
7300
7301 if (!bound) {
7302 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
7303 dev_dbg(mdev->device,
7304 "no suitable IB device found to bind to, added to unaffiliated list.\n");
7305 }
7306 mutex_unlock(&mlx5_ib_multiport_mutex);
7307
7308 return mpi;
7309 }
7310
7311 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
7312 {
7313 const struct mlx5_ib_profile *profile;
7314 enum rdma_link_layer ll;
7315 struct mlx5_ib_dev *dev;
7316 int port_type_cap;
7317 int num_ports;
7318
7319 printk_once(KERN_INFO "%s", mlx5_version);
7320
7321 if (MLX5_ESWITCH_MANAGER(mdev) &&
7322 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
7323 if (!mlx5_core_mp_enabled(mdev))
7324 mlx5_ib_register_vport_reps(mdev);
7325 return mdev;
7326 }
7327
7328 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
7329 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
7330
7331 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
7332 return mlx5_ib_add_slave_port(mdev);
7333
7334 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
7335 MLX5_CAP_GEN(mdev, num_vhca_ports));
7336 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
7337 if (!dev)
7338 return NULL;
7339 dev->port = kcalloc(num_ports, sizeof(*dev->port),
7340 GFP_KERNEL);
7341 if (!dev->port) {
7342 ib_dealloc_device(&dev->ib_dev);
7343 return NULL;
7344 }
7345
7346 dev->mdev = mdev;
7347 dev->num_ports = num_ports;
7348
7349 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
7350 profile = &raw_eth_profile;
7351 else
7352 profile = &pf_profile;
7353
7354 return __mlx5_ib_add(dev, profile);
7355 }
7356
7357 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
7358 {
7359 struct mlx5_ib_multiport_info *mpi;
7360 struct mlx5_ib_dev *dev;
7361
7362 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
7363 mlx5_ib_unregister_vport_reps(mdev);
7364 return;
7365 }
7366
7367 if (mlx5_core_is_mp_slave(mdev)) {
7368 mpi = context;
7369 mutex_lock(&mlx5_ib_multiport_mutex);
7370 if (mpi->ibdev)
7371 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
7372 list_del(&mpi->list);
7373 mutex_unlock(&mlx5_ib_multiport_mutex);
7374 kfree(mpi);
7375 return;
7376 }
7377
7378 dev = context;
7379 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
7380 }
7381
7382 static struct mlx5_interface mlx5_ib_interface = {
7383 .add = mlx5_ib_add,
7384 .remove = mlx5_ib_remove,
7385 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
7386 };
7387
7388 unsigned long mlx5_ib_get_xlt_emergency_page(void)
7389 {
7390 mutex_lock(&xlt_emergency_page_mutex);
7391 return xlt_emergency_page;
7392 }
7393
7394 void mlx5_ib_put_xlt_emergency_page(void)
7395 {
7396 mutex_unlock(&xlt_emergency_page_mutex);
7397 }
7398
7399 static int __init mlx5_ib_init(void)
7400 {
7401 int err;
7402
7403 xlt_emergency_page = __get_free_page(GFP_KERNEL);
7404 if (!xlt_emergency_page)
7405 return -ENOMEM;
7406
7407 mutex_init(&xlt_emergency_page_mutex);
7408
7409 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
7410 if (!mlx5_ib_event_wq) {
7411 free_page(xlt_emergency_page);
7412 return -ENOMEM;
7413 }
7414
7415 mlx5_ib_odp_init();
7416
7417 err = mlx5_register_interface(&mlx5_ib_interface);
7418
7419 return err;
7420 }
7421
7422 static void __exit mlx5_ib_cleanup(void)
7423 {
7424 mlx5_unregister_interface(&mlx5_ib_interface);
7425 destroy_workqueue(mlx5_ib_event_wq);
7426 mutex_destroy(&xlt_emergency_page_mutex);
7427 free_page(xlt_emergency_page);
7428 }
7429
7430 module_init(mlx5_ib_init);
7431 module_exit(mlx5_ib_cleanup);
Linux with added FPC-III support