drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/bitfield.h>
  18
  19 #include <dt-bindings/net/ti-dp83867.h>
  20
  21 #define DP83867_PHY_ID          0x2000a231
  22 #define DP83867_DEVADDR         0x1f
  23
  24 #define MII_DP83867_PHYCTRL     0x10
  25 #define MII_DP83867_PHYSTS      0x11
  26 #define MII_DP83867_MICR        0x12
  27 #define MII_DP83867_ISR         0x13
  28 #define DP83867_CFG2            0x14
  29 #define DP83867_CFG3            0x1e
  30 #define DP83867_CTRL            0x1f
  31
  32 /* Extended Registers */
  33 #define DP83867_FLD_THR_CFG     0x002e
  34 #define DP83867_CFG4            0x0031
  35 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  38 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  39 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  40
  41 #define DP83867_RGMIICTL        0x0032
  42 #define DP83867_STRAP_STS1      0x006E
  43 #define DP83867_STRAP_STS2      0x006f
  44 #define DP83867_RGMIIDCTL       0x0086
  45 #define DP83867_RXFCFG          0x0134
  46 #define DP83867_RXFPMD1 0x0136
  47 #define DP83867_RXFPMD2 0x0137
  48 #define DP83867_RXFPMD3 0x0138
  49 #define DP83867_RXFSOP1 0x0139
  50 #define DP83867_RXFSOP2 0x013A
  51 #define DP83867_RXFSOP3 0x013B
  52 #define DP83867_IO_MUX_CFG      0x0170
  53 #define DP83867_SGMIICTL        0x00D3
  54 #define DP83867_10M_SGMII_CFG   0x016F
  55 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  56
  57 #define DP83867_SW_RESET        BIT(15)
  58 #define DP83867_SW_RESTART      BIT(14)
  59
  60 /* MICR Interrupt bits */
  61 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  62 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  63 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  64 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  65 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  66 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  67 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  68 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  69 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  70 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  71 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  72 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  73
  74 /* RGMIICTL bits */
  75 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  76 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  77
  78 /* SGMIICTL bits */
  79 #define DP83867_SGMII_TYPE              BIT(14)
  80
  81 /* RXFCFG bits*/
  82 #define DP83867_WOL_MAGIC_EN            BIT(0)
  83 #define DP83867_WOL_BCAST_EN            BIT(2)
  84 #define DP83867_WOL_UCAST_EN            BIT(4)
  85 #define DP83867_WOL_SEC_EN              BIT(5)
  86 #define DP83867_WOL_ENH_MAC             BIT(7)
  87
  88 /* STRAP_STS1 bits */
  89 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  90
  91 /* STRAP_STS2 bits */
  92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  93 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  95 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  96 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  97 #define DP83867_STRAP_STS2_STRAP_FLD            BIT(10)
  98
  99 /* PHY CTRL bits */
 100 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
 101 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
 102 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
 103 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 104 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 105 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 106 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 107
 108 /* RGMIIDCTL bits */
 109 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 110 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 111 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 112 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 113 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 114 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 115
 116
 117 /* IO_MUX_CFG bits */
 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 120 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 121 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 122 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 123 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 124
 125 /* PHY STS bits */
 126 #define DP83867_PHYSTS_1000                     BIT(15)
 127 #define DP83867_PHYSTS_100                      BIT(14)
 128 #define DP83867_PHYSTS_DUPLEX                   BIT(13)
 129 #define DP83867_PHYSTS_LINK                     BIT(10)
 130
 131 /* CFG2 bits */
 132 #define DP83867_DOWNSHIFT_EN            (BIT(8) | BIT(9))
 133 #define DP83867_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
 134 #define DP83867_DOWNSHIFT_1_COUNT_VAL   0
 135 #define DP83867_DOWNSHIFT_2_COUNT_VAL   1
 136 #define DP83867_DOWNSHIFT_4_COUNT_VAL   2
 137 #define DP83867_DOWNSHIFT_8_COUNT_VAL   3
 138 #define DP83867_DOWNSHIFT_1_COUNT       1
 139 #define DP83867_DOWNSHIFT_2_COUNT       2
 140 #define DP83867_DOWNSHIFT_4_COUNT       4
 141 #define DP83867_DOWNSHIFT_8_COUNT       8
 142
 143 /* CFG3 bits */
 144 #define DP83867_CFG3_INT_OE                     BIT(7)
 145 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 146
 147 /* CFG4 bits */
 148 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 149
 150 /* FLD_THR_CFG */
 151 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK        0x7
 152
 153 enum {
 154         DP83867_PORT_MIRROING_KEEP,
 155         DP83867_PORT_MIRROING_EN,
 156         DP83867_PORT_MIRROING_DIS,
 157 };
 158
 159 struct dp83867_private {
 160         u32 rx_id_delay;
 161         u32 tx_id_delay;
 162         u32 tx_fifo_depth;
 163         u32 rx_fifo_depth;
 164         int io_impedance;
 165         int port_mirroring;
 166         bool rxctrl_strap_quirk;
 167         bool set_clk_output;
 168         u32 clk_output_sel;
 169         bool sgmii_ref_clk_en;
 170 };
 171
 172 static int dp83867_ack_interrupt(struct phy_device *phydev)
 173 {
 174         int err = phy_read(phydev, MII_DP83867_ISR);
 175
 176         if (err < 0)
 177                 return err;
 178
 179         return 0;
 180 }
 181
 182 static int dp83867_set_wol(struct phy_device *phydev,
 183                            struct ethtool_wolinfo *wol)
 184 {
 185         struct net_device *ndev = phydev->attached_dev;
 186         u16 val_rxcfg, val_micr;
 187         u8 *mac;
 188
 189         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 190         val_micr = phy_read(phydev, MII_DP83867_MICR);
 191
 192         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 193                             WAKE_BCAST)) {
 194                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 195                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 196
 197                 if (wol->wolopts & WAKE_MAGIC) {
 198                         mac = (u8 *)ndev->dev_addr;
 199
 200                         if (!is_valid_ether_addr(mac))
 201                                 return -EINVAL;
 202
 203                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 204                                       (mac[1] << 8 | mac[0]));
 205                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 206                                       (mac[3] << 8 | mac[2]));
 207                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 208                                       (mac[5] << 8 | mac[4]));
 209
 210                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 211                 } else {
 212                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 213                 }
 214
 215                 if (wol->wolopts & WAKE_MAGICSECURE) {
 216                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 217                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 218                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 219                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 220                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 221                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 222
 223                         val_rxcfg |= DP83867_WOL_SEC_EN;
 224                 } else {
 225                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 226                 }
 227
 228                 if (wol->wolopts & WAKE_UCAST)
 229                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 230                 else
 231                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 232
 233                 if (wol->wolopts & WAKE_BCAST)
 234                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 235                 else
 236                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 237         } else {
 238                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 239                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 240         }
 241
 242         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 243         phy_write(phydev, MII_DP83867_MICR, val_micr);
 244
 245         return 0;
 246 }
 247
 248 static void dp83867_get_wol(struct phy_device *phydev,
 249                             struct ethtool_wolinfo *wol)
 250 {
 251         u16 value, sopass_val;
 252
 253         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 254                         WAKE_MAGICSECURE);
 255         wol->wolopts = 0;
 256
 257         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 258
 259         if (value & DP83867_WOL_UCAST_EN)
 260                 wol->wolopts |= WAKE_UCAST;
 261
 262         if (value & DP83867_WOL_BCAST_EN)
 263                 wol->wolopts |= WAKE_BCAST;
 264
 265         if (value & DP83867_WOL_MAGIC_EN)
 266                 wol->wolopts |= WAKE_MAGIC;
 267
 268         if (value & DP83867_WOL_SEC_EN) {
 269                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 270                                           DP83867_RXFSOP1);
 271                 wol->sopass[0] = (sopass_val & 0xff);
 272                 wol->sopass[1] = (sopass_val >> 8);
 273
 274                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 275                                           DP83867_RXFSOP2);
 276                 wol->sopass[2] = (sopass_val & 0xff);
 277                 wol->sopass[3] = (sopass_val >> 8);
 278
 279                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 280                                           DP83867_RXFSOP3);
 281                 wol->sopass[4] = (sopass_val & 0xff);
 282                 wol->sopass[5] = (sopass_val >> 8);
 283
 284                 wol->wolopts |= WAKE_MAGICSECURE;
 285         }
 286
 287         if (!(value & DP83867_WOL_ENH_MAC))
 288                 wol->wolopts = 0;
 289 }
 290
 291 static int dp83867_config_intr(struct phy_device *phydev)
 292 {
 293         int micr_status;
 294
 295         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 296                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 297                 if (micr_status < 0)
 298                         return micr_status;
 299
 300                 micr_status |=
 301                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 302                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 303                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 304                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 305                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 306                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 307
 308                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 309         }
 310
 311         micr_status = 0x0;
 312         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 313 }
 314
 315 static int dp83867_read_status(struct phy_device *phydev)
 316 {
 317         int status = phy_read(phydev, MII_DP83867_PHYSTS);
 318         int ret;
 319
 320         ret = genphy_read_status(phydev);
 321         if (ret)
 322                 return ret;
 323
 324         if (status < 0)
 325                 return status;
 326
 327         if (status & DP83867_PHYSTS_DUPLEX)
 328                 phydev->duplex = DUPLEX_FULL;
 329         else
 330                 phydev->duplex = DUPLEX_HALF;
 331
 332         if (status & DP83867_PHYSTS_1000)
 333                 phydev->speed = SPEED_1000;
 334         else if (status & DP83867_PHYSTS_100)
 335                 phydev->speed = SPEED_100;
 336         else
 337                 phydev->speed = SPEED_10;
 338
 339         return 0;
 340 }
 341
 342 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
 343 {
 344         int val, cnt, enable, count;
 345
 346         val = phy_read(phydev, DP83867_CFG2);
 347         if (val < 0)
 348                 return val;
 349
 350         enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
 351         cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
 352
 353         switch (cnt) {
 354         case DP83867_DOWNSHIFT_1_COUNT_VAL:
 355                 count = DP83867_DOWNSHIFT_1_COUNT;
 356                 break;
 357         case DP83867_DOWNSHIFT_2_COUNT_VAL:
 358                 count = DP83867_DOWNSHIFT_2_COUNT;
 359                 break;
 360         case DP83867_DOWNSHIFT_4_COUNT_VAL:
 361                 count = DP83867_DOWNSHIFT_4_COUNT;
 362                 break;
 363         case DP83867_DOWNSHIFT_8_COUNT_VAL:
 364                 count = DP83867_DOWNSHIFT_8_COUNT;
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         };
 369
 370         *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
 371
 372         return 0;
 373 }
 374
 375 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
 376 {
 377         int val, count;
 378
 379         if (cnt > DP83867_DOWNSHIFT_8_COUNT)
 380                 return -E2BIG;
 381
 382         if (!cnt)
 383                 return phy_clear_bits(phydev, DP83867_CFG2,
 384                                       DP83867_DOWNSHIFT_EN);
 385
 386         switch (cnt) {
 387                 case DP83867_DOWNSHIFT_1_COUNT:
 388                         count = DP83867_DOWNSHIFT_1_COUNT_VAL;
 389                         break;
 390                 case DP83867_DOWNSHIFT_2_COUNT:
 391                         count = DP83867_DOWNSHIFT_2_COUNT_VAL;
 392                         break;
 393                 case DP83867_DOWNSHIFT_4_COUNT:
 394                         count = DP83867_DOWNSHIFT_4_COUNT_VAL;
 395                         break;
 396                 case DP83867_DOWNSHIFT_8_COUNT:
 397                         count = DP83867_DOWNSHIFT_8_COUNT_VAL;
 398                         break;
 399                 default:
 400                         phydev_err(phydev,
 401                                    "Downshift count must be 1, 2, 4 or 8\n");
 402                         return -EINVAL;
 403         };
 404
 405         val = DP83867_DOWNSHIFT_EN;
 406         val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
 407
 408         return phy_modify(phydev, DP83867_CFG2,
 409                           DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
 410                           val);
 411 }
 412
 413 static int dp83867_get_tunable(struct phy_device *phydev,
 414                                 struct ethtool_tunable *tuna, void *data)
 415 {
 416         switch (tuna->id) {
 417         case ETHTOOL_PHY_DOWNSHIFT:
 418                 return dp83867_get_downshift(phydev, data);
 419         default:
 420                 return -EOPNOTSUPP;
 421         }
 422 }
 423
 424 static int dp83867_set_tunable(struct phy_device *phydev,
 425                                 struct ethtool_tunable *tuna, const void *data)
 426 {
 427         switch (tuna->id) {
 428         case ETHTOOL_PHY_DOWNSHIFT:
 429                 return dp83867_set_downshift(phydev, *(const u8 *)data);
 430         default:
 431                 return -EOPNOTSUPP;
 432         }
 433 }
 434
 435 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 436 {
 437         struct dp83867_private *dp83867 =
 438                 (struct dp83867_private *)phydev->priv;
 439
 440         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 441                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 442                                  DP83867_CFG4_PORT_MIRROR_EN);
 443         else
 444                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 445                                    DP83867_CFG4_PORT_MIRROR_EN);
 446         return 0;
 447 }
 448
 449 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 450 {
 451         struct dp83867_private *dp83867 = phydev->priv;
 452
 453         /* Existing behavior was to use default pin strapping delay in rgmii
 454          * mode, but rgmii should have meant no delay.  Warn existing users.
 455          */
 456         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 457                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 458                                              DP83867_STRAP_STS2);
 459                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 460                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 461                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 462                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 463
 464                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 465                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 466                         phydev_warn(phydev,
 467                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 468                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 469                                     txskew, rxskew);
 470         }
 471
 472         /* RX delay *must* be specified if internal delay of RX is used. */
 473         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 474              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 475              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 476                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 477                 return -EINVAL;
 478         }
 479
 480         /* TX delay *must* be specified if internal delay of TX is used. */
 481         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 482              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 483              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 484                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 485                 return -EINVAL;
 486         }
 487
 488         return 0;
 489 }
 490
 491 #if IS_ENABLED(CONFIG_OF_MDIO)
 492 static int dp83867_of_init(struct phy_device *phydev)
 493 {
 494         struct dp83867_private *dp83867 = phydev->priv;
 495         struct device *dev = &phydev->mdio.dev;
 496         struct device_node *of_node = dev->of_node;
 497         int ret;
 498
 499         if (!of_node)
 500                 return -ENODEV;
 501
 502         /* Optional configuration */
 503         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 504                                    &dp83867->clk_output_sel);
 505         /* If not set, keep default */
 506         if (!ret) {
 507                 dp83867->set_clk_output = true;
 508                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 509                  * DP83867_CLK_O_SEL_OFF.
 510                  */
 511                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 512                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 513                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 514                                    dp83867->clk_output_sel);
 515                         return -EINVAL;
 516                 }
 517         }
 518
 519         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 520                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 521         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 522                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 523         else
 524                 dp83867->io_impedance = -1; /* leave at default */
 525
 526         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 527                                         "ti,dp83867-rxctrl-strap-quirk");
 528
 529         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 530                                         "ti,sgmii-ref-clock-output-enable");
 531
 532
 533         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 534         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 535                                    &dp83867->rx_id_delay);
 536         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 537                 phydev_err(phydev,
 538                            "ti,rx-internal-delay value of %u out of range\n",
 539                            dp83867->rx_id_delay);
 540                 return -EINVAL;
 541         }
 542
 543         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 544         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 545                                    &dp83867->tx_id_delay);
 546         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 547                 phydev_err(phydev,
 548                            "ti,tx-internal-delay value of %u out of range\n",
 549                            dp83867->tx_id_delay);
 550                 return -EINVAL;
 551         }
 552
 553         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 554                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 555
 556         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 557                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 558
 559         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 560                                    &dp83867->tx_fifo_depth);
 561         if (ret) {
 562                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 563                                            &dp83867->tx_fifo_depth);
 564                 if (ret)
 565                         dp83867->tx_fifo_depth =
 566                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 567         }
 568
 569         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 570                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 571                            dp83867->tx_fifo_depth);
 572                 return -EINVAL;
 573         }
 574
 575         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 576                                    &dp83867->rx_fifo_depth);
 577         if (ret)
 578                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 579
 580         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 581                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 582                            dp83867->rx_fifo_depth);
 583                 return -EINVAL;
 584         }
 585
 586         return 0;
 587 }
 588 #else
 589 static int dp83867_of_init(struct phy_device *phydev)
 590 {
 591         return 0;
 592 }
 593 #endif /* CONFIG_OF_MDIO */
 594
 595 static int dp83867_probe(struct phy_device *phydev)
 596 {
 597         struct dp83867_private *dp83867;
 598
 599         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 600                                GFP_KERNEL);
 601         if (!dp83867)
 602                 return -ENOMEM;
 603
 604         phydev->priv = dp83867;
 605
 606         return dp83867_of_init(phydev);
 607 }
 608
 609 static int dp83867_config_init(struct phy_device *phydev)
 610 {
 611         struct dp83867_private *dp83867 = phydev->priv;
 612         int ret, val, bs;
 613         u16 delay;
 614
 615         /* Force speed optimization for the PHY even if it strapped */
 616         ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
 617                          DP83867_DOWNSHIFT_EN);
 618         if (ret)
 619                 return ret;
 620
 621         ret = dp83867_verify_rgmii_cfg(phydev);
 622         if (ret)
 623                 return ret;
 624
 625         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 626         if (dp83867->rxctrl_strap_quirk)
 627                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 628                                    BIT(7));
 629
 630         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 631         if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
 632                 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
 633                  * be set to 0x2. This may causes the PHY link to be unstable -
 634                  * the default value 0x1 need to be restored.
 635                  */
 636                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 637                                      DP83867_FLD_THR_CFG,
 638                                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
 639                                      0x1);
 640                 if (ret)
 641                         return ret;
 642         }
 643
 644         if (phy_interface_is_rgmii(phydev) ||
 645             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 646                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 647                 if (val < 0)
 648                         return val;
 649
 650                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 651                 val |= (dp83867->tx_fifo_depth <<
 652                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 653
 654                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 655                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 656                         val |= (dp83867->rx_fifo_depth <<
 657                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 658                 }
 659
 660                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 661                 if (ret)
 662                         return ret;
 663         }
 664
 665         if (phy_interface_is_rgmii(phydev)) {
 666                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 667                 if (val < 0)
 668                         return val;
 669
 670                 /* The code below checks if "port mirroring" N/A MODE4 has been
 671                  * enabled during power on bootstrap.
 672                  *
 673                  * Such N/A mode enabled by mistake can put PHY IC in some
 674                  * internal testing mode and disable RGMII transmission.
 675                  *
 676                  * In this particular case one needs to check STRAP_STS1
 677                  * register's bit 11 (marked as RESERVED).
 678                  */
 679
 680                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 681                 if (bs & DP83867_STRAP_STS1_RESERVED)
 682                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 683
 684                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 685                 if (ret)
 686                         return ret;
 687
 688                 /* If rgmii mode with no internal delay is selected, we do NOT use
 689                  * aligned mode as one might expect.  Instead we use the PHY's default
 690                  * based on pin strapping.  And the "mode 0" default is to *use*
 691                  * internal delay with a value of 7 (2.00 ns).
 692                  *
 693                  * Set up RGMII delays
 694                  */
 695                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 696
 697                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 698                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 699                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 700
 701                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 702                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 703
 704                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 705                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 706
 707                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 708
 709                 delay = 0;
 710                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 711                         delay |= dp83867->rx_id_delay;
 712                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 713                         delay |= dp83867->tx_id_delay <<
 714                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 715
 716                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 717                               delay);
 718         }
 719
 720         /* If specified, set io impedance */
 721         if (dp83867->io_impedance >= 0)
 722                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 723                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 724                                dp83867->io_impedance);
 725
 726         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 727                 /* For support SPEED_10 in SGMII mode
 728                  * DP83867_10M_SGMII_RATE_ADAPT bit
 729                  * has to be cleared by software. That
 730                  * does not affect SPEED_100 and
 731                  * SPEED_1000.
 732                  */
 733                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 734                                      DP83867_10M_SGMII_CFG,
 735                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 736                                      0);
 737                 if (ret)
 738                         return ret;
 739
 740                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 741                  * are 01). That is not enough to finalize autoneg on some
 742                  * devices. Increase this timer duration to maximum 16ms.
 743                  */
 744                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 745                                      DP83867_CFG4,
 746                                      DP83867_CFG4_SGMII_ANEG_MASK,
 747                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 748
 749                 if (ret)
 750                         return ret;
 751
 752                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 753                 /* SGMII type is set to 4-wire mode by default.
 754                  * If we place appropriate property in dts (see above)
 755                  * switch on 6-wire mode.
 756                  */
 757                 if (dp83867->sgmii_ref_clk_en)
 758                         val |= DP83867_SGMII_TYPE;
 759                 else
 760                         val &= ~DP83867_SGMII_TYPE;
 761                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 762         }
 763
 764         val = phy_read(phydev, DP83867_CFG3);
 765         /* Enable Interrupt output INT_OE in CFG3 register */
 766         if (phy_interrupt_is_valid(phydev))
 767                 val |= DP83867_CFG3_INT_OE;
 768
 769         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 770         phy_write(phydev, DP83867_CFG3, val);
 771
 772         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 773                 dp83867_config_port_mirroring(phydev);
 774
 775         /* Clock output selection if muxing property is set */
 776         if (dp83867->set_clk_output) {
 777                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 778
 779                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 780                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 781                 } else {
 782                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 783                         val = dp83867->clk_output_sel <<
 784                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 785                 }
 786
 787                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 788                                mask, val);
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int dp83867_phy_reset(struct phy_device *phydev)
 795 {
 796         int err;
 797
 798         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 799         if (err < 0)
 800                 return err;
 801
 802         usleep_range(10, 20);
 803
 804         /* After reset FORCE_LINK_GOOD bit is set. Although the
 805          * default value should be unset. Disable FORCE_LINK_GOOD
 806          * for the phy to work properly.
 807          */
 808         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 809                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 810 }
 811
 812 static struct phy_driver dp83867_driver[] = {
 813         {
 814                 .phy_id         = DP83867_PHY_ID,
 815                 .phy_id_mask    = 0xfffffff0,
 816                 .name           = "TI DP83867",
 817                 /* PHY_GBIT_FEATURES */
 818
 819                 .probe          = dp83867_probe,
 820                 .config_init    = dp83867_config_init,
 821                 .soft_reset     = dp83867_phy_reset,
 822
 823                 .read_status    = dp83867_read_status,
 824                 .get_tunable    = dp83867_get_tunable,
 825                 .set_tunable    = dp83867_set_tunable,
 826
 827                 .get_wol        = dp83867_get_wol,
 828                 .set_wol        = dp83867_set_wol,
 829
 830                 /* IRQ related */
 831                 .ack_interrupt  = dp83867_ack_interrupt,
 832                 .config_intr    = dp83867_config_intr,
 833
 834                 .suspend        = genphy_suspend,
 835                 .resume         = genphy_resume,
 836         },
 837 };
 838 module_phy_driver(dp83867_driver);
 839
 840 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 841         { DP83867_PHY_ID, 0xfffffff0 },
 842         { }
 843 };
 844
 845 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 846
 847 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 848 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 849 MODULE_LICENSE("GPL v2");