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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / net / phy / micrel.c
blob3a4d83fa52dca3c31245428dc0cba5171a641838
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/phy.h>
25 #include <linux/micrel_phy.h>
26 #include <linux/of.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29
30 /* Operation Mode Strap Override */
31 #define MII_KSZPHY_OMSO 0x16
32 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
33 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
34 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
35 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
36 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
37
38 /* general Interrupt control/status reg in vendor specific block. */
39 #define MII_KSZPHY_INTCS 0x1B
40 #define KSZPHY_INTCS_JABBER BIT(15)
41 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
42 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
43 #define KSZPHY_INTCS_PARELLEL BIT(12)
44 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
45 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
46 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
47 #define KSZPHY_INTCS_LINK_UP BIT(8)
48 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
49 KSZPHY_INTCS_LINK_DOWN)
50
51 /* PHY Control 1 */
52 #define MII_KSZPHY_CTRL_1 0x1e
53
54 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
55 #define MII_KSZPHY_CTRL_2 0x1f
56 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
57 /* bitmap of PHY register to set interrupt mode */
58 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
59 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
60
61 /* Write/read to/from extended registers */
62 #define MII_KSZPHY_EXTREG 0x0b
63 #define KSZPHY_EXTREG_WRITE 0x8000
64
65 #define MII_KSZPHY_EXTREG_WRITE 0x0c
66 #define MII_KSZPHY_EXTREG_READ 0x0d
67
68 /* Extended registers */
69 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
70 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
71 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
72
73 #define PS_TO_REG 200
74
75 struct kszphy_hw_stat {
76 const char *string;
77 u8 reg;
78 u8 bits;
79 };
80
81 static struct kszphy_hw_stat kszphy_hw_stats[] = {
82 { "phy_receive_errors", 21, 16},
83 { "phy_idle_errors", 10, 8 },
84 };
85
86 struct kszphy_type {
87 u32 led_mode_reg;
88 u16 interrupt_level_mask;
89 bool has_broadcast_disable;
90 bool has_nand_tree_disable;
91 bool has_rmii_ref_clk_sel;
92 };
93
94 struct kszphy_priv {
95 const struct kszphy_type *type;
96 int led_mode;
97 bool rmii_ref_clk_sel;
98 bool rmii_ref_clk_sel_val;
99 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
100 };
101
102 static const struct kszphy_type ksz8021_type = {
103 .led_mode_reg = MII_KSZPHY_CTRL_2,
104 .has_broadcast_disable = true,
105 .has_nand_tree_disable = true,
106 .has_rmii_ref_clk_sel = true,
107 };
108
109 static const struct kszphy_type ksz8041_type = {
110 .led_mode_reg = MII_KSZPHY_CTRL_1,
111 };
112
113 static const struct kszphy_type ksz8051_type = {
114 .led_mode_reg = MII_KSZPHY_CTRL_2,
115 .has_nand_tree_disable = true,
116 };
117
118 static const struct kszphy_type ksz8081_type = {
119 .led_mode_reg = MII_KSZPHY_CTRL_2,
120 .has_broadcast_disable = true,
121 .has_nand_tree_disable = true,
122 .has_rmii_ref_clk_sel = true,
123 };
124
125 static const struct kszphy_type ks8737_type = {
126 .interrupt_level_mask = BIT(14),
127 };
128
129 static const struct kszphy_type ksz9021_type = {
130 .interrupt_level_mask = BIT(14),
131 };
132
133 static int kszphy_extended_write(struct phy_device *phydev,
134 u32 regnum, u16 val)
135 {
136 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
137 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
138 }
139
140 static int kszphy_extended_read(struct phy_device *phydev,
141 u32 regnum)
142 {
143 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
144 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
145 }
146
147 static int kszphy_ack_interrupt(struct phy_device *phydev)
148 {
149 /* bit[7..0] int status, which is a read and clear register. */
150 int rc;
151
152 rc = phy_read(phydev, MII_KSZPHY_INTCS);
153
154 return (rc < 0) ? rc : 0;
155 }
156
157 static int kszphy_config_intr(struct phy_device *phydev)
158 {
159 const struct kszphy_type *type = phydev->drv->driver_data;
160 int temp;
161 u16 mask;
162
163 if (type && type->interrupt_level_mask)
164 mask = type->interrupt_level_mask;
165 else
166 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
167
168 /* set the interrupt pin active low */
169 temp = phy_read(phydev, MII_KSZPHY_CTRL);
170 if (temp < 0)
171 return temp;
172 temp &= ~mask;
173 phy_write(phydev, MII_KSZPHY_CTRL, temp);
174
175 /* enable / disable interrupts */
176 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
177 temp = KSZPHY_INTCS_ALL;
178 else
179 temp = 0;
180
181 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
182 }
183
184 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
185 {
186 int ctrl;
187
188 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
189 if (ctrl < 0)
190 return ctrl;
191
192 if (val)
193 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
194 else
195 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
196
197 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
198 }
199
200 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
201 {
202 int rc, temp, shift;
203
204 switch (reg) {
205 case MII_KSZPHY_CTRL_1:
206 shift = 14;
207 break;
208 case MII_KSZPHY_CTRL_2:
209 shift = 4;
210 break;
211 default:
212 return -EINVAL;
213 }
214
215 temp = phy_read(phydev, reg);
216 if (temp < 0) {
217 rc = temp;
218 goto out;
219 }
220
221 temp &= ~(3 << shift);
222 temp |= val << shift;
223 rc = phy_write(phydev, reg, temp);
224 out:
225 if (rc < 0)
226 phydev_err(phydev, "failed to set led mode\n");
227
228 return rc;
229 }
230
231 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
232 * unique (non-broadcast) address on a shared bus.
233 */
234 static int kszphy_broadcast_disable(struct phy_device *phydev)
235 {
236 int ret;
237
238 ret = phy_read(phydev, MII_KSZPHY_OMSO);
239 if (ret < 0)
240 goto out;
241
242 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
243 out:
244 if (ret)
245 phydev_err(phydev, "failed to disable broadcast address\n");
246
247 return ret;
248 }
249
250 static int kszphy_nand_tree_disable(struct phy_device *phydev)
251 {
252 int ret;
253
254 ret = phy_read(phydev, MII_KSZPHY_OMSO);
255 if (ret < 0)
256 goto out;
257
258 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
259 return 0;
260
261 ret = phy_write(phydev, MII_KSZPHY_OMSO,
262 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
263 out:
264 if (ret)
265 phydev_err(phydev, "failed to disable NAND tree mode\n");
266
267 return ret;
268 }
269
270 /* Some config bits need to be set again on resume, handle them here. */
271 static int kszphy_config_reset(struct phy_device *phydev)
272 {
273 struct kszphy_priv *priv = phydev->priv;
274 int ret;
275
276 if (priv->rmii_ref_clk_sel) {
277 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
278 if (ret) {
279 phydev_err(phydev,
280 "failed to set rmii reference clock\n");
281 return ret;
282 }
283 }
284
285 if (priv->led_mode >= 0)
286 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
287
288 return 0;
289 }
290
291 static int kszphy_config_init(struct phy_device *phydev)
292 {
293 struct kszphy_priv *priv = phydev->priv;
294 const struct kszphy_type *type;
295
296 if (!priv)
297 return 0;
298
299 type = priv->type;
300
301 if (type->has_broadcast_disable)
302 kszphy_broadcast_disable(phydev);
303
304 if (type->has_nand_tree_disable)
305 kszphy_nand_tree_disable(phydev);
306
307 return kszphy_config_reset(phydev);
308 }
309
310 static int ksz8041_config_init(struct phy_device *phydev)
311 {
312 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
313
314 struct device_node *of_node = phydev->mdio.dev.of_node;
315
316 /* Limit supported and advertised modes in fiber mode */
317 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
318 phydev->dev_flags |= MICREL_PHY_FXEN;
319 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
320 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
321
322 linkmode_and(phydev->supported, phydev->supported, mask);
323 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
324 phydev->supported);
325 linkmode_and(phydev->advertising, phydev->advertising, mask);
326 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
327 phydev->advertising);
328 phydev->autoneg = AUTONEG_DISABLE;
329 }
330
331 return kszphy_config_init(phydev);
332 }
333
334 static int ksz8041_config_aneg(struct phy_device *phydev)
335 {
336 /* Skip auto-negotiation in fiber mode */
337 if (phydev->dev_flags & MICREL_PHY_FXEN) {
338 phydev->speed = SPEED_100;
339 return 0;
340 }
341
342 return genphy_config_aneg(phydev);
343 }
344
345 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
346 const u32 ksz_phy_id)
347 {
348 int ret;
349
350 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id)
351 return 0;
352
353 ret = phy_read(phydev, MII_BMSR);
354 if (ret < 0)
355 return ret;
356
357 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
358 * exact PHY ID. However, they can be told apart by the extended
359 * capability registers presence. The KSZ8051 PHY has them while
360 * the switch does not.
361 */
362 ret &= BMSR_ERCAP;
363 if (ksz_phy_id == PHY_ID_KSZ8051)
364 return ret;
365 else
366 return !ret;
367 }
368
369 static int ksz8051_match_phy_device(struct phy_device *phydev)
370 {
371 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051);
372 }
373
374 static int ksz8081_config_init(struct phy_device *phydev)
375 {
376 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
377 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
378 * pull-down is missing, the factory test mode should be cleared by
379 * manually writing a 0.
380 */
381 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
382
383 return kszphy_config_init(phydev);
384 }
385
386 static int ksz8061_config_init(struct phy_device *phydev)
387 {
388 int ret;
389
390 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
391 if (ret)
392 return ret;
393
394 return kszphy_config_init(phydev);
395 }
396
397 static int ksz8795_match_phy_device(struct phy_device *phydev)
398 {
399 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX);
400 }
401
402 static int ksz9021_load_values_from_of(struct phy_device *phydev,
403 const struct device_node *of_node,
404 u16 reg,
405 const char *field1, const char *field2,
406 const char *field3, const char *field4)
407 {
408 int val1 = -1;
409 int val2 = -2;
410 int val3 = -3;
411 int val4 = -4;
412 int newval;
413 int matches = 0;
414
415 if (!of_property_read_u32(of_node, field1, &val1))
416 matches++;
417
418 if (!of_property_read_u32(of_node, field2, &val2))
419 matches++;
420
421 if (!of_property_read_u32(of_node, field3, &val3))
422 matches++;
423
424 if (!of_property_read_u32(of_node, field4, &val4))
425 matches++;
426
427 if (!matches)
428 return 0;
429
430 if (matches < 4)
431 newval = kszphy_extended_read(phydev, reg);
432 else
433 newval = 0;
434
435 if (val1 != -1)
436 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
437
438 if (val2 != -2)
439 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
440
441 if (val3 != -3)
442 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
443
444 if (val4 != -4)
445 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
446
447 return kszphy_extended_write(phydev, reg, newval);
448 }
449
450 static int ksz9021_config_init(struct phy_device *phydev)
451 {
452 const struct device *dev = &phydev->mdio.dev;
453 const struct device_node *of_node = dev->of_node;
454 const struct device *dev_walker;
455
456 /* The Micrel driver has a deprecated option to place phy OF
457 * properties in the MAC node. Walk up the tree of devices to
458 * find a device with an OF node.
459 */
460 dev_walker = &phydev->mdio.dev;
461 do {
462 of_node = dev_walker->of_node;
463 dev_walker = dev_walker->parent;
464
465 } while (!of_node && dev_walker);
466
467 if (of_node) {
468 ksz9021_load_values_from_of(phydev, of_node,
469 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
470 "txen-skew-ps", "txc-skew-ps",
471 "rxdv-skew-ps", "rxc-skew-ps");
472 ksz9021_load_values_from_of(phydev, of_node,
473 MII_KSZPHY_RX_DATA_PAD_SKEW,
474 "rxd0-skew-ps", "rxd1-skew-ps",
475 "rxd2-skew-ps", "rxd3-skew-ps");
476 ksz9021_load_values_from_of(phydev, of_node,
477 MII_KSZPHY_TX_DATA_PAD_SKEW,
478 "txd0-skew-ps", "txd1-skew-ps",
479 "txd2-skew-ps", "txd3-skew-ps");
480 }
481 return 0;
482 }
483
484 #define KSZ9031_PS_TO_REG 60
485
486 /* Extended registers */
487 /* MMD Address 0x0 */
488 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
489 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
490
491 /* MMD Address 0x2 */
492 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
493 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
494 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
495 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
496
497 /* MMD Address 0x1C */
498 #define MII_KSZ9031RN_EDPD 0x23
499 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
500
501 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
502 const struct device_node *of_node,
503 u16 reg, size_t field_sz,
504 const char *field[], u8 numfields)
505 {
506 int val[4] = {-1, -2, -3, -4};
507 int matches = 0;
508 u16 mask;
509 u16 maxval;
510 u16 newval;
511 int i;
512
513 for (i = 0; i < numfields; i++)
514 if (!of_property_read_u32(of_node, field[i], val + i))
515 matches++;
516
517 if (!matches)
518 return 0;
519
520 if (matches < numfields)
521 newval = phy_read_mmd(phydev, 2, reg);
522 else
523 newval = 0;
524
525 maxval = (field_sz == 4) ? 0xf : 0x1f;
526 for (i = 0; i < numfields; i++)
527 if (val[i] != -(i + 1)) {
528 mask = 0xffff;
529 mask ^= maxval << (field_sz * i);
530 newval = (newval & mask) |
531 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
532 << (field_sz * i));
533 }
534
535 return phy_write_mmd(phydev, 2, reg, newval);
536 }
537
538 /* Center KSZ9031RNX FLP timing at 16ms. */
539 static int ksz9031_center_flp_timing(struct phy_device *phydev)
540 {
541 int result;
542
543 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
544 0x0006);
545 if (result)
546 return result;
547
548 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
549 0x1A80);
550 if (result)
551 return result;
552
553 return genphy_restart_aneg(phydev);
554 }
555
556 /* Enable energy-detect power-down mode */
557 static int ksz9031_enable_edpd(struct phy_device *phydev)
558 {
559 int reg;
560
561 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
562 if (reg < 0)
563 return reg;
564 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
565 reg | MII_KSZ9031RN_EDPD_ENABLE);
566 }
567
568 static int ksz9031_config_init(struct phy_device *phydev)
569 {
570 const struct device *dev = &phydev->mdio.dev;
571 const struct device_node *of_node = dev->of_node;
572 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
573 static const char *rx_data_skews[4] = {
574 "rxd0-skew-ps", "rxd1-skew-ps",
575 "rxd2-skew-ps", "rxd3-skew-ps"
576 };
577 static const char *tx_data_skews[4] = {
578 "txd0-skew-ps", "txd1-skew-ps",
579 "txd2-skew-ps", "txd3-skew-ps"
580 };
581 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
582 const struct device *dev_walker;
583 int result;
584
585 result = ksz9031_enable_edpd(phydev);
586 if (result < 0)
587 return result;
588
589 /* The Micrel driver has a deprecated option to place phy OF
590 * properties in the MAC node. Walk up the tree of devices to
591 * find a device with an OF node.
592 */
593 dev_walker = &phydev->mdio.dev;
594 do {
595 of_node = dev_walker->of_node;
596 dev_walker = dev_walker->parent;
597 } while (!of_node && dev_walker);
598
599 if (of_node) {
600 ksz9031_of_load_skew_values(phydev, of_node,
601 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
602 clk_skews, 2);
603
604 ksz9031_of_load_skew_values(phydev, of_node,
605 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
606 control_skews, 2);
607
608 ksz9031_of_load_skew_values(phydev, of_node,
609 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
610 rx_data_skews, 4);
611
612 ksz9031_of_load_skew_values(phydev, of_node,
613 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
614 tx_data_skews, 4);
615
616 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
617 * When the device links in the 1000BASE-T slave mode only,
618 * the optional 125MHz reference output clock (CLK125_NDO)
619 * has wide duty cycle variation.
620 *
621 * The optional CLK125_NDO clock does not meet the RGMII
622 * 45/55 percent (min/max) duty cycle requirement and therefore
623 * cannot be used directly by the MAC side for clocking
624 * applications that have setup/hold time requirements on
625 * rising and falling clock edges.
626 *
627 * Workaround:
628 * Force the phy to be the master to receive a stable clock
629 * which meets the duty cycle requirement.
630 */
631 if (of_property_read_bool(of_node, "micrel,force-master")) {
632 result = phy_read(phydev, MII_CTRL1000);
633 if (result < 0)
634 goto err_force_master;
635
636 /* enable master mode, config & prefer master */
637 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
638 result = phy_write(phydev, MII_CTRL1000, result);
639 if (result < 0)
640 goto err_force_master;
641 }
642 }
643
644 return ksz9031_center_flp_timing(phydev);
645
646 err_force_master:
647 phydev_err(phydev, "failed to force the phy to master mode\n");
648 return result;
649 }
650
651 #define KSZ9131_SKEW_5BIT_MAX 2400
652 #define KSZ9131_SKEW_4BIT_MAX 800
653 #define KSZ9131_OFFSET 700
654 #define KSZ9131_STEP 100
655
656 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
657 struct device_node *of_node,
658 u16 reg, size_t field_sz,
659 char *field[], u8 numfields)
660 {
661 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
662 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
663 int skewval, skewmax = 0;
664 int matches = 0;
665 u16 maxval;
666 u16 newval;
667 u16 mask;
668 int i;
669
670 /* psec properties in dts should mean x pico seconds */
671 if (field_sz == 5)
672 skewmax = KSZ9131_SKEW_5BIT_MAX;
673 else
674 skewmax = KSZ9131_SKEW_4BIT_MAX;
675
676 for (i = 0; i < numfields; i++)
677 if (!of_property_read_s32(of_node, field[i], &skewval)) {
678 if (skewval < -KSZ9131_OFFSET)
679 skewval = -KSZ9131_OFFSET;
680 else if (skewval > skewmax)
681 skewval = skewmax;
682
683 val[i] = skewval + KSZ9131_OFFSET;
684 matches++;
685 }
686
687 if (!matches)
688 return 0;
689
690 if (matches < numfields)
691 newval = phy_read_mmd(phydev, 2, reg);
692 else
693 newval = 0;
694
695 maxval = (field_sz == 4) ? 0xf : 0x1f;
696 for (i = 0; i < numfields; i++)
697 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
698 mask = 0xffff;
699 mask ^= maxval << (field_sz * i);
700 newval = (newval & mask) |
701 (((val[i] / KSZ9131_STEP) & maxval)
702 << (field_sz * i));
703 }
704
705 return phy_write_mmd(phydev, 2, reg, newval);
706 }
707
708 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
709 #define KSZ9131RN_RXC_DLL_CTRL 76
710 #define KSZ9131RN_TXC_DLL_CTRL 77
711 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
712 #define KSZ9131RN_DLL_ENABLE_DELAY 0
713 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
714
715 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
716 {
717 u16 rxcdll_val, txcdll_val;
718 int ret;
719
720 switch (phydev->interface) {
721 case PHY_INTERFACE_MODE_RGMII:
722 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
723 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
724 break;
725 case PHY_INTERFACE_MODE_RGMII_ID:
726 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
727 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
728 break;
729 case PHY_INTERFACE_MODE_RGMII_RXID:
730 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
731 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
732 break;
733 case PHY_INTERFACE_MODE_RGMII_TXID:
734 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
735 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
736 break;
737 default:
738 return 0;
739 }
740
741 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
742 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
743 rxcdll_val);
744 if (ret < 0)
745 return ret;
746
747 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
748 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
749 txcdll_val);
750 }
751
752 static int ksz9131_config_init(struct phy_device *phydev)
753 {
754 const struct device *dev = &phydev->mdio.dev;
755 struct device_node *of_node = dev->of_node;
756 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
757 char *rx_data_skews[4] = {
758 "rxd0-skew-psec", "rxd1-skew-psec",
759 "rxd2-skew-psec", "rxd3-skew-psec"
760 };
761 char *tx_data_skews[4] = {
762 "txd0-skew-psec", "txd1-skew-psec",
763 "txd2-skew-psec", "txd3-skew-psec"
764 };
765 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
766 const struct device *dev_walker;
767 int ret;
768
769 dev_walker = &phydev->mdio.dev;
770 do {
771 of_node = dev_walker->of_node;
772 dev_walker = dev_walker->parent;
773 } while (!of_node && dev_walker);
774
775 if (!of_node)
776 return 0;
777
778 if (phy_interface_is_rgmii(phydev)) {
779 ret = ksz9131_config_rgmii_delay(phydev);
780 if (ret < 0)
781 return ret;
782 }
783
784 ret = ksz9131_of_load_skew_values(phydev, of_node,
785 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
786 clk_skews, 2);
787 if (ret < 0)
788 return ret;
789
790 ret = ksz9131_of_load_skew_values(phydev, of_node,
791 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
792 control_skews, 2);
793 if (ret < 0)
794 return ret;
795
796 ret = ksz9131_of_load_skew_values(phydev, of_node,
797 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
798 rx_data_skews, 4);
799 if (ret < 0)
800 return ret;
801
802 ret = ksz9131_of_load_skew_values(phydev, of_node,
803 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
804 tx_data_skews, 4);
805 if (ret < 0)
806 return ret;
807
808 return 0;
809 }
810
811 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
812 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
813 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
814 static int ksz8873mll_read_status(struct phy_device *phydev)
815 {
816 int regval;
817
818 /* dummy read */
819 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
820
821 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
822
823 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
824 phydev->duplex = DUPLEX_HALF;
825 else
826 phydev->duplex = DUPLEX_FULL;
827
828 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
829 phydev->speed = SPEED_10;
830 else
831 phydev->speed = SPEED_100;
832
833 phydev->link = 1;
834 phydev->pause = phydev->asym_pause = 0;
835
836 return 0;
837 }
838
839 static int ksz9031_get_features(struct phy_device *phydev)
840 {
841 int ret;
842
843 ret = genphy_read_abilities(phydev);
844 if (ret < 0)
845 return ret;
846
847 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
848 * Whenever the device's Asymmetric Pause capability is set to 1,
849 * link-up may fail after a link-up to link-down transition.
850 *
851 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
852 *
853 * Workaround:
854 * Do not enable the Asymmetric Pause capability bit.
855 */
856 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
857
858 /* We force setting the Pause capability as the core will force the
859 * Asymmetric Pause capability to 1 otherwise.
860 */
861 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
862
863 return 0;
864 }
865
866 static int ksz9031_read_status(struct phy_device *phydev)
867 {
868 int err;
869 int regval;
870
871 err = genphy_read_status(phydev);
872 if (err)
873 return err;
874
875 /* Make sure the PHY is not broken. Read idle error count,
876 * and reset the PHY if it is maxed out.
877 */
878 regval = phy_read(phydev, MII_STAT1000);
879 if ((regval & 0xFF) == 0xFF) {
880 phy_init_hw(phydev);
881 phydev->link = 0;
882 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
883 phydev->drv->config_intr(phydev);
884 return genphy_config_aneg(phydev);
885 }
886
887 return 0;
888 }
889
890 static int ksz8873mll_config_aneg(struct phy_device *phydev)
891 {
892 return 0;
893 }
894
895 static int kszphy_get_sset_count(struct phy_device *phydev)
896 {
897 return ARRAY_SIZE(kszphy_hw_stats);
898 }
899
900 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
901 {
902 int i;
903
904 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
905 strlcpy(data + i * ETH_GSTRING_LEN,
906 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
907 }
908 }
909
910 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
911 {
912 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
913 struct kszphy_priv *priv = phydev->priv;
914 int val;
915 u64 ret;
916
917 val = phy_read(phydev, stat.reg);
918 if (val < 0) {
919 ret = U64_MAX;
920 } else {
921 val = val & ((1 << stat.bits) - 1);
922 priv->stats[i] += val;
923 ret = priv->stats[i];
924 }
925
926 return ret;
927 }
928
929 static void kszphy_get_stats(struct phy_device *phydev,
930 struct ethtool_stats *stats, u64 *data)
931 {
932 int i;
933
934 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
935 data[i] = kszphy_get_stat(phydev, i);
936 }
937
938 static int kszphy_suspend(struct phy_device *phydev)
939 {
940 /* Disable PHY Interrupts */
941 if (phy_interrupt_is_valid(phydev)) {
942 phydev->interrupts = PHY_INTERRUPT_DISABLED;
943 if (phydev->drv->config_intr)
944 phydev->drv->config_intr(phydev);
945 }
946
947 return genphy_suspend(phydev);
948 }
949
950 static int kszphy_resume(struct phy_device *phydev)
951 {
952 int ret;
953
954 genphy_resume(phydev);
955
956 /* After switching from power-down to normal mode, an internal global
957 * reset is automatically generated. Wait a minimum of 1 ms before
958 * read/write access to the PHY registers.
959 */
960 usleep_range(1000, 2000);
961
962 ret = kszphy_config_reset(phydev);
963 if (ret)
964 return ret;
965
966 /* Enable PHY Interrupts */
967 if (phy_interrupt_is_valid(phydev)) {
968 phydev->interrupts = PHY_INTERRUPT_ENABLED;
969 if (phydev->drv->config_intr)
970 phydev->drv->config_intr(phydev);
971 }
972
973 return 0;
974 }
975
976 static int kszphy_probe(struct phy_device *phydev)
977 {
978 const struct kszphy_type *type = phydev->drv->driver_data;
979 const struct device_node *np = phydev->mdio.dev.of_node;
980 struct kszphy_priv *priv;
981 struct clk *clk;
982 int ret;
983
984 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
985 if (!priv)
986 return -ENOMEM;
987
988 phydev->priv = priv;
989
990 priv->type = type;
991
992 if (type->led_mode_reg) {
993 ret = of_property_read_u32(np, "micrel,led-mode",
994 &priv->led_mode);
995 if (ret)
996 priv->led_mode = -1;
997
998 if (priv->led_mode > 3) {
999 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1000 priv->led_mode);
1001 priv->led_mode = -1;
1002 }
1003 } else {
1004 priv->led_mode = -1;
1005 }
1006
1007 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1008 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1009 if (!IS_ERR_OR_NULL(clk)) {
1010 unsigned long rate = clk_get_rate(clk);
1011 bool rmii_ref_clk_sel_25_mhz;
1012
1013 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1014 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1015 "micrel,rmii-reference-clock-select-25-mhz");
1016
1017 if (rate > 24500000 && rate < 25500000) {
1018 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1019 } else if (rate > 49500000 && rate < 50500000) {
1020 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1021 } else {
1022 phydev_err(phydev, "Clock rate out of range: %ld\n",
1023 rate);
1024 return -EINVAL;
1025 }
1026 }
1027
1028 /* Support legacy board-file configuration */
1029 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1030 priv->rmii_ref_clk_sel = true;
1031 priv->rmii_ref_clk_sel_val = true;
1032 }
1033
1034 return 0;
1035 }
1036
1037 static struct phy_driver ksphy_driver[] = {
1038 {
1039 .phy_id = PHY_ID_KS8737,
1040 .phy_id_mask = MICREL_PHY_ID_MASK,
1041 .name = "Micrel KS8737",
1042 /* PHY_BASIC_FEATURES */
1043 .driver_data = &ks8737_type,
1044 .config_init = kszphy_config_init,
1045 .ack_interrupt = kszphy_ack_interrupt,
1046 .config_intr = kszphy_config_intr,
1047 .suspend = genphy_suspend,
1048 .resume = genphy_resume,
1049 }, {
1050 .phy_id = PHY_ID_KSZ8021,
1051 .phy_id_mask = 0x00ffffff,
1052 .name = "Micrel KSZ8021 or KSZ8031",
1053 /* PHY_BASIC_FEATURES */
1054 .driver_data = &ksz8021_type,
1055 .probe = kszphy_probe,
1056 .config_init = kszphy_config_init,
1057 .ack_interrupt = kszphy_ack_interrupt,
1058 .config_intr = kszphy_config_intr,
1059 .get_sset_count = kszphy_get_sset_count,
1060 .get_strings = kszphy_get_strings,
1061 .get_stats = kszphy_get_stats,
1062 .suspend = genphy_suspend,
1063 .resume = genphy_resume,
1064 }, {
1065 .phy_id = PHY_ID_KSZ8031,
1066 .phy_id_mask = 0x00ffffff,
1067 .name = "Micrel KSZ8031",
1068 /* PHY_BASIC_FEATURES */
1069 .driver_data = &ksz8021_type,
1070 .probe = kszphy_probe,
1071 .config_init = kszphy_config_init,
1072 .ack_interrupt = kszphy_ack_interrupt,
1073 .config_intr = kszphy_config_intr,
1074 .get_sset_count = kszphy_get_sset_count,
1075 .get_strings = kszphy_get_strings,
1076 .get_stats = kszphy_get_stats,
1077 .suspend = genphy_suspend,
1078 .resume = genphy_resume,
1079 }, {
1080 .phy_id = PHY_ID_KSZ8041,
1081 .phy_id_mask = MICREL_PHY_ID_MASK,
1082 .name = "Micrel KSZ8041",
1083 /* PHY_BASIC_FEATURES */
1084 .driver_data = &ksz8041_type,
1085 .probe = kszphy_probe,
1086 .config_init = ksz8041_config_init,
1087 .config_aneg = ksz8041_config_aneg,
1088 .ack_interrupt = kszphy_ack_interrupt,
1089 .config_intr = kszphy_config_intr,
1090 .get_sset_count = kszphy_get_sset_count,
1091 .get_strings = kszphy_get_strings,
1092 .get_stats = kszphy_get_stats,
1093 .suspend = genphy_suspend,
1094 .resume = genphy_resume,
1095 }, {
1096 .phy_id = PHY_ID_KSZ8041RNLI,
1097 .phy_id_mask = MICREL_PHY_ID_MASK,
1098 .name = "Micrel KSZ8041RNLI",
1099 /* PHY_BASIC_FEATURES */
1100 .driver_data = &ksz8041_type,
1101 .probe = kszphy_probe,
1102 .config_init = kszphy_config_init,
1103 .ack_interrupt = kszphy_ack_interrupt,
1104 .config_intr = kszphy_config_intr,
1105 .get_sset_count = kszphy_get_sset_count,
1106 .get_strings = kszphy_get_strings,
1107 .get_stats = kszphy_get_stats,
1108 .suspend = genphy_suspend,
1109 .resume = genphy_resume,
1110 }, {
1111 .name = "Micrel KSZ8051",
1112 /* PHY_BASIC_FEATURES */
1113 .driver_data = &ksz8051_type,
1114 .probe = kszphy_probe,
1115 .config_init = kszphy_config_init,
1116 .ack_interrupt = kszphy_ack_interrupt,
1117 .config_intr = kszphy_config_intr,
1118 .get_sset_count = kszphy_get_sset_count,
1119 .get_strings = kszphy_get_strings,
1120 .get_stats = kszphy_get_stats,
1121 .match_phy_device = ksz8051_match_phy_device,
1122 .suspend = genphy_suspend,
1123 .resume = genphy_resume,
1124 }, {
1125 .phy_id = PHY_ID_KSZ8001,
1126 .name = "Micrel KSZ8001 or KS8721",
1127 .phy_id_mask = 0x00fffffc,
1128 /* PHY_BASIC_FEATURES */
1129 .driver_data = &ksz8041_type,
1130 .probe = kszphy_probe,
1131 .config_init = kszphy_config_init,
1132 .ack_interrupt = kszphy_ack_interrupt,
1133 .config_intr = kszphy_config_intr,
1134 .get_sset_count = kszphy_get_sset_count,
1135 .get_strings = kszphy_get_strings,
1136 .get_stats = kszphy_get_stats,
1137 .suspend = genphy_suspend,
1138 .resume = genphy_resume,
1139 }, {
1140 .phy_id = PHY_ID_KSZ8081,
1141 .name = "Micrel KSZ8081 or KSZ8091",
1142 .phy_id_mask = MICREL_PHY_ID_MASK,
1143 /* PHY_BASIC_FEATURES */
1144 .driver_data = &ksz8081_type,
1145 .probe = kszphy_probe,
1146 .config_init = ksz8081_config_init,
1147 .ack_interrupt = kszphy_ack_interrupt,
1148 .config_intr = kszphy_config_intr,
1149 .get_sset_count = kszphy_get_sset_count,
1150 .get_strings = kszphy_get_strings,
1151 .get_stats = kszphy_get_stats,
1152 .suspend = kszphy_suspend,
1153 .resume = kszphy_resume,
1154 }, {
1155 .phy_id = PHY_ID_KSZ8061,
1156 .name = "Micrel KSZ8061",
1157 .phy_id_mask = MICREL_PHY_ID_MASK,
1158 /* PHY_BASIC_FEATURES */
1159 .config_init = ksz8061_config_init,
1160 .ack_interrupt = kszphy_ack_interrupt,
1161 .config_intr = kszphy_config_intr,
1162 .suspend = genphy_suspend,
1163 .resume = genphy_resume,
1164 }, {
1165 .phy_id = PHY_ID_KSZ9021,
1166 .phy_id_mask = 0x000ffffe,
1167 .name = "Micrel KSZ9021 Gigabit PHY",
1168 /* PHY_GBIT_FEATURES */
1169 .driver_data = &ksz9021_type,
1170 .probe = kszphy_probe,
1171 .get_features = ksz9031_get_features,
1172 .config_init = ksz9021_config_init,
1173 .ack_interrupt = kszphy_ack_interrupt,
1174 .config_intr = kszphy_config_intr,
1175 .get_sset_count = kszphy_get_sset_count,
1176 .get_strings = kszphy_get_strings,
1177 .get_stats = kszphy_get_stats,
1178 .suspend = genphy_suspend,
1179 .resume = genphy_resume,
1180 .read_mmd = genphy_read_mmd_unsupported,
1181 .write_mmd = genphy_write_mmd_unsupported,
1182 }, {
1183 .phy_id = PHY_ID_KSZ9031,
1184 .phy_id_mask = MICREL_PHY_ID_MASK,
1185 .name = "Micrel KSZ9031 Gigabit PHY",
1186 .driver_data = &ksz9021_type,
1187 .probe = kszphy_probe,
1188 .get_features = ksz9031_get_features,
1189 .config_init = ksz9031_config_init,
1190 .soft_reset = genphy_soft_reset,
1191 .read_status = ksz9031_read_status,
1192 .ack_interrupt = kszphy_ack_interrupt,
1193 .config_intr = kszphy_config_intr,
1194 .get_sset_count = kszphy_get_sset_count,
1195 .get_strings = kszphy_get_strings,
1196 .get_stats = kszphy_get_stats,
1197 .suspend = genphy_suspend,
1198 .resume = kszphy_resume,
1199 }, {
1200 .phy_id = PHY_ID_KSZ9131,
1201 .phy_id_mask = MICREL_PHY_ID_MASK,
1202 .name = "Microchip KSZ9131 Gigabit PHY",
1203 /* PHY_GBIT_FEATURES */
1204 .driver_data = &ksz9021_type,
1205 .probe = kszphy_probe,
1206 .config_init = ksz9131_config_init,
1207 .read_status = genphy_read_status,
1208 .ack_interrupt = kszphy_ack_interrupt,
1209 .config_intr = kszphy_config_intr,
1210 .get_sset_count = kszphy_get_sset_count,
1211 .get_strings = kszphy_get_strings,
1212 .get_stats = kszphy_get_stats,
1213 .suspend = genphy_suspend,
1214 .resume = kszphy_resume,
1215 }, {
1216 .phy_id = PHY_ID_KSZ8873MLL,
1217 .phy_id_mask = MICREL_PHY_ID_MASK,
1218 .name = "Micrel KSZ8873MLL Switch",
1219 /* PHY_BASIC_FEATURES */
1220 .config_init = kszphy_config_init,
1221 .config_aneg = ksz8873mll_config_aneg,
1222 .read_status = ksz8873mll_read_status,
1223 .suspend = genphy_suspend,
1224 .resume = genphy_resume,
1225 }, {
1226 .phy_id = PHY_ID_KSZ886X,
1227 .phy_id_mask = MICREL_PHY_ID_MASK,
1228 .name = "Micrel KSZ886X Switch",
1229 /* PHY_BASIC_FEATURES */
1230 .config_init = kszphy_config_init,
1231 .suspend = genphy_suspend,
1232 .resume = genphy_resume,
1233 }, {
1234 .name = "Micrel KSZ87XX Switch",
1235 /* PHY_BASIC_FEATURES */
1236 .config_init = kszphy_config_init,
1237 .config_aneg = ksz8873mll_config_aneg,
1238 .read_status = ksz8873mll_read_status,
1239 .match_phy_device = ksz8795_match_phy_device,
1240 .suspend = genphy_suspend,
1241 .resume = genphy_resume,
1242 }, {
1243 .phy_id = PHY_ID_KSZ9477,
1244 .phy_id_mask = MICREL_PHY_ID_MASK,
1245 .name = "Microchip KSZ9477",
1246 /* PHY_GBIT_FEATURES */
1247 .config_init = kszphy_config_init,
1248 .suspend = genphy_suspend,
1249 .resume = genphy_resume,
1250 } };
1251
1252 module_phy_driver(ksphy_driver);
1253
1254 MODULE_DESCRIPTION("Micrel PHY driver");
1255 MODULE_AUTHOR("David J. Choi");
1256 MODULE_LICENSE("GPL");
1257
1258 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1259 { PHY_ID_KSZ9021, 0x000ffffe },
1260 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1261 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1262 { PHY_ID_KSZ8001, 0x00fffffc },
1263 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1264 { PHY_ID_KSZ8021, 0x00ffffff },
1265 { PHY_ID_KSZ8031, 0x00ffffff },
1266 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1267 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1268 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1269 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1270 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1271 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1272 { }
1273 };
1274
1275 MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux with added FPC-III support