drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/realtek.c
   4  *
   5  * Driver for Realtek PHYs
   6  *
   7  * Author: Johnson Leung <r58129@freescale.com>
   8  *
   9  * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14
  15 #define RTL821x_PHYSR                           0x11
  16 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  17 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  18
  19 #define RTL821x_INER                            0x12
  20 #define RTL8211B_INER_INIT                      0x6400
  21 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  22 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  23
  24 #define RTL821x_INSR                            0x13
  25
  26 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  27 #define RTL821x_PAGE_SELECT                     0x1f
  28
  29 #define RTL8211F_INSR                           0x1d
  30
  31 #define RTL8211F_TX_DELAY                       BIT(8)
  32 #define RTL8211F_RX_DELAY                       BIT(3)
  33
  34 #define RTL8211E_TX_DELAY                       BIT(1)
  35 #define RTL8211E_RX_DELAY                       BIT(2)
  36 #define RTL8211E_MODE_MII_GMII                  BIT(3)
  37
  38 #define RTL8201F_ISR                            0x1e
  39 #define RTL8201F_IER                            0x13
  40
  41 #define RTL8366RB_POWER_SAVE                    0x15
  42 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  43
  44 #define RTL_SUPPORTS_5000FULL                   BIT(14)
  45 #define RTL_SUPPORTS_2500FULL                   BIT(13)
  46 #define RTL_SUPPORTS_10000FULL                  BIT(0)
  47 #define RTL_ADV_2500FULL                        BIT(7)
  48 #define RTL_LPADV_10000FULL                     BIT(11)
  49 #define RTL_LPADV_5000FULL                      BIT(6)
  50 #define RTL_LPADV_2500FULL                      BIT(5)
  51
  52 #define RTLGEN_SPEED_MASK                       0x0630
  53
  54 #define RTL_GENERIC_PHYID                       0x001cc800
  55
  56 MODULE_DESCRIPTION("Realtek PHY driver");
  57 MODULE_AUTHOR("Johnson Leung");
  58 MODULE_LICENSE("GPL");
  59
  60 static int rtl821x_read_page(struct phy_device *phydev)
  61 {
  62         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  63 }
  64
  65 static int rtl821x_write_page(struct phy_device *phydev, int page)
  66 {
  67         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  68 }
  69
  70 static int rtl8201_ack_interrupt(struct phy_device *phydev)
  71 {
  72         int err;
  73
  74         err = phy_read(phydev, RTL8201F_ISR);
  75
  76         return (err < 0) ? err : 0;
  77 }
  78
  79 static int rtl821x_ack_interrupt(struct phy_device *phydev)
  80 {
  81         int err;
  82
  83         err = phy_read(phydev, RTL821x_INSR);
  84
  85         return (err < 0) ? err : 0;
  86 }
  87
  88 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  89 {
  90         int err;
  91
  92         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  93
  94         return (err < 0) ? err : 0;
  95 }
  96
  97 static int rtl8201_config_intr(struct phy_device *phydev)
  98 {
  99         u16 val;
 100
 101         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 102                 val = BIT(13) | BIT(12) | BIT(11);
 103         else
 104                 val = 0;
 105
 106         return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 107 }
 108
 109 static int rtl8211b_config_intr(struct phy_device *phydev)
 110 {
 111         int err;
 112
 113         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 114                 err = phy_write(phydev, RTL821x_INER,
 115                                 RTL8211B_INER_INIT);
 116         else
 117                 err = phy_write(phydev, RTL821x_INER, 0);
 118
 119         return err;
 120 }
 121
 122 static int rtl8211e_config_intr(struct phy_device *phydev)
 123 {
 124         int err;
 125
 126         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 127                 err = phy_write(phydev, RTL821x_INER,
 128                                 RTL8211E_INER_LINK_STATUS);
 129         else
 130                 err = phy_write(phydev, RTL821x_INER, 0);
 131
 132         return err;
 133 }
 134
 135 static int rtl8211f_config_intr(struct phy_device *phydev)
 136 {
 137         u16 val;
 138
 139         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 140                 val = RTL8211F_INER_LINK_STATUS;
 141         else
 142                 val = 0;
 143
 144         return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 145 }
 146
 147 static int rtl8211_config_aneg(struct phy_device *phydev)
 148 {
 149         int ret;
 150
 151         ret = genphy_config_aneg(phydev);
 152         if (ret < 0)
 153                 return ret;
 154
 155         /* Quirk was copied from vendor driver. Unfortunately it includes no
 156          * description of the magic numbers.
 157          */
 158         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 159                 phy_write(phydev, 0x17, 0x2138);
 160                 phy_write(phydev, 0x0e, 0x0260);
 161         } else {
 162                 phy_write(phydev, 0x17, 0x2108);
 163                 phy_write(phydev, 0x0e, 0x0000);
 164         }
 165
 166         return 0;
 167 }
 168
 169 static int rtl8211c_config_init(struct phy_device *phydev)
 170 {
 171         /* RTL8211C has an issue when operating in Gigabit slave mode */
 172         return phy_set_bits(phydev, MII_CTRL1000,
 173                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 174 }
 175
 176 static int rtl8211f_config_init(struct phy_device *phydev)
 177 {
 178         struct device *dev = &phydev->mdio.dev;
 179         u16 val_txdly, val_rxdly;
 180         int ret;
 181
 182         switch (phydev->interface) {
 183         case PHY_INTERFACE_MODE_RGMII:
 184                 val_txdly = 0;
 185                 val_rxdly = 0;
 186                 break;
 187
 188         case PHY_INTERFACE_MODE_RGMII_RXID:
 189                 val_txdly = 0;
 190                 val_rxdly = RTL8211F_RX_DELAY;
 191                 break;
 192
 193         case PHY_INTERFACE_MODE_RGMII_TXID:
 194                 val_txdly = RTL8211F_TX_DELAY;
 195                 val_rxdly = 0;
 196                 break;
 197
 198         case PHY_INTERFACE_MODE_RGMII_ID:
 199                 val_txdly = RTL8211F_TX_DELAY;
 200                 val_rxdly = RTL8211F_RX_DELAY;
 201                 break;
 202
 203         default: /* the rest of the modes imply leaving delay as is. */
 204                 return 0;
 205         }
 206
 207         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 208                                        val_txdly);
 209         if (ret < 0) {
 210                 dev_err(dev, "Failed to update the TX delay register\n");
 211                 return ret;
 212         } else if (ret) {
 213                 dev_dbg(dev,
 214                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 215                         val_txdly ? "Enabling" : "Disabling");
 216         } else {
 217                 dev_dbg(dev,
 218                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 219                         val_txdly ? "enabled" : "disabled");
 220         }
 221
 222         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 223                                        val_rxdly);
 224         if (ret < 0) {
 225                 dev_err(dev, "Failed to update the RX delay register\n");
 226                 return ret;
 227         } else if (ret) {
 228                 dev_dbg(dev,
 229                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 230                         val_rxdly ? "Enabling" : "Disabling");
 231         } else {
 232                 dev_dbg(dev,
 233                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 234                         val_rxdly ? "enabled" : "disabled");
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int rtl8211e_config_init(struct phy_device *phydev)
 241 {
 242         int ret = 0, oldpage;
 243         u16 val;
 244
 245         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 246         switch (phydev->interface) {
 247         case PHY_INTERFACE_MODE_RGMII:
 248                 val = 0;
 249                 break;
 250         case PHY_INTERFACE_MODE_RGMII_ID:
 251                 val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 252                 break;
 253         case PHY_INTERFACE_MODE_RGMII_RXID:
 254                 val = RTL8211E_RX_DELAY;
 255                 break;
 256         case PHY_INTERFACE_MODE_RGMII_TXID:
 257                 val = RTL8211E_TX_DELAY;
 258                 break;
 259         default: /* the rest of the modes imply leaving delays as is. */
 260                 return 0;
 261         }
 262
 263         /* According to a sample driver there is a 0x1c config register on the
 264          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 265          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
 266          * also be used to customize the whole configuration register:
 267          * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
 268          * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
 269          * for details).
 270          */
 271         oldpage = phy_select_page(phydev, 0x7);
 272         if (oldpage < 0)
 273                 goto err_restore_page;
 274
 275         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 276         if (ret)
 277                 goto err_restore_page;
 278
 279         ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 280                            val);
 281
 282 err_restore_page:
 283         return phy_restore_page(phydev, oldpage, ret);
 284 }
 285
 286 static int rtl8211b_suspend(struct phy_device *phydev)
 287 {
 288         phy_write(phydev, MII_MMD_DATA, BIT(9));
 289
 290         return genphy_suspend(phydev);
 291 }
 292
 293 static int rtl8211b_resume(struct phy_device *phydev)
 294 {
 295         phy_write(phydev, MII_MMD_DATA, 0);
 296
 297         return genphy_resume(phydev);
 298 }
 299
 300 static int rtl8366rb_config_init(struct phy_device *phydev)
 301 {
 302         int ret;
 303
 304         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 305                            RTL8366RB_POWER_SAVE_ON);
 306         if (ret) {
 307                 dev_err(&phydev->mdio.dev,
 308                         "error enabling power management\n");
 309         }
 310
 311         return ret;
 312 }
 313
 314 /* get actual speed to cover the downshift case */
 315 static int rtlgen_get_speed(struct phy_device *phydev)
 316 {
 317         int val;
 318
 319         if (!phydev->link)
 320                 return 0;
 321
 322         val = phy_read_paged(phydev, 0xa43, 0x12);
 323         if (val < 0)
 324                 return val;
 325
 326         switch (val & RTLGEN_SPEED_MASK) {
 327         case 0x0000:
 328                 phydev->speed = SPEED_10;
 329                 break;
 330         case 0x0010:
 331                 phydev->speed = SPEED_100;
 332                 break;
 333         case 0x0020:
 334                 phydev->speed = SPEED_1000;
 335                 break;
 336         case 0x0200:
 337                 phydev->speed = SPEED_10000;
 338                 break;
 339         case 0x0210:
 340                 phydev->speed = SPEED_2500;
 341                 break;
 342         case 0x0220:
 343                 phydev->speed = SPEED_5000;
 344                 break;
 345         default:
 346                 break;
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int rtlgen_read_status(struct phy_device *phydev)
 353 {
 354         int ret;
 355
 356         ret = genphy_read_status(phydev);
 357         if (ret < 0)
 358                 return ret;
 359
 360         return rtlgen_get_speed(phydev);
 361 }
 362
 363 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 364 {
 365         int ret;
 366
 367         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 368                 rtl821x_write_page(phydev, 0xa5c);
 369                 ret = __phy_read(phydev, 0x12);
 370                 rtl821x_write_page(phydev, 0);
 371         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 372                 rtl821x_write_page(phydev, 0xa5d);
 373                 ret = __phy_read(phydev, 0x10);
 374                 rtl821x_write_page(phydev, 0);
 375         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 376                 rtl821x_write_page(phydev, 0xa5d);
 377                 ret = __phy_read(phydev, 0x11);
 378                 rtl821x_write_page(phydev, 0);
 379         } else {
 380                 ret = -EOPNOTSUPP;
 381         }
 382
 383         return ret;
 384 }
 385
 386 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 387                             u16 val)
 388 {
 389         int ret;
 390
 391         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 392                 rtl821x_write_page(phydev, 0xa5d);
 393                 ret = __phy_write(phydev, 0x10, val);
 394                 rtl821x_write_page(phydev, 0);
 395         } else {
 396                 ret = -EOPNOTSUPP;
 397         }
 398
 399         return ret;
 400 }
 401
 402 static int rtl8125_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 403 {
 404         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 405
 406         if (ret != -EOPNOTSUPP)
 407                 return ret;
 408
 409         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 410                 rtl821x_write_page(phydev, 0xa6e);
 411                 ret = __phy_read(phydev, 0x16);
 412                 rtl821x_write_page(phydev, 0);
 413         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 414                 rtl821x_write_page(phydev, 0xa6d);
 415                 ret = __phy_read(phydev, 0x12);
 416                 rtl821x_write_page(phydev, 0);
 417         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 418                 rtl821x_write_page(phydev, 0xa6d);
 419                 ret = __phy_read(phydev, 0x10);
 420                 rtl821x_write_page(phydev, 0);
 421         }
 422
 423         return ret;
 424 }
 425
 426 static int rtl8125_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 427                              u16 val)
 428 {
 429         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 430
 431         if (ret != -EOPNOTSUPP)
 432                 return ret;
 433
 434         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 435                 rtl821x_write_page(phydev, 0xa6d);
 436                 ret = __phy_write(phydev, 0x12, val);
 437                 rtl821x_write_page(phydev, 0);
 438         }
 439
 440         return ret;
 441 }
 442
 443 static int rtl8125_get_features(struct phy_device *phydev)
 444 {
 445         int val;
 446
 447         val = phy_read_paged(phydev, 0xa61, 0x13);
 448         if (val < 0)
 449                 return val;
 450
 451         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 452                          phydev->supported, val & RTL_SUPPORTS_2500FULL);
 453         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 454                          phydev->supported, val & RTL_SUPPORTS_5000FULL);
 455         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 456                          phydev->supported, val & RTL_SUPPORTS_10000FULL);
 457
 458         return genphy_read_abilities(phydev);
 459 }
 460
 461 static int rtl8125_config_aneg(struct phy_device *phydev)
 462 {
 463         int ret = 0;
 464
 465         if (phydev->autoneg == AUTONEG_ENABLE) {
 466                 u16 adv2500 = 0;
 467
 468                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 469                                       phydev->advertising))
 470                         adv2500 = RTL_ADV_2500FULL;
 471
 472                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 473                                                RTL_ADV_2500FULL, adv2500);
 474                 if (ret < 0)
 475                         return ret;
 476         }
 477
 478         return __genphy_config_aneg(phydev, ret);
 479 }
 480
 481 static int rtl8125_read_status(struct phy_device *phydev)
 482 {
 483         int ret;
 484
 485         if (phydev->autoneg == AUTONEG_ENABLE) {
 486                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 487
 488                 if (lpadv < 0)
 489                         return lpadv;
 490
 491                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 492                         phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
 493                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 494                         phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
 495                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 496                         phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
 497         }
 498
 499         ret = genphy_read_status(phydev);
 500         if (ret < 0)
 501                 return ret;
 502
 503         return rtlgen_get_speed(phydev);
 504 }
 505
 506 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 507 {
 508         int val;
 509
 510         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
 511         val = phy_read(phydev, 0x13);
 512         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 513
 514         return val >= 0 && val & RTL_SUPPORTS_2500FULL;
 515 }
 516
 517 static int rtlgen_match_phy_device(struct phy_device *phydev)
 518 {
 519         return phydev->phy_id == RTL_GENERIC_PHYID &&
 520                !rtlgen_supports_2_5gbps(phydev);
 521 }
 522
 523 static int rtl8125_match_phy_device(struct phy_device *phydev)
 524 {
 525         return phydev->phy_id == RTL_GENERIC_PHYID &&
 526                rtlgen_supports_2_5gbps(phydev);
 527 }
 528
 529 static struct phy_driver realtek_drvs[] = {
 530         {
 531                 PHY_ID_MATCH_EXACT(0x00008201),
 532                 .name           = "RTL8201CP Ethernet",
 533         }, {
 534                 PHY_ID_MATCH_EXACT(0x001cc816),
 535                 .name           = "RTL8201F Fast Ethernet",
 536                 .ack_interrupt  = &rtl8201_ack_interrupt,
 537                 .config_intr    = &rtl8201_config_intr,
 538                 .suspend        = genphy_suspend,
 539                 .resume         = genphy_resume,
 540                 .read_page      = rtl821x_read_page,
 541                 .write_page     = rtl821x_write_page,
 542         }, {
 543                 PHY_ID_MATCH_MODEL(0x001cc880),
 544                 .name           = "RTL8208 Fast Ethernet",
 545                 .read_mmd       = genphy_read_mmd_unsupported,
 546                 .write_mmd      = genphy_write_mmd_unsupported,
 547                 .suspend        = genphy_suspend,
 548                 .resume         = genphy_resume,
 549                 .read_page      = rtl821x_read_page,
 550                 .write_page     = rtl821x_write_page,
 551         }, {
 552                 PHY_ID_MATCH_EXACT(0x001cc910),
 553                 .name           = "RTL8211 Gigabit Ethernet",
 554                 .config_aneg    = rtl8211_config_aneg,
 555                 .read_mmd       = &genphy_read_mmd_unsupported,
 556                 .write_mmd      = &genphy_write_mmd_unsupported,
 557                 .read_page      = rtl821x_read_page,
 558                 .write_page     = rtl821x_write_page,
 559         }, {
 560                 PHY_ID_MATCH_EXACT(0x001cc912),
 561                 .name           = "RTL8211B Gigabit Ethernet",
 562                 .ack_interrupt  = &rtl821x_ack_interrupt,
 563                 .config_intr    = &rtl8211b_config_intr,
 564                 .read_mmd       = &genphy_read_mmd_unsupported,
 565                 .write_mmd      = &genphy_write_mmd_unsupported,
 566                 .suspend        = rtl8211b_suspend,
 567                 .resume         = rtl8211b_resume,
 568                 .read_page      = rtl821x_read_page,
 569                 .write_page     = rtl821x_write_page,
 570         }, {
 571                 PHY_ID_MATCH_EXACT(0x001cc913),
 572                 .name           = "RTL8211C Gigabit Ethernet",
 573                 .config_init    = rtl8211c_config_init,
 574                 .read_mmd       = &genphy_read_mmd_unsupported,
 575                 .write_mmd      = &genphy_write_mmd_unsupported,
 576                 .read_page      = rtl821x_read_page,
 577                 .write_page     = rtl821x_write_page,
 578         }, {
 579                 PHY_ID_MATCH_EXACT(0x001cc914),
 580                 .name           = "RTL8211DN Gigabit Ethernet",
 581                 .ack_interrupt  = rtl821x_ack_interrupt,
 582                 .config_intr    = rtl8211e_config_intr,
 583                 .suspend        = genphy_suspend,
 584                 .resume         = genphy_resume,
 585                 .read_page      = rtl821x_read_page,
 586                 .write_page     = rtl821x_write_page,
 587         }, {
 588                 PHY_ID_MATCH_EXACT(0x001cc915),
 589                 .name           = "RTL8211E Gigabit Ethernet",
 590                 .config_init    = &rtl8211e_config_init,
 591                 .ack_interrupt  = &rtl821x_ack_interrupt,
 592                 .config_intr    = &rtl8211e_config_intr,
 593                 .suspend        = genphy_suspend,
 594                 .resume         = genphy_resume,
 595                 .read_page      = rtl821x_read_page,
 596                 .write_page     = rtl821x_write_page,
 597         }, {
 598                 PHY_ID_MATCH_EXACT(0x001cc916),
 599                 .name           = "RTL8211F Gigabit Ethernet",
 600                 .config_init    = &rtl8211f_config_init,
 601                 .ack_interrupt  = &rtl8211f_ack_interrupt,
 602                 .config_intr    = &rtl8211f_config_intr,
 603                 .suspend        = genphy_suspend,
 604                 .resume         = genphy_resume,
 605                 .read_page      = rtl821x_read_page,
 606                 .write_page     = rtl821x_write_page,
 607         }, {
 608                 .name           = "Generic FE-GE Realtek PHY",
 609                 .match_phy_device = rtlgen_match_phy_device,
 610                 .read_status    = rtlgen_read_status,
 611                 .suspend        = genphy_suspend,
 612                 .resume         = genphy_resume,
 613                 .read_page      = rtl821x_read_page,
 614                 .write_page     = rtl821x_write_page,
 615                 .read_mmd       = rtlgen_read_mmd,
 616                 .write_mmd      = rtlgen_write_mmd,
 617         }, {
 618                 .name           = "RTL8125 2.5Gbps internal",
 619                 .match_phy_device = rtl8125_match_phy_device,
 620                 .get_features   = rtl8125_get_features,
 621                 .config_aneg    = rtl8125_config_aneg,
 622                 .read_status    = rtl8125_read_status,
 623                 .suspend        = genphy_suspend,
 624                 .resume         = genphy_resume,
 625                 .read_page      = rtl821x_read_page,
 626                 .write_page     = rtl821x_write_page,
 627                 .read_mmd       = rtl8125_read_mmd,
 628                 .write_mmd      = rtl8125_write_mmd,
 629         }, {
 630                 PHY_ID_MATCH_EXACT(0x001cc961),
 631                 .name           = "RTL8366RB Gigabit Ethernet",
 632                 .config_init    = &rtl8366rb_config_init,
 633                 /* These interrupts are handled by the irq controller
 634                  * embedded inside the RTL8366RB, they get unmasked when the
 635                  * irq is requested and ACKed by reading the status register,
 636                  * which is done by the irqchip code.
 637                  */
 638                 .ack_interrupt  = genphy_no_ack_interrupt,
 639                 .config_intr    = genphy_no_config_intr,
 640                 .suspend        = genphy_suspend,
 641                 .resume         = genphy_resume,
 642         },
 643 };
 644
 645 module_phy_driver(realtek_drvs);
 646
 647 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
 648         { PHY_ID_MATCH_VENDOR(0x001cc800) },
 649         { }
 650 };
 651
 652 MODULE_DEVICE_TABLE(mdio, realtek_tbl);