?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / pci / controller / pci-aardvark.c
blob2ecc79c03ade13536b3e85379dfa9f86c7891f4e
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
4 * 3700.
5 *
6 * Copyright (C) 2016 Marvell
7 *
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/msi.h>
21 #include <linux/of_address.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_pci.h>
24
25 #include "../pci.h"
26 #include "../pci-bridge-emul.h"
27
28 /* PCIe core registers */
29 #define PCIE_CORE_DEV_ID_REG 0x0
30 #define PCIE_CORE_CMD_STATUS_REG 0x4
31 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
32 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
33 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
34 #define PCIE_CORE_DEV_REV_REG 0x8
35 #define PCIE_CORE_PCIEXP_CAP 0xc0
36 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
37 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
38 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
39 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
40 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
41 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
42 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
43 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
44 #define PCIE_CORE_LINK_TRAINING BIT(5)
45 #define PCIE_CORE_LINK_SPEED_SHIFT 16
46 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
47 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
48 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
49 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
50 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
51 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
52 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
53 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
54 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
55 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
56 /* PIO registers base address and register offsets */
57 #define PIO_BASE_ADDR 0x4000
58 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
59 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
60 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
61 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
62 #define PIO_COMPLETION_STATUS_SHIFT 7
63 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
64 #define PIO_COMPLETION_STATUS_OK 0
65 #define PIO_COMPLETION_STATUS_UR 1
66 #define PIO_COMPLETION_STATUS_CRS 2
67 #define PIO_COMPLETION_STATUS_CA 4
68 #define PIO_NON_POSTED_REQ BIT(0)
69 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
70 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
71 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
72 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
73 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
74 #define PIO_START (PIO_BASE_ADDR + 0x1c)
75 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
76 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
77
78 /* Aardvark Control registers */
79 #define CONTROL_BASE_ADDR 0x4800
80 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
81 #define PCIE_GEN_SEL_MSK 0x3
82 #define PCIE_GEN_SEL_SHIFT 0x0
83 #define SPEED_GEN_1 0
84 #define SPEED_GEN_2 1
85 #define SPEED_GEN_3 2
86 #define IS_RC_MSK 1
87 #define IS_RC_SHIFT 2
88 #define LANE_CNT_MSK 0x18
89 #define LANE_CNT_SHIFT 0x3
90 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
91 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
92 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
93 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
94 #define LINK_TRAINING_EN BIT(6)
95 #define LEGACY_INTA BIT(28)
96 #define LEGACY_INTB BIT(29)
97 #define LEGACY_INTC BIT(30)
98 #define LEGACY_INTD BIT(31)
99 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
100 #define HOT_RESET_GEN BIT(0)
101 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
102 #define PCIE_CORE_CTRL2_RESERVED 0x7
103 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
104 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
105 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
106 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
107 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
108 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
109 #define PCIE_MSG_PM_PME_MASK BIT(7)
110 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
111 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
112 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
113 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
114 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
115 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
116 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
117 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
118 #define PCIE_ISR1_FLUSH BIT(5)
119 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
120 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
121 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
122 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
123 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
124 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
125 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
126
127 /* LMI registers base address and register offsets */
128 #define LMI_BASE_ADDR 0x6000
129 #define CFG_REG (LMI_BASE_ADDR + 0x0)
130 #define LTSSM_SHIFT 24
131 #define LTSSM_MASK 0x3f
132 #define LTSSM_L0 0x10
133 #define RC_BAR_CONFIG 0x300
134
135 /* PCIe core controller registers */
136 #define CTRL_CORE_BASE_ADDR 0x18000
137 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
138 #define CTRL_MODE_SHIFT 0x0
139 #define CTRL_MODE_MASK 0x1
140 #define PCIE_CORE_MODE_DIRECT 0x0
141 #define PCIE_CORE_MODE_COMMAND 0x1
142
143 /* PCIe Central Interrupts Registers */
144 #define CENTRAL_INT_BASE_ADDR 0x1b000
145 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
146 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
147 #define PCIE_IRQ_CMDQ_INT BIT(0)
148 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
149 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
150 #define PCIE_IRQ_DMA_INT BIT(4)
151 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
152 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
153 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
154 #define PCIE_IRQ_COMPQ_INT BIT(12)
155 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
156 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
157 #define PCIE_IRQ_CORE_INT BIT(16)
158 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
159 #define PCIE_IRQ_DPMU_INT BIT(18)
160 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
161 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
162 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
163 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
164 #define PCIE_IRQ_EP_STATUS BIT(23)
165 #define PCIE_IRQ_ALL_MASK 0xfff0fb
166 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
167
168 /* Transaction types */
169 #define PCIE_CONFIG_RD_TYPE0 0x8
170 #define PCIE_CONFIG_RD_TYPE1 0x9
171 #define PCIE_CONFIG_WR_TYPE0 0xa
172 #define PCIE_CONFIG_WR_TYPE1 0xb
173
174 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
175 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
176 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
177 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
178 #define PCIE_CONF_ADDR(bus, devfn, where) \
179 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
180 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
181
182 #define PIO_RETRY_CNT 500
183 #define PIO_RETRY_DELAY 2 /* 2 us*/
184
185 #define LINK_WAIT_MAX_RETRIES 10
186 #define LINK_WAIT_USLEEP_MIN 90000
187 #define LINK_WAIT_USLEEP_MAX 100000
188 #define RETRAIN_WAIT_MAX_RETRIES 10
189 #define RETRAIN_WAIT_USLEEP_US 2000
190
191 #define MSI_IRQ_NUM 32
192
193 struct advk_pcie {
194 struct platform_device *pdev;
195 void __iomem *base;
196 struct irq_domain *irq_domain;
197 struct irq_chip irq_chip;
198 struct irq_domain *msi_domain;
199 struct irq_domain *msi_inner_domain;
200 struct irq_chip msi_bottom_irq_chip;
201 struct irq_chip msi_irq_chip;
202 struct msi_domain_info msi_domain_info;
203 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
204 struct mutex msi_used_lock;
205 u16 msi_msg;
206 int root_bus_nr;
207 int link_gen;
208 struct pci_bridge_emul bridge;
209 struct gpio_desc *reset_gpio;
210 };
211
212 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
213 {
214 writel(val, pcie->base + reg);
215 }
216
217 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
218 {
219 return readl(pcie->base + reg);
220 }
221
222 static int advk_pcie_link_up(struct advk_pcie *pcie)
223 {
224 u32 val, ltssm_state;
225
226 val = advk_readl(pcie, CFG_REG);
227 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
228 return ltssm_state >= LTSSM_L0;
229 }
230
231 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
232 {
233 int retries;
234
235 /* check if the link is up or not */
236 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
237 if (advk_pcie_link_up(pcie))
238 return 0;
239
240 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
241 }
242
243 return -ETIMEDOUT;
244 }
245
246 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
247 {
248 size_t retries;
249
250 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
251 if (!advk_pcie_link_up(pcie))
252 break;
253 udelay(RETRAIN_WAIT_USLEEP_US);
254 }
255 }
256
257 static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen)
258 {
259 int ret, neg_gen;
260 u32 reg;
261
262 /* Setup link speed */
263 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
264 reg &= ~PCIE_GEN_SEL_MSK;
265 if (gen == 3)
266 reg |= SPEED_GEN_3;
267 else if (gen == 2)
268 reg |= SPEED_GEN_2;
269 else
270 reg |= SPEED_GEN_1;
271 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
272
273 /*
274 * Enable link training. This is not needed in every call to this
275 * function, just once suffices, but it does not break anything either.
276 */
277 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
278 reg |= LINK_TRAINING_EN;
279 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
280
281 /*
282 * Start link training immediately after enabling it.
283 * This solves problems for some buggy cards.
284 */
285 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
286 reg |= PCIE_CORE_LINK_TRAINING;
287 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
288
289 ret = advk_pcie_wait_for_link(pcie);
290 if (ret)
291 return ret;
292
293 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
294 neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf;
295
296 return neg_gen;
297 }
298
299 static void advk_pcie_train_link(struct advk_pcie *pcie)
300 {
301 struct device *dev = &pcie->pdev->dev;
302 int neg_gen = -1, gen;
303
304 /*
305 * Try link training at link gen specified by device tree property
306 * 'max-link-speed'. If this fails, iteratively train at lower gen.
307 */
308 for (gen = pcie->link_gen; gen > 0; --gen) {
309 neg_gen = advk_pcie_train_at_gen(pcie, gen);
310 if (neg_gen > 0)
311 break;
312 }
313
314 if (neg_gen < 0)
315 goto err;
316
317 /*
318 * After successful training if negotiated gen is lower than requested,
319 * train again on negotiated gen. This solves some stability issues for
320 * some buggy gen1 cards.
321 */
322 if (neg_gen < gen) {
323 gen = neg_gen;
324 neg_gen = advk_pcie_train_at_gen(pcie, gen);
325 }
326
327 if (neg_gen == gen) {
328 dev_info(dev, "link up at gen %i\n", gen);
329 return;
330 }
331
332 err:
333 dev_err(dev, "link never came up\n");
334 }
335
336 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
337 {
338 u32 reg;
339
340 if (!pcie->reset_gpio)
341 return;
342
343 /* PERST does not work for some cards when link training is enabled */
344 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
345 reg &= ~LINK_TRAINING_EN;
346 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
347
348 /* 10ms delay is needed for some cards */
349 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
350 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
351 usleep_range(10000, 11000);
352 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
353 }
354
355 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
356 {
357 u32 reg;
358
359 advk_pcie_issue_perst(pcie);
360
361 /* Set to Direct mode */
362 reg = advk_readl(pcie, CTRL_CONFIG_REG);
363 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
364 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
365 advk_writel(pcie, reg, CTRL_CONFIG_REG);
366
367 /* Set PCI global control register to RC mode */
368 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
369 reg |= (IS_RC_MSK << IS_RC_SHIFT);
370 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
371
372 /* Set Advanced Error Capabilities and Control PF0 register */
373 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
374 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
375 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
376 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
377 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
378
379 /* Set PCIe Device Control and Status 1 PF0 register */
380 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
381 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
382 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
383 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
384 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
385 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
386
387 /* Program PCIe Control 2 to disable strict ordering */
388 reg = PCIE_CORE_CTRL2_RESERVED |
389 PCIE_CORE_CTRL2_TD_ENABLE;
390 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
391
392 /* Set lane X1 */
393 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
394 reg &= ~LANE_CNT_MSK;
395 reg |= LANE_COUNT_1;
396 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
397
398 /* Enable MSI */
399 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
400 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
401 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
402
403 /* Clear all interrupts */
404 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
405 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
406 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
407
408 /* Disable All ISR0/1 Sources */
409 reg = PCIE_ISR0_ALL_MASK;
410 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
411 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
412
413 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
414
415 /* Unmask all MSIs */
416 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
417
418 /* Enable summary interrupt for GIC SPI source */
419 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
420 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
421
422 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
423 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
424 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
425
426 /* Bypass the address window mapping for PIO */
427 reg = advk_readl(pcie, PIO_CTRL);
428 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
429 advk_writel(pcie, reg, PIO_CTRL);
430
431 /*
432 * PERST# signal could have been asserted by pinctrl subsystem before
433 * probe() callback has been called or issued explicitly by reset gpio
434 * function advk_pcie_issue_perst(), making the endpoint going into
435 * fundamental reset. As required by PCI Express spec a delay for at
436 * least 100ms after such a reset before link training is needed.
437 */
438 msleep(PCI_PM_D3COLD_WAIT);
439
440 advk_pcie_train_link(pcie);
441
442 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
443 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
444 PCIE_CORE_CMD_IO_ACCESS_EN |
445 PCIE_CORE_CMD_MEM_IO_REQ_EN;
446 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
447 }
448
449 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
450 {
451 struct device *dev = &pcie->pdev->dev;
452 u32 reg;
453 unsigned int status;
454 char *strcomp_status, *str_posted;
455
456 reg = advk_readl(pcie, PIO_STAT);
457 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
458 PIO_COMPLETION_STATUS_SHIFT;
459
460 if (!status)
461 return;
462
463 switch (status) {
464 case PIO_COMPLETION_STATUS_UR:
465 strcomp_status = "UR";
466 break;
467 case PIO_COMPLETION_STATUS_CRS:
468 strcomp_status = "CRS";
469 break;
470 case PIO_COMPLETION_STATUS_CA:
471 strcomp_status = "CA";
472 break;
473 default:
474 strcomp_status = "Unknown";
475 break;
476 }
477
478 if (reg & PIO_NON_POSTED_REQ)
479 str_posted = "Non-posted";
480 else
481 str_posted = "Posted";
482
483 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
484 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
485 }
486
487 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
488 {
489 struct device *dev = &pcie->pdev->dev;
490 int i;
491
492 for (i = 0; i < PIO_RETRY_CNT; i++) {
493 u32 start, isr;
494
495 start = advk_readl(pcie, PIO_START);
496 isr = advk_readl(pcie, PIO_ISR);
497 if (!start && isr)
498 return 0;
499 udelay(PIO_RETRY_DELAY);
500 }
501
502 dev_err(dev, "config read/write timed out\n");
503 return -ETIMEDOUT;
504 }
505
506
507 static pci_bridge_emul_read_status_t
508 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
509 int reg, u32 *value)
510 {
511 struct advk_pcie *pcie = bridge->data;
512
513
514 switch (reg) {
515 case PCI_EXP_SLTCTL:
516 *value = PCI_EXP_SLTSTA_PDS << 16;
517 return PCI_BRIDGE_EMUL_HANDLED;
518
519 case PCI_EXP_RTCTL: {
520 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
521 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
522 return PCI_BRIDGE_EMUL_HANDLED;
523 }
524
525 case PCI_EXP_RTSTA: {
526 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
527 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
528 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16);
529 return PCI_BRIDGE_EMUL_HANDLED;
530 }
531
532 case PCI_EXP_LNKCTL: {
533 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
534 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
535 ~(PCI_EXP_LNKSTA_LT << 16);
536 if (!advk_pcie_link_up(pcie))
537 val |= (PCI_EXP_LNKSTA_LT << 16);
538 *value = val;
539 return PCI_BRIDGE_EMUL_HANDLED;
540 }
541
542 case PCI_CAP_LIST_ID:
543 case PCI_EXP_DEVCAP:
544 case PCI_EXP_DEVCTL:
545 case PCI_EXP_LNKCAP:
546 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
547 return PCI_BRIDGE_EMUL_HANDLED;
548 default:
549 return PCI_BRIDGE_EMUL_NOT_HANDLED;
550 }
551
552 }
553
554 static void
555 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
556 int reg, u32 old, u32 new, u32 mask)
557 {
558 struct advk_pcie *pcie = bridge->data;
559
560 switch (reg) {
561 case PCI_EXP_DEVCTL:
562 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
563 break;
564
565 case PCI_EXP_LNKCTL:
566 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
567 if (new & PCI_EXP_LNKCTL_RL)
568 advk_pcie_wait_for_retrain(pcie);
569 break;
570
571 case PCI_EXP_RTCTL: {
572 /* Only mask/unmask PME interrupt */
573 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
574 ~PCIE_MSG_PM_PME_MASK;
575 if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
576 val |= PCIE_MSG_PM_PME_MASK;
577 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
578 break;
579 }
580
581 case PCI_EXP_RTSTA:
582 new = (new & PCI_EXP_RTSTA_PME) >> 9;
583 advk_writel(pcie, new, PCIE_ISR0_REG);
584 break;
585
586 default:
587 break;
588 }
589 }
590
591 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
592 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
593 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
594 };
595
596 /*
597 * Initialize the configuration space of the PCI-to-PCI bridge
598 * associated with the given PCIe interface.
599 */
600 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
601 {
602 struct pci_bridge_emul *bridge = &pcie->bridge;
603
604 bridge->conf.vendor =
605 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
606 bridge->conf.device =
607 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
608 bridge->conf.class_revision =
609 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
610
611 /* Support 32 bits I/O addressing */
612 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
613 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
614
615 /* Support 64 bits memory pref */
616 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
617 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
618
619 /* Support interrupt A for MSI feature */
620 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
621
622 bridge->has_pcie = true;
623 bridge->data = pcie;
624 bridge->ops = &advk_pci_bridge_emul_ops;
625
626 pci_bridge_emul_init(bridge, 0);
627
628 }
629
630 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
631 int devfn)
632 {
633 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
634 return false;
635
636 return true;
637 }
638
639 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
640 int where, int size, u32 *val)
641 {
642 struct advk_pcie *pcie = bus->sysdata;
643 u32 reg;
644 int ret;
645
646 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
647 *val = 0xffffffff;
648 return PCIBIOS_DEVICE_NOT_FOUND;
649 }
650
651 if (bus->number == pcie->root_bus_nr)
652 return pci_bridge_emul_conf_read(&pcie->bridge, where,
653 size, val);
654
655 /* Start PIO */
656 advk_writel(pcie, 0, PIO_START);
657 advk_writel(pcie, 1, PIO_ISR);
658
659 /* Program the control register */
660 reg = advk_readl(pcie, PIO_CTRL);
661 reg &= ~PIO_CTRL_TYPE_MASK;
662 if (bus->primary == pcie->root_bus_nr)
663 reg |= PCIE_CONFIG_RD_TYPE0;
664 else
665 reg |= PCIE_CONFIG_RD_TYPE1;
666 advk_writel(pcie, reg, PIO_CTRL);
667
668 /* Program the address registers */
669 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
670 advk_writel(pcie, reg, PIO_ADDR_LS);
671 advk_writel(pcie, 0, PIO_ADDR_MS);
672
673 /* Program the data strobe */
674 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
675
676 /* Start the transfer */
677 advk_writel(pcie, 1, PIO_START);
678
679 ret = advk_pcie_wait_pio(pcie);
680 if (ret < 0)
681 return PCIBIOS_SET_FAILED;
682
683 advk_pcie_check_pio_status(pcie);
684
685 /* Get the read result */
686 *val = advk_readl(pcie, PIO_RD_DATA);
687 if (size == 1)
688 *val = (*val >> (8 * (where & 3))) & 0xff;
689 else if (size == 2)
690 *val = (*val >> (8 * (where & 3))) & 0xffff;
691
692 return PCIBIOS_SUCCESSFUL;
693 }
694
695 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
696 int where, int size, u32 val)
697 {
698 struct advk_pcie *pcie = bus->sysdata;
699 u32 reg;
700 u32 data_strobe = 0x0;
701 int offset;
702 int ret;
703
704 if (!advk_pcie_valid_device(pcie, bus, devfn))
705 return PCIBIOS_DEVICE_NOT_FOUND;
706
707 if (bus->number == pcie->root_bus_nr)
708 return pci_bridge_emul_conf_write(&pcie->bridge, where,
709 size, val);
710
711 if (where % size)
712 return PCIBIOS_SET_FAILED;
713
714 /* Start PIO */
715 advk_writel(pcie, 0, PIO_START);
716 advk_writel(pcie, 1, PIO_ISR);
717
718 /* Program the control register */
719 reg = advk_readl(pcie, PIO_CTRL);
720 reg &= ~PIO_CTRL_TYPE_MASK;
721 if (bus->primary == pcie->root_bus_nr)
722 reg |= PCIE_CONFIG_WR_TYPE0;
723 else
724 reg |= PCIE_CONFIG_WR_TYPE1;
725 advk_writel(pcie, reg, PIO_CTRL);
726
727 /* Program the address registers */
728 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
729 advk_writel(pcie, reg, PIO_ADDR_LS);
730 advk_writel(pcie, 0, PIO_ADDR_MS);
731
732 /* Calculate the write strobe */
733 offset = where & 0x3;
734 reg = val << (8 * offset);
735 data_strobe = GENMASK(size - 1, 0) << offset;
736
737 /* Program the data register */
738 advk_writel(pcie, reg, PIO_WR_DATA);
739
740 /* Program the data strobe */
741 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
742
743 /* Start the transfer */
744 advk_writel(pcie, 1, PIO_START);
745
746 ret = advk_pcie_wait_pio(pcie);
747 if (ret < 0)
748 return PCIBIOS_SET_FAILED;
749
750 advk_pcie_check_pio_status(pcie);
751
752 return PCIBIOS_SUCCESSFUL;
753 }
754
755 static struct pci_ops advk_pcie_ops = {
756 .read = advk_pcie_rd_conf,
757 .write = advk_pcie_wr_conf,
758 };
759
760 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
761 struct msi_msg *msg)
762 {
763 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
764 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
765
766 msg->address_lo = lower_32_bits(msi_msg);
767 msg->address_hi = upper_32_bits(msi_msg);
768 msg->data = data->irq;
769 }
770
771 static int advk_msi_set_affinity(struct irq_data *irq_data,
772 const struct cpumask *mask, bool force)
773 {
774 return -EINVAL;
775 }
776
777 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
778 unsigned int virq,
779 unsigned int nr_irqs, void *args)
780 {
781 struct advk_pcie *pcie = domain->host_data;
782 int hwirq, i;
783
784 mutex_lock(&pcie->msi_used_lock);
785 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
786 0, nr_irqs, 0);
787 if (hwirq >= MSI_IRQ_NUM) {
788 mutex_unlock(&pcie->msi_used_lock);
789 return -ENOSPC;
790 }
791
792 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
793 mutex_unlock(&pcie->msi_used_lock);
794
795 for (i = 0; i < nr_irqs; i++)
796 irq_domain_set_info(domain, virq + i, hwirq + i,
797 &pcie->msi_bottom_irq_chip,
798 domain->host_data, handle_simple_irq,
799 NULL, NULL);
800
801 return hwirq;
802 }
803
804 static void advk_msi_irq_domain_free(struct irq_domain *domain,
805 unsigned int virq, unsigned int nr_irqs)
806 {
807 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
808 struct advk_pcie *pcie = domain->host_data;
809
810 mutex_lock(&pcie->msi_used_lock);
811 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
812 mutex_unlock(&pcie->msi_used_lock);
813 }
814
815 static const struct irq_domain_ops advk_msi_domain_ops = {
816 .alloc = advk_msi_irq_domain_alloc,
817 .free = advk_msi_irq_domain_free,
818 };
819
820 static void advk_pcie_irq_mask(struct irq_data *d)
821 {
822 struct advk_pcie *pcie = d->domain->host_data;
823 irq_hw_number_t hwirq = irqd_to_hwirq(d);
824 u32 mask;
825
826 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
827 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
828 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
829 }
830
831 static void advk_pcie_irq_unmask(struct irq_data *d)
832 {
833 struct advk_pcie *pcie = d->domain->host_data;
834 irq_hw_number_t hwirq = irqd_to_hwirq(d);
835 u32 mask;
836
837 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
838 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
839 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
840 }
841
842 static int advk_pcie_irq_map(struct irq_domain *h,
843 unsigned int virq, irq_hw_number_t hwirq)
844 {
845 struct advk_pcie *pcie = h->host_data;
846
847 advk_pcie_irq_mask(irq_get_irq_data(virq));
848 irq_set_status_flags(virq, IRQ_LEVEL);
849 irq_set_chip_and_handler(virq, &pcie->irq_chip,
850 handle_level_irq);
851 irq_set_chip_data(virq, pcie);
852
853 return 0;
854 }
855
856 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
857 .map = advk_pcie_irq_map,
858 .xlate = irq_domain_xlate_onecell,
859 };
860
861 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
862 {
863 struct device *dev = &pcie->pdev->dev;
864 struct device_node *node = dev->of_node;
865 struct irq_chip *bottom_ic, *msi_ic;
866 struct msi_domain_info *msi_di;
867 phys_addr_t msi_msg_phys;
868
869 mutex_init(&pcie->msi_used_lock);
870
871 bottom_ic = &pcie->msi_bottom_irq_chip;
872
873 bottom_ic->name = "MSI";
874 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
875 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
876
877 msi_ic = &pcie->msi_irq_chip;
878 msi_ic->name = "advk-MSI";
879
880 msi_di = &pcie->msi_domain_info;
881 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
882 MSI_FLAG_MULTI_PCI_MSI;
883 msi_di->chip = msi_ic;
884
885 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
886
887 advk_writel(pcie, lower_32_bits(msi_msg_phys),
888 PCIE_MSI_ADDR_LOW_REG);
889 advk_writel(pcie, upper_32_bits(msi_msg_phys),
890 PCIE_MSI_ADDR_HIGH_REG);
891
892 pcie->msi_inner_domain =
893 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
894 &advk_msi_domain_ops, pcie);
895 if (!pcie->msi_inner_domain)
896 return -ENOMEM;
897
898 pcie->msi_domain =
899 pci_msi_create_irq_domain(of_node_to_fwnode(node),
900 msi_di, pcie->msi_inner_domain);
901 if (!pcie->msi_domain) {
902 irq_domain_remove(pcie->msi_inner_domain);
903 return -ENOMEM;
904 }
905
906 return 0;
907 }
908
909 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
910 {
911 irq_domain_remove(pcie->msi_domain);
912 irq_domain_remove(pcie->msi_inner_domain);
913 }
914
915 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
916 {
917 struct device *dev = &pcie->pdev->dev;
918 struct device_node *node = dev->of_node;
919 struct device_node *pcie_intc_node;
920 struct irq_chip *irq_chip;
921 int ret = 0;
922
923 pcie_intc_node = of_get_next_child(node, NULL);
924 if (!pcie_intc_node) {
925 dev_err(dev, "No PCIe Intc node found\n");
926 return -ENODEV;
927 }
928
929 irq_chip = &pcie->irq_chip;
930
931 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
932 dev_name(dev));
933 if (!irq_chip->name) {
934 ret = -ENOMEM;
935 goto out_put_node;
936 }
937
938 irq_chip->irq_mask = advk_pcie_irq_mask;
939 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
940 irq_chip->irq_unmask = advk_pcie_irq_unmask;
941
942 pcie->irq_domain =
943 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
944 &advk_pcie_irq_domain_ops, pcie);
945 if (!pcie->irq_domain) {
946 dev_err(dev, "Failed to get a INTx IRQ domain\n");
947 ret = -ENOMEM;
948 goto out_put_node;
949 }
950
951 out_put_node:
952 of_node_put(pcie_intc_node);
953 return ret;
954 }
955
956 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
957 {
958 irq_domain_remove(pcie->irq_domain);
959 }
960
961 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
962 {
963 u32 msi_val, msi_mask, msi_status, msi_idx;
964 u16 msi_data;
965
966 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
967 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
968 msi_status = msi_val & ~msi_mask;
969
970 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
971 if (!(BIT(msi_idx) & msi_status))
972 continue;
973
974 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
975 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
976 generic_handle_irq(msi_data);
977 }
978
979 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
980 PCIE_ISR0_REG);
981 }
982
983 static void advk_pcie_handle_int(struct advk_pcie *pcie)
984 {
985 u32 isr0_val, isr0_mask, isr0_status;
986 u32 isr1_val, isr1_mask, isr1_status;
987 int i, virq;
988
989 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
990 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
991 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
992
993 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
994 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
995 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
996
997 if (!isr0_status && !isr1_status) {
998 advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
999 advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
1000 return;
1001 }
1002
1003 /* Process MSI interrupts */
1004 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1005 advk_pcie_handle_msi(pcie);
1006
1007 /* Process legacy interrupts */
1008 for (i = 0; i < PCI_NUM_INTX; i++) {
1009 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1010 continue;
1011
1012 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1013 PCIE_ISR1_REG);
1014
1015 virq = irq_find_mapping(pcie->irq_domain, i);
1016 generic_handle_irq(virq);
1017 }
1018 }
1019
1020 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
1021 {
1022 struct advk_pcie *pcie = arg;
1023 u32 status;
1024
1025 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1026 if (!(status & PCIE_IRQ_CORE_INT))
1027 return IRQ_NONE;
1028
1029 advk_pcie_handle_int(pcie);
1030
1031 /* Clear interrupt */
1032 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1033
1034 return IRQ_HANDLED;
1035 }
1036
1037 static int advk_pcie_probe(struct platform_device *pdev)
1038 {
1039 struct device *dev = &pdev->dev;
1040 struct advk_pcie *pcie;
1041 struct resource *res, *bus;
1042 struct pci_host_bridge *bridge;
1043 int ret, irq;
1044
1045 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1046 if (!bridge)
1047 return -ENOMEM;
1048
1049 pcie = pci_host_bridge_priv(bridge);
1050 pcie->pdev = pdev;
1051
1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 pcie->base = devm_ioremap_resource(dev, res);
1054 if (IS_ERR(pcie->base))
1055 return PTR_ERR(pcie->base);
1056
1057 irq = platform_get_irq(pdev, 0);
1058 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1059 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1060 pcie);
1061 if (ret) {
1062 dev_err(dev, "Failed to register interrupt\n");
1063 return ret;
1064 }
1065
1066 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
1067 &bridge->dma_ranges, &bus);
1068 if (ret) {
1069 dev_err(dev, "Failed to parse resources\n");
1070 return ret;
1071 }
1072 pcie->root_bus_nr = bus->start;
1073
1074 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
1075 "reset-gpios", 0,
1076 GPIOD_OUT_LOW,
1077 "pcie1-reset");
1078 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1079 if (ret) {
1080 if (ret == -ENOENT) {
1081 pcie->reset_gpio = NULL;
1082 } else {
1083 if (ret != -EPROBE_DEFER)
1084 dev_err(dev, "Failed to get reset-gpio: %i\n",
1085 ret);
1086 return ret;
1087 }
1088 }
1089
1090 ret = of_pci_get_max_link_speed(dev->of_node);
1091 if (ret <= 0 || ret > 3)
1092 pcie->link_gen = 3;
1093 else
1094 pcie->link_gen = ret;
1095
1096 advk_pcie_setup_hw(pcie);
1097
1098 advk_sw_pci_bridge_init(pcie);
1099
1100 ret = advk_pcie_init_irq_domain(pcie);
1101 if (ret) {
1102 dev_err(dev, "Failed to initialize irq\n");
1103 return ret;
1104 }
1105
1106 ret = advk_pcie_init_msi_irq_domain(pcie);
1107 if (ret) {
1108 dev_err(dev, "Failed to initialize irq\n");
1109 advk_pcie_remove_irq_domain(pcie);
1110 return ret;
1111 }
1112
1113 bridge->dev.parent = dev;
1114 bridge->sysdata = pcie;
1115 bridge->busnr = 0;
1116 bridge->ops = &advk_pcie_ops;
1117 bridge->map_irq = of_irq_parse_and_map_pci;
1118 bridge->swizzle_irq = pci_common_swizzle;
1119
1120 ret = pci_host_probe(bridge);
1121 if (ret < 0) {
1122 advk_pcie_remove_msi_irq_domain(pcie);
1123 advk_pcie_remove_irq_domain(pcie);
1124 return ret;
1125 }
1126
1127 return 0;
1128 }
1129
1130 static const struct of_device_id advk_pcie_of_match_table[] = {
1131 { .compatible = "marvell,armada-3700-pcie", },
1132 {},
1133 };
1134
1135 static struct platform_driver advk_pcie_driver = {
1136 .driver = {
1137 .name = "advk-pcie",
1138 .of_match_table = advk_pcie_of_match_table,
1139 /* Driver unloading/unbinding currently not supported */
1140 .suppress_bind_attrs = true,
1141 },
1142 .probe = advk_pcie_probe,
1143 };
1144 builtin_platform_driver(advk_pcie_driver);
Linux with added FPC-III support