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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / pci / controller / pcie-rcar.c
blob1bae6a4abaaebd410815831ba6a5ae52b76ff6f5
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE BIT(31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 BIT(8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEPHYSR 0x0007f0
42 #define PHYRDY BIT(0)
43 #define PCIEMSITXR 0x000840
44
45 /* Transfer control */
46 #define PCIETCTLR 0x02000
47 #define DL_DOWN BIT(3)
48 #define CFINIT BIT(0)
49 #define PCIETSTR 0x02004
50 #define DATA_LINK_ACTIVE BIT(0)
51 #define PCIEERRFR 0x02020
52 #define UNSUPPORTED_REQUEST BIT(4)
53 #define PCIEMSIFR 0x02044
54 #define PCIEMSIALR 0x02048
55 #define MSIFE BIT(0)
56 #define PCIEMSIAUR 0x0204c
57 #define PCIEMSIIER 0x02050
58
59 /* root port address */
60 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
61
62 /* local address reg & mask */
63 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
64 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
65 #define LAM_PREFETCH BIT(3)
66 #define LAM_64BIT BIT(2)
67 #define LAR_ENABLE BIT(1)
68
69 /* PCIe address reg & mask */
70 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
71 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
72 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
73 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
74 #define PAR_ENABLE BIT(31)
75 #define IO_SPACE BIT(8)
76
77 /* Configuration */
78 #define PCICONF(x) (0x010000 + ((x) * 0x4))
79 #define PMCAP(x) (0x010040 + ((x) * 0x4))
80 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
81 #define VCCAP(x) (0x010100 + ((x) * 0x4))
82
83 /* link layer */
84 #define IDSETR1 0x011004
85 #define TLCTLR 0x011048
86 #define MACSR 0x011054
87 #define SPCHGFIN BIT(4)
88 #define SPCHGFAIL BIT(6)
89 #define SPCHGSUC BIT(7)
90 #define LINK_SPEED (0xf << 16)
91 #define LINK_SPEED_2_5GTS (1 << 16)
92 #define LINK_SPEED_5_0GTS (2 << 16)
93 #define MACCTLR 0x011058
94 #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
95 #define SPEED_CHANGE BIT(24)
96 #define SCRAMBLE_DISABLE BIT(27)
97 #define LTSMDIS BIT(31)
98 #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
99 #define PMSR 0x01105c
100 #define MACS2R 0x011078
101 #define MACCGSPSETR 0x011084
102 #define SPCNGRSN BIT(31)
103
104 /* R-Car H1 PHY */
105 #define H1_PCIEPHYADRR 0x04000c
106 #define WRITE_CMD BIT(16)
107 #define PHY_ACK BIT(24)
108 #define RATE_POS 12
109 #define LANE_POS 8
110 #define ADR_POS 0
111 #define H1_PCIEPHYDOUTR 0x040014
112
113 /* R-Car Gen2 PHY */
114 #define GEN2_PCIEPHYADDR 0x780
115 #define GEN2_PCIEPHYDATA 0x784
116 #define GEN2_PCIEPHYCTRL 0x78c
117
118 #define INT_PCI_MSI_NR 32
119
120 #define RCONF(x) (PCICONF(0) + (x))
121 #define RPMCAP(x) (PMCAP(0) + (x))
122 #define REXPCAP(x) (EXPCAP(0) + (x))
123 #define RVCCAP(x) (VCCAP(0) + (x))
124
125 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
126 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
127 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
128
129 #define RCAR_PCI_MAX_RESOURCES 4
130 #define MAX_NR_INBOUND_MAPS 6
131
132 struct rcar_msi {
133 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
134 struct irq_domain *domain;
135 struct msi_controller chip;
136 unsigned long pages;
137 struct mutex lock;
138 int irq1;
139 int irq2;
140 };
141
142 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
143 {
144 return container_of(chip, struct rcar_msi, chip);
145 }
146
147 /* Structure representing the PCIe interface */
148 struct rcar_pcie {
149 struct device *dev;
150 struct phy *phy;
151 void __iomem *base;
152 struct list_head resources;
153 int root_bus_nr;
154 struct clk *bus_clk;
155 struct rcar_msi msi;
156 };
157
158 static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val,
159 unsigned int reg)
160 {
161 writel(val, pcie->base + reg);
162 }
163
164 static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
165 {
166 return readl(pcie->base + reg);
167 }
168
169 enum {
170 RCAR_PCI_ACCESS_READ,
171 RCAR_PCI_ACCESS_WRITE,
172 };
173
174 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
175 {
176 unsigned int shift = BITS_PER_BYTE * (where & 3);
177 u32 val = rcar_pci_read_reg(pcie, where & ~3);
178
179 val &= ~(mask << shift);
180 val |= data << shift;
181 rcar_pci_write_reg(pcie, val, where & ~3);
182 }
183
184 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
185 {
186 unsigned int shift = BITS_PER_BYTE * (where & 3);
187 u32 val = rcar_pci_read_reg(pcie, where & ~3);
188
189 return val >> shift;
190 }
191
192 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
193 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
194 unsigned char access_type, struct pci_bus *bus,
195 unsigned int devfn, int where, u32 *data)
196 {
197 unsigned int dev, func, reg, index;
198
199 dev = PCI_SLOT(devfn);
200 func = PCI_FUNC(devfn);
201 reg = where & ~3;
202 index = reg / 4;
203
204 /*
205 * While each channel has its own memory-mapped extended config
206 * space, it's generally only accessible when in endpoint mode.
207 * When in root complex mode, the controller is unable to target
208 * itself with either type 0 or type 1 accesses, and indeed, any
209 * controller initiated target transfer to its own config space
210 * result in a completer abort.
211 *
212 * Each channel effectively only supports a single device, but as
213 * the same channel <-> device access works for any PCI_SLOT()
214 * value, we cheat a bit here and bind the controller's config
215 * space to devfn 0 in order to enable self-enumeration. In this
216 * case the regular ECAR/ECDR path is sidelined and the mangled
217 * config access itself is initiated as an internal bus transaction.
218 */
219 if (pci_is_root_bus(bus)) {
220 if (dev != 0)
221 return PCIBIOS_DEVICE_NOT_FOUND;
222
223 if (access_type == RCAR_PCI_ACCESS_READ) {
224 *data = rcar_pci_read_reg(pcie, PCICONF(index));
225 } else {
226 /* Keep an eye out for changes to the root bus number */
227 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
228 pcie->root_bus_nr = *data & 0xff;
229
230 rcar_pci_write_reg(pcie, *data, PCICONF(index));
231 }
232
233 return PCIBIOS_SUCCESSFUL;
234 }
235
236 if (pcie->root_bus_nr < 0)
237 return PCIBIOS_DEVICE_NOT_FOUND;
238
239 /* Clear errors */
240 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
241
242 /* Set the PIO address */
243 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
244 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
245
246 /* Enable the configuration access */
247 if (bus->parent->number == pcie->root_bus_nr)
248 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
249 else
250 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
251
252 /* Check for errors */
253 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
254 return PCIBIOS_DEVICE_NOT_FOUND;
255
256 /* Check for master and target aborts */
257 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
258 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
259 return PCIBIOS_DEVICE_NOT_FOUND;
260
261 if (access_type == RCAR_PCI_ACCESS_READ)
262 *data = rcar_pci_read_reg(pcie, PCIECDR);
263 else
264 rcar_pci_write_reg(pcie, *data, PCIECDR);
265
266 /* Disable the configuration access */
267 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
268
269 return PCIBIOS_SUCCESSFUL;
270 }
271
272 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
273 int where, int size, u32 *val)
274 {
275 struct rcar_pcie *pcie = bus->sysdata;
276 int ret;
277
278 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
279 bus, devfn, where, val);
280 if (ret != PCIBIOS_SUCCESSFUL) {
281 *val = 0xffffffff;
282 return ret;
283 }
284
285 if (size == 1)
286 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
287 else if (size == 2)
288 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
289
290 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
291 bus->number, devfn, where, size, *val);
292
293 return ret;
294 }
295
296 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
297 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
298 int where, int size, u32 val)
299 {
300 struct rcar_pcie *pcie = bus->sysdata;
301 unsigned int shift;
302 u32 data;
303 int ret;
304
305 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
306 bus, devfn, where, &data);
307 if (ret != PCIBIOS_SUCCESSFUL)
308 return ret;
309
310 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
311 bus->number, devfn, where, size, val);
312
313 if (size == 1) {
314 shift = BITS_PER_BYTE * (where & 3);
315 data &= ~(0xff << shift);
316 data |= ((val & 0xff) << shift);
317 } else if (size == 2) {
318 shift = BITS_PER_BYTE * (where & 2);
319 data &= ~(0xffff << shift);
320 data |= ((val & 0xffff) << shift);
321 } else
322 data = val;
323
324 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
325 bus, devfn, where, &data);
326
327 return ret;
328 }
329
330 static struct pci_ops rcar_pcie_ops = {
331 .read = rcar_pcie_read_conf,
332 .write = rcar_pcie_write_conf,
333 };
334
335 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
336 struct resource_entry *window)
337 {
338 /* Setup PCIe address space mappings for each resource */
339 resource_size_t size;
340 resource_size_t res_start;
341 struct resource *res = window->res;
342 u32 mask;
343
344 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
345
346 /*
347 * The PAMR mask is calculated in units of 128Bytes, which
348 * keeps things pretty simple.
349 */
350 size = resource_size(res);
351 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
352 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
353
354 if (res->flags & IORESOURCE_IO)
355 res_start = pci_pio_to_address(res->start) - window->offset;
356 else
357 res_start = res->start - window->offset;
358
359 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
360 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
361 PCIEPALR(win));
362
363 /* First resource is for IO */
364 mask = PAR_ENABLE;
365 if (res->flags & IORESOURCE_IO)
366 mask |= IO_SPACE;
367
368 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
369 }
370
371 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
372 {
373 struct resource_entry *win;
374 int i = 0;
375
376 /* Setup PCI resources */
377 resource_list_for_each_entry(win, &pci->resources) {
378 struct resource *res = win->res;
379
380 if (!res->flags)
381 continue;
382
383 switch (resource_type(res)) {
384 case IORESOURCE_IO:
385 case IORESOURCE_MEM:
386 rcar_pcie_setup_window(i, pci, win);
387 i++;
388 break;
389 case IORESOURCE_BUS:
390 pci->root_bus_nr = res->start;
391 break;
392 default:
393 continue;
394 }
395
396 pci_add_resource(resource, res);
397 }
398
399 return 1;
400 }
401
402 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
403 {
404 struct device *dev = pcie->dev;
405 unsigned int timeout = 1000;
406 u32 macsr;
407
408 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
409 return;
410
411 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
412 dev_err(dev, "Speed change already in progress\n");
413 return;
414 }
415
416 macsr = rcar_pci_read_reg(pcie, MACSR);
417 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
418 goto done;
419
420 /* Set target link speed to 5.0 GT/s */
421 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
422 PCI_EXP_LNKSTA_CLS_5_0GB);
423
424 /* Set speed change reason as intentional factor */
425 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
426
427 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
428 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
429 rcar_pci_write_reg(pcie, macsr, MACSR);
430
431 /* Start link speed change */
432 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
433
434 while (timeout--) {
435 macsr = rcar_pci_read_reg(pcie, MACSR);
436 if (macsr & SPCHGFIN) {
437 /* Clear the interrupt bits */
438 rcar_pci_write_reg(pcie, macsr, MACSR);
439
440 if (macsr & SPCHGFAIL)
441 dev_err(dev, "Speed change failed\n");
442
443 goto done;
444 }
445
446 msleep(1);
447 }
448
449 dev_err(dev, "Speed change timed out\n");
450
451 done:
452 dev_info(dev, "Current link speed is %s GT/s\n",
453 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
454 }
455
456 static int rcar_pcie_enable(struct rcar_pcie *pcie)
457 {
458 struct device *dev = pcie->dev;
459 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
460 struct pci_bus *bus, *child;
461 int ret;
462
463 /* Try setting 5 GT/s link speed */
464 rcar_pcie_force_speedup(pcie);
465
466 rcar_pcie_setup(&bridge->windows, pcie);
467
468 pci_add_flags(PCI_REASSIGN_ALL_BUS);
469
470 bridge->dev.parent = dev;
471 bridge->sysdata = pcie;
472 bridge->busnr = pcie->root_bus_nr;
473 bridge->ops = &rcar_pcie_ops;
474 bridge->map_irq = of_irq_parse_and_map_pci;
475 bridge->swizzle_irq = pci_common_swizzle;
476 if (IS_ENABLED(CONFIG_PCI_MSI))
477 bridge->msi = &pcie->msi.chip;
478
479 ret = pci_scan_root_bus_bridge(bridge);
480 if (ret < 0)
481 return ret;
482
483 bus = bridge->bus;
484
485 pci_bus_size_bridges(bus);
486 pci_bus_assign_resources(bus);
487
488 list_for_each_entry(child, &bus->children, node)
489 pcie_bus_configure_settings(child);
490
491 pci_bus_add_devices(bus);
492
493 return 0;
494 }
495
496 static int phy_wait_for_ack(struct rcar_pcie *pcie)
497 {
498 struct device *dev = pcie->dev;
499 unsigned int timeout = 100;
500
501 while (timeout--) {
502 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
503 return 0;
504
505 udelay(100);
506 }
507
508 dev_err(dev, "Access to PCIe phy timed out\n");
509
510 return -ETIMEDOUT;
511 }
512
513 static void phy_write_reg(struct rcar_pcie *pcie,
514 unsigned int rate, u32 addr,
515 unsigned int lane, u32 data)
516 {
517 u32 phyaddr;
518
519 phyaddr = WRITE_CMD |
520 ((rate & 1) << RATE_POS) |
521 ((lane & 0xf) << LANE_POS) |
522 ((addr & 0xff) << ADR_POS);
523
524 /* Set write data */
525 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
526 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
527
528 /* Ignore errors as they will be dealt with if the data link is down */
529 phy_wait_for_ack(pcie);
530
531 /* Clear command */
532 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
533 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
534
535 /* Ignore errors as they will be dealt with if the data link is down */
536 phy_wait_for_ack(pcie);
537 }
538
539 static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
540 {
541 unsigned int timeout = 10;
542
543 while (timeout--) {
544 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
545 return 0;
546
547 msleep(5);
548 }
549
550 return -ETIMEDOUT;
551 }
552
553 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
554 {
555 unsigned int timeout = 10000;
556
557 while (timeout--) {
558 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
559 return 0;
560
561 udelay(5);
562 cpu_relax();
563 }
564
565 return -ETIMEDOUT;
566 }
567
568 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
569 {
570 int err;
571
572 /* Begin initialization */
573 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
574
575 /* Set mode */
576 rcar_pci_write_reg(pcie, 1, PCIEMSR);
577
578 err = rcar_pcie_wait_for_phyrdy(pcie);
579 if (err)
580 return err;
581
582 /*
583 * Initial header for port config space is type 1, set the device
584 * class to match. Hardware takes care of propagating the IDSETR
585 * settings, so there is no need to bother with a quirk.
586 */
587 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
588
589 /*
590 * Setup Secondary Bus Number & Subordinate Bus Number, even though
591 * they aren't used, to avoid bridge being detected as broken.
592 */
593 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
594 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
595
596 /* Initialize default capabilities. */
597 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
598 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
599 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
600 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
601 PCI_HEADER_TYPE_BRIDGE);
602
603 /* Enable data link layer active state reporting */
604 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
605 PCI_EXP_LNKCAP_DLLLARC);
606
607 /* Write out the physical slot number = 0 */
608 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
609
610 /* Set the completion timer timeout to the maximum 50ms. */
611 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
612
613 /* Terminate list of capabilities (Next Capability Offset=0) */
614 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
615
616 /* Enable MSI */
617 if (IS_ENABLED(CONFIG_PCI_MSI))
618 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
619
620 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
621
622 /* Finish initialization - establish a PCI Express link */
623 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
624
625 /* This will timeout if we don't have a link. */
626 err = rcar_pcie_wait_for_dl(pcie);
627 if (err)
628 return err;
629
630 /* Enable INTx interrupts */
631 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
632
633 wmb();
634
635 return 0;
636 }
637
638 static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
639 {
640 /* Initialize the phy */
641 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
642 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
643 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
644 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
645 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
646 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
647 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
648 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
649 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
650 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
651 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
652 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
653
654 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
655 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
656 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
657
658 return 0;
659 }
660
661 static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
662 {
663 /*
664 * These settings come from the R-Car Series, 2nd Generation User's
665 * Manual, section 50.3.1 (2) Initialization of the physical layer.
666 */
667 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
668 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
669 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
670 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
671
672 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
673 /* The following value is for DC connection, no termination resistor */
674 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
675 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
676 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
677
678 return 0;
679 }
680
681 static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
682 {
683 int err;
684
685 err = phy_init(pcie->phy);
686 if (err)
687 return err;
688
689 err = phy_power_on(pcie->phy);
690 if (err)
691 phy_exit(pcie->phy);
692
693 return err;
694 }
695
696 static int rcar_msi_alloc(struct rcar_msi *chip)
697 {
698 int msi;
699
700 mutex_lock(&chip->lock);
701
702 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
703 if (msi < INT_PCI_MSI_NR)
704 set_bit(msi, chip->used);
705 else
706 msi = -ENOSPC;
707
708 mutex_unlock(&chip->lock);
709
710 return msi;
711 }
712
713 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
714 {
715 int msi;
716
717 mutex_lock(&chip->lock);
718 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
719 order_base_2(no_irqs));
720 mutex_unlock(&chip->lock);
721
722 return msi;
723 }
724
725 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
726 {
727 mutex_lock(&chip->lock);
728 clear_bit(irq, chip->used);
729 mutex_unlock(&chip->lock);
730 }
731
732 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
733 {
734 struct rcar_pcie *pcie = data;
735 struct rcar_msi *msi = &pcie->msi;
736 struct device *dev = pcie->dev;
737 unsigned long reg;
738
739 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
740
741 /* MSI & INTx share an interrupt - we only handle MSI here */
742 if (!reg)
743 return IRQ_NONE;
744
745 while (reg) {
746 unsigned int index = find_first_bit(&reg, 32);
747 unsigned int msi_irq;
748
749 /* clear the interrupt */
750 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
751
752 msi_irq = irq_find_mapping(msi->domain, index);
753 if (msi_irq) {
754 if (test_bit(index, msi->used))
755 generic_handle_irq(msi_irq);
756 else
757 dev_info(dev, "unhandled MSI\n");
758 } else {
759 /* Unknown MSI, just clear it */
760 dev_dbg(dev, "unexpected MSI\n");
761 }
762
763 /* see if there's any more pending in this vector */
764 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
765 }
766
767 return IRQ_HANDLED;
768 }
769
770 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
771 struct msi_desc *desc)
772 {
773 struct rcar_msi *msi = to_rcar_msi(chip);
774 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
775 struct msi_msg msg;
776 unsigned int irq;
777 int hwirq;
778
779 hwirq = rcar_msi_alloc(msi);
780 if (hwirq < 0)
781 return hwirq;
782
783 irq = irq_find_mapping(msi->domain, hwirq);
784 if (!irq) {
785 rcar_msi_free(msi, hwirq);
786 return -EINVAL;
787 }
788
789 irq_set_msi_desc(irq, desc);
790
791 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
792 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
793 msg.data = hwirq;
794
795 pci_write_msi_msg(irq, &msg);
796
797 return 0;
798 }
799
800 static int rcar_msi_setup_irqs(struct msi_controller *chip,
801 struct pci_dev *pdev, int nvec, int type)
802 {
803 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
804 struct rcar_msi *msi = to_rcar_msi(chip);
805 struct msi_desc *desc;
806 struct msi_msg msg;
807 unsigned int irq;
808 int hwirq;
809 int i;
810
811 /* MSI-X interrupts are not supported */
812 if (type == PCI_CAP_ID_MSIX)
813 return -EINVAL;
814
815 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
816 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
817
818 hwirq = rcar_msi_alloc_region(msi, nvec);
819 if (hwirq < 0)
820 return -ENOSPC;
821
822 irq = irq_find_mapping(msi->domain, hwirq);
823 if (!irq)
824 return -ENOSPC;
825
826 for (i = 0; i < nvec; i++) {
827 /*
828 * irq_create_mapping() called from rcar_pcie_probe() pre-
829 * allocates descs, so there is no need to allocate descs here.
830 * We can therefore assume that if irq_find_mapping() above
831 * returns non-zero, then the descs are also successfully
832 * allocated.
833 */
834 if (irq_set_msi_desc_off(irq, i, desc)) {
835 /* TODO: clear */
836 return -EINVAL;
837 }
838 }
839
840 desc->nvec_used = nvec;
841 desc->msi_attrib.multiple = order_base_2(nvec);
842
843 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
844 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
845 msg.data = hwirq;
846
847 pci_write_msi_msg(irq, &msg);
848
849 return 0;
850 }
851
852 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
853 {
854 struct rcar_msi *msi = to_rcar_msi(chip);
855 struct irq_data *d = irq_get_irq_data(irq);
856
857 rcar_msi_free(msi, d->hwirq);
858 }
859
860 static struct irq_chip rcar_msi_irq_chip = {
861 .name = "R-Car PCIe MSI",
862 .irq_enable = pci_msi_unmask_irq,
863 .irq_disable = pci_msi_mask_irq,
864 .irq_mask = pci_msi_mask_irq,
865 .irq_unmask = pci_msi_unmask_irq,
866 };
867
868 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
869 irq_hw_number_t hwirq)
870 {
871 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
872 irq_set_chip_data(irq, domain->host_data);
873
874 return 0;
875 }
876
877 static const struct irq_domain_ops msi_domain_ops = {
878 .map = rcar_msi_map,
879 };
880
881 static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie)
882 {
883 struct rcar_msi *msi = &pcie->msi;
884 int i, irq;
885
886 for (i = 0; i < INT_PCI_MSI_NR; i++) {
887 irq = irq_find_mapping(msi->domain, i);
888 if (irq > 0)
889 irq_dispose_mapping(irq);
890 }
891
892 irq_domain_remove(msi->domain);
893 }
894
895 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
896 {
897 struct device *dev = pcie->dev;
898 struct rcar_msi *msi = &pcie->msi;
899 phys_addr_t base;
900 int err, i;
901
902 mutex_init(&msi->lock);
903
904 msi->chip.dev = dev;
905 msi->chip.setup_irq = rcar_msi_setup_irq;
906 msi->chip.setup_irqs = rcar_msi_setup_irqs;
907 msi->chip.teardown_irq = rcar_msi_teardown_irq;
908
909 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
910 &msi_domain_ops, &msi->chip);
911 if (!msi->domain) {
912 dev_err(dev, "failed to create IRQ domain\n");
913 return -ENOMEM;
914 }
915
916 for (i = 0; i < INT_PCI_MSI_NR; i++)
917 irq_create_mapping(msi->domain, i);
918
919 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
920 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
921 IRQF_SHARED | IRQF_NO_THREAD,
922 rcar_msi_irq_chip.name, pcie);
923 if (err < 0) {
924 dev_err(dev, "failed to request IRQ: %d\n", err);
925 goto err;
926 }
927
928 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
929 IRQF_SHARED | IRQF_NO_THREAD,
930 rcar_msi_irq_chip.name, pcie);
931 if (err < 0) {
932 dev_err(dev, "failed to request IRQ: %d\n", err);
933 goto err;
934 }
935
936 /* setup MSI data target */
937 msi->pages = __get_free_pages(GFP_KERNEL, 0);
938 if (!msi->pages) {
939 err = -ENOMEM;
940 goto err;
941 }
942 base = virt_to_phys((void *)msi->pages);
943
944 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
945 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
946
947 /* enable all MSI interrupts */
948 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
949
950 return 0;
951
952 err:
953 rcar_pcie_unmap_msi(pcie);
954 return err;
955 }
956
957 static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
958 {
959 struct rcar_msi *msi = &pcie->msi;
960
961 /* Disable all MSI interrupts */
962 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
963
964 /* Disable address decoding of the MSI interrupt, MSIFE */
965 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
966
967 free_pages(msi->pages, 0);
968
969 rcar_pcie_unmap_msi(pcie);
970 }
971
972 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
973 {
974 struct device *dev = pcie->dev;
975 struct resource res;
976 int err, i;
977
978 pcie->phy = devm_phy_optional_get(dev, "pcie");
979 if (IS_ERR(pcie->phy))
980 return PTR_ERR(pcie->phy);
981
982 err = of_address_to_resource(dev->of_node, 0, &res);
983 if (err)
984 return err;
985
986 pcie->base = devm_ioremap_resource(dev, &res);
987 if (IS_ERR(pcie->base))
988 return PTR_ERR(pcie->base);
989
990 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
991 if (IS_ERR(pcie->bus_clk)) {
992 dev_err(dev, "cannot get pcie bus clock\n");
993 return PTR_ERR(pcie->bus_clk);
994 }
995
996 i = irq_of_parse_and_map(dev->of_node, 0);
997 if (!i) {
998 dev_err(dev, "cannot get platform resources for msi interrupt\n");
999 err = -ENOENT;
1000 goto err_irq1;
1001 }
1002 pcie->msi.irq1 = i;
1003
1004 i = irq_of_parse_and_map(dev->of_node, 1);
1005 if (!i) {
1006 dev_err(dev, "cannot get platform resources for msi interrupt\n");
1007 err = -ENOENT;
1008 goto err_irq2;
1009 }
1010 pcie->msi.irq2 = i;
1011
1012 return 0;
1013
1014 err_irq2:
1015 irq_dispose_mapping(pcie->msi.irq1);
1016 err_irq1:
1017 return err;
1018 }
1019
1020 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
1021 struct resource_entry *entry,
1022 int *index)
1023 {
1024 u64 restype = entry->res->flags;
1025 u64 cpu_addr = entry->res->start;
1026 u64 cpu_end = entry->res->end;
1027 u64 pci_addr = entry->res->start - entry->offset;
1028 u32 flags = LAM_64BIT | LAR_ENABLE;
1029 u64 mask;
1030 u64 size = resource_size(entry->res);
1031 int idx = *index;
1032
1033 if (restype & IORESOURCE_PREFETCH)
1034 flags |= LAM_PREFETCH;
1035
1036 while (cpu_addr < cpu_end) {
1037 if (idx >= MAX_NR_INBOUND_MAPS - 1) {
1038 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1039 return -EINVAL;
1040 }
1041 /*
1042 * If the size of the range is larger than the alignment of
1043 * the start address, we have to use multiple entries to
1044 * perform the mapping.
1045 */
1046 if (cpu_addr > 0) {
1047 unsigned long nr_zeros = __ffs64(cpu_addr);
1048 u64 alignment = 1ULL << nr_zeros;
1049
1050 size = min(size, alignment);
1051 }
1052 /* Hardware supports max 4GiB inbound region */
1053 size = min(size, 1ULL << 32);
1054
1055 mask = roundup_pow_of_two(size) - 1;
1056 mask &= ~0xf;
1057
1058 /*
1059 * Set up 64-bit inbound regions as the range parser doesn't
1060 * distinguish between 32 and 64-bit types.
1061 */
1062 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1063 PCIEPRAR(idx));
1064 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1065 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1066 PCIELAMR(idx));
1067
1068 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1069 PCIEPRAR(idx + 1));
1070 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1071 PCIELAR(idx + 1));
1072 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1073
1074 pci_addr += size;
1075 cpu_addr += size;
1076 idx += 2;
1077 }
1078 *index = idx;
1079
1080 return 0;
1081 }
1082
1083 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie)
1084 {
1085 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1086 struct resource_entry *entry;
1087 int index = 0, err = 0;
1088
1089 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
1090 err = rcar_pcie_inbound_ranges(pcie, entry, &index);
1091 if (err)
1092 break;
1093 }
1094
1095 return err;
1096 }
1097
1098 static const struct of_device_id rcar_pcie_of_match[] = {
1099 { .compatible = "renesas,pcie-r8a7779",
1100 .data = rcar_pcie_phy_init_h1 },
1101 { .compatible = "renesas,pcie-r8a7790",
1102 .data = rcar_pcie_phy_init_gen2 },
1103 { .compatible = "renesas,pcie-r8a7791",
1104 .data = rcar_pcie_phy_init_gen2 },
1105 { .compatible = "renesas,pcie-rcar-gen2",
1106 .data = rcar_pcie_phy_init_gen2 },
1107 { .compatible = "renesas,pcie-r8a7795",
1108 .data = rcar_pcie_phy_init_gen3 },
1109 { .compatible = "renesas,pcie-rcar-gen3",
1110 .data = rcar_pcie_phy_init_gen3 },
1111 {},
1112 };
1113
1114 static int rcar_pcie_probe(struct platform_device *pdev)
1115 {
1116 struct device *dev = &pdev->dev;
1117 struct rcar_pcie *pcie;
1118 u32 data;
1119 int err;
1120 int (*phy_init_fn)(struct rcar_pcie *);
1121 struct pci_host_bridge *bridge;
1122
1123 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1124 if (!bridge)
1125 return -ENOMEM;
1126
1127 pcie = pci_host_bridge_priv(bridge);
1128
1129 pcie->dev = dev;
1130 platform_set_drvdata(pdev, pcie);
1131
1132 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources,
1133 &bridge->dma_ranges, NULL);
1134 if (err)
1135 goto err_free_bridge;
1136
1137 pm_runtime_enable(pcie->dev);
1138 err = pm_runtime_get_sync(pcie->dev);
1139 if (err < 0) {
1140 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1141 goto err_pm_disable;
1142 }
1143
1144 err = rcar_pcie_get_resources(pcie);
1145 if (err < 0) {
1146 dev_err(dev, "failed to request resources: %d\n", err);
1147 goto err_pm_put;
1148 }
1149
1150 err = clk_prepare_enable(pcie->bus_clk);
1151 if (err) {
1152 dev_err(dev, "failed to enable bus clock: %d\n", err);
1153 goto err_unmap_msi_irqs;
1154 }
1155
1156 err = rcar_pcie_parse_map_dma_ranges(pcie);
1157 if (err)
1158 goto err_clk_disable;
1159
1160 phy_init_fn = of_device_get_match_data(dev);
1161 err = phy_init_fn(pcie);
1162 if (err) {
1163 dev_err(dev, "failed to init PCIe PHY\n");
1164 goto err_clk_disable;
1165 }
1166
1167 /* Failure to get a link might just be that no cards are inserted */
1168 if (rcar_pcie_hw_init(pcie)) {
1169 dev_info(dev, "PCIe link down\n");
1170 err = -ENODEV;
1171 goto err_phy_shutdown;
1172 }
1173
1174 data = rcar_pci_read_reg(pcie, MACSR);
1175 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1176
1177 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1178 err = rcar_pcie_enable_msi(pcie);
1179 if (err < 0) {
1180 dev_err(dev,
1181 "failed to enable MSI support: %d\n",
1182 err);
1183 goto err_phy_shutdown;
1184 }
1185 }
1186
1187 err = rcar_pcie_enable(pcie);
1188 if (err)
1189 goto err_msi_teardown;
1190
1191 return 0;
1192
1193 err_msi_teardown:
1194 if (IS_ENABLED(CONFIG_PCI_MSI))
1195 rcar_pcie_teardown_msi(pcie);
1196
1197 err_phy_shutdown:
1198 if (pcie->phy) {
1199 phy_power_off(pcie->phy);
1200 phy_exit(pcie->phy);
1201 }
1202
1203 err_clk_disable:
1204 clk_disable_unprepare(pcie->bus_clk);
1205
1206 err_unmap_msi_irqs:
1207 irq_dispose_mapping(pcie->msi.irq2);
1208 irq_dispose_mapping(pcie->msi.irq1);
1209
1210 err_pm_put:
1211 pm_runtime_put(dev);
1212
1213 err_pm_disable:
1214 pm_runtime_disable(dev);
1215 pci_free_resource_list(&pcie->resources);
1216
1217 err_free_bridge:
1218 pci_free_host_bridge(bridge);
1219
1220 return err;
1221 }
1222
1223 static int rcar_pcie_resume_noirq(struct device *dev)
1224 {
1225 struct rcar_pcie *pcie = dev_get_drvdata(dev);
1226
1227 if (rcar_pci_read_reg(pcie, PMSR) &&
1228 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1229 return 0;
1230
1231 /* Re-establish the PCIe link */
1232 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1233 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1234 return rcar_pcie_wait_for_dl(pcie);
1235 }
1236
1237 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1238 .resume_noirq = rcar_pcie_resume_noirq,
1239 };
1240
1241 static struct platform_driver rcar_pcie_driver = {
1242 .driver = {
1243 .name = "rcar-pcie",
1244 .of_match_table = rcar_pcie_of_match,
1245 .pm = &rcar_pcie_pm_ops,
1246 .suppress_bind_attrs = true,
1247 },
1248 .probe = rcar_pcie_probe,
1249 };
1250 builtin_platform_driver(rcar_pcie_driver);
Linux with added FPC-III support