drivers/pci/pcie/dpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCI Express Downstream Port Containment services driver
   4  * Author: Keith Busch <keith.busch@intel.com>
   5  *
   6  * Copyright (C) 2016 Intel Corp.
   7  */
   8
   9 #define dev_fmt(fmt) "DPC: " fmt
  10
  11 #include <linux/aer.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16
  17 #include "portdrv.h"
  18 #include "../pci.h"
  19
  20 static const char * const rp_pio_error_string[] = {
  21         "Configuration Request received UR Completion",  /* Bit Position 0  */
  22         "Configuration Request received CA Completion",  /* Bit Position 1  */
  23         "Configuration Request Completion Timeout",      /* Bit Position 2  */
  24         NULL,
  25         NULL,
  26         NULL,
  27         NULL,
  28         NULL,
  29         "I/O Request received UR Completion",            /* Bit Position 8  */
  30         "I/O Request received CA Completion",            /* Bit Position 9  */
  31         "I/O Request Completion Timeout",                /* Bit Position 10 */
  32         NULL,
  33         NULL,
  34         NULL,
  35         NULL,
  36         NULL,
  37         "Memory Request received UR Completion",         /* Bit Position 16 */
  38         "Memory Request received CA Completion",         /* Bit Position 17 */
  39         "Memory Request Completion Timeout",             /* Bit Position 18 */
  40 };
  41
  42 void pci_save_dpc_state(struct pci_dev *dev)
  43 {
  44         struct pci_cap_saved_state *save_state;
  45         u16 *cap;
  46
  47         if (!pci_is_pcie(dev))
  48                 return;
  49
  50         save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
  51         if (!save_state)
  52                 return;
  53
  54         cap = (u16 *)&save_state->cap.data[0];
  55         pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
  56 }
  57
  58 void pci_restore_dpc_state(struct pci_dev *dev)
  59 {
  60         struct pci_cap_saved_state *save_state;
  61         u16 *cap;
  62
  63         if (!pci_is_pcie(dev))
  64                 return;
  65
  66         save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
  67         if (!save_state)
  68                 return;
  69
  70         cap = (u16 *)&save_state->cap.data[0];
  71         pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
  72 }
  73
  74 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
  75 {
  76         unsigned long timeout = jiffies + HZ;
  77         u16 cap = pdev->dpc_cap, status;
  78
  79         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  80         while (status & PCI_EXP_DPC_RP_BUSY &&
  81                                         !time_after(jiffies, timeout)) {
  82                 msleep(10);
  83                 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
  84         }
  85         if (status & PCI_EXP_DPC_RP_BUSY) {
  86                 pci_warn(pdev, "root port still busy\n");
  87                 return -EBUSY;
  88         }
  89         return 0;
  90 }
  91
  92 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
  93 {
  94         u16 cap;
  95
  96         /*
  97          * DPC disables the Link automatically in hardware, so it has
  98          * already been reset by the time we get here.
  99          */
 100         cap = pdev->dpc_cap;
 101
 102         /*
 103          * Wait until the Link is inactive, then clear DPC Trigger Status
 104          * to allow the Port to leave DPC.
 105          */
 106         pcie_wait_for_link(pdev, false);
 107
 108         if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
 109                 return PCI_ERS_RESULT_DISCONNECT;
 110
 111         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 112                               PCI_EXP_DPC_STATUS_TRIGGER);
 113
 114         if (!pcie_wait_for_link(pdev, true))
 115                 return PCI_ERS_RESULT_DISCONNECT;
 116
 117         return PCI_ERS_RESULT_RECOVERED;
 118 }
 119
 120 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
 121 {
 122         u16 cap = pdev->dpc_cap, dpc_status, first_error;
 123         u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
 124         int i;
 125
 126         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
 127         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
 128         pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
 129                 status, mask);
 130
 131         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
 132         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
 133         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
 134         pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
 135                 sev, syserr, exc);
 136
 137         /* Get First Error Pointer */
 138         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
 139         first_error = (dpc_status & 0x1f00) >> 8;
 140
 141         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
 142                 if ((status & ~mask) & (1 << i))
 143                         pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
 144                                 first_error == i ? " (First)" : "");
 145         }
 146
 147         if (pdev->dpc_rp_log_size < 4)
 148                 goto clear_status;
 149         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
 150                               &dw0);
 151         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
 152                               &dw1);
 153         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
 154                               &dw2);
 155         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
 156                               &dw3);
 157         pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
 158                 dw0, dw1, dw2, dw3);
 159
 160         if (pdev->dpc_rp_log_size < 5)
 161                 goto clear_status;
 162         pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
 163         pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
 164
 165         for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
 166                 pci_read_config_dword(pdev,
 167                         cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
 168                 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
 169         }
 170  clear_status:
 171         pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
 172 }
 173
 174 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
 175                                           struct aer_err_info *info)
 176 {
 177         int pos = dev->aer_cap;
 178         u32 status, mask, sev;
 179
 180         pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
 181         pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
 182         status &= ~mask;
 183         if (!status)
 184                 return 0;
 185
 186         pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
 187         status &= sev;
 188         if (status)
 189                 info->severity = AER_FATAL;
 190         else
 191                 info->severity = AER_NONFATAL;
 192
 193         return 1;
 194 }
 195
 196 void dpc_process_error(struct pci_dev *pdev)
 197 {
 198         u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
 199         struct aer_err_info info;
 200
 201         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 202         pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
 203
 204         pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
 205                  status, source);
 206
 207         reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
 208         ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
 209         pci_warn(pdev, "%s detected\n",
 210                  (reason == 0) ? "unmasked uncorrectable error" :
 211                  (reason == 1) ? "ERR_NONFATAL" :
 212                  (reason == 2) ? "ERR_FATAL" :
 213                  (ext_reason == 0) ? "RP PIO error" :
 214                  (ext_reason == 1) ? "software trigger" :
 215                                      "reserved error");
 216
 217         /* show RP PIO error detail information */
 218         if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
 219                 dpc_process_rp_pio_error(pdev);
 220         else if (reason == 0 &&
 221                  dpc_get_aer_uncorrect_severity(pdev, &info) &&
 222                  aer_get_device_error_info(pdev, &info)) {
 223                 aer_print_error(pdev, &info);
 224                 pci_aer_clear_nonfatal_status(pdev);
 225                 pci_aer_clear_fatal_status(pdev);
 226         }
 227 }
 228
 229 static irqreturn_t dpc_handler(int irq, void *context)
 230 {
 231         struct pci_dev *pdev = context;
 232
 233         dpc_process_error(pdev);
 234
 235         /* We configure DPC so it only triggers on ERR_FATAL */
 236         pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
 237
 238         return IRQ_HANDLED;
 239 }
 240
 241 static irqreturn_t dpc_irq(int irq, void *context)
 242 {
 243         struct pci_dev *pdev = context;
 244         u16 cap = pdev->dpc_cap, status;
 245
 246         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 247
 248         if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0))
 249                 return IRQ_NONE;
 250
 251         pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
 252                               PCI_EXP_DPC_STATUS_INTERRUPT);
 253         if (status & PCI_EXP_DPC_STATUS_TRIGGER)
 254                 return IRQ_WAKE_THREAD;
 255         return IRQ_HANDLED;
 256 }
 257
 258 void pci_dpc_init(struct pci_dev *pdev)
 259 {
 260         u16 cap;
 261
 262         pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
 263         if (!pdev->dpc_cap)
 264                 return;
 265
 266         pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
 267         if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
 268                 return;
 269
 270         pdev->dpc_rp_extensions = true;
 271         pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
 272         if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
 273                 pci_err(pdev, "RP PIO log size %u is invalid\n",
 274                         pdev->dpc_rp_log_size);
 275                 pdev->dpc_rp_log_size = 0;
 276         }
 277 }
 278
 279 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
 280 static int dpc_probe(struct pcie_device *dev)
 281 {
 282         struct pci_dev *pdev = dev->port;
 283         struct device *device = &dev->device;
 284         int status;
 285         u16 ctl, cap;
 286
 287         if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native)
 288                 return -ENOTSUPP;
 289
 290         status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
 291                                            dpc_handler, IRQF_SHARED,
 292                                            "pcie-dpc", pdev);
 293         if (status) {
 294                 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
 295                          status);
 296                 return status;
 297         }
 298
 299         pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
 300         pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
 301
 302         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
 303         pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
 304
 305         pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 306                  cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
 307                  FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
 308                  FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
 309                  FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
 310
 311         pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
 312         return status;
 313 }
 314
 315 static void dpc_remove(struct pcie_device *dev)
 316 {
 317         struct pci_dev *pdev = dev->port;
 318         u16 ctl;
 319
 320         pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
 321         ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
 322         pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
 323 }
 324
 325 static struct pcie_port_service_driver dpcdriver = {
 326         .name           = "dpc",
 327         .port_type      = PCIE_ANY_PORT,
 328         .service        = PCIE_PORT_SERVICE_DPC,
 329         .probe          = dpc_probe,
 330         .remove         = dpc_remove,
 331 };
 332
 333 int __init pcie_dpc_init(void)
 334 {
 335         return pcie_port_service_register(&dpcdriver);
 336 }