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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / pci / setup-bus.c
blobbbcef1a053ab112e678a9f7098eefa32f34633e6
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
15 */
16
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
26 #include "pci.h"
27
28 unsigned int pci_flags;
29
30 struct pci_dev_resource {
31 struct list_head list;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39 };
40
41 static void free_list(struct list_head *head)
42 {
43 struct pci_dev_resource *dev_res, *tmp;
44
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
47 kfree(dev_res);
48 }
49 }
50
51 /**
52 * add_to_list() - Add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: Device to which the resource belongs
55 * @res: Resource to be tracked
56 * @add_size: Additional size to be optionally added to the resource
57 */
58 static int add_to_list(struct list_head *head, struct pci_dev *dev,
59 struct resource *res, resource_size_t add_size,
60 resource_size_t min_align)
61 {
62 struct pci_dev_resource *tmp;
63
64 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
65 if (!tmp)
66 return -ENOMEM;
67
68 tmp->res = res;
69 tmp->dev = dev;
70 tmp->start = res->start;
71 tmp->end = res->end;
72 tmp->flags = res->flags;
73 tmp->add_size = add_size;
74 tmp->min_align = min_align;
75
76 list_add(&tmp->list, head);
77
78 return 0;
79 }
80
81 static void remove_from_list(struct list_head *head, struct resource *res)
82 {
83 struct pci_dev_resource *dev_res, *tmp;
84
85 list_for_each_entry_safe(dev_res, tmp, head, list) {
86 if (dev_res->res == res) {
87 list_del(&dev_res->list);
88 kfree(dev_res);
89 break;
90 }
91 }
92 }
93
94 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
95 struct resource *res)
96 {
97 struct pci_dev_resource *dev_res;
98
99 list_for_each_entry(dev_res, head, list) {
100 if (dev_res->res == res)
101 return dev_res;
102 }
103
104 return NULL;
105 }
106
107 static resource_size_t get_res_add_size(struct list_head *head,
108 struct resource *res)
109 {
110 struct pci_dev_resource *dev_res;
111
112 dev_res = res_to_dev_res(head, res);
113 return dev_res ? dev_res->add_size : 0;
114 }
115
116 static resource_size_t get_res_add_align(struct list_head *head,
117 struct resource *res)
118 {
119 struct pci_dev_resource *dev_res;
120
121 dev_res = res_to_dev_res(head, res);
122 return dev_res ? dev_res->min_align : 0;
123 }
124
125
126 /* Sort resources by alignment */
127 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
128 {
129 int i;
130
131 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
132 struct resource *r;
133 struct pci_dev_resource *dev_res, *tmp;
134 resource_size_t r_align;
135 struct list_head *n;
136
137 r = &dev->resource[i];
138
139 if (r->flags & IORESOURCE_PCI_FIXED)
140 continue;
141
142 if (!(r->flags) || r->parent)
143 continue;
144
145 r_align = pci_resource_alignment(dev, r);
146 if (!r_align) {
147 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
148 i, r);
149 continue;
150 }
151
152 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
153 if (!tmp)
154 panic("pdev_sort_resources(): kmalloc() failed!\n");
155 tmp->res = r;
156 tmp->dev = dev;
157
158 /* Fallback is smallest one or list is empty */
159 n = head;
160 list_for_each_entry(dev_res, head, list) {
161 resource_size_t align;
162
163 align = pci_resource_alignment(dev_res->dev,
164 dev_res->res);
165
166 if (r_align > align) {
167 n = &dev_res->list;
168 break;
169 }
170 }
171 /* Insert it just before n */
172 list_add_tail(&tmp->list, n);
173 }
174 }
175
176 static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
177 {
178 u16 class = dev->class >> 8;
179
180 /* Don't touch classless devices or host bridges or IOAPICs */
181 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
182 return;
183
184 /* Don't touch IOAPIC devices already enabled by firmware */
185 if (class == PCI_CLASS_SYSTEM_PIC) {
186 u16 command;
187 pci_read_config_word(dev, PCI_COMMAND, &command);
188 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
189 return;
190 }
191
192 pdev_sort_resources(dev, head);
193 }
194
195 static inline void reset_resource(struct resource *res)
196 {
197 res->start = 0;
198 res->end = 0;
199 res->flags = 0;
200 }
201
202 /**
203 * reassign_resources_sorted() - Satisfy any additional resource requests
204 *
205 * @realloc_head: Head of the list tracking requests requiring
206 * additional resources
207 * @head: Head of the list tracking requests with allocated
208 * resources
209 *
210 * Walk through each element of the realloc_head and try to procure additional
211 * resources for the element, provided the element is in the head list.
212 */
213 static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
215 {
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size, align;
220 int idx;
221
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
224
225 res = add_res->res;
226 /* Skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* Skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
236 }
237 if (!found_match) /* Just skip */
238 continue;
239
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 align = add_res->min_align;
243 if (!resource_size(res)) {
244 res->start = align;
245 res->end = res->start + add_size - 1;
246 if (pci_assign_resource(add_res->dev, idx))
247 reset_resource(res);
248 } else {
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
252 add_size, align))
253 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
254 (unsigned long long) add_size, idx,
255 res);
256 }
257 out:
258 list_del(&add_res->list);
259 kfree(add_res);
260 }
261 }
262
263 /**
264 * assign_requested_resources_sorted() - Satisfy resource requests
265 *
266 * @head: Head of the list tracking requests for resources
267 * @fail_head: Head of the list tracking requests that could not be
268 * allocated
269 *
270 * Satisfy resource requests of each element in the list. Add requests that
271 * could not be satisfied to the failed_list.
272 */
273 static void assign_requested_resources_sorted(struct list_head *head,
274 struct list_head *fail_head)
275 {
276 struct resource *res;
277 struct pci_dev_resource *dev_res;
278 int idx;
279
280 list_for_each_entry(dev_res, head, list) {
281 res = dev_res->res;
282 idx = res - &dev_res->dev->resource[0];
283 if (resource_size(res) &&
284 pci_assign_resource(dev_res->dev, idx)) {
285 if (fail_head) {
286 /*
287 * If the failed resource is a ROM BAR and
288 * it will be enabled later, don't add it
289 * to the list.
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* don't care */,
296 0 /* don't care */);
297 }
298 reset_resource(res);
299 }
300 }
301 }
302
303 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
304 {
305 struct pci_dev_resource *fail_res;
306 unsigned long mask = 0;
307
308 /* Check failed type */
309 list_for_each_entry(fail_res, fail_head, list)
310 mask |= fail_res->flags;
311
312 /*
313 * One pref failed resource will set IORESOURCE_MEM, as we can
314 * allocate pref in non-pref range. Will release all assigned
315 * non-pref sibling resources according to that bit.
316 */
317 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
318 }
319
320 static bool pci_need_to_release(unsigned long mask, struct resource *res)
321 {
322 if (res->flags & IORESOURCE_IO)
323 return !!(mask & IORESOURCE_IO);
324
325 /* Check pref at first */
326 if (res->flags & IORESOURCE_PREFETCH) {
327 if (mask & IORESOURCE_PREFETCH)
328 return true;
329 /* Count pref if its parent is non-pref */
330 else if ((mask & IORESOURCE_MEM) &&
331 !(res->parent->flags & IORESOURCE_PREFETCH))
332 return true;
333 else
334 return false;
335 }
336
337 if (res->flags & IORESOURCE_MEM)
338 return !!(mask & IORESOURCE_MEM);
339
340 return false; /* Should not get here */
341 }
342
343 static void __assign_resources_sorted(struct list_head *head,
344 struct list_head *realloc_head,
345 struct list_head *fail_head)
346 {
347 /*
348 * Should not assign requested resources at first. They could be
349 * adjacent, so later reassign can not reallocate them one by one in
350 * parent resource window.
351 *
352 * Try to assign requested + add_size at beginning. If could do that,
353 * could get out early. If could not do that, we still try to assign
354 * requested at first, then try to reassign add_size for some resources.
355 *
356 * Separate three resource type checking if we need to release
357 * assigned resource after requested + add_size try.
358 *
359 * 1. If IO port assignment fails, will release assigned IO
360 * port.
361 * 2. If pref MMIO assignment fails, release assigned pref
362 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
363 * and non-pref MMIO assignment fails, will release that
364 * assigned pref MMIO.
365 * 3. If non-pref MMIO assignment fails or pref MMIO
366 * assignment fails, will release assigned non-pref MMIO.
367 */
368 LIST_HEAD(save_head);
369 LIST_HEAD(local_fail_head);
370 struct pci_dev_resource *save_res;
371 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
372 unsigned long fail_type;
373 resource_size_t add_align, align;
374
375 /* Check if optional add_size is there */
376 if (!realloc_head || list_empty(realloc_head))
377 goto requested_and_reassign;
378
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res, head, list) {
381 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
382 free_list(&save_head);
383 goto requested_and_reassign;
384 }
385 }
386
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
389 dev_res->res->end += get_res_add_size(realloc_head,
390 dev_res->res);
391
392 /*
393 * There are two kinds of additional resources in the list:
394 * 1. bridge resource -- IORESOURCE_STARTALIGN
395 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
396 * Here just fix the additional alignment for bridge
397 */
398 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
399 continue;
400
401 add_align = get_res_add_align(realloc_head, dev_res->res);
402
403 /*
404 * The "head" list is sorted by alignment so resources with
405 * bigger alignment will be assigned first. After we
406 * change the alignment of a dev_res in "head" list, we
407 * need to reorder the list by alignment to make it
408 * consistent.
409 */
410 if (add_align > dev_res->res->start) {
411 resource_size_t r_size = resource_size(dev_res->res);
412
413 dev_res->res->start = add_align;
414 dev_res->res->end = add_align + r_size - 1;
415
416 list_for_each_entry(dev_res2, head, list) {
417 align = pci_resource_alignment(dev_res2->dev,
418 dev_res2->res);
419 if (add_align > align) {
420 list_move_tail(&dev_res->list,
421 &dev_res2->list);
422 break;
423 }
424 }
425 }
426
427 }
428
429 /* Try updated head list with add_size added */
430 assign_requested_resources_sorted(head, &local_fail_head);
431
432 /* All assigned with add_size? */
433 if (list_empty(&local_fail_head)) {
434 /* Remove head list from realloc_head list */
435 list_for_each_entry(dev_res, head, list)
436 remove_from_list(realloc_head, dev_res->res);
437 free_list(&save_head);
438 free_list(head);
439 return;
440 }
441
442 /* Check failed type */
443 fail_type = pci_fail_res_type_mask(&local_fail_head);
444 /* Remove not need to be released assigned res from head list etc */
445 list_for_each_entry_safe(dev_res, tmp_res, head, list)
446 if (dev_res->res->parent &&
447 !pci_need_to_release(fail_type, dev_res->res)) {
448 /* Remove it from realloc_head list */
449 remove_from_list(realloc_head, dev_res->res);
450 remove_from_list(&save_head, dev_res->res);
451 list_del(&dev_res->list);
452 kfree(dev_res);
453 }
454
455 free_list(&local_fail_head);
456 /* Release assigned resource */
457 list_for_each_entry(dev_res, head, list)
458 if (dev_res->res->parent)
459 release_resource(dev_res->res);
460 /* Restore start/end/flags from saved list */
461 list_for_each_entry(save_res, &save_head, list) {
462 struct resource *res = save_res->res;
463
464 res->start = save_res->start;
465 res->end = save_res->end;
466 res->flags = save_res->flags;
467 }
468 free_list(&save_head);
469
470 requested_and_reassign:
471 /* Satisfy the must-have resource requests */
472 assign_requested_resources_sorted(head, fail_head);
473
474 /* Try to satisfy any additional optional resource requests */
475 if (realloc_head)
476 reassign_resources_sorted(realloc_head, head);
477 free_list(head);
478 }
479
480 static void pdev_assign_resources_sorted(struct pci_dev *dev,
481 struct list_head *add_head,
482 struct list_head *fail_head)
483 {
484 LIST_HEAD(head);
485
486 __dev_sort_resources(dev, &head);
487 __assign_resources_sorted(&head, add_head, fail_head);
488
489 }
490
491 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
492 struct list_head *realloc_head,
493 struct list_head *fail_head)
494 {
495 struct pci_dev *dev;
496 LIST_HEAD(head);
497
498 list_for_each_entry(dev, &bus->devices, bus_list)
499 __dev_sort_resources(dev, &head);
500
501 __assign_resources_sorted(&head, realloc_head, fail_head);
502 }
503
504 void pci_setup_cardbus(struct pci_bus *bus)
505 {
506 struct pci_dev *bridge = bus->self;
507 struct resource *res;
508 struct pci_bus_region region;
509
510 pci_info(bridge, "CardBus bridge to %pR\n",
511 &bus->busn_res);
512
513 res = bus->resource[0];
514 pcibios_resource_to_bus(bridge->bus, &region, res);
515 if (res->flags & IORESOURCE_IO) {
516 /*
517 * The IO resource is allocated a range twice as large as it
518 * would normally need. This allows us to set both IO regs.
519 */
520 pci_info(bridge, " bridge window %pR\n", res);
521 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
522 region.start);
523 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
524 region.end);
525 }
526
527 res = bus->resource[1];
528 pcibios_resource_to_bus(bridge->bus, &region, res);
529 if (res->flags & IORESOURCE_IO) {
530 pci_info(bridge, " bridge window %pR\n", res);
531 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
532 region.start);
533 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
534 region.end);
535 }
536
537 res = bus->resource[2];
538 pcibios_resource_to_bus(bridge->bus, &region, res);
539 if (res->flags & IORESOURCE_MEM) {
540 pci_info(bridge, " bridge window %pR\n", res);
541 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
542 region.start);
543 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
544 region.end);
545 }
546
547 res = bus->resource[3];
548 pcibios_resource_to_bus(bridge->bus, &region, res);
549 if (res->flags & IORESOURCE_MEM) {
550 pci_info(bridge, " bridge window %pR\n", res);
551 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
552 region.start);
553 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
554 region.end);
555 }
556 }
557 EXPORT_SYMBOL(pci_setup_cardbus);
558
559 /*
560 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
561 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
562 * are no I/O ports or memory behind the bridge, the corresponding range
563 * must be turned off by writing base value greater than limit to the
564 * bridge's base/limit registers.
565 *
566 * Note: care must be taken when updating I/O base/limit registers of
567 * bridges which support 32-bit I/O. This update requires two config space
568 * writes, so it's quite possible that an I/O window of the bridge will
569 * have some undesirable address (e.g. 0) after the first write. Ditto
570 * 64-bit prefetchable MMIO.
571 */
572 static void pci_setup_bridge_io(struct pci_dev *bridge)
573 {
574 struct resource *res;
575 struct pci_bus_region region;
576 unsigned long io_mask;
577 u8 io_base_lo, io_limit_lo;
578 u16 l;
579 u32 io_upper16;
580
581 io_mask = PCI_IO_RANGE_MASK;
582 if (bridge->io_window_1k)
583 io_mask = PCI_IO_1K_RANGE_MASK;
584
585 /* Set up the top and bottom of the PCI I/O segment for this bus */
586 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
587 pcibios_resource_to_bus(bridge->bus, &region, res);
588 if (res->flags & IORESOURCE_IO) {
589 pci_read_config_word(bridge, PCI_IO_BASE, &l);
590 io_base_lo = (region.start >> 8) & io_mask;
591 io_limit_lo = (region.end >> 8) & io_mask;
592 l = ((u16) io_limit_lo << 8) | io_base_lo;
593 /* Set up upper 16 bits of I/O base/limit */
594 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
595 pci_info(bridge, " bridge window %pR\n", res);
596 } else {
597 /* Clear upper 16 bits of I/O base/limit */
598 io_upper16 = 0;
599 l = 0x00f0;
600 }
601 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
602 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
603 /* Update lower 16 bits of I/O base/limit */
604 pci_write_config_word(bridge, PCI_IO_BASE, l);
605 /* Update upper 16 bits of I/O base/limit */
606 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
607 }
608
609 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
610 {
611 struct resource *res;
612 struct pci_bus_region region;
613 u32 l;
614
615 /* Set up the top and bottom of the PCI Memory segment for this bus */
616 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
617 pcibios_resource_to_bus(bridge->bus, &region, res);
618 if (res->flags & IORESOURCE_MEM) {
619 l = (region.start >> 16) & 0xfff0;
620 l |= region.end & 0xfff00000;
621 pci_info(bridge, " bridge window %pR\n", res);
622 } else {
623 l = 0x0000fff0;
624 }
625 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
626 }
627
628 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
629 {
630 struct resource *res;
631 struct pci_bus_region region;
632 u32 l, bu, lu;
633
634 /*
635 * Clear out the upper 32 bits of PREF limit. If
636 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
637 * PREF range, which is ok.
638 */
639 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
640
641 /* Set up PREF base/limit */
642 bu = lu = 0;
643 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
644 pcibios_resource_to_bus(bridge->bus, &region, res);
645 if (res->flags & IORESOURCE_PREFETCH) {
646 l = (region.start >> 16) & 0xfff0;
647 l |= region.end & 0xfff00000;
648 if (res->flags & IORESOURCE_MEM_64) {
649 bu = upper_32_bits(region.start);
650 lu = upper_32_bits(region.end);
651 }
652 pci_info(bridge, " bridge window %pR\n", res);
653 } else {
654 l = 0x0000fff0;
655 }
656 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
657
658 /* Set the upper 32 bits of PREF base & limit */
659 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
660 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
661 }
662
663 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
664 {
665 struct pci_dev *bridge = bus->self;
666
667 pci_info(bridge, "PCI bridge to %pR\n",
668 &bus->busn_res);
669
670 if (type & IORESOURCE_IO)
671 pci_setup_bridge_io(bridge);
672
673 if (type & IORESOURCE_MEM)
674 pci_setup_bridge_mmio(bridge);
675
676 if (type & IORESOURCE_PREFETCH)
677 pci_setup_bridge_mmio_pref(bridge);
678
679 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
680 }
681
682 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
683 {
684 }
685
686 void pci_setup_bridge(struct pci_bus *bus)
687 {
688 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
689 IORESOURCE_PREFETCH;
690
691 pcibios_setup_bridge(bus, type);
692 __pci_setup_bridge(bus, type);
693 }
694
695
696 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
697 {
698 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
699 return 0;
700
701 if (pci_claim_resource(bridge, i) == 0)
702 return 0; /* Claimed the window */
703
704 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
705 return 0;
706
707 if (!pci_bus_clip_resource(bridge, i))
708 return -EINVAL; /* Clipping didn't change anything */
709
710 switch (i - PCI_BRIDGE_RESOURCES) {
711 case 0:
712 pci_setup_bridge_io(bridge);
713 break;
714 case 1:
715 pci_setup_bridge_mmio(bridge);
716 break;
717 case 2:
718 pci_setup_bridge_mmio_pref(bridge);
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 if (pci_claim_resource(bridge, i) == 0)
725 return 0; /* Claimed a smaller window */
726
727 return -EINVAL;
728 }
729
730 /*
731 * Check whether the bridge supports optional I/O and prefetchable memory
732 * ranges. If not, the respective base/limit registers must be read-only
733 * and read as 0.
734 */
735 static void pci_bridge_check_ranges(struct pci_bus *bus)
736 {
737 struct pci_dev *bridge = bus->self;
738 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
739
740 b_res[1].flags |= IORESOURCE_MEM;
741
742 if (bridge->io_window)
743 b_res[0].flags |= IORESOURCE_IO;
744
745 if (bridge->pref_window) {
746 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
747 if (bridge->pref_64_window) {
748 b_res[2].flags |= IORESOURCE_MEM_64;
749 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
750 }
751 }
752 }
753
754 /*
755 * Helper function for sizing routines. Assigned resources have non-NULL
756 * parent resource.
757 *
758 * Return first unassigned resource of the correct type. If there is none,
759 * return first assigned resource of the correct type. If none of the
760 * above, return NULL.
761 *
762 * Returning an assigned resource of the correct type allows the caller to
763 * distinguish between already assigned and no resource of the correct type.
764 */
765 static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
766 unsigned long type_mask,
767 unsigned long type)
768 {
769 struct resource *r, *r_assigned = NULL;
770 int i;
771
772 pci_bus_for_each_resource(bus, r, i) {
773 if (r == &ioport_resource || r == &iomem_resource)
774 continue;
775 if (r && (r->flags & type_mask) == type && !r->parent)
776 return r;
777 if (r && (r->flags & type_mask) == type && !r_assigned)
778 r_assigned = r;
779 }
780 return r_assigned;
781 }
782
783 static resource_size_t calculate_iosize(resource_size_t size,
784 resource_size_t min_size,
785 resource_size_t size1,
786 resource_size_t add_size,
787 resource_size_t children_add_size,
788 resource_size_t old_size,
789 resource_size_t align)
790 {
791 if (size < min_size)
792 size = min_size;
793 if (old_size == 1)
794 old_size = 0;
795 /*
796 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
797 * struct pci_bus.
798 */
799 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
800 size = (size & 0xff) + ((size & ~0xffUL) << 2);
801 #endif
802 size = size + size1;
803 if (size < old_size)
804 size = old_size;
805
806 size = ALIGN(max(size, add_size) + children_add_size, align);
807 return size;
808 }
809
810 static resource_size_t calculate_memsize(resource_size_t size,
811 resource_size_t min_size,
812 resource_size_t add_size,
813 resource_size_t children_add_size,
814 resource_size_t old_size,
815 resource_size_t align)
816 {
817 if (size < min_size)
818 size = min_size;
819 if (old_size == 1)
820 old_size = 0;
821 if (size < old_size)
822 size = old_size;
823
824 size = ALIGN(max(size, add_size) + children_add_size, align);
825 return size;
826 }
827
828 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
829 unsigned long type)
830 {
831 return 1;
832 }
833
834 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
835 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
836 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
837
838 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
839 {
840 resource_size_t align = 1, arch_align;
841
842 if (type & IORESOURCE_MEM)
843 align = PCI_P2P_DEFAULT_MEM_ALIGN;
844 else if (type & IORESOURCE_IO) {
845 /*
846 * Per spec, I/O windows are 4K-aligned, but some bridges have
847 * an extension to support 1K alignment.
848 */
849 if (bus->self && bus->self->io_window_1k)
850 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
851 else
852 align = PCI_P2P_DEFAULT_IO_ALIGN;
853 }
854
855 arch_align = pcibios_window_alignment(bus, type);
856 return max(align, arch_align);
857 }
858
859 /**
860 * pbus_size_io() - Size the I/O window of a given bus
861 *
862 * @bus: The bus
863 * @min_size: The minimum I/O window that must be allocated
864 * @add_size: Additional optional I/O window
865 * @realloc_head: Track the additional I/O window on this list
866 *
867 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
868 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
869 * devices are limited to 256 bytes. We must be careful with the ISA
870 * aliasing though.
871 */
872 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
873 resource_size_t add_size,
874 struct list_head *realloc_head)
875 {
876 struct pci_dev *dev;
877 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
878 IORESOURCE_IO);
879 resource_size_t size = 0, size0 = 0, size1 = 0;
880 resource_size_t children_add_size = 0;
881 resource_size_t min_align, align;
882
883 if (!b_res)
884 return;
885
886 /* If resource is already assigned, nothing more to do */
887 if (b_res->parent)
888 return;
889
890 min_align = window_alignment(bus, IORESOURCE_IO);
891 list_for_each_entry(dev, &bus->devices, bus_list) {
892 int i;
893
894 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
895 struct resource *r = &dev->resource[i];
896 unsigned long r_size;
897
898 if (r->parent || !(r->flags & IORESOURCE_IO))
899 continue;
900 r_size = resource_size(r);
901
902 if (r_size < 0x400)
903 /* Might be re-aligned for ISA */
904 size += r_size;
905 else
906 size1 += r_size;
907
908 align = pci_resource_alignment(dev, r);
909 if (align > min_align)
910 min_align = align;
911
912 if (realloc_head)
913 children_add_size += get_res_add_size(realloc_head, r);
914 }
915 }
916
917 size0 = calculate_iosize(size, min_size, size1, 0, 0,
918 resource_size(b_res), min_align);
919 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
920 calculate_iosize(size, min_size, size1, add_size, children_add_size,
921 resource_size(b_res), min_align);
922 if (!size0 && !size1) {
923 if (bus->self && (b_res->start || b_res->end))
924 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
925 b_res, &bus->busn_res);
926 b_res->flags = 0;
927 return;
928 }
929
930 b_res->start = min_align;
931 b_res->end = b_res->start + size0 - 1;
932 b_res->flags |= IORESOURCE_STARTALIGN;
933 if (bus->self && size1 > size0 && realloc_head) {
934 add_to_list(realloc_head, bus->self, b_res, size1-size0,
935 min_align);
936 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
937 b_res, &bus->busn_res,
938 (unsigned long long) size1 - size0);
939 }
940 }
941
942 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
943 int max_order)
944 {
945 resource_size_t align = 0;
946 resource_size_t min_align = 0;
947 int order;
948
949 for (order = 0; order <= max_order; order++) {
950 resource_size_t align1 = 1;
951
952 align1 <<= (order + 20);
953
954 if (!align)
955 min_align = align1;
956 else if (ALIGN(align + min_align, min_align) < align1)
957 min_align = align1 >> 1;
958 align += aligns[order];
959 }
960
961 return min_align;
962 }
963
964 /**
965 * pbus_size_mem() - Size the memory window of a given bus
966 *
967 * @bus: The bus
968 * @mask: Mask the resource flag, then compare it with type
969 * @type: The type of free resource from bridge
970 * @type2: Second match type
971 * @type3: Third match type
972 * @min_size: The minimum memory window that must be allocated
973 * @add_size: Additional optional memory window
974 * @realloc_head: Track the additional memory window on this list
975 *
976 * Calculate the size of the bus and minimal alignment which guarantees
977 * that all child resources fit in this size.
978 *
979 * Return -ENOSPC if there's no available bus resource of the desired
980 * type. Otherwise, set the bus resource start/end to indicate the
981 * required size, add things to realloc_head (if supplied), and return 0.
982 */
983 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
984 unsigned long type, unsigned long type2,
985 unsigned long type3, resource_size_t min_size,
986 resource_size_t add_size,
987 struct list_head *realloc_head)
988 {
989 struct pci_dev *dev;
990 resource_size_t min_align, align, size, size0, size1;
991 resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
992 int order, max_order;
993 struct resource *b_res = find_bus_resource_of_type(bus,
994 mask | IORESOURCE_PREFETCH, type);
995 resource_size_t children_add_size = 0;
996 resource_size_t children_add_align = 0;
997 resource_size_t add_align = 0;
998
999 if (!b_res)
1000 return -ENOSPC;
1001
1002 /* If resource is already assigned, nothing more to do */
1003 if (b_res->parent)
1004 return 0;
1005
1006 memset(aligns, 0, sizeof(aligns));
1007 max_order = 0;
1008 size = 0;
1009
1010 list_for_each_entry(dev, &bus->devices, bus_list) {
1011 int i;
1012
1013 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1014 struct resource *r = &dev->resource[i];
1015 resource_size_t r_size;
1016
1017 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1018 ((r->flags & mask) != type &&
1019 (r->flags & mask) != type2 &&
1020 (r->flags & mask) != type3))
1021 continue;
1022 r_size = resource_size(r);
1023 #ifdef CONFIG_PCI_IOV
1024 /* Put SRIOV requested res to the optional list */
1025 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1026 i <= PCI_IOV_RESOURCE_END) {
1027 add_align = max(pci_resource_alignment(dev, r), add_align);
1028 r->end = r->start - 1;
1029 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1030 children_add_size += r_size;
1031 continue;
1032 }
1033 #endif
1034 /*
1035 * aligns[0] is for 1MB (since bridge memory
1036 * windows are always at least 1MB aligned), so
1037 * keep "order" from being negative for smaller
1038 * resources.
1039 */
1040 align = pci_resource_alignment(dev, r);
1041 order = __ffs(align) - 20;
1042 if (order < 0)
1043 order = 0;
1044 if (order >= ARRAY_SIZE(aligns)) {
1045 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1046 i, r, (unsigned long long) align);
1047 r->flags = 0;
1048 continue;
1049 }
1050 size += max(r_size, align);
1051 /*
1052 * Exclude ranges with size > align from calculation of
1053 * the alignment.
1054 */
1055 if (r_size <= align)
1056 aligns[order] += align;
1057 if (order > max_order)
1058 max_order = order;
1059
1060 if (realloc_head) {
1061 children_add_size += get_res_add_size(realloc_head, r);
1062 children_add_align = get_res_add_align(realloc_head, r);
1063 add_align = max(add_align, children_add_align);
1064 }
1065 }
1066 }
1067
1068 min_align = calculate_mem_align(aligns, max_order);
1069 min_align = max(min_align, window_alignment(bus, b_res->flags));
1070 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1071 add_align = max(min_align, add_align);
1072 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1073 calculate_memsize(size, min_size, add_size, children_add_size,
1074 resource_size(b_res), add_align);
1075 if (!size0 && !size1) {
1076 if (bus->self && (b_res->start || b_res->end))
1077 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1078 b_res, &bus->busn_res);
1079 b_res->flags = 0;
1080 return 0;
1081 }
1082 b_res->start = min_align;
1083 b_res->end = size0 + min_align - 1;
1084 b_res->flags |= IORESOURCE_STARTALIGN;
1085 if (bus->self && size1 > size0 && realloc_head) {
1086 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1087 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1088 b_res, &bus->busn_res,
1089 (unsigned long long) (size1 - size0),
1090 (unsigned long long) add_align);
1091 }
1092 return 0;
1093 }
1094
1095 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1096 {
1097 if (res->flags & IORESOURCE_IO)
1098 return pci_cardbus_io_size;
1099 if (res->flags & IORESOURCE_MEM)
1100 return pci_cardbus_mem_size;
1101 return 0;
1102 }
1103
1104 static void pci_bus_size_cardbus(struct pci_bus *bus,
1105 struct list_head *realloc_head)
1106 {
1107 struct pci_dev *bridge = bus->self;
1108 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1109 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1110 u16 ctrl;
1111
1112 if (b_res[0].parent)
1113 goto handle_b_res_1;
1114 /*
1115 * Reserve some resources for CardBus. We reserve a fixed amount
1116 * of bus space for CardBus bridges.
1117 */
1118 b_res[0].start = pci_cardbus_io_size;
1119 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1120 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1121 if (realloc_head) {
1122 b_res[0].end -= pci_cardbus_io_size;
1123 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1124 pci_cardbus_io_size);
1125 }
1126
1127 handle_b_res_1:
1128 if (b_res[1].parent)
1129 goto handle_b_res_2;
1130 b_res[1].start = pci_cardbus_io_size;
1131 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1132 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1133 if (realloc_head) {
1134 b_res[1].end -= pci_cardbus_io_size;
1135 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1136 pci_cardbus_io_size);
1137 }
1138
1139 handle_b_res_2:
1140 /* MEM1 must not be pref MMIO */
1141 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1142 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1143 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1144 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1145 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1146 }
1147
1148 /* Check whether prefetchable memory is supported by this bridge. */
1149 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1150 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1151 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1152 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1153 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1154 }
1155
1156 if (b_res[2].parent)
1157 goto handle_b_res_3;
1158 /*
1159 * If we have prefetchable memory support, allocate two regions.
1160 * Otherwise, allocate one region of twice the size.
1161 */
1162 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1163 b_res[2].start = pci_cardbus_mem_size;
1164 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1165 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1166 IORESOURCE_STARTALIGN;
1167 if (realloc_head) {
1168 b_res[2].end -= pci_cardbus_mem_size;
1169 add_to_list(realloc_head, bridge, b_res+2,
1170 pci_cardbus_mem_size, pci_cardbus_mem_size);
1171 }
1172
1173 /* Reduce that to half */
1174 b_res_3_size = pci_cardbus_mem_size;
1175 }
1176
1177 handle_b_res_3:
1178 if (b_res[3].parent)
1179 goto handle_done;
1180 b_res[3].start = pci_cardbus_mem_size;
1181 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1182 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1183 if (realloc_head) {
1184 b_res[3].end -= b_res_3_size;
1185 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1186 pci_cardbus_mem_size);
1187 }
1188
1189 handle_done:
1190 ;
1191 }
1192
1193 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1194 {
1195 struct pci_dev *dev;
1196 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1197 resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1198 additional_mmio_pref_size = 0;
1199 struct resource *pref;
1200 struct pci_host_bridge *host;
1201 int hdr_type, i, ret;
1202
1203 list_for_each_entry(dev, &bus->devices, bus_list) {
1204 struct pci_bus *b = dev->subordinate;
1205 if (!b)
1206 continue;
1207
1208 switch (dev->hdr_type) {
1209 case PCI_HEADER_TYPE_CARDBUS:
1210 pci_bus_size_cardbus(b, realloc_head);
1211 break;
1212
1213 case PCI_HEADER_TYPE_BRIDGE:
1214 default:
1215 __pci_bus_size_bridges(b, realloc_head);
1216 break;
1217 }
1218 }
1219
1220 /* The root bus? */
1221 if (pci_is_root_bus(bus)) {
1222 host = to_pci_host_bridge(bus->bridge);
1223 if (!host->size_windows)
1224 return;
1225 pci_bus_for_each_resource(bus, pref, i)
1226 if (pref && (pref->flags & IORESOURCE_PREFETCH))
1227 break;
1228 hdr_type = -1; /* Intentionally invalid - not a PCI device. */
1229 } else {
1230 pref = &bus->self->resource[PCI_BRIDGE_RESOURCES + 2];
1231 hdr_type = bus->self->hdr_type;
1232 }
1233
1234 switch (hdr_type) {
1235 case PCI_HEADER_TYPE_CARDBUS:
1236 /* Don't size CardBuses yet */
1237 break;
1238
1239 case PCI_HEADER_TYPE_BRIDGE:
1240 pci_bridge_check_ranges(bus);
1241 if (bus->self->is_hotplug_bridge) {
1242 additional_io_size = pci_hotplug_io_size;
1243 additional_mmio_size = pci_hotplug_mmio_size;
1244 additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1245 }
1246 /* Fall through */
1247 default:
1248 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1249 additional_io_size, realloc_head);
1250
1251 /*
1252 * If there's a 64-bit prefetchable MMIO window, compute
1253 * the size required to put all 64-bit prefetchable
1254 * resources in it.
1255 */
1256 mask = IORESOURCE_MEM;
1257 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1258 if (pref && (pref->flags & IORESOURCE_MEM_64)) {
1259 prefmask |= IORESOURCE_MEM_64;
1260 ret = pbus_size_mem(bus, prefmask, prefmask,
1261 prefmask, prefmask,
1262 realloc_head ? 0 : additional_mmio_pref_size,
1263 additional_mmio_pref_size, realloc_head);
1264
1265 /*
1266 * If successful, all non-prefetchable resources
1267 * and any 32-bit prefetchable resources will go in
1268 * the non-prefetchable window.
1269 */
1270 if (ret == 0) {
1271 mask = prefmask;
1272 type2 = prefmask & ~IORESOURCE_MEM_64;
1273 type3 = prefmask & ~IORESOURCE_PREFETCH;
1274 }
1275 }
1276
1277 /*
1278 * If there is no 64-bit prefetchable window, compute the
1279 * size required to put all prefetchable resources in the
1280 * 32-bit prefetchable window (if there is one).
1281 */
1282 if (!type2) {
1283 prefmask &= ~IORESOURCE_MEM_64;
1284 ret = pbus_size_mem(bus, prefmask, prefmask,
1285 prefmask, prefmask,
1286 realloc_head ? 0 : additional_mmio_pref_size,
1287 additional_mmio_pref_size, realloc_head);
1288
1289 /*
1290 * If successful, only non-prefetchable resources
1291 * will go in the non-prefetchable window.
1292 */
1293 if (ret == 0)
1294 mask = prefmask;
1295 else
1296 additional_mmio_size += additional_mmio_pref_size;
1297
1298 type2 = type3 = IORESOURCE_MEM;
1299 }
1300
1301 /*
1302 * Compute the size required to put everything else in the
1303 * non-prefetchable window. This includes:
1304 *
1305 * - all non-prefetchable resources
1306 * - 32-bit prefetchable resources if there's a 64-bit
1307 * prefetchable window or no prefetchable window at all
1308 * - 64-bit prefetchable resources if there's no prefetchable
1309 * window at all
1310 *
1311 * Note that the strategy in __pci_assign_resource() must match
1312 * that used here. Specifically, we cannot put a 32-bit
1313 * prefetchable resource in a 64-bit prefetchable window.
1314 */
1315 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1316 realloc_head ? 0 : additional_mmio_size,
1317 additional_mmio_size, realloc_head);
1318 break;
1319 }
1320 }
1321
1322 void pci_bus_size_bridges(struct pci_bus *bus)
1323 {
1324 __pci_bus_size_bridges(bus, NULL);
1325 }
1326 EXPORT_SYMBOL(pci_bus_size_bridges);
1327
1328 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1329 {
1330 int i;
1331 struct resource *parent_r;
1332 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1333 IORESOURCE_PREFETCH;
1334
1335 pci_bus_for_each_resource(b, parent_r, i) {
1336 if (!parent_r)
1337 continue;
1338
1339 if ((r->flags & mask) == (parent_r->flags & mask) &&
1340 resource_contains(parent_r, r))
1341 request_resource(parent_r, r);
1342 }
1343 }
1344
1345 /*
1346 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1347 * skipped by pbus_assign_resources_sorted().
1348 */
1349 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1350 {
1351 int i;
1352
1353 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1354 struct pci_bus *b;
1355 struct resource *r = &dev->resource[i];
1356
1357 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1358 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1359 continue;
1360
1361 b = dev->bus;
1362 while (b && !r->parent) {
1363 assign_fixed_resource_on_bus(b, r);
1364 b = b->parent;
1365 }
1366 }
1367 }
1368
1369 void __pci_bus_assign_resources(const struct pci_bus *bus,
1370 struct list_head *realloc_head,
1371 struct list_head *fail_head)
1372 {
1373 struct pci_bus *b;
1374 struct pci_dev *dev;
1375
1376 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1377
1378 list_for_each_entry(dev, &bus->devices, bus_list) {
1379 pdev_assign_fixed_resources(dev);
1380
1381 b = dev->subordinate;
1382 if (!b)
1383 continue;
1384
1385 __pci_bus_assign_resources(b, realloc_head, fail_head);
1386
1387 switch (dev->hdr_type) {
1388 case PCI_HEADER_TYPE_BRIDGE:
1389 if (!pci_is_enabled(dev))
1390 pci_setup_bridge(b);
1391 break;
1392
1393 case PCI_HEADER_TYPE_CARDBUS:
1394 pci_setup_cardbus(b);
1395 break;
1396
1397 default:
1398 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1399 pci_domain_nr(b), b->number);
1400 break;
1401 }
1402 }
1403 }
1404
1405 void pci_bus_assign_resources(const struct pci_bus *bus)
1406 {
1407 __pci_bus_assign_resources(bus, NULL, NULL);
1408 }
1409 EXPORT_SYMBOL(pci_bus_assign_resources);
1410
1411 static void pci_claim_device_resources(struct pci_dev *dev)
1412 {
1413 int i;
1414
1415 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1416 struct resource *r = &dev->resource[i];
1417
1418 if (!r->flags || r->parent)
1419 continue;
1420
1421 pci_claim_resource(dev, i);
1422 }
1423 }
1424
1425 static void pci_claim_bridge_resources(struct pci_dev *dev)
1426 {
1427 int i;
1428
1429 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1430 struct resource *r = &dev->resource[i];
1431
1432 if (!r->flags || r->parent)
1433 continue;
1434
1435 pci_claim_bridge_resource(dev, i);
1436 }
1437 }
1438
1439 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1440 {
1441 struct pci_dev *dev;
1442 struct pci_bus *child;
1443
1444 list_for_each_entry(dev, &b->devices, bus_list) {
1445 pci_claim_device_resources(dev);
1446
1447 child = dev->subordinate;
1448 if (child)
1449 pci_bus_allocate_dev_resources(child);
1450 }
1451 }
1452
1453 static void pci_bus_allocate_resources(struct pci_bus *b)
1454 {
1455 struct pci_bus *child;
1456
1457 /*
1458 * Carry out a depth-first search on the PCI bus tree to allocate
1459 * bridge apertures. Read the programmed bridge bases and
1460 * recursively claim the respective bridge resources.
1461 */
1462 if (b->self) {
1463 pci_read_bridge_bases(b);
1464 pci_claim_bridge_resources(b->self);
1465 }
1466
1467 list_for_each_entry(child, &b->children, node)
1468 pci_bus_allocate_resources(child);
1469 }
1470
1471 void pci_bus_claim_resources(struct pci_bus *b)
1472 {
1473 pci_bus_allocate_resources(b);
1474 pci_bus_allocate_dev_resources(b);
1475 }
1476 EXPORT_SYMBOL(pci_bus_claim_resources);
1477
1478 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1479 struct list_head *add_head,
1480 struct list_head *fail_head)
1481 {
1482 struct pci_bus *b;
1483
1484 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1485 add_head, fail_head);
1486
1487 b = bridge->subordinate;
1488 if (!b)
1489 return;
1490
1491 __pci_bus_assign_resources(b, add_head, fail_head);
1492
1493 switch (bridge->class >> 8) {
1494 case PCI_CLASS_BRIDGE_PCI:
1495 pci_setup_bridge(b);
1496 break;
1497
1498 case PCI_CLASS_BRIDGE_CARDBUS:
1499 pci_setup_cardbus(b);
1500 break;
1501
1502 default:
1503 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1504 pci_domain_nr(b), b->number);
1505 break;
1506 }
1507 }
1508
1509 #define PCI_RES_TYPE_MASK \
1510 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1511 IORESOURCE_MEM_64)
1512
1513 static void pci_bridge_release_resources(struct pci_bus *bus,
1514 unsigned long type)
1515 {
1516 struct pci_dev *dev = bus->self;
1517 struct resource *r;
1518 unsigned old_flags = 0;
1519 struct resource *b_res;
1520 int idx = 1;
1521
1522 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1523
1524 /*
1525 * 1. If IO port assignment fails, release bridge IO port.
1526 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1527 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1528 * release bridge pref MMIO.
1529 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1530 * release bridge pref MMIO.
1531 * 5. If pref MMIO assignment fails, and bridge pref is not
1532 * assigned, release bridge nonpref MMIO.
1533 */
1534 if (type & IORESOURCE_IO)
1535 idx = 0;
1536 else if (!(type & IORESOURCE_PREFETCH))
1537 idx = 1;
1538 else if ((type & IORESOURCE_MEM_64) &&
1539 (b_res[2].flags & IORESOURCE_MEM_64))
1540 idx = 2;
1541 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1542 (b_res[2].flags & IORESOURCE_PREFETCH))
1543 idx = 2;
1544 else
1545 idx = 1;
1546
1547 r = &b_res[idx];
1548
1549 if (!r->parent)
1550 return;
1551
1552 /* If there are children, release them all */
1553 release_child_resources(r);
1554 if (!release_resource(r)) {
1555 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1556 pci_info(dev, "resource %d %pR released\n",
1557 PCI_BRIDGE_RESOURCES + idx, r);
1558 /* Keep the old size */
1559 r->end = resource_size(r) - 1;
1560 r->start = 0;
1561 r->flags = 0;
1562
1563 /* Avoiding touch the one without PREF */
1564 if (type & IORESOURCE_PREFETCH)
1565 type = IORESOURCE_PREFETCH;
1566 __pci_setup_bridge(bus, type);
1567 /* For next child res under same bridge */
1568 r->flags = old_flags;
1569 }
1570 }
1571
1572 enum release_type {
1573 leaf_only,
1574 whole_subtree,
1575 };
1576
1577 /*
1578 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1579 * a larger window later.
1580 */
1581 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1582 unsigned long type,
1583 enum release_type rel_type)
1584 {
1585 struct pci_dev *dev;
1586 bool is_leaf_bridge = true;
1587
1588 list_for_each_entry(dev, &bus->devices, bus_list) {
1589 struct pci_bus *b = dev->subordinate;
1590 if (!b)
1591 continue;
1592
1593 is_leaf_bridge = false;
1594
1595 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1596 continue;
1597
1598 if (rel_type == whole_subtree)
1599 pci_bus_release_bridge_resources(b, type,
1600 whole_subtree);
1601 }
1602
1603 if (pci_is_root_bus(bus))
1604 return;
1605
1606 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1607 return;
1608
1609 if ((rel_type == whole_subtree) || is_leaf_bridge)
1610 pci_bridge_release_resources(bus, type);
1611 }
1612
1613 static void pci_bus_dump_res(struct pci_bus *bus)
1614 {
1615 struct resource *res;
1616 int i;
1617
1618 pci_bus_for_each_resource(bus, res, i) {
1619 if (!res || !res->end || !res->flags)
1620 continue;
1621
1622 dev_info(&bus->dev, "resource %d %pR\n", i, res);
1623 }
1624 }
1625
1626 static void pci_bus_dump_resources(struct pci_bus *bus)
1627 {
1628 struct pci_bus *b;
1629 struct pci_dev *dev;
1630
1631
1632 pci_bus_dump_res(bus);
1633
1634 list_for_each_entry(dev, &bus->devices, bus_list) {
1635 b = dev->subordinate;
1636 if (!b)
1637 continue;
1638
1639 pci_bus_dump_resources(b);
1640 }
1641 }
1642
1643 static int pci_bus_get_depth(struct pci_bus *bus)
1644 {
1645 int depth = 0;
1646 struct pci_bus *child_bus;
1647
1648 list_for_each_entry(child_bus, &bus->children, node) {
1649 int ret;
1650
1651 ret = pci_bus_get_depth(child_bus);
1652 if (ret + 1 > depth)
1653 depth = ret + 1;
1654 }
1655
1656 return depth;
1657 }
1658
1659 /*
1660 * -1: undefined, will auto detect later
1661 * 0: disabled by user
1662 * 1: disabled by auto detect
1663 * 2: enabled by user
1664 * 3: enabled by auto detect
1665 */
1666 enum enable_type {
1667 undefined = -1,
1668 user_disabled,
1669 auto_disabled,
1670 user_enabled,
1671 auto_enabled,
1672 };
1673
1674 static enum enable_type pci_realloc_enable = undefined;
1675 void __init pci_realloc_get_opt(char *str)
1676 {
1677 if (!strncmp(str, "off", 3))
1678 pci_realloc_enable = user_disabled;
1679 else if (!strncmp(str, "on", 2))
1680 pci_realloc_enable = user_enabled;
1681 }
1682 static bool pci_realloc_enabled(enum enable_type enable)
1683 {
1684 return enable >= user_enabled;
1685 }
1686
1687 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1688 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1689 {
1690 int i;
1691 bool *unassigned = data;
1692
1693 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1694 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1695 struct pci_bus_region region;
1696
1697 /* Not assigned or rejected by kernel? */
1698 if (!r->flags)
1699 continue;
1700
1701 pcibios_resource_to_bus(dev->bus, &region, r);
1702 if (!region.start) {
1703 *unassigned = true;
1704 return 1; /* Return early from pci_walk_bus() */
1705 }
1706 }
1707
1708 return 0;
1709 }
1710
1711 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1712 enum enable_type enable_local)
1713 {
1714 bool unassigned = false;
1715 struct pci_host_bridge *host;
1716
1717 if (enable_local != undefined)
1718 return enable_local;
1719
1720 host = pci_find_host_bridge(bus);
1721 if (host->preserve_config)
1722 return auto_disabled;
1723
1724 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1725 if (unassigned)
1726 return auto_enabled;
1727
1728 return enable_local;
1729 }
1730 #else
1731 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1732 enum enable_type enable_local)
1733 {
1734 return enable_local;
1735 }
1736 #endif
1737
1738 /*
1739 * First try will not touch PCI bridge res.
1740 * Second and later try will clear small leaf bridge res.
1741 * Will stop till to the max depth if can not find good one.
1742 */
1743 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1744 {
1745 LIST_HEAD(realloc_head);
1746 /* List of resources that want additional resources */
1747 struct list_head *add_list = NULL;
1748 int tried_times = 0;
1749 enum release_type rel_type = leaf_only;
1750 LIST_HEAD(fail_head);
1751 struct pci_dev_resource *fail_res;
1752 int pci_try_num = 1;
1753 enum enable_type enable_local;
1754
1755 /* Don't realloc if asked to do so */
1756 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1757 if (pci_realloc_enabled(enable_local)) {
1758 int max_depth = pci_bus_get_depth(bus);
1759
1760 pci_try_num = max_depth + 1;
1761 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
1762 max_depth, pci_try_num);
1763 }
1764
1765 again:
1766 /*
1767 * Last try will use add_list, otherwise will try good to have as must
1768 * have, so can realloc parent bridge resource
1769 */
1770 if (tried_times + 1 == pci_try_num)
1771 add_list = &realloc_head;
1772 /*
1773 * Depth first, calculate sizes and alignments of all subordinate buses.
1774 */
1775 __pci_bus_size_bridges(bus, add_list);
1776
1777 /* Depth last, allocate resources and update the hardware. */
1778 __pci_bus_assign_resources(bus, add_list, &fail_head);
1779 if (add_list)
1780 BUG_ON(!list_empty(add_list));
1781 tried_times++;
1782
1783 /* Any device complain? */
1784 if (list_empty(&fail_head))
1785 goto dump;
1786
1787 if (tried_times >= pci_try_num) {
1788 if (enable_local == undefined)
1789 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1790 else if (enable_local == auto_enabled)
1791 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1792
1793 free_list(&fail_head);
1794 goto dump;
1795 }
1796
1797 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1798 tried_times + 1);
1799
1800 /* Third times and later will not check if it is leaf */
1801 if ((tried_times + 1) > 2)
1802 rel_type = whole_subtree;
1803
1804 /*
1805 * Try to release leaf bridge's resources that doesn't fit resource of
1806 * child device under that bridge.
1807 */
1808 list_for_each_entry(fail_res, &fail_head, list)
1809 pci_bus_release_bridge_resources(fail_res->dev->bus,
1810 fail_res->flags & PCI_RES_TYPE_MASK,
1811 rel_type);
1812
1813 /* Restore size and flags */
1814 list_for_each_entry(fail_res, &fail_head, list) {
1815 struct resource *res = fail_res->res;
1816 int idx;
1817
1818 res->start = fail_res->start;
1819 res->end = fail_res->end;
1820 res->flags = fail_res->flags;
1821
1822 if (pci_is_bridge(fail_res->dev)) {
1823 idx = res - &fail_res->dev->resource[0];
1824 if (idx >= PCI_BRIDGE_RESOURCES &&
1825 idx <= PCI_BRIDGE_RESOURCE_END)
1826 res->flags = 0;
1827 }
1828 }
1829 free_list(&fail_head);
1830
1831 goto again;
1832
1833 dump:
1834 /* Dump the resource on buses */
1835 pci_bus_dump_resources(bus);
1836 }
1837
1838 void __init pci_assign_unassigned_resources(void)
1839 {
1840 struct pci_bus *root_bus;
1841
1842 list_for_each_entry(root_bus, &pci_root_buses, node) {
1843 pci_assign_unassigned_root_bus_resources(root_bus);
1844
1845 /* Make sure the root bridge has a companion ACPI device */
1846 if (ACPI_HANDLE(root_bus->bridge))
1847 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1848 }
1849 }
1850
1851 static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1852 struct list_head *add_list,
1853 resource_size_t new_size)
1854 {
1855 resource_size_t add_size, size = resource_size(res);
1856
1857 if (res->parent)
1858 return;
1859
1860 if (!new_size)
1861 return;
1862
1863 if (new_size > size) {
1864 add_size = new_size - size;
1865 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1866 &add_size);
1867 } else if (new_size < size) {
1868 add_size = size - new_size;
1869 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1870 &add_size);
1871 }
1872
1873 res->end = res->start + new_size - 1;
1874 remove_from_list(add_list, res);
1875 }
1876
1877 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1878 struct list_head *add_list,
1879 struct resource io,
1880 struct resource mmio,
1881 struct resource mmio_pref)
1882 {
1883 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1884 struct resource *io_res, *mmio_res, *mmio_pref_res;
1885 struct pci_dev *dev, *bridge = bus->self;
1886 resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
1887
1888 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1889 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1890 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1891
1892 /*
1893 * The alignment of this bridge is yet to be considered, hence it must
1894 * be done now before extending its bridge window.
1895 */
1896 align = pci_resource_alignment(bridge, io_res);
1897 if (!io_res->parent && align)
1898 io.start = min(ALIGN(io.start, align), io.end + 1);
1899
1900 align = pci_resource_alignment(bridge, mmio_res);
1901 if (!mmio_res->parent && align)
1902 mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
1903
1904 align = pci_resource_alignment(bridge, mmio_pref_res);
1905 if (!mmio_pref_res->parent && align)
1906 mmio_pref.start = min(ALIGN(mmio_pref.start, align),
1907 mmio_pref.end + 1);
1908
1909 /*
1910 * Now that we have adjusted for alignment, update the bridge window
1911 * resources to fill as much remaining resource space as possible.
1912 */
1913 adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
1914 adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
1915 adjust_bridge_window(bridge, mmio_pref_res, add_list,
1916 resource_size(&mmio_pref));
1917
1918 /*
1919 * Calculate how many hotplug bridges and normal bridges there
1920 * are on this bus. We will distribute the additional available
1921 * resources between hotplug bridges.
1922 */
1923 for_each_pci_bridge(dev, bus) {
1924 if (dev->is_hotplug_bridge)
1925 hotplug_bridges++;
1926 else
1927 normal_bridges++;
1928 }
1929
1930 /*
1931 * There is only one bridge on the bus so it gets all available
1932 * resources which it can then distribute to the possible hotplug
1933 * bridges below.
1934 */
1935 if (hotplug_bridges + normal_bridges == 1) {
1936 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1937 if (dev->subordinate)
1938 pci_bus_distribute_available_resources(dev->subordinate,
1939 add_list, io, mmio, mmio_pref);
1940 return;
1941 }
1942
1943 if (hotplug_bridges == 0)
1944 return;
1945
1946 /*
1947 * Calculate the total amount of extra resource space we can
1948 * pass to bridges below this one. This is basically the
1949 * extra space reduced by the minimal required space for the
1950 * non-hotplug bridges.
1951 */
1952 for_each_pci_bridge(dev, bus) {
1953 resource_size_t used_size;
1954 struct resource *res;
1955
1956 if (dev->is_hotplug_bridge)
1957 continue;
1958
1959 /*
1960 * Reduce the available resource space by what the
1961 * bridge and devices below it occupy.
1962 */
1963 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1964 align = pci_resource_alignment(dev, res);
1965 align = align ? ALIGN(io.start, align) - io.start : 0;
1966 used_size = align + resource_size(res);
1967 if (!res->parent)
1968 io.start = min(io.start + used_size, io.end + 1);
1969
1970 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1971 align = pci_resource_alignment(dev, res);
1972 align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
1973 used_size = align + resource_size(res);
1974 if (!res->parent)
1975 mmio.start = min(mmio.start + used_size, mmio.end + 1);
1976
1977 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1978 align = pci_resource_alignment(dev, res);
1979 align = align ? ALIGN(mmio_pref.start, align) -
1980 mmio_pref.start : 0;
1981 used_size = align + resource_size(res);
1982 if (!res->parent)
1983 mmio_pref.start = min(mmio_pref.start + used_size,
1984 mmio_pref.end + 1);
1985 }
1986
1987 io_per_hp = div64_ul(resource_size(&io), hotplug_bridges);
1988 mmio_per_hp = div64_ul(resource_size(&mmio), hotplug_bridges);
1989 mmio_pref_per_hp = div64_ul(resource_size(&mmio_pref),
1990 hotplug_bridges);
1991
1992 /*
1993 * Go over devices on this bus and distribute the remaining
1994 * resource space between hotplug bridges.
1995 */
1996 for_each_pci_bridge(dev, bus) {
1997 struct pci_bus *b;
1998
1999 b = dev->subordinate;
2000 if (!b || !dev->is_hotplug_bridge)
2001 continue;
2002
2003 /*
2004 * Distribute available extra resources equally between
2005 * hotplug-capable downstream ports taking alignment into
2006 * account.
2007 */
2008 io.end = io.start + io_per_hp - 1;
2009 mmio.end = mmio.start + mmio_per_hp - 1;
2010 mmio_pref.end = mmio_pref.start + mmio_pref_per_hp - 1;
2011
2012 pci_bus_distribute_available_resources(b, add_list, io, mmio,
2013 mmio_pref);
2014
2015 io.start += io_per_hp;
2016 mmio.start += mmio_per_hp;
2017 mmio_pref.start += mmio_pref_per_hp;
2018 }
2019 }
2020
2021 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2022 struct list_head *add_list)
2023 {
2024 struct resource available_io, available_mmio, available_mmio_pref;
2025
2026 if (!bridge->is_hotplug_bridge)
2027 return;
2028
2029 /* Take the initial extra resources from the hotplug port */
2030 available_io = bridge->resource[PCI_BRIDGE_RESOURCES + 0];
2031 available_mmio = bridge->resource[PCI_BRIDGE_RESOURCES + 1];
2032 available_mmio_pref = bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2033
2034 pci_bus_distribute_available_resources(bridge->subordinate,
2035 add_list, available_io,
2036 available_mmio,
2037 available_mmio_pref);
2038 }
2039
2040 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2041 {
2042 struct pci_bus *parent = bridge->subordinate;
2043 /* List of resources that want additional resources */
2044 LIST_HEAD(add_list);
2045
2046 int tried_times = 0;
2047 LIST_HEAD(fail_head);
2048 struct pci_dev_resource *fail_res;
2049 int retval;
2050
2051 again:
2052 __pci_bus_size_bridges(parent, &add_list);
2053
2054 /*
2055 * Distribute remaining resources (if any) equally between hotplug
2056 * bridges below. This makes it possible to extend the hierarchy
2057 * later without running out of resources.
2058 */
2059 pci_bridge_distribute_available_resources(bridge, &add_list);
2060
2061 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2062 BUG_ON(!list_empty(&add_list));
2063 tried_times++;
2064
2065 if (list_empty(&fail_head))
2066 goto enable_all;
2067
2068 if (tried_times >= 2) {
2069 /* Still fail, don't need to try more */
2070 free_list(&fail_head);
2071 goto enable_all;
2072 }
2073
2074 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2075 tried_times + 1);
2076
2077 /*
2078 * Try to release leaf bridge's resources that aren't big enough
2079 * to contain child device resources.
2080 */
2081 list_for_each_entry(fail_res, &fail_head, list)
2082 pci_bus_release_bridge_resources(fail_res->dev->bus,
2083 fail_res->flags & PCI_RES_TYPE_MASK,
2084 whole_subtree);
2085
2086 /* Restore size and flags */
2087 list_for_each_entry(fail_res, &fail_head, list) {
2088 struct resource *res = fail_res->res;
2089 int idx;
2090
2091 res->start = fail_res->start;
2092 res->end = fail_res->end;
2093 res->flags = fail_res->flags;
2094
2095 if (pci_is_bridge(fail_res->dev)) {
2096 idx = res - &fail_res->dev->resource[0];
2097 if (idx >= PCI_BRIDGE_RESOURCES &&
2098 idx <= PCI_BRIDGE_RESOURCE_END)
2099 res->flags = 0;
2100 }
2101 }
2102 free_list(&fail_head);
2103
2104 goto again;
2105
2106 enable_all:
2107 retval = pci_reenable_device(bridge);
2108 if (retval)
2109 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2110 pci_set_master(bridge);
2111 }
2112 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2113
2114 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2115 {
2116 struct pci_dev_resource *dev_res;
2117 struct pci_dev *next;
2118 LIST_HEAD(saved);
2119 LIST_HEAD(added);
2120 LIST_HEAD(failed);
2121 unsigned int i;
2122 int ret;
2123
2124 down_read(&pci_bus_sem);
2125
2126 /* Walk to the root hub, releasing bridge BARs when possible */
2127 next = bridge;
2128 do {
2129 bridge = next;
2130 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2131 i++) {
2132 struct resource *res = &bridge->resource[i];
2133
2134 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2135 continue;
2136
2137 /* Ignore BARs which are still in use */
2138 if (res->child)
2139 continue;
2140
2141 ret = add_to_list(&saved, bridge, res, 0, 0);
2142 if (ret)
2143 goto cleanup;
2144
2145 pci_info(bridge, "BAR %d: releasing %pR\n",
2146 i, res);
2147
2148 if (res->parent)
2149 release_resource(res);
2150 res->start = 0;
2151 res->end = 0;
2152 break;
2153 }
2154 if (i == PCI_BRIDGE_RESOURCE_END)
2155 break;
2156
2157 next = bridge->bus ? bridge->bus->self : NULL;
2158 } while (next);
2159
2160 if (list_empty(&saved)) {
2161 up_read(&pci_bus_sem);
2162 return -ENOENT;
2163 }
2164
2165 __pci_bus_size_bridges(bridge->subordinate, &added);
2166 __pci_bridge_assign_resources(bridge, &added, &failed);
2167 BUG_ON(!list_empty(&added));
2168
2169 if (!list_empty(&failed)) {
2170 ret = -ENOSPC;
2171 goto cleanup;
2172 }
2173
2174 list_for_each_entry(dev_res, &saved, list) {
2175 /* Skip the bridge we just assigned resources for */
2176 if (bridge == dev_res->dev)
2177 continue;
2178
2179 bridge = dev_res->dev;
2180 pci_setup_bridge(bridge->subordinate);
2181 }
2182
2183 free_list(&saved);
2184 up_read(&pci_bus_sem);
2185 return 0;
2186
2187 cleanup:
2188 /* Restore size and flags */
2189 list_for_each_entry(dev_res, &failed, list) {
2190 struct resource *res = dev_res->res;
2191
2192 res->start = dev_res->start;
2193 res->end = dev_res->end;
2194 res->flags = dev_res->flags;
2195 }
2196 free_list(&failed);
2197
2198 /* Revert to the old configuration */
2199 list_for_each_entry(dev_res, &saved, list) {
2200 struct resource *res = dev_res->res;
2201
2202 bridge = dev_res->dev;
2203 i = res - bridge->resource;
2204
2205 res->start = dev_res->start;
2206 res->end = dev_res->end;
2207 res->flags = dev_res->flags;
2208
2209 pci_claim_resource(bridge, i);
2210 pci_setup_bridge(bridge->subordinate);
2211 }
2212 free_list(&saved);
2213 up_read(&pci_bus_sem);
2214
2215 return ret;
2216 }
2217
2218 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2219 {
2220 struct pci_dev *dev;
2221 /* List of resources that want additional resources */
2222 LIST_HEAD(add_list);
2223
2224 down_read(&pci_bus_sem);
2225 for_each_pci_bridge(dev, bus)
2226 if (pci_has_subordinate(dev))
2227 __pci_bus_size_bridges(dev->subordinate, &add_list);
2228 up_read(&pci_bus_sem);
2229 __pci_bus_assign_resources(bus, &add_list, NULL);
2230 BUG_ON(!list_empty(&add_list));
2231 }
2232 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
Linux with added FPC-III support