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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / tty / serial / amba-pl010.c
blob3284f34e9dfe145036d60a16ba63351eb84ed15f
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This is a generic driver for ARM AMBA-type serial ports. They
11 * have a lot of 16550-like features, but are not register compatible.
12 * Note that although they do have CTS, DCD and DSR inputs, they do
13 * not have an RI input, nor do they have DTR or RTS outputs. If
14 * required, these have to be supplied via some other means (eg, GPIO)
15 * and hooked into this driver.
16 */
17
18 #include <linux/module.h>
19 #include <linux/ioport.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/sysrq.h>
23 #include <linux/device.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/serial.h>
30 #include <linux/clk.h>
31 #include <linux/slab.h>
32 #include <linux/io.h>
33
34 #define UART_NR 8
35
36 #define SERIAL_AMBA_MAJOR 204
37 #define SERIAL_AMBA_MINOR 16
38 #define SERIAL_AMBA_NR UART_NR
39
40 #define AMBA_ISR_PASS_LIMIT 256
41
42 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
43 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
44
45 #define UART_DUMMY_RSR_RX 256
46 #define UART_PORT_SIZE 64
47
48 /*
49 * We wrap our port structure around the generic uart_port.
50 */
51 struct uart_amba_port {
52 struct uart_port port;
53 struct clk *clk;
54 struct amba_device *dev;
55 struct amba_pl010_data *data;
56 unsigned int old_status;
57 };
58
59 static void pl010_stop_tx(struct uart_port *port)
60 {
61 struct uart_amba_port *uap =
62 container_of(port, struct uart_amba_port, port);
63 unsigned int cr;
64
65 cr = readb(uap->port.membase + UART010_CR);
66 cr &= ~UART010_CR_TIE;
67 writel(cr, uap->port.membase + UART010_CR);
68 }
69
70 static void pl010_start_tx(struct uart_port *port)
71 {
72 struct uart_amba_port *uap =
73 container_of(port, struct uart_amba_port, port);
74 unsigned int cr;
75
76 cr = readb(uap->port.membase + UART010_CR);
77 cr |= UART010_CR_TIE;
78 writel(cr, uap->port.membase + UART010_CR);
79 }
80
81 static void pl010_stop_rx(struct uart_port *port)
82 {
83 struct uart_amba_port *uap =
84 container_of(port, struct uart_amba_port, port);
85 unsigned int cr;
86
87 cr = readb(uap->port.membase + UART010_CR);
88 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
89 writel(cr, uap->port.membase + UART010_CR);
90 }
91
92 static void pl010_disable_ms(struct uart_port *port)
93 {
94 struct uart_amba_port *uap = (struct uart_amba_port *)port;
95 unsigned int cr;
96
97 cr = readb(uap->port.membase + UART010_CR);
98 cr &= ~UART010_CR_MSIE;
99 writel(cr, uap->port.membase + UART010_CR);
100 }
101
102 static void pl010_enable_ms(struct uart_port *port)
103 {
104 struct uart_amba_port *uap =
105 container_of(port, struct uart_amba_port, port);
106 unsigned int cr;
107
108 cr = readb(uap->port.membase + UART010_CR);
109 cr |= UART010_CR_MSIE;
110 writel(cr, uap->port.membase + UART010_CR);
111 }
112
113 static void pl010_rx_chars(struct uart_amba_port *uap)
114 {
115 unsigned int status, ch, flag, rsr, max_count = 256;
116
117 status = readb(uap->port.membase + UART01x_FR);
118 while (UART_RX_DATA(status) && max_count--) {
119 ch = readb(uap->port.membase + UART01x_DR);
120 flag = TTY_NORMAL;
121
122 uap->port.icount.rx++;
123
124 /*
125 * Note that the error handling code is
126 * out of the main execution path
127 */
128 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
129 if (unlikely(rsr & UART01x_RSR_ANY)) {
130 writel(0, uap->port.membase + UART01x_ECR);
131
132 if (rsr & UART01x_RSR_BE) {
133 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
134 uap->port.icount.brk++;
135 if (uart_handle_break(&uap->port))
136 goto ignore_char;
137 } else if (rsr & UART01x_RSR_PE)
138 uap->port.icount.parity++;
139 else if (rsr & UART01x_RSR_FE)
140 uap->port.icount.frame++;
141 if (rsr & UART01x_RSR_OE)
142 uap->port.icount.overrun++;
143
144 rsr &= uap->port.read_status_mask;
145
146 if (rsr & UART01x_RSR_BE)
147 flag = TTY_BREAK;
148 else if (rsr & UART01x_RSR_PE)
149 flag = TTY_PARITY;
150 else if (rsr & UART01x_RSR_FE)
151 flag = TTY_FRAME;
152 }
153
154 if (uart_handle_sysrq_char(&uap->port, ch))
155 goto ignore_char;
156
157 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
158
159 ignore_char:
160 status = readb(uap->port.membase + UART01x_FR);
161 }
162 spin_unlock(&uap->port.lock);
163 tty_flip_buffer_push(&uap->port.state->port);
164 spin_lock(&uap->port.lock);
165 }
166
167 static void pl010_tx_chars(struct uart_amba_port *uap)
168 {
169 struct circ_buf *xmit = &uap->port.state->xmit;
170 int count;
171
172 if (uap->port.x_char) {
173 writel(uap->port.x_char, uap->port.membase + UART01x_DR);
174 uap->port.icount.tx++;
175 uap->port.x_char = 0;
176 return;
177 }
178 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
179 pl010_stop_tx(&uap->port);
180 return;
181 }
182
183 count = uap->port.fifosize >> 1;
184 do {
185 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
186 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
187 uap->port.icount.tx++;
188 if (uart_circ_empty(xmit))
189 break;
190 } while (--count > 0);
191
192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
193 uart_write_wakeup(&uap->port);
194
195 if (uart_circ_empty(xmit))
196 pl010_stop_tx(&uap->port);
197 }
198
199 static void pl010_modem_status(struct uart_amba_port *uap)
200 {
201 unsigned int status, delta;
202
203 writel(0, uap->port.membase + UART010_ICR);
204
205 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
206
207 delta = status ^ uap->old_status;
208 uap->old_status = status;
209
210 if (!delta)
211 return;
212
213 if (delta & UART01x_FR_DCD)
214 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
215
216 if (delta & UART01x_FR_DSR)
217 uap->port.icount.dsr++;
218
219 if (delta & UART01x_FR_CTS)
220 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
221
222 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
223 }
224
225 static irqreturn_t pl010_int(int irq, void *dev_id)
226 {
227 struct uart_amba_port *uap = dev_id;
228 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
229 int handled = 0;
230
231 spin_lock(&uap->port.lock);
232
233 status = readb(uap->port.membase + UART010_IIR);
234 if (status) {
235 do {
236 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
237 pl010_rx_chars(uap);
238 if (status & UART010_IIR_MIS)
239 pl010_modem_status(uap);
240 if (status & UART010_IIR_TIS)
241 pl010_tx_chars(uap);
242
243 if (pass_counter-- == 0)
244 break;
245
246 status = readb(uap->port.membase + UART010_IIR);
247 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
248 UART010_IIR_TIS));
249 handled = 1;
250 }
251
252 spin_unlock(&uap->port.lock);
253
254 return IRQ_RETVAL(handled);
255 }
256
257 static unsigned int pl010_tx_empty(struct uart_port *port)
258 {
259 struct uart_amba_port *uap =
260 container_of(port, struct uart_amba_port, port);
261 unsigned int status = readb(uap->port.membase + UART01x_FR);
262 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
263 }
264
265 static unsigned int pl010_get_mctrl(struct uart_port *port)
266 {
267 struct uart_amba_port *uap =
268 container_of(port, struct uart_amba_port, port);
269 unsigned int result = 0;
270 unsigned int status;
271
272 status = readb(uap->port.membase + UART01x_FR);
273 if (status & UART01x_FR_DCD)
274 result |= TIOCM_CAR;
275 if (status & UART01x_FR_DSR)
276 result |= TIOCM_DSR;
277 if (status & UART01x_FR_CTS)
278 result |= TIOCM_CTS;
279
280 return result;
281 }
282
283 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
284 {
285 struct uart_amba_port *uap =
286 container_of(port, struct uart_amba_port, port);
287
288 if (uap->data)
289 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
290 }
291
292 static void pl010_break_ctl(struct uart_port *port, int break_state)
293 {
294 struct uart_amba_port *uap =
295 container_of(port, struct uart_amba_port, port);
296 unsigned long flags;
297 unsigned int lcr_h;
298
299 spin_lock_irqsave(&uap->port.lock, flags);
300 lcr_h = readb(uap->port.membase + UART010_LCRH);
301 if (break_state == -1)
302 lcr_h |= UART01x_LCRH_BRK;
303 else
304 lcr_h &= ~UART01x_LCRH_BRK;
305 writel(lcr_h, uap->port.membase + UART010_LCRH);
306 spin_unlock_irqrestore(&uap->port.lock, flags);
307 }
308
309 static int pl010_startup(struct uart_port *port)
310 {
311 struct uart_amba_port *uap =
312 container_of(port, struct uart_amba_port, port);
313 int retval;
314
315 /*
316 * Try to enable the clock producer.
317 */
318 retval = clk_prepare_enable(uap->clk);
319 if (retval)
320 goto out;
321
322 uap->port.uartclk = clk_get_rate(uap->clk);
323
324 /*
325 * Allocate the IRQ
326 */
327 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
328 if (retval)
329 goto clk_dis;
330
331 /*
332 * initialise the old status of the modem signals
333 */
334 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
335
336 /*
337 * Finally, enable interrupts
338 */
339 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
340 uap->port.membase + UART010_CR);
341
342 return 0;
343
344 clk_dis:
345 clk_disable_unprepare(uap->clk);
346 out:
347 return retval;
348 }
349
350 static void pl010_shutdown(struct uart_port *port)
351 {
352 struct uart_amba_port *uap =
353 container_of(port, struct uart_amba_port, port);
354
355 /*
356 * Free the interrupt
357 */
358 free_irq(uap->port.irq, uap);
359
360 /*
361 * disable all interrupts, disable the port
362 */
363 writel(0, uap->port.membase + UART010_CR);
364
365 /* disable break condition and fifos */
366 writel(readb(uap->port.membase + UART010_LCRH) &
367 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
368 uap->port.membase + UART010_LCRH);
369
370 /*
371 * Shut down the clock producer
372 */
373 clk_disable_unprepare(uap->clk);
374 }
375
376 static void
377 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
378 struct ktermios *old)
379 {
380 struct uart_amba_port *uap =
381 container_of(port, struct uart_amba_port, port);
382 unsigned int lcr_h, old_cr;
383 unsigned long flags;
384 unsigned int baud, quot;
385
386 /*
387 * Ask the core to calculate the divisor for us.
388 */
389 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
390 quot = uart_get_divisor(port, baud);
391
392 switch (termios->c_cflag & CSIZE) {
393 case CS5:
394 lcr_h = UART01x_LCRH_WLEN_5;
395 break;
396 case CS6:
397 lcr_h = UART01x_LCRH_WLEN_6;
398 break;
399 case CS7:
400 lcr_h = UART01x_LCRH_WLEN_7;
401 break;
402 default: // CS8
403 lcr_h = UART01x_LCRH_WLEN_8;
404 break;
405 }
406 if (termios->c_cflag & CSTOPB)
407 lcr_h |= UART01x_LCRH_STP2;
408 if (termios->c_cflag & PARENB) {
409 lcr_h |= UART01x_LCRH_PEN;
410 if (!(termios->c_cflag & PARODD))
411 lcr_h |= UART01x_LCRH_EPS;
412 }
413 if (uap->port.fifosize > 1)
414 lcr_h |= UART01x_LCRH_FEN;
415
416 spin_lock_irqsave(&uap->port.lock, flags);
417
418 /*
419 * Update the per-port timeout.
420 */
421 uart_update_timeout(port, termios->c_cflag, baud);
422
423 uap->port.read_status_mask = UART01x_RSR_OE;
424 if (termios->c_iflag & INPCK)
425 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
426 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
427 uap->port.read_status_mask |= UART01x_RSR_BE;
428
429 /*
430 * Characters to ignore
431 */
432 uap->port.ignore_status_mask = 0;
433 if (termios->c_iflag & IGNPAR)
434 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
435 if (termios->c_iflag & IGNBRK) {
436 uap->port.ignore_status_mask |= UART01x_RSR_BE;
437 /*
438 * If we're ignoring parity and break indicators,
439 * ignore overruns too (for real raw support).
440 */
441 if (termios->c_iflag & IGNPAR)
442 uap->port.ignore_status_mask |= UART01x_RSR_OE;
443 }
444
445 /*
446 * Ignore all characters if CREAD is not set.
447 */
448 if ((termios->c_cflag & CREAD) == 0)
449 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
450
451 /* first, disable everything */
452 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
453
454 if (UART_ENABLE_MS(port, termios->c_cflag))
455 old_cr |= UART010_CR_MSIE;
456
457 writel(0, uap->port.membase + UART010_CR);
458
459 /* Set baud rate */
460 quot -= 1;
461 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
462 writel(quot & 0xff, uap->port.membase + UART010_LCRL);
463
464 /*
465 * ----------v----------v----------v----------v-----
466 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
467 * ----------^----------^----------^----------^-----
468 */
469 writel(lcr_h, uap->port.membase + UART010_LCRH);
470 writel(old_cr, uap->port.membase + UART010_CR);
471
472 spin_unlock_irqrestore(&uap->port.lock, flags);
473 }
474
475 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
476 {
477 if (termios->c_line == N_PPS) {
478 port->flags |= UPF_HARDPPS_CD;
479 spin_lock_irq(&port->lock);
480 pl010_enable_ms(port);
481 spin_unlock_irq(&port->lock);
482 } else {
483 port->flags &= ~UPF_HARDPPS_CD;
484 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
485 spin_lock_irq(&port->lock);
486 pl010_disable_ms(port);
487 spin_unlock_irq(&port->lock);
488 }
489 }
490 }
491
492 static const char *pl010_type(struct uart_port *port)
493 {
494 return port->type == PORT_AMBA ? "AMBA" : NULL;
495 }
496
497 /*
498 * Release the memory region(s) being used by 'port'
499 */
500 static void pl010_release_port(struct uart_port *port)
501 {
502 release_mem_region(port->mapbase, UART_PORT_SIZE);
503 }
504
505 /*
506 * Request the memory region(s) being used by 'port'
507 */
508 static int pl010_request_port(struct uart_port *port)
509 {
510 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
511 != NULL ? 0 : -EBUSY;
512 }
513
514 /*
515 * Configure/autoconfigure the port.
516 */
517 static void pl010_config_port(struct uart_port *port, int flags)
518 {
519 if (flags & UART_CONFIG_TYPE) {
520 port->type = PORT_AMBA;
521 pl010_request_port(port);
522 }
523 }
524
525 /*
526 * verify the new serial_struct (for TIOCSSERIAL).
527 */
528 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
529 {
530 int ret = 0;
531 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
532 ret = -EINVAL;
533 if (ser->irq < 0 || ser->irq >= nr_irqs)
534 ret = -EINVAL;
535 if (ser->baud_base < 9600)
536 ret = -EINVAL;
537 return ret;
538 }
539
540 static const struct uart_ops amba_pl010_pops = {
541 .tx_empty = pl010_tx_empty,
542 .set_mctrl = pl010_set_mctrl,
543 .get_mctrl = pl010_get_mctrl,
544 .stop_tx = pl010_stop_tx,
545 .start_tx = pl010_start_tx,
546 .stop_rx = pl010_stop_rx,
547 .enable_ms = pl010_enable_ms,
548 .break_ctl = pl010_break_ctl,
549 .startup = pl010_startup,
550 .shutdown = pl010_shutdown,
551 .set_termios = pl010_set_termios,
552 .set_ldisc = pl010_set_ldisc,
553 .type = pl010_type,
554 .release_port = pl010_release_port,
555 .request_port = pl010_request_port,
556 .config_port = pl010_config_port,
557 .verify_port = pl010_verify_port,
558 };
559
560 static struct uart_amba_port *amba_ports[UART_NR];
561
562 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
563
564 static void pl010_console_putchar(struct uart_port *port, int ch)
565 {
566 struct uart_amba_port *uap =
567 container_of(port, struct uart_amba_port, port);
568 unsigned int status;
569
570 do {
571 status = readb(uap->port.membase + UART01x_FR);
572 barrier();
573 } while (!UART_TX_READY(status));
574 writel(ch, uap->port.membase + UART01x_DR);
575 }
576
577 static void
578 pl010_console_write(struct console *co, const char *s, unsigned int count)
579 {
580 struct uart_amba_port *uap = amba_ports[co->index];
581 unsigned int status, old_cr;
582
583 clk_enable(uap->clk);
584
585 /*
586 * First save the CR then disable the interrupts
587 */
588 old_cr = readb(uap->port.membase + UART010_CR);
589 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
590
591 uart_console_write(&uap->port, s, count, pl010_console_putchar);
592
593 /*
594 * Finally, wait for transmitter to become empty
595 * and restore the TCR
596 */
597 do {
598 status = readb(uap->port.membase + UART01x_FR);
599 barrier();
600 } while (status & UART01x_FR_BUSY);
601 writel(old_cr, uap->port.membase + UART010_CR);
602
603 clk_disable(uap->clk);
604 }
605
606 static void __init
607 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
608 int *parity, int *bits)
609 {
610 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
611 unsigned int lcr_h, quot;
612 lcr_h = readb(uap->port.membase + UART010_LCRH);
613
614 *parity = 'n';
615 if (lcr_h & UART01x_LCRH_PEN) {
616 if (lcr_h & UART01x_LCRH_EPS)
617 *parity = 'e';
618 else
619 *parity = 'o';
620 }
621
622 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
623 *bits = 7;
624 else
625 *bits = 8;
626
627 quot = readb(uap->port.membase + UART010_LCRL) |
628 readb(uap->port.membase + UART010_LCRM) << 8;
629 *baud = uap->port.uartclk / (16 * (quot + 1));
630 }
631 }
632
633 static int __init pl010_console_setup(struct console *co, char *options)
634 {
635 struct uart_amba_port *uap;
636 int baud = 38400;
637 int bits = 8;
638 int parity = 'n';
639 int flow = 'n';
640 int ret;
641
642 /*
643 * Check whether an invalid uart number has been specified, and
644 * if so, search for the first available port that does have
645 * console support.
646 */
647 if (co->index >= UART_NR)
648 co->index = 0;
649 uap = amba_ports[co->index];
650 if (!uap)
651 return -ENODEV;
652
653 ret = clk_prepare(uap->clk);
654 if (ret)
655 return ret;
656
657 uap->port.uartclk = clk_get_rate(uap->clk);
658
659 if (options)
660 uart_parse_options(options, &baud, &parity, &bits, &flow);
661 else
662 pl010_console_get_options(uap, &baud, &parity, &bits);
663
664 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
665 }
666
667 static struct uart_driver amba_reg;
668 static struct console amba_console = {
669 .name = "ttyAM",
670 .write = pl010_console_write,
671 .device = uart_console_device,
672 .setup = pl010_console_setup,
673 .flags = CON_PRINTBUFFER,
674 .index = -1,
675 .data = &amba_reg,
676 };
677
678 #define AMBA_CONSOLE &amba_console
679 #else
680 #define AMBA_CONSOLE NULL
681 #endif
682
683 static DEFINE_MUTEX(amba_reg_lock);
684 static struct uart_driver amba_reg = {
685 .owner = THIS_MODULE,
686 .driver_name = "ttyAM",
687 .dev_name = "ttyAM",
688 .major = SERIAL_AMBA_MAJOR,
689 .minor = SERIAL_AMBA_MINOR,
690 .nr = UART_NR,
691 .cons = AMBA_CONSOLE,
692 };
693
694 static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
695 {
696 struct uart_amba_port *uap;
697 void __iomem *base;
698 int i, ret;
699
700 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
701 if (amba_ports[i] == NULL)
702 break;
703
704 if (i == ARRAY_SIZE(amba_ports))
705 return -EBUSY;
706
707 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
708 GFP_KERNEL);
709 if (!uap)
710 return -ENOMEM;
711
712 base = devm_ioremap(&dev->dev, dev->res.start,
713 resource_size(&dev->res));
714 if (!base)
715 return -ENOMEM;
716
717 uap->clk = devm_clk_get(&dev->dev, NULL);
718 if (IS_ERR(uap->clk))
719 return PTR_ERR(uap->clk);
720
721 uap->port.dev = &dev->dev;
722 uap->port.mapbase = dev->res.start;
723 uap->port.membase = base;
724 uap->port.iotype = UPIO_MEM;
725 uap->port.irq = dev->irq[0];
726 uap->port.fifosize = 16;
727 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL010_CONSOLE);
728 uap->port.ops = &amba_pl010_pops;
729 uap->port.flags = UPF_BOOT_AUTOCONF;
730 uap->port.line = i;
731 uap->dev = dev;
732 uap->data = dev_get_platdata(&dev->dev);
733
734 amba_ports[i] = uap;
735
736 amba_set_drvdata(dev, uap);
737
738 mutex_lock(&amba_reg_lock);
739 if (!amba_reg.state) {
740 ret = uart_register_driver(&amba_reg);
741 if (ret < 0) {
742 mutex_unlock(&amba_reg_lock);
743 dev_err(uap->port.dev,
744 "Failed to register AMBA-PL010 driver\n");
745 return ret;
746 }
747 }
748 mutex_unlock(&amba_reg_lock);
749
750 ret = uart_add_one_port(&amba_reg, &uap->port);
751 if (ret)
752 amba_ports[i] = NULL;
753
754 return ret;
755 }
756
757 static int pl010_remove(struct amba_device *dev)
758 {
759 struct uart_amba_port *uap = amba_get_drvdata(dev);
760 int i;
761 bool busy = false;
762
763 uart_remove_one_port(&amba_reg, &uap->port);
764
765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
766 if (amba_ports[i] == uap)
767 amba_ports[i] = NULL;
768 else if (amba_ports[i])
769 busy = true;
770
771 if (!busy)
772 uart_unregister_driver(&amba_reg);
773
774 return 0;
775 }
776
777 #ifdef CONFIG_PM_SLEEP
778 static int pl010_suspend(struct device *dev)
779 {
780 struct uart_amba_port *uap = dev_get_drvdata(dev);
781
782 if (uap)
783 uart_suspend_port(&amba_reg, &uap->port);
784
785 return 0;
786 }
787
788 static int pl010_resume(struct device *dev)
789 {
790 struct uart_amba_port *uap = dev_get_drvdata(dev);
791
792 if (uap)
793 uart_resume_port(&amba_reg, &uap->port);
794
795 return 0;
796 }
797 #endif
798
799 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
800
801 static const struct amba_id pl010_ids[] = {
802 {
803 .id = 0x00041010,
804 .mask = 0x000fffff,
805 },
806 { 0, 0 },
807 };
808
809 MODULE_DEVICE_TABLE(amba, pl010_ids);
810
811 static struct amba_driver pl010_driver = {
812 .drv = {
813 .name = "uart-pl010",
814 .pm = &pl010_dev_pm_ops,
815 },
816 .id_table = pl010_ids,
817 .probe = pl010_probe,
818 .remove = pl010_remove,
819 };
820
821 static int __init pl010_init(void)
822 {
823 printk(KERN_INFO "Serial: AMBA driver\n");
824
825 return amba_driver_register(&pl010_driver);
826 }
827
828 static void __exit pl010_exit(void)
829 {
830 amba_driver_unregister(&pl010_driver);
831 }
832
833 module_init(pl010_init);
834 module_exit(pl010_exit);
835
836 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
837 MODULE_DESCRIPTION("ARM AMBA serial port driver");
838 MODULE_LICENSE("GPL");
Linux with added FPC-III support