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dm writecache: add cond_resched to loop in persistent_memory_claim()
[linux/fpc-iii.git] / drivers / tty / serial / sa1100.c
blob75c2a22895f90514fb2cc3b3788b63454d8568ed
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for SA11x0 serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 */
9
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/sysrq.h>
15 #include <linux/platform_data/sa11x0-serial.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/io.h>
22
23 #include <asm/irq.h>
24 #include <mach/hardware.h>
25 #include <mach/irqs.h>
26
27 #include "serial_mctrl_gpio.h"
28
29 /* We've been assigned a range on the "Low-density serial ports" major */
30 #define SERIAL_SA1100_MAJOR 204
31 #define MINOR_START 5
32
33 #define NR_PORTS 3
34
35 #define SA1100_ISR_PASS_LIMIT 256
36
37 /*
38 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
39 */
40 #define SM_TO_UTSR0(x) ((x) & 0xff)
41 #define SM_TO_UTSR1(x) ((x) >> 8)
42 #define UTSR0_TO_SM(x) ((x))
43 #define UTSR1_TO_SM(x) ((x) << 8)
44
45 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
46 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
47 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
48 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
49 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
50 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
51 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
52
53 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
54 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
55 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
56 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
57 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
58 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
59 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
60
61 /*
62 * This is the size of our serial port register set.
63 */
64 #define UART_PORT_SIZE 0x24
65
66 /*
67 * This determines how often we check the modem status signals
68 * for any change. They generally aren't connected to an IRQ
69 * so we have to poll them. We also check immediately before
70 * filling the TX fifo incase CTS has been dropped.
71 */
72 #define MCTRL_TIMEOUT (250*HZ/1000)
73
74 struct sa1100_port {
75 struct uart_port port;
76 struct timer_list timer;
77 unsigned int old_status;
78 struct mctrl_gpios *gpios;
79 };
80
81 /*
82 * Handle any change of modem status signal since we were last called.
83 */
84 static void sa1100_mctrl_check(struct sa1100_port *sport)
85 {
86 unsigned int status, changed;
87
88 status = sport->port.ops->get_mctrl(&sport->port);
89 changed = status ^ sport->old_status;
90
91 if (changed == 0)
92 return;
93
94 sport->old_status = status;
95
96 if (changed & TIOCM_RI)
97 sport->port.icount.rng++;
98 if (changed & TIOCM_DSR)
99 sport->port.icount.dsr++;
100 if (changed & TIOCM_CAR)
101 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
102 if (changed & TIOCM_CTS)
103 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
104
105 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
106 }
107
108 /*
109 * This is our per-port timeout handler, for checking the
110 * modem status signals.
111 */
112 static void sa1100_timeout(struct timer_list *t)
113 {
114 struct sa1100_port *sport = from_timer(sport, t, timer);
115 unsigned long flags;
116
117 if (sport->port.state) {
118 spin_lock_irqsave(&sport->port.lock, flags);
119 sa1100_mctrl_check(sport);
120 spin_unlock_irqrestore(&sport->port.lock, flags);
121
122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
123 }
124 }
125
126 /*
127 * interrupts disabled on entry
128 */
129 static void sa1100_stop_tx(struct uart_port *port)
130 {
131 struct sa1100_port *sport =
132 container_of(port, struct sa1100_port, port);
133 u32 utcr3;
134
135 utcr3 = UART_GET_UTCR3(sport);
136 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
137 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
138 }
139
140 /*
141 * port locked and interrupts disabled
142 */
143 static void sa1100_start_tx(struct uart_port *port)
144 {
145 struct sa1100_port *sport =
146 container_of(port, struct sa1100_port, port);
147 u32 utcr3;
148
149 utcr3 = UART_GET_UTCR3(sport);
150 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
151 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
152 }
153
154 /*
155 * Interrupts enabled
156 */
157 static void sa1100_stop_rx(struct uart_port *port)
158 {
159 struct sa1100_port *sport =
160 container_of(port, struct sa1100_port, port);
161 u32 utcr3;
162
163 utcr3 = UART_GET_UTCR3(sport);
164 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
165 }
166
167 /*
168 * Set the modem control timer to fire immediately.
169 */
170 static void sa1100_enable_ms(struct uart_port *port)
171 {
172 struct sa1100_port *sport =
173 container_of(port, struct sa1100_port, port);
174
175 mod_timer(&sport->timer, jiffies);
176
177 mctrl_gpio_enable_ms(sport->gpios);
178 }
179
180 static void
181 sa1100_rx_chars(struct sa1100_port *sport)
182 {
183 unsigned int status, ch, flg;
184
185 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
186 UTSR0_TO_SM(UART_GET_UTSR0(sport));
187 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
188 ch = UART_GET_CHAR(sport);
189
190 sport->port.icount.rx++;
191
192 flg = TTY_NORMAL;
193
194 /*
195 * note that the error handling code is
196 * out of the main execution path
197 */
198 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
199 if (status & UTSR1_TO_SM(UTSR1_PRE))
200 sport->port.icount.parity++;
201 else if (status & UTSR1_TO_SM(UTSR1_FRE))
202 sport->port.icount.frame++;
203 if (status & UTSR1_TO_SM(UTSR1_ROR))
204 sport->port.icount.overrun++;
205
206 status &= sport->port.read_status_mask;
207
208 if (status & UTSR1_TO_SM(UTSR1_PRE))
209 flg = TTY_PARITY;
210 else if (status & UTSR1_TO_SM(UTSR1_FRE))
211 flg = TTY_FRAME;
212
213 sport->port.sysrq = 0;
214 }
215
216 if (uart_handle_sysrq_char(&sport->port, ch))
217 goto ignore_char;
218
219 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
220
221 ignore_char:
222 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
223 UTSR0_TO_SM(UART_GET_UTSR0(sport));
224 }
225
226 spin_unlock(&sport->port.lock);
227 tty_flip_buffer_push(&sport->port.state->port);
228 spin_lock(&sport->port.lock);
229 }
230
231 static void sa1100_tx_chars(struct sa1100_port *sport)
232 {
233 struct circ_buf *xmit = &sport->port.state->xmit;
234
235 if (sport->port.x_char) {
236 UART_PUT_CHAR(sport, sport->port.x_char);
237 sport->port.icount.tx++;
238 sport->port.x_char = 0;
239 return;
240 }
241
242 /*
243 * Check the modem control lines before
244 * transmitting anything.
245 */
246 sa1100_mctrl_check(sport);
247
248 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
249 sa1100_stop_tx(&sport->port);
250 return;
251 }
252
253 /*
254 * Tried using FIFO (not checking TNF) for fifo fill:
255 * still had the '4 bytes repeated' problem.
256 */
257 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
258 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
259 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
260 sport->port.icount.tx++;
261 if (uart_circ_empty(xmit))
262 break;
263 }
264
265 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
266 uart_write_wakeup(&sport->port);
267
268 if (uart_circ_empty(xmit))
269 sa1100_stop_tx(&sport->port);
270 }
271
272 static irqreturn_t sa1100_int(int irq, void *dev_id)
273 {
274 struct sa1100_port *sport = dev_id;
275 unsigned int status, pass_counter = 0;
276
277 spin_lock(&sport->port.lock);
278 status = UART_GET_UTSR0(sport);
279 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
280 do {
281 if (status & (UTSR0_RFS | UTSR0_RID)) {
282 /* Clear the receiver idle bit, if set */
283 if (status & UTSR0_RID)
284 UART_PUT_UTSR0(sport, UTSR0_RID);
285 sa1100_rx_chars(sport);
286 }
287
288 /* Clear the relevant break bits */
289 if (status & (UTSR0_RBB | UTSR0_REB))
290 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
291
292 if (status & UTSR0_RBB)
293 sport->port.icount.brk++;
294
295 if (status & UTSR0_REB)
296 uart_handle_break(&sport->port);
297
298 if (status & UTSR0_TFS)
299 sa1100_tx_chars(sport);
300 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
301 break;
302 status = UART_GET_UTSR0(sport);
303 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
304 ~UTSR0_TFS;
305 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
306 spin_unlock(&sport->port.lock);
307
308 return IRQ_HANDLED;
309 }
310
311 /*
312 * Return TIOCSER_TEMT when transmitter is not busy.
313 */
314 static unsigned int sa1100_tx_empty(struct uart_port *port)
315 {
316 struct sa1100_port *sport =
317 container_of(port, struct sa1100_port, port);
318
319 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
320 }
321
322 static unsigned int sa1100_get_mctrl(struct uart_port *port)
323 {
324 struct sa1100_port *sport =
325 container_of(port, struct sa1100_port, port);
326 int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
327
328 mctrl_gpio_get(sport->gpios, &ret);
329
330 return ret;
331 }
332
333 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
334 {
335 struct sa1100_port *sport =
336 container_of(port, struct sa1100_port, port);
337
338 mctrl_gpio_set(sport->gpios, mctrl);
339 }
340
341 /*
342 * Interrupts always disabled.
343 */
344 static void sa1100_break_ctl(struct uart_port *port, int break_state)
345 {
346 struct sa1100_port *sport =
347 container_of(port, struct sa1100_port, port);
348 unsigned long flags;
349 unsigned int utcr3;
350
351 spin_lock_irqsave(&sport->port.lock, flags);
352 utcr3 = UART_GET_UTCR3(sport);
353 if (break_state == -1)
354 utcr3 |= UTCR3_BRK;
355 else
356 utcr3 &= ~UTCR3_BRK;
357 UART_PUT_UTCR3(sport, utcr3);
358 spin_unlock_irqrestore(&sport->port.lock, flags);
359 }
360
361 static int sa1100_startup(struct uart_port *port)
362 {
363 struct sa1100_port *sport =
364 container_of(port, struct sa1100_port, port);
365 int retval;
366
367 /*
368 * Allocate the IRQ
369 */
370 retval = request_irq(sport->port.irq, sa1100_int, 0,
371 "sa11x0-uart", sport);
372 if (retval)
373 return retval;
374
375 /*
376 * Finally, clear and enable interrupts
377 */
378 UART_PUT_UTSR0(sport, -1);
379 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
380
381 /*
382 * Enable modem status interrupts
383 */
384 spin_lock_irq(&sport->port.lock);
385 sa1100_enable_ms(&sport->port);
386 spin_unlock_irq(&sport->port.lock);
387
388 return 0;
389 }
390
391 static void sa1100_shutdown(struct uart_port *port)
392 {
393 struct sa1100_port *sport =
394 container_of(port, struct sa1100_port, port);
395
396 /*
397 * Stop our timer.
398 */
399 del_timer_sync(&sport->timer);
400
401 /*
402 * Free the interrupt
403 */
404 free_irq(sport->port.irq, sport);
405
406 /*
407 * Disable all interrupts, port and break condition.
408 */
409 UART_PUT_UTCR3(sport, 0);
410 }
411
412 static void
413 sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
414 struct ktermios *old)
415 {
416 struct sa1100_port *sport =
417 container_of(port, struct sa1100_port, port);
418 unsigned long flags;
419 unsigned int utcr0, old_utcr3, baud, quot;
420 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
421
422 /*
423 * We only support CS7 and CS8.
424 */
425 while ((termios->c_cflag & CSIZE) != CS7 &&
426 (termios->c_cflag & CSIZE) != CS8) {
427 termios->c_cflag &= ~CSIZE;
428 termios->c_cflag |= old_csize;
429 old_csize = CS8;
430 }
431
432 if ((termios->c_cflag & CSIZE) == CS8)
433 utcr0 = UTCR0_DSS;
434 else
435 utcr0 = 0;
436
437 if (termios->c_cflag & CSTOPB)
438 utcr0 |= UTCR0_SBS;
439 if (termios->c_cflag & PARENB) {
440 utcr0 |= UTCR0_PE;
441 if (!(termios->c_cflag & PARODD))
442 utcr0 |= UTCR0_OES;
443 }
444
445 /*
446 * Ask the core to calculate the divisor for us.
447 */
448 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
449 quot = uart_get_divisor(port, baud);
450
451 spin_lock_irqsave(&sport->port.lock, flags);
452
453 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
454 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
455 if (termios->c_iflag & INPCK)
456 sport->port.read_status_mask |=
457 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
458 if (termios->c_iflag & (BRKINT | PARMRK))
459 sport->port.read_status_mask |=
460 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
461
462 /*
463 * Characters to ignore
464 */
465 sport->port.ignore_status_mask = 0;
466 if (termios->c_iflag & IGNPAR)
467 sport->port.ignore_status_mask |=
468 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
469 if (termios->c_iflag & IGNBRK) {
470 sport->port.ignore_status_mask |=
471 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
472 /*
473 * If we're ignoring parity and break indicators,
474 * ignore overruns too (for real raw support).
475 */
476 if (termios->c_iflag & IGNPAR)
477 sport->port.ignore_status_mask |=
478 UTSR1_TO_SM(UTSR1_ROR);
479 }
480
481 del_timer_sync(&sport->timer);
482
483 /*
484 * Update the per-port timeout.
485 */
486 uart_update_timeout(port, termios->c_cflag, baud);
487
488 /*
489 * disable interrupts and drain transmitter
490 */
491 old_utcr3 = UART_GET_UTCR3(sport);
492 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
493
494 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
495 barrier();
496
497 /* then, disable everything */
498 UART_PUT_UTCR3(sport, 0);
499
500 /* set the parity, stop bits and data size */
501 UART_PUT_UTCR0(sport, utcr0);
502
503 /* set the baud rate */
504 quot -= 1;
505 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
506 UART_PUT_UTCR2(sport, (quot & 0xff));
507
508 UART_PUT_UTSR0(sport, -1);
509
510 UART_PUT_UTCR3(sport, old_utcr3);
511
512 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
513 sa1100_enable_ms(&sport->port);
514
515 spin_unlock_irqrestore(&sport->port.lock, flags);
516 }
517
518 static const char *sa1100_type(struct uart_port *port)
519 {
520 struct sa1100_port *sport =
521 container_of(port, struct sa1100_port, port);
522
523 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
524 }
525
526 /*
527 * Release the memory region(s) being used by 'port'.
528 */
529 static void sa1100_release_port(struct uart_port *port)
530 {
531 struct sa1100_port *sport =
532 container_of(port, struct sa1100_port, port);
533
534 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
535 }
536
537 /*
538 * Request the memory region(s) being used by 'port'.
539 */
540 static int sa1100_request_port(struct uart_port *port)
541 {
542 struct sa1100_port *sport =
543 container_of(port, struct sa1100_port, port);
544
545 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
546 "sa11x0-uart") != NULL ? 0 : -EBUSY;
547 }
548
549 /*
550 * Configure/autoconfigure the port.
551 */
552 static void sa1100_config_port(struct uart_port *port, int flags)
553 {
554 struct sa1100_port *sport =
555 container_of(port, struct sa1100_port, port);
556
557 if (flags & UART_CONFIG_TYPE &&
558 sa1100_request_port(&sport->port) == 0)
559 sport->port.type = PORT_SA1100;
560 }
561
562 /*
563 * Verify the new serial_struct (for TIOCSSERIAL).
564 * The only change we allow are to the flags and type, and
565 * even then only between PORT_SA1100 and PORT_UNKNOWN
566 */
567 static int
568 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
569 {
570 struct sa1100_port *sport =
571 container_of(port, struct sa1100_port, port);
572 int ret = 0;
573
574 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
575 ret = -EINVAL;
576 if (sport->port.irq != ser->irq)
577 ret = -EINVAL;
578 if (ser->io_type != SERIAL_IO_MEM)
579 ret = -EINVAL;
580 if (sport->port.uartclk / 16 != ser->baud_base)
581 ret = -EINVAL;
582 if ((void *)sport->port.mapbase != ser->iomem_base)
583 ret = -EINVAL;
584 if (sport->port.iobase != ser->port)
585 ret = -EINVAL;
586 if (ser->hub6 != 0)
587 ret = -EINVAL;
588 return ret;
589 }
590
591 static struct uart_ops sa1100_pops = {
592 .tx_empty = sa1100_tx_empty,
593 .set_mctrl = sa1100_set_mctrl,
594 .get_mctrl = sa1100_get_mctrl,
595 .stop_tx = sa1100_stop_tx,
596 .start_tx = sa1100_start_tx,
597 .stop_rx = sa1100_stop_rx,
598 .enable_ms = sa1100_enable_ms,
599 .break_ctl = sa1100_break_ctl,
600 .startup = sa1100_startup,
601 .shutdown = sa1100_shutdown,
602 .set_termios = sa1100_set_termios,
603 .type = sa1100_type,
604 .release_port = sa1100_release_port,
605 .request_port = sa1100_request_port,
606 .config_port = sa1100_config_port,
607 .verify_port = sa1100_verify_port,
608 };
609
610 static struct sa1100_port sa1100_ports[NR_PORTS];
611
612 /*
613 * Setup the SA1100 serial ports. Note that we don't include the IrDA
614 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
615 *
616 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
617 * Which serial port this ends up being depends on the machine you're
618 * running this kernel on. I'm not convinced that this is a good idea,
619 * but that's the way it traditionally works.
620 *
621 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
622 * used here.
623 */
624 static void __init sa1100_init_ports(void)
625 {
626 static int first = 1;
627 int i;
628
629 if (!first)
630 return;
631 first = 0;
632
633 for (i = 0; i < NR_PORTS; i++) {
634 sa1100_ports[i].port.uartclk = 3686400;
635 sa1100_ports[i].port.ops = &sa1100_pops;
636 sa1100_ports[i].port.fifosize = 8;
637 sa1100_ports[i].port.line = i;
638 sa1100_ports[i].port.iotype = UPIO_MEM;
639 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
640 }
641
642 /*
643 * make transmit lines outputs, so that when the port
644 * is closed, the output is in the MARK state.
645 */
646 PPDR |= PPC_TXD1 | PPC_TXD3;
647 PPSR |= PPC_TXD1 | PPC_TXD3;
648 }
649
650 void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
651 {
652 if (fns->get_mctrl)
653 sa1100_pops.get_mctrl = fns->get_mctrl;
654 if (fns->set_mctrl)
655 sa1100_pops.set_mctrl = fns->set_mctrl;
656
657 sa1100_pops.pm = fns->pm;
658 /*
659 * FIXME: fns->set_wake is unused - this should be called from
660 * the suspend() callback if device_may_wakeup(dev)) is set.
661 */
662 }
663
664 void __init sa1100_register_uart(int idx, int port)
665 {
666 if (idx >= NR_PORTS) {
667 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
668 return;
669 }
670
671 switch (port) {
672 case 1:
673 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
674 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
675 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
676 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
677 break;
678
679 case 2:
680 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
681 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
682 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
683 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
684 break;
685
686 case 3:
687 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
688 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
689 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
690 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
691 break;
692
693 default:
694 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
695 }
696 }
697
698
699 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
700 static void sa1100_console_putchar(struct uart_port *port, int ch)
701 {
702 struct sa1100_port *sport =
703 container_of(port, struct sa1100_port, port);
704
705 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
706 barrier();
707 UART_PUT_CHAR(sport, ch);
708 }
709
710 /*
711 * Interrupts are disabled on entering
712 */
713 static void
714 sa1100_console_write(struct console *co, const char *s, unsigned int count)
715 {
716 struct sa1100_port *sport = &sa1100_ports[co->index];
717 unsigned int old_utcr3, status;
718
719 /*
720 * First, save UTCR3 and then disable interrupts
721 */
722 old_utcr3 = UART_GET_UTCR3(sport);
723 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
724 UTCR3_TXE);
725
726 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
727
728 /*
729 * Finally, wait for transmitter to become empty
730 * and restore UTCR3
731 */
732 do {
733 status = UART_GET_UTSR1(sport);
734 } while (status & UTSR1_TBY);
735 UART_PUT_UTCR3(sport, old_utcr3);
736 }
737
738 /*
739 * If the port was already initialised (eg, by a boot loader),
740 * try to determine the current setup.
741 */
742 static void __init
743 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
744 int *parity, int *bits)
745 {
746 unsigned int utcr3;
747
748 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
749 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
750 /* ok, the port was enabled */
751 unsigned int utcr0, quot;
752
753 utcr0 = UART_GET_UTCR0(sport);
754
755 *parity = 'n';
756 if (utcr0 & UTCR0_PE) {
757 if (utcr0 & UTCR0_OES)
758 *parity = 'e';
759 else
760 *parity = 'o';
761 }
762
763 if (utcr0 & UTCR0_DSS)
764 *bits = 8;
765 else
766 *bits = 7;
767
768 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
769 quot &= 0xfff;
770 *baud = sport->port.uartclk / (16 * (quot + 1));
771 }
772 }
773
774 static int __init
775 sa1100_console_setup(struct console *co, char *options)
776 {
777 struct sa1100_port *sport;
778 int baud = 9600;
779 int bits = 8;
780 int parity = 'n';
781 int flow = 'n';
782
783 /*
784 * Check whether an invalid uart number has been specified, and
785 * if so, search for the first available port that does have
786 * console support.
787 */
788 if (co->index == -1 || co->index >= NR_PORTS)
789 co->index = 0;
790 sport = &sa1100_ports[co->index];
791
792 if (options)
793 uart_parse_options(options, &baud, &parity, &bits, &flow);
794 else
795 sa1100_console_get_options(sport, &baud, &parity, &bits);
796
797 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
798 }
799
800 static struct uart_driver sa1100_reg;
801 static struct console sa1100_console = {
802 .name = "ttySA",
803 .write = sa1100_console_write,
804 .device = uart_console_device,
805 .setup = sa1100_console_setup,
806 .flags = CON_PRINTBUFFER,
807 .index = -1,
808 .data = &sa1100_reg,
809 };
810
811 static int __init sa1100_rs_console_init(void)
812 {
813 sa1100_init_ports();
814 register_console(&sa1100_console);
815 return 0;
816 }
817 console_initcall(sa1100_rs_console_init);
818
819 #define SA1100_CONSOLE &sa1100_console
820 #else
821 #define SA1100_CONSOLE NULL
822 #endif
823
824 static struct uart_driver sa1100_reg = {
825 .owner = THIS_MODULE,
826 .driver_name = "ttySA",
827 .dev_name = "ttySA",
828 .major = SERIAL_SA1100_MAJOR,
829 .minor = MINOR_START,
830 .nr = NR_PORTS,
831 .cons = SA1100_CONSOLE,
832 };
833
834 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
835 {
836 struct sa1100_port *sport = platform_get_drvdata(dev);
837
838 if (sport)
839 uart_suspend_port(&sa1100_reg, &sport->port);
840
841 return 0;
842 }
843
844 static int sa1100_serial_resume(struct platform_device *dev)
845 {
846 struct sa1100_port *sport = platform_get_drvdata(dev);
847
848 if (sport)
849 uart_resume_port(&sa1100_reg, &sport->port);
850
851 return 0;
852 }
853
854 static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
855 {
856 sport->port.dev = &dev->dev;
857 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);
858
859 // mctrl_gpio_init() requires that the GPIO driver supports interrupts,
860 // but we need to support GPIO drivers for hardware that has no such
861 // interrupts. Use mctrl_gpio_init_noauto() instead.
862 sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
863 if (IS_ERR(sport->gpios)) {
864 int err = PTR_ERR(sport->gpios);
865
866 dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
867 err);
868
869 if (err == -EPROBE_DEFER)
870 return err;
871
872 sport->gpios = NULL;
873 }
874
875 platform_set_drvdata(dev, sport);
876
877 return uart_add_one_port(&sa1100_reg, &sport->port);
878 }
879
880 static int sa1100_serial_probe(struct platform_device *dev)
881 {
882 struct resource *res = dev->resource;
883 int i;
884
885 for (i = 0; i < dev->num_resources; i++, res++)
886 if (res->flags & IORESOURCE_MEM)
887 break;
888
889 if (i < dev->num_resources) {
890 for (i = 0; i < NR_PORTS; i++) {
891 if (sa1100_ports[i].port.mapbase != res->start)
892 continue;
893
894 sa1100_serial_add_one_port(&sa1100_ports[i], dev);
895 break;
896 }
897 }
898
899 return 0;
900 }
901
902 static int sa1100_serial_remove(struct platform_device *pdev)
903 {
904 struct sa1100_port *sport = platform_get_drvdata(pdev);
905
906 if (sport)
907 uart_remove_one_port(&sa1100_reg, &sport->port);
908
909 return 0;
910 }
911
912 static struct platform_driver sa11x0_serial_driver = {
913 .probe = sa1100_serial_probe,
914 .remove = sa1100_serial_remove,
915 .suspend = sa1100_serial_suspend,
916 .resume = sa1100_serial_resume,
917 .driver = {
918 .name = "sa11x0-uart",
919 },
920 };
921
922 static int __init sa1100_serial_init(void)
923 {
924 int ret;
925
926 printk(KERN_INFO "Serial: SA11x0 driver\n");
927
928 sa1100_init_ports();
929
930 ret = uart_register_driver(&sa1100_reg);
931 if (ret == 0) {
932 ret = platform_driver_register(&sa11x0_serial_driver);
933 if (ret)
934 uart_unregister_driver(&sa1100_reg);
935 }
936 return ret;
937 }
938
939 static void __exit sa1100_serial_exit(void)
940 {
941 platform_driver_unregister(&sa11x0_serial_driver);
942 uart_unregister_driver(&sa1100_reg);
943 }
944
945 module_init(sa1100_serial_init);
946 module_exit(sa1100_serial_exit);
947
948 MODULE_AUTHOR("Deep Blue Solutions Ltd");
949 MODULE_DESCRIPTION("SA1100 generic serial port driver");
950 MODULE_LICENSE("GPL");
951 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
952 MODULE_ALIAS("platform:sa11x0-uart");
Linux with added FPC-III support