drivers/clocksource/acpi_pm.c

   1 /*
   2  * linux/drivers/clocksource/acpi_pm.c
   3  *
   4  * This file contains the ACPI PM based clocksource.
   5  *
   6  * This code was largely moved from the i386 timer_pm.c file
   7  * which was (C) Dominik Brodowski <linux@brodo.de> 2003
   8  * and contained the following comments:
   9  *
  10  * Driver to use the Power Management Timer (PMTMR) available in some
  11  * southbridges as primary timing source for the Linux kernel.
  12  *
  13  * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
  14  * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
  15  *
  16  * This file is licensed under the GPL v2.
  17  */
  18
  19 #include <linux/acpi_pmtmr.h>
  20 #include <linux/clocksource.h>
  21 #include <linux/timex.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/pci.h>
  25 #include <linux/delay.h>
  26 #include <asm/io.h>
  27
  28 /*
  29  * The I/O port the PMTMR resides at.
  30  * The location is detected during setup_arch(),
  31  * in arch/i386/kernel/acpi/boot.c
  32  */
  33 u32 pmtmr_ioport __read_mostly;
  34
  35 static inline u32 read_pmtmr(void)
  36 {
  37         /* mask the output to 24 bits */
  38         return inl(pmtmr_ioport) & ACPI_PM_MASK;
  39 }
  40
  41 u32 acpi_pm_read_verified(void)
  42 {
  43         u32 v1 = 0, v2 = 0, v3 = 0;
  44
  45         /*
  46          * It has been reported that because of various broken
  47          * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
  48          * source is not latched, you must read it multiple
  49          * times to ensure a safe value is read:
  50          */
  51         do {
  52                 v1 = read_pmtmr();
  53                 v2 = read_pmtmr();
  54                 v3 = read_pmtmr();
  55         } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
  56                           || (v3 > v1 && v3 < v2)));
  57
  58         return v2;
  59 }
  60
  61 static cycle_t acpi_pm_read(struct clocksource *cs)
  62 {
  63         return (cycle_t)read_pmtmr();
  64 }
  65
  66 static struct clocksource clocksource_acpi_pm = {
  67         .name           = "acpi_pm",
  68         .rating         = 200,
  69         .read           = acpi_pm_read,
  70         .mask           = (cycle_t)ACPI_PM_MASK,
  71         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  72 };
  73
  74
  75 #ifdef CONFIG_PCI
  76 static int acpi_pm_good;
  77 static int __init acpi_pm_good_setup(char *__str)
  78 {
  79         acpi_pm_good = 1;
  80         return 1;
  81 }
  82 __setup("acpi_pm_good", acpi_pm_good_setup);
  83
  84 static cycle_t acpi_pm_read_slow(struct clocksource *cs)
  85 {
  86         return (cycle_t)acpi_pm_read_verified();
  87 }
  88
  89 static inline void acpi_pm_need_workaround(void)
  90 {
  91         clocksource_acpi_pm.read = acpi_pm_read_slow;
  92         clocksource_acpi_pm.rating = 120;
  93 }
  94
  95 /*
  96  * PIIX4 Errata:
  97  *
  98  * The power management timer may return improper results when read.
  99  * Although the timer value settles properly after incrementing,
 100  * while incrementing there is a 3 ns window every 69.8 ns where the
 101  * timer value is indeterminate (a 4.2% chance that the data will be
 102  * incorrect when read). As a result, the ACPI free running count up
 103  * timer specification is violated due to erroneous reads.
 104  */
 105 static void acpi_pm_check_blacklist(struct pci_dev *dev)
 106 {
 107         if (acpi_pm_good)
 108                 return;
 109
 110         /* the bug has been fixed in PIIX4M */
 111         if (dev->revision < 3) {
 112                 printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
 113                        " Due to workarounds for a bug,\n"
 114                        "* this clock source is slow. Consider trying"
 115                        " other clock sources\n");
 116
 117                 acpi_pm_need_workaround();
 118         }
 119 }
 120 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
 121                         acpi_pm_check_blacklist);
 122
 123 static void acpi_pm_check_graylist(struct pci_dev *dev)
 124 {
 125         if (acpi_pm_good)
 126                 return;
 127
 128         printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
 129                " workarounds for a bug,\n"
 130                "* this clock source is slow. If you are sure your timer"
 131                " does not have\n"
 132                "* this bug, please use \"acpi_pm_good\" to disable the"
 133                " workaround\n");
 134
 135         acpi_pm_need_workaround();
 136 }
 137 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 138                         acpi_pm_check_graylist);
 139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
 140                         acpi_pm_check_graylist);
 141 #endif
 142
 143 #ifndef CONFIG_X86_64
 144 #include <asm/mach_timer.h>
 145 #define PMTMR_EXPECTED_RATE \
 146   ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10))
 147 /*
 148  * Some boards have the PMTMR running way too fast. We check
 149  * the PMTMR rate against PIT channel 2 to catch these cases.
 150  */
 151 static int verify_pmtmr_rate(void)
 152 {
 153         cycle_t value1, value2;
 154         unsigned long count, delta;
 155
 156         mach_prepare_counter();
 157         value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
 158         mach_countup(&count);
 159         value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
 160         delta = (value2 - value1) & ACPI_PM_MASK;
 161
 162         /* Check that the PMTMR delta is within 5% of what we expect */
 163         if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
 164             delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
 165                 printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
 166                         "of normal - aborting.\n",
 167                         100UL * delta / PMTMR_EXPECTED_RATE);
 168                 return -1;
 169         }
 170
 171         return 0;
 172 }
 173 #else
 174 #define verify_pmtmr_rate() (0)
 175 #endif
 176
 177 /* Number of monotonicity checks to perform during initialization */
 178 #define ACPI_PM_MONOTONICITY_CHECKS 10
 179 /* Number of reads we try to get two different values */
 180 #define ACPI_PM_READ_CHECKS 10000
 181
 182 static int __init init_acpi_pm_clocksource(void)
 183 {
 184         cycle_t value1, value2;
 185         unsigned int i, j = 0;
 186
 187         if (!pmtmr_ioport)
 188                 return -ENODEV;
 189
 190         /* "verify" this timing source: */
 191         for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
 192                 udelay(100 * j);
 193                 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
 194                 for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
 195                         value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
 196                         if (value2 == value1)
 197                                 continue;
 198                         if (value2 > value1)
 199                                 break;
 200                         if ((value2 < value1) && ((value2) < 0xFFF))
 201                                 break;
 202                         printk(KERN_INFO "PM-Timer had inconsistent results:"
 203                                " 0x%#llx, 0x%#llx - aborting.\n",
 204                                value1, value2);
 205                         pmtmr_ioport = 0;
 206                         return -EINVAL;
 207                 }
 208                 if (i == ACPI_PM_READ_CHECKS) {
 209                         printk(KERN_INFO "PM-Timer failed consistency check "
 210                                " (0x%#llx) - aborting.\n", value1);
 211                         pmtmr_ioport = 0;
 212                         return -ENODEV;
 213                 }
 214         }
 215
 216         if (verify_pmtmr_rate() != 0){
 217                 pmtmr_ioport = 0;
 218                 return -ENODEV;
 219         }
 220
 221         return clocksource_register_hz(&clocksource_acpi_pm,
 222                                                 PMTMR_TICKS_PER_SEC);
 223 }
 224
 225 /* We use fs_initcall because we want the PCI fixups to have run
 226  * but we still need to load before device_initcall
 227  */
 228 fs_initcall(init_acpi_pm_clocksource);
 229
 230 /*
 231  * Allow an override of the IOPort. Stupid BIOSes do not tell us about
 232  * the PMTimer, but we might know where it is.
 233  */
 234 static int __init parse_pmtmr(char *arg)
 235 {
 236         unsigned int base;
 237         int ret;
 238
 239         ret = kstrtouint(arg, 16, &base);
 240         if (ret)
 241                 return ret;
 242
 243         pr_info("PMTMR IOPort override: 0x%04x -> 0x%04x\n", pmtmr_ioport,
 244                 base);
 245         pmtmr_ioport = base;
 246
 247         return 1;
 248 }
 249 __setup("pmtmr=", parse_pmtmr);