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Merge 5.8-rc6 into usb-next
[linux/fpc-iii.git] / drivers / usb / gadget / udc / atmel_usba_udc.c
blob5ca75e69e251b8f7c9945c0ce96391f1212f4ba1
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Atmel USBA high speed USB device controller
4 *
5 * Copyright (C) 2005-2007 Atmel Corporation
6 */
7 #include <linux/clk.h>
8 #include <linux/clk/at91_pmc.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/slab.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/list.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/ctype.h>
21 #include <linux/usb.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24 #include <linux/delay.h>
25 #include <linux/of.h>
26 #include <linux/irq.h>
27 #include <linux/gpio/consumer.h>
28
29 #include "atmel_usba_udc.h"
30 #define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \
31 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)
32
33 #ifdef CONFIG_USB_GADGET_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/uaccess.h>
36
37 static int queue_dbg_open(struct inode *inode, struct file *file)
38 {
39 struct usba_ep *ep = inode->i_private;
40 struct usba_request *req, *req_copy;
41 struct list_head *queue_data;
42
43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
44 if (!queue_data)
45 return -ENOMEM;
46 INIT_LIST_HEAD(queue_data);
47
48 spin_lock_irq(&ep->udc->lock);
49 list_for_each_entry(req, &ep->queue, queue) {
50 req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
51 if (!req_copy)
52 goto fail;
53 list_add_tail(&req_copy->queue, queue_data);
54 }
55 spin_unlock_irq(&ep->udc->lock);
56
57 file->private_data = queue_data;
58 return 0;
59
60 fail:
61 spin_unlock_irq(&ep->udc->lock);
62 list_for_each_entry_safe(req, req_copy, queue_data, queue) {
63 list_del(&req->queue);
64 kfree(req);
65 }
66 kfree(queue_data);
67 return -ENOMEM;
68 }
69
70 /*
71 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
72 *
73 * b: buffer address
74 * l: buffer length
75 * I/i: interrupt/no interrupt
76 * Z/z: zero/no zero
77 * S/s: short ok/short not ok
78 * s: status
79 * n: nr_packets
80 * F/f: submitted/not submitted to FIFO
81 * D/d: using/not using DMA
82 * L/l: last transaction/not last transaction
83 */
84 static ssize_t queue_dbg_read(struct file *file, char __user *buf,
85 size_t nbytes, loff_t *ppos)
86 {
87 struct list_head *queue = file->private_data;
88 struct usba_request *req, *tmp_req;
89 size_t len, remaining, actual = 0;
90 char tmpbuf[38];
91
92 if (!access_ok(buf, nbytes))
93 return -EFAULT;
94
95 inode_lock(file_inode(file));
96 list_for_each_entry_safe(req, tmp_req, queue, queue) {
97 len = snprintf(tmpbuf, sizeof(tmpbuf),
98 "%8p %08x %c%c%c %5d %c%c%c\n",
99 req->req.buf, req->req.length,
100 req->req.no_interrupt ? 'i' : 'I',
101 req->req.zero ? 'Z' : 'z',
102 req->req.short_not_ok ? 's' : 'S',
103 req->req.status,
104 req->submitted ? 'F' : 'f',
105 req->using_dma ? 'D' : 'd',
106 req->last_transaction ? 'L' : 'l');
107 len = min(len, sizeof(tmpbuf));
108 if (len > nbytes)
109 break;
110
111 list_del(&req->queue);
112 kfree(req);
113
114 remaining = __copy_to_user(buf, tmpbuf, len);
115 actual += len - remaining;
116 if (remaining)
117 break;
118
119 nbytes -= len;
120 buf += len;
121 }
122 inode_unlock(file_inode(file));
123
124 return actual;
125 }
126
127 static int queue_dbg_release(struct inode *inode, struct file *file)
128 {
129 struct list_head *queue_data = file->private_data;
130 struct usba_request *req, *tmp_req;
131
132 list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
133 list_del(&req->queue);
134 kfree(req);
135 }
136 kfree(queue_data);
137 return 0;
138 }
139
140 static int regs_dbg_open(struct inode *inode, struct file *file)
141 {
142 struct usba_udc *udc;
143 unsigned int i;
144 u32 *data;
145 int ret = -ENOMEM;
146
147 inode_lock(inode);
148 udc = inode->i_private;
149 data = kmalloc(inode->i_size, GFP_KERNEL);
150 if (!data)
151 goto out;
152
153 spin_lock_irq(&udc->lock);
154 for (i = 0; i < inode->i_size / 4; i++)
155 data[i] = readl_relaxed(udc->regs + i * 4);
156 spin_unlock_irq(&udc->lock);
157
158 file->private_data = data;
159 ret = 0;
160
161 out:
162 inode_unlock(inode);
163
164 return ret;
165 }
166
167 static ssize_t regs_dbg_read(struct file *file, char __user *buf,
168 size_t nbytes, loff_t *ppos)
169 {
170 struct inode *inode = file_inode(file);
171 int ret;
172
173 inode_lock(inode);
174 ret = simple_read_from_buffer(buf, nbytes, ppos,
175 file->private_data,
176 file_inode(file)->i_size);
177 inode_unlock(inode);
178
179 return ret;
180 }
181
182 static int regs_dbg_release(struct inode *inode, struct file *file)
183 {
184 kfree(file->private_data);
185 return 0;
186 }
187
188 static const struct file_operations queue_dbg_fops = {
189 .owner = THIS_MODULE,
190 .open = queue_dbg_open,
191 .llseek = no_llseek,
192 .read = queue_dbg_read,
193 .release = queue_dbg_release,
194 };
195
196 static const struct file_operations regs_dbg_fops = {
197 .owner = THIS_MODULE,
198 .open = regs_dbg_open,
199 .llseek = generic_file_llseek,
200 .read = regs_dbg_read,
201 .release = regs_dbg_release,
202 };
203
204 static void usba_ep_init_debugfs(struct usba_udc *udc,
205 struct usba_ep *ep)
206 {
207 struct dentry *ep_root;
208
209 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
210 ep->debugfs_dir = ep_root;
211
212 debugfs_create_file("queue", 0400, ep_root, ep, &queue_dbg_fops);
213 if (ep->can_dma)
214 debugfs_create_u32("dma_status", 0400, ep_root,
215 &ep->last_dma_status);
216 if (ep_is_control(ep))
217 debugfs_create_u32("state", 0400, ep_root, &ep->state);
218 }
219
220 static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
221 {
222 debugfs_remove_recursive(ep->debugfs_dir);
223 }
224
225 static void usba_init_debugfs(struct usba_udc *udc)
226 {
227 struct dentry *root;
228 struct resource *regs_resource;
229
230 root = debugfs_create_dir(udc->gadget.name, usb_debug_root);
231 udc->debugfs_root = root;
232
233 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
234 CTRL_IOMEM_ID);
235
236 if (regs_resource) {
237 debugfs_create_file_size("regs", 0400, root, udc,
238 &regs_dbg_fops,
239 resource_size(regs_resource));
240 }
241
242 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
243 }
244
245 static void usba_cleanup_debugfs(struct usba_udc *udc)
246 {
247 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
248 debugfs_remove_recursive(udc->debugfs_root);
249 }
250 #else
251 static inline void usba_ep_init_debugfs(struct usba_udc *udc,
252 struct usba_ep *ep)
253 {
254
255 }
256
257 static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
258 {
259
260 }
261
262 static inline void usba_init_debugfs(struct usba_udc *udc)
263 {
264
265 }
266
267 static inline void usba_cleanup_debugfs(struct usba_udc *udc)
268 {
269
270 }
271 #endif
272
273 static ushort fifo_mode;
274
275 module_param(fifo_mode, ushort, 0x0);
276 MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
277
278 /* mode 0 - uses autoconfig */
279
280 /* mode 1 - fits in 8KB, generic max fifo configuration */
281 static struct usba_fifo_cfg mode_1_cfg[] = {
282 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
283 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
284 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, },
285 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, },
286 { .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, },
287 { .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, },
288 { .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, },
289 };
290
291 /* mode 2 - fits in 8KB, performance max fifo configuration */
292 static struct usba_fifo_cfg mode_2_cfg[] = {
293 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
294 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, },
295 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, },
296 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, },
297 };
298
299 /* mode 3 - fits in 8KB, mixed fifo configuration */
300 static struct usba_fifo_cfg mode_3_cfg[] = {
301 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
302 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
303 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
304 { .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, },
305 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
306 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
307 { .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, },
308 };
309
310 /* mode 4 - fits in 8KB, custom fifo configuration */
311 static struct usba_fifo_cfg mode_4_cfg[] = {
312 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
313 { .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, },
314 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
315 { .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, },
316 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
317 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
318 { .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, },
319 { .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, },
320 { .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, },
321 };
322 /* Add additional configurations here */
323
324 static int usba_config_fifo_table(struct usba_udc *udc)
325 {
326 int n;
327
328 switch (fifo_mode) {
329 default:
330 fifo_mode = 0;
331 /* fall through */
332 case 0:
333 udc->fifo_cfg = NULL;
334 n = 0;
335 break;
336 case 1:
337 udc->fifo_cfg = mode_1_cfg;
338 n = ARRAY_SIZE(mode_1_cfg);
339 break;
340 case 2:
341 udc->fifo_cfg = mode_2_cfg;
342 n = ARRAY_SIZE(mode_2_cfg);
343 break;
344 case 3:
345 udc->fifo_cfg = mode_3_cfg;
346 n = ARRAY_SIZE(mode_3_cfg);
347 break;
348 case 4:
349 udc->fifo_cfg = mode_4_cfg;
350 n = ARRAY_SIZE(mode_4_cfg);
351 break;
352 }
353 DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
354
355 return n;
356 }
357
358 static inline u32 usba_int_enb_get(struct usba_udc *udc)
359 {
360 return udc->int_enb_cache;
361 }
362
363 static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask)
364 {
365 u32 val;
366
367 val = udc->int_enb_cache | mask;
368 usba_writel(udc, INT_ENB, val);
369 udc->int_enb_cache = val;
370 }
371
372 static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask)
373 {
374 u32 val;
375
376 val = udc->int_enb_cache & ~mask;
377 usba_writel(udc, INT_ENB, val);
378 udc->int_enb_cache = val;
379 }
380
381 static int vbus_is_present(struct usba_udc *udc)
382 {
383 if (udc->vbus_pin)
384 return gpiod_get_value(udc->vbus_pin);
385
386 /* No Vbus detection: Assume always present */
387 return 1;
388 }
389
390 static void toggle_bias(struct usba_udc *udc, int is_on)
391 {
392 if (udc->errata && udc->errata->toggle_bias)
393 udc->errata->toggle_bias(udc, is_on);
394 }
395
396 static void generate_bias_pulse(struct usba_udc *udc)
397 {
398 if (!udc->bias_pulse_needed)
399 return;
400
401 if (udc->errata && udc->errata->pulse_bias)
402 udc->errata->pulse_bias(udc);
403
404 udc->bias_pulse_needed = false;
405 }
406
407 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
408 {
409 unsigned int transaction_len;
410
411 transaction_len = req->req.length - req->req.actual;
412 req->last_transaction = 1;
413 if (transaction_len > ep->ep.maxpacket) {
414 transaction_len = ep->ep.maxpacket;
415 req->last_transaction = 0;
416 } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
417 req->last_transaction = 0;
418
419 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
420 ep->ep.name, req, transaction_len,
421 req->last_transaction ? ", done" : "");
422
423 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
424 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
425 req->req.actual += transaction_len;
426 }
427
428 static void submit_request(struct usba_ep *ep, struct usba_request *req)
429 {
430 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
431 ep->ep.name, req, req->req.length);
432
433 req->req.actual = 0;
434 req->submitted = 1;
435
436 if (req->using_dma) {
437 if (req->req.length == 0) {
438 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
439 return;
440 }
441
442 if (req->req.zero)
443 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
444 else
445 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
446
447 usba_dma_writel(ep, ADDRESS, req->req.dma);
448 usba_dma_writel(ep, CONTROL, req->ctrl);
449 } else {
450 next_fifo_transaction(ep, req);
451 if (req->last_transaction) {
452 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
453 if (ep_is_control(ep))
454 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
455 } else {
456 if (ep_is_control(ep))
457 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
458 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
459 }
460 }
461 }
462
463 static void submit_next_request(struct usba_ep *ep)
464 {
465 struct usba_request *req;
466
467 if (list_empty(&ep->queue)) {
468 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
469 return;
470 }
471
472 req = list_entry(ep->queue.next, struct usba_request, queue);
473 if (!req->submitted)
474 submit_request(ep, req);
475 }
476
477 static void send_status(struct usba_udc *udc, struct usba_ep *ep)
478 {
479 ep->state = STATUS_STAGE_IN;
480 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
481 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
482 }
483
484 static void receive_data(struct usba_ep *ep)
485 {
486 struct usba_udc *udc = ep->udc;
487 struct usba_request *req;
488 unsigned long status;
489 unsigned int bytecount, nr_busy;
490 int is_complete = 0;
491
492 status = usba_ep_readl(ep, STA);
493 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
494
495 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
496
497 while (nr_busy > 0) {
498 if (list_empty(&ep->queue)) {
499 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
500 break;
501 }
502 req = list_entry(ep->queue.next,
503 struct usba_request, queue);
504
505 bytecount = USBA_BFEXT(BYTE_COUNT, status);
506
507 if (status & (1 << 31))
508 is_complete = 1;
509 if (req->req.actual + bytecount >= req->req.length) {
510 is_complete = 1;
511 bytecount = req->req.length - req->req.actual;
512 }
513
514 memcpy_fromio(req->req.buf + req->req.actual,
515 ep->fifo, bytecount);
516 req->req.actual += bytecount;
517
518 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
519
520 if (is_complete) {
521 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
522 req->req.status = 0;
523 list_del_init(&req->queue);
524 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
525 spin_unlock(&udc->lock);
526 usb_gadget_giveback_request(&ep->ep, &req->req);
527 spin_lock(&udc->lock);
528 }
529
530 status = usba_ep_readl(ep, STA);
531 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
532
533 if (is_complete && ep_is_control(ep)) {
534 send_status(udc, ep);
535 break;
536 }
537 }
538 }
539
540 static void
541 request_complete(struct usba_ep *ep, struct usba_request *req, int status)
542 {
543 struct usba_udc *udc = ep->udc;
544
545 WARN_ON(!list_empty(&req->queue));
546
547 if (req->req.status == -EINPROGRESS)
548 req->req.status = status;
549
550 if (req->using_dma)
551 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
552
553 DBG(DBG_GADGET | DBG_REQ,
554 "%s: req %p complete: status %d, actual %u\n",
555 ep->ep.name, req, req->req.status, req->req.actual);
556
557 spin_unlock(&udc->lock);
558 usb_gadget_giveback_request(&ep->ep, &req->req);
559 spin_lock(&udc->lock);
560 }
561
562 static void
563 request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
564 {
565 struct usba_request *req, *tmp_req;
566
567 list_for_each_entry_safe(req, tmp_req, list, queue) {
568 list_del_init(&req->queue);
569 request_complete(ep, req, status);
570 }
571 }
572
573 static int
574 usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
575 {
576 struct usba_ep *ep = to_usba_ep(_ep);
577 struct usba_udc *udc = ep->udc;
578 unsigned long flags, maxpacket;
579 unsigned int nr_trans;
580
581 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
582
583 maxpacket = usb_endpoint_maxp(desc);
584
585 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
586 || ep->index == 0
587 || desc->bDescriptorType != USB_DT_ENDPOINT
588 || maxpacket == 0
589 || maxpacket > ep->fifo_size) {
590 DBG(DBG_ERR, "ep_enable: Invalid argument");
591 return -EINVAL;
592 }
593
594 ep->is_isoc = 0;
595 ep->is_in = 0;
596
597 DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
598 ep->ep.name, ep->ept_cfg, maxpacket);
599
600 if (usb_endpoint_dir_in(desc)) {
601 ep->is_in = 1;
602 ep->ept_cfg |= USBA_EPT_DIR_IN;
603 }
604
605 switch (usb_endpoint_type(desc)) {
606 case USB_ENDPOINT_XFER_CONTROL:
607 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
608 break;
609 case USB_ENDPOINT_XFER_ISOC:
610 if (!ep->can_isoc) {
611 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
612 ep->ep.name);
613 return -EINVAL;
614 }
615
616 /*
617 * Bits 11:12 specify number of _additional_
618 * transactions per microframe.
619 */
620 nr_trans = usb_endpoint_maxp_mult(desc);
621 if (nr_trans > 3)
622 return -EINVAL;
623
624 ep->is_isoc = 1;
625 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
626 ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
627
628 break;
629 case USB_ENDPOINT_XFER_BULK:
630 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
631 break;
632 case USB_ENDPOINT_XFER_INT:
633 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
634 break;
635 }
636
637 spin_lock_irqsave(&ep->udc->lock, flags);
638
639 ep->ep.desc = desc;
640 ep->ep.maxpacket = maxpacket;
641
642 usba_ep_writel(ep, CFG, ep->ept_cfg);
643 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
644
645 if (ep->can_dma) {
646 u32 ctrl;
647
648 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index) |
649 USBA_BF(DMA_INT, 1 << ep->index));
650 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
651 usba_ep_writel(ep, CTL_ENB, ctrl);
652 } else {
653 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index));
654 }
655
656 spin_unlock_irqrestore(&udc->lock, flags);
657
658 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
659 (unsigned long)usba_ep_readl(ep, CFG));
660 DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
661 (unsigned long)usba_int_enb_get(udc));
662
663 return 0;
664 }
665
666 static int usba_ep_disable(struct usb_ep *_ep)
667 {
668 struct usba_ep *ep = to_usba_ep(_ep);
669 struct usba_udc *udc = ep->udc;
670 LIST_HEAD(req_list);
671 unsigned long flags;
672
673 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
674
675 spin_lock_irqsave(&udc->lock, flags);
676
677 if (!ep->ep.desc) {
678 spin_unlock_irqrestore(&udc->lock, flags);
679 DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
680 return -EINVAL;
681 }
682 ep->ep.desc = NULL;
683
684 list_splice_init(&ep->queue, &req_list);
685 if (ep->can_dma) {
686 usba_dma_writel(ep, CONTROL, 0);
687 usba_dma_writel(ep, ADDRESS, 0);
688 usba_dma_readl(ep, STATUS);
689 }
690 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
691 usba_int_enb_clear(udc, USBA_BF(EPT_INT, 1 << ep->index));
692
693 request_complete_list(ep, &req_list, -ESHUTDOWN);
694
695 spin_unlock_irqrestore(&udc->lock, flags);
696
697 return 0;
698 }
699
700 static struct usb_request *
701 usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
702 {
703 struct usba_request *req;
704
705 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
706
707 req = kzalloc(sizeof(*req), gfp_flags);
708 if (!req)
709 return NULL;
710
711 INIT_LIST_HEAD(&req->queue);
712
713 return &req->req;
714 }
715
716 static void
717 usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
718 {
719 struct usba_request *req = to_usba_req(_req);
720
721 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
722
723 kfree(req);
724 }
725
726 static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
727 struct usba_request *req, gfp_t gfp_flags)
728 {
729 unsigned long flags;
730 int ret;
731
732 DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
733 ep->ep.name, req->req.length, &req->req.dma,
734 req->req.zero ? 'Z' : 'z',
735 req->req.short_not_ok ? 'S' : 's',
736 req->req.no_interrupt ? 'I' : 'i');
737
738 if (req->req.length > 0x10000) {
739 /* Lengths from 0 to 65536 (inclusive) are supported */
740 DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
741 return -EINVAL;
742 }
743
744 ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
745 if (ret)
746 return ret;
747
748 req->using_dma = 1;
749 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
750 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
751 | USBA_DMA_END_BUF_EN;
752
753 if (!ep->is_in)
754 req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
755
756 /*
757 * Add this request to the queue and submit for DMA if
758 * possible. Check if we're still alive first -- we may have
759 * received a reset since last time we checked.
760 */
761 ret = -ESHUTDOWN;
762 spin_lock_irqsave(&udc->lock, flags);
763 if (ep->ep.desc) {
764 if (list_empty(&ep->queue))
765 submit_request(ep, req);
766
767 list_add_tail(&req->queue, &ep->queue);
768 ret = 0;
769 }
770 spin_unlock_irqrestore(&udc->lock, flags);
771
772 return ret;
773 }
774
775 static int
776 usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
777 {
778 struct usba_request *req = to_usba_req(_req);
779 struct usba_ep *ep = to_usba_ep(_ep);
780 struct usba_udc *udc = ep->udc;
781 unsigned long flags;
782 int ret;
783
784 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
785 ep->ep.name, req, _req->length);
786
787 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
788 !ep->ep.desc)
789 return -ESHUTDOWN;
790
791 req->submitted = 0;
792 req->using_dma = 0;
793 req->last_transaction = 0;
794
795 _req->status = -EINPROGRESS;
796 _req->actual = 0;
797
798 if (ep->can_dma)
799 return queue_dma(udc, ep, req, gfp_flags);
800
801 /* May have received a reset since last time we checked */
802 ret = -ESHUTDOWN;
803 spin_lock_irqsave(&udc->lock, flags);
804 if (ep->ep.desc) {
805 list_add_tail(&req->queue, &ep->queue);
806
807 if ((!ep_is_control(ep) && ep->is_in) ||
808 (ep_is_control(ep)
809 && (ep->state == DATA_STAGE_IN
810 || ep->state == STATUS_STAGE_IN)))
811 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
812 else
813 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
814 ret = 0;
815 }
816 spin_unlock_irqrestore(&udc->lock, flags);
817
818 return ret;
819 }
820
821 static void
822 usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
823 {
824 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
825 }
826
827 static int stop_dma(struct usba_ep *ep, u32 *pstatus)
828 {
829 unsigned int timeout;
830 u32 status;
831
832 /*
833 * Stop the DMA controller. When writing both CH_EN
834 * and LINK to 0, the other bits are not affected.
835 */
836 usba_dma_writel(ep, CONTROL, 0);
837
838 /* Wait for the FIFO to empty */
839 for (timeout = 40; timeout; --timeout) {
840 status = usba_dma_readl(ep, STATUS);
841 if (!(status & USBA_DMA_CH_EN))
842 break;
843 udelay(1);
844 }
845
846 if (pstatus)
847 *pstatus = status;
848
849 if (timeout == 0) {
850 dev_err(&ep->udc->pdev->dev,
851 "%s: timed out waiting for DMA FIFO to empty\n",
852 ep->ep.name);
853 return -ETIMEDOUT;
854 }
855
856 return 0;
857 }
858
859 static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
860 {
861 struct usba_ep *ep = to_usba_ep(_ep);
862 struct usba_udc *udc = ep->udc;
863 struct usba_request *req;
864 unsigned long flags;
865 u32 status;
866
867 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
868 ep->ep.name, _req);
869
870 spin_lock_irqsave(&udc->lock, flags);
871
872 list_for_each_entry(req, &ep->queue, queue) {
873 if (&req->req == _req)
874 break;
875 }
876
877 if (&req->req != _req) {
878 spin_unlock_irqrestore(&udc->lock, flags);
879 return -EINVAL;
880 }
881
882 if (req->using_dma) {
883 /*
884 * If this request is currently being transferred,
885 * stop the DMA controller and reset the FIFO.
886 */
887 if (ep->queue.next == &req->queue) {
888 status = usba_dma_readl(ep, STATUS);
889 if (status & USBA_DMA_CH_EN)
890 stop_dma(ep, &status);
891
892 #ifdef CONFIG_USB_GADGET_DEBUG_FS
893 ep->last_dma_status = status;
894 #endif
895
896 usba_writel(udc, EPT_RST, 1 << ep->index);
897
898 usba_update_req(ep, req, status);
899 }
900 }
901
902 /*
903 * Errors should stop the queue from advancing until the
904 * completion function returns.
905 */
906 list_del_init(&req->queue);
907
908 request_complete(ep, req, -ECONNRESET);
909
910 /* Process the next request if any */
911 submit_next_request(ep);
912 spin_unlock_irqrestore(&udc->lock, flags);
913
914 return 0;
915 }
916
917 static int usba_ep_set_halt(struct usb_ep *_ep, int value)
918 {
919 struct usba_ep *ep = to_usba_ep(_ep);
920 struct usba_udc *udc = ep->udc;
921 unsigned long flags;
922 int ret = 0;
923
924 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
925 value ? "set" : "clear");
926
927 if (!ep->ep.desc) {
928 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
929 ep->ep.name);
930 return -ENODEV;
931 }
932 if (ep->is_isoc) {
933 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
934 ep->ep.name);
935 return -ENOTTY;
936 }
937
938 spin_lock_irqsave(&udc->lock, flags);
939
940 /*
941 * We can't halt IN endpoints while there are still data to be
942 * transferred
943 */
944 if (!list_empty(&ep->queue)
945 || ((value && ep->is_in && (usba_ep_readl(ep, STA)
946 & USBA_BF(BUSY_BANKS, -1L))))) {
947 ret = -EAGAIN;
948 } else {
949 if (value)
950 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
951 else
952 usba_ep_writel(ep, CLR_STA,
953 USBA_FORCE_STALL | USBA_TOGGLE_CLR);
954 usba_ep_readl(ep, STA);
955 }
956
957 spin_unlock_irqrestore(&udc->lock, flags);
958
959 return ret;
960 }
961
962 static int usba_ep_fifo_status(struct usb_ep *_ep)
963 {
964 struct usba_ep *ep = to_usba_ep(_ep);
965
966 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
967 }
968
969 static void usba_ep_fifo_flush(struct usb_ep *_ep)
970 {
971 struct usba_ep *ep = to_usba_ep(_ep);
972 struct usba_udc *udc = ep->udc;
973
974 usba_writel(udc, EPT_RST, 1 << ep->index);
975 }
976
977 static const struct usb_ep_ops usba_ep_ops = {
978 .enable = usba_ep_enable,
979 .disable = usba_ep_disable,
980 .alloc_request = usba_ep_alloc_request,
981 .free_request = usba_ep_free_request,
982 .queue = usba_ep_queue,
983 .dequeue = usba_ep_dequeue,
984 .set_halt = usba_ep_set_halt,
985 .fifo_status = usba_ep_fifo_status,
986 .fifo_flush = usba_ep_fifo_flush,
987 };
988
989 static int usba_udc_get_frame(struct usb_gadget *gadget)
990 {
991 struct usba_udc *udc = to_usba_udc(gadget);
992
993 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
994 }
995
996 static int usba_udc_wakeup(struct usb_gadget *gadget)
997 {
998 struct usba_udc *udc = to_usba_udc(gadget);
999 unsigned long flags;
1000 u32 ctrl;
1001 int ret = -EINVAL;
1002
1003 spin_lock_irqsave(&udc->lock, flags);
1004 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
1005 ctrl = usba_readl(udc, CTRL);
1006 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
1007 ret = 0;
1008 }
1009 spin_unlock_irqrestore(&udc->lock, flags);
1010
1011 return ret;
1012 }
1013
1014 static int
1015 usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1016 {
1017 struct usba_udc *udc = to_usba_udc(gadget);
1018 unsigned long flags;
1019
1020 gadget->is_selfpowered = (is_selfpowered != 0);
1021 spin_lock_irqsave(&udc->lock, flags);
1022 if (is_selfpowered)
1023 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1024 else
1025 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1026 spin_unlock_irqrestore(&udc->lock, flags);
1027
1028 return 0;
1029 }
1030
1031 static int atmel_usba_start(struct usb_gadget *gadget,
1032 struct usb_gadget_driver *driver);
1033 static int atmel_usba_stop(struct usb_gadget *gadget);
1034
1035 static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget,
1036 struct usb_endpoint_descriptor *desc,
1037 struct usb_ss_ep_comp_descriptor *ep_comp)
1038 {
1039 struct usb_ep *_ep;
1040 struct usba_ep *ep;
1041
1042 /* Look at endpoints until an unclaimed one looks usable */
1043 list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
1044 if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
1045 goto found_ep;
1046 }
1047 /* Fail */
1048 return NULL;
1049
1050 found_ep:
1051
1052 if (fifo_mode == 0) {
1053 /* Optimize hw fifo size based on ep type and other info */
1054 ep = to_usba_ep(_ep);
1055
1056 switch (usb_endpoint_type(desc)) {
1057 case USB_ENDPOINT_XFER_CONTROL:
1058 break;
1059
1060 case USB_ENDPOINT_XFER_ISOC:
1061 ep->fifo_size = 1024;
1062 ep->nr_banks = 2;
1063 break;
1064
1065 case USB_ENDPOINT_XFER_BULK:
1066 ep->fifo_size = 512;
1067 ep->nr_banks = 1;
1068 break;
1069
1070 case USB_ENDPOINT_XFER_INT:
1071 if (desc->wMaxPacketSize == 0)
1072 ep->fifo_size =
1073 roundup_pow_of_two(_ep->maxpacket_limit);
1074 else
1075 ep->fifo_size =
1076 roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
1077 ep->nr_banks = 1;
1078 break;
1079 }
1080
1081 /* It might be a little bit late to set this */
1082 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
1083
1084 /* Generate ept_cfg basd on FIFO size and number of banks */
1085 if (ep->fifo_size <= 8)
1086 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
1087 else
1088 /* LSB is bit 1, not 0 */
1089 ep->ept_cfg =
1090 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
1091
1092 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
1093
1094 ep->udc->configured_ep++;
1095 }
1096
1097 return _ep;
1098 }
1099
1100 static const struct usb_gadget_ops usba_udc_ops = {
1101 .get_frame = usba_udc_get_frame,
1102 .wakeup = usba_udc_wakeup,
1103 .set_selfpowered = usba_udc_set_selfpowered,
1104 .udc_start = atmel_usba_start,
1105 .udc_stop = atmel_usba_stop,
1106 .match_ep = atmel_usba_match_ep,
1107 };
1108
1109 static struct usb_endpoint_descriptor usba_ep0_desc = {
1110 .bLength = USB_DT_ENDPOINT_SIZE,
1111 .bDescriptorType = USB_DT_ENDPOINT,
1112 .bEndpointAddress = 0,
1113 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1114 .wMaxPacketSize = cpu_to_le16(64),
1115 /* FIXME: I have no idea what to put here */
1116 .bInterval = 1,
1117 };
1118
1119 static const struct usb_gadget usba_gadget_template = {
1120 .ops = &usba_udc_ops,
1121 .max_speed = USB_SPEED_HIGH,
1122 .name = "atmel_usba_udc",
1123 };
1124
1125 /*
1126 * Called with interrupts disabled and udc->lock held.
1127 */
1128 static void reset_all_endpoints(struct usba_udc *udc)
1129 {
1130 struct usba_ep *ep;
1131 struct usba_request *req, *tmp_req;
1132
1133 usba_writel(udc, EPT_RST, ~0UL);
1134
1135 ep = to_usba_ep(udc->gadget.ep0);
1136 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1137 list_del_init(&req->queue);
1138 request_complete(ep, req, -ECONNRESET);
1139 }
1140 }
1141
1142 static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
1143 {
1144 struct usba_ep *ep;
1145
1146 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1147 return to_usba_ep(udc->gadget.ep0);
1148
1149 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1150 u8 bEndpointAddress;
1151
1152 if (!ep->ep.desc)
1153 continue;
1154 bEndpointAddress = ep->ep.desc->bEndpointAddress;
1155 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1156 continue;
1157 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
1158 == (wIndex & USB_ENDPOINT_NUMBER_MASK))
1159 return ep;
1160 }
1161
1162 return NULL;
1163 }
1164
1165 /* Called with interrupts disabled and udc->lock held */
1166 static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
1167 {
1168 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
1169 ep->state = WAIT_FOR_SETUP;
1170 }
1171
1172 static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
1173 {
1174 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
1175 return 1;
1176 return 0;
1177 }
1178
1179 static inline void set_address(struct usba_udc *udc, unsigned int addr)
1180 {
1181 u32 regval;
1182
1183 DBG(DBG_BUS, "setting address %u...\n", addr);
1184 regval = usba_readl(udc, CTRL);
1185 regval = USBA_BFINS(DEV_ADDR, addr, regval);
1186 usba_writel(udc, CTRL, regval);
1187 }
1188
1189 static int do_test_mode(struct usba_udc *udc)
1190 {
1191 static const char test_packet_buffer[] = {
1192 /* JKJKJKJK * 9 */
1193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1194 /* JJKKJJKK * 8 */
1195 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1196 /* JJKKJJKK * 8 */
1197 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1198 /* JJJJJJJKKKKKKK * 8 */
1199 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1200 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1201 /* JJJJJJJK * 8 */
1202 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
1203 /* {JKKKKKKK * 10}, JK */
1204 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
1205 };
1206 struct usba_ep *ep;
1207 struct device *dev = &udc->pdev->dev;
1208 int test_mode;
1209
1210 test_mode = udc->test_mode;
1211
1212 /* Start from a clean slate */
1213 reset_all_endpoints(udc);
1214
1215 switch (test_mode) {
1216 case 0x0100:
1217 /* Test_J */
1218 usba_writel(udc, TST, USBA_TST_J_MODE);
1219 dev_info(dev, "Entering Test_J mode...\n");
1220 break;
1221 case 0x0200:
1222 /* Test_K */
1223 usba_writel(udc, TST, USBA_TST_K_MODE);
1224 dev_info(dev, "Entering Test_K mode...\n");
1225 break;
1226 case 0x0300:
1227 /*
1228 * Test_SE0_NAK: Force high-speed mode and set up ep0
1229 * for Bulk IN transfers
1230 */
1231 ep = &udc->usba_ep[0];
1232 usba_writel(udc, TST,
1233 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
1234 usba_ep_writel(ep, CFG,
1235 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1236 | USBA_EPT_DIR_IN
1237 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1238 | USBA_BF(BK_NUMBER, 1));
1239 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1240 set_protocol_stall(udc, ep);
1241 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
1242 } else {
1243 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1244 dev_info(dev, "Entering Test_SE0_NAK mode...\n");
1245 }
1246 break;
1247 case 0x0400:
1248 /* Test_Packet */
1249 ep = &udc->usba_ep[0];
1250 usba_ep_writel(ep, CFG,
1251 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1252 | USBA_EPT_DIR_IN
1253 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1254 | USBA_BF(BK_NUMBER, 1));
1255 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1256 set_protocol_stall(udc, ep);
1257 dev_err(dev, "Test_Packet: ep0 not mapped\n");
1258 } else {
1259 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1260 usba_writel(udc, TST, USBA_TST_PKT_MODE);
1261 memcpy_toio(ep->fifo, test_packet_buffer,
1262 sizeof(test_packet_buffer));
1263 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1264 dev_info(dev, "Entering Test_Packet mode...\n");
1265 }
1266 break;
1267 default:
1268 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
1269 return -EINVAL;
1270 }
1271
1272 return 0;
1273 }
1274
1275 /* Avoid overly long expressions */
1276 static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
1277 {
1278 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
1279 return true;
1280 return false;
1281 }
1282
1283 static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
1284 {
1285 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
1286 return true;
1287 return false;
1288 }
1289
1290 static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
1291 {
1292 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
1293 return true;
1294 return false;
1295 }
1296
1297 static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
1298 struct usb_ctrlrequest *crq)
1299 {
1300 int retval = 0;
1301
1302 switch (crq->bRequest) {
1303 case USB_REQ_GET_STATUS: {
1304 u16 status;
1305
1306 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
1307 status = cpu_to_le16(udc->devstatus);
1308 } else if (crq->bRequestType
1309 == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
1310 status = cpu_to_le16(0);
1311 } else if (crq->bRequestType
1312 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1313 struct usba_ep *target;
1314
1315 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1316 if (!target)
1317 goto stall;
1318
1319 status = 0;
1320 if (is_stalled(udc, target))
1321 status |= cpu_to_le16(1);
1322 } else
1323 goto delegate;
1324
1325 /* Write directly to the FIFO. No queueing is done. */
1326 if (crq->wLength != cpu_to_le16(sizeof(status)))
1327 goto stall;
1328 ep->state = DATA_STAGE_IN;
1329 writew_relaxed(status, ep->fifo);
1330 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1331 break;
1332 }
1333
1334 case USB_REQ_CLEAR_FEATURE: {
1335 if (crq->bRequestType == USB_RECIP_DEVICE) {
1336 if (feature_is_dev_remote_wakeup(crq))
1337 udc->devstatus
1338 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1339 else
1340 /* Can't CLEAR_FEATURE TEST_MODE */
1341 goto stall;
1342 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1343 struct usba_ep *target;
1344
1345 if (crq->wLength != cpu_to_le16(0)
1346 || !feature_is_ep_halt(crq))
1347 goto stall;
1348 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1349 if (!target)
1350 goto stall;
1351
1352 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
1353 if (target->index != 0)
1354 usba_ep_writel(target, CLR_STA,
1355 USBA_TOGGLE_CLR);
1356 } else {
1357 goto delegate;
1358 }
1359
1360 send_status(udc, ep);
1361 break;
1362 }
1363
1364 case USB_REQ_SET_FEATURE: {
1365 if (crq->bRequestType == USB_RECIP_DEVICE) {
1366 if (feature_is_dev_test_mode(crq)) {
1367 send_status(udc, ep);
1368 ep->state = STATUS_STAGE_TEST;
1369 udc->test_mode = le16_to_cpu(crq->wIndex);
1370 return 0;
1371 } else if (feature_is_dev_remote_wakeup(crq)) {
1372 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
1373 } else {
1374 goto stall;
1375 }
1376 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1377 struct usba_ep *target;
1378
1379 if (crq->wLength != cpu_to_le16(0)
1380 || !feature_is_ep_halt(crq))
1381 goto stall;
1382
1383 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1384 if (!target)
1385 goto stall;
1386
1387 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
1388 } else
1389 goto delegate;
1390
1391 send_status(udc, ep);
1392 break;
1393 }
1394
1395 case USB_REQ_SET_ADDRESS:
1396 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1397 goto delegate;
1398
1399 set_address(udc, le16_to_cpu(crq->wValue));
1400 send_status(udc, ep);
1401 ep->state = STATUS_STAGE_ADDR;
1402 break;
1403
1404 default:
1405 delegate:
1406 spin_unlock(&udc->lock);
1407 retval = udc->driver->setup(&udc->gadget, crq);
1408 spin_lock(&udc->lock);
1409 }
1410
1411 return retval;
1412
1413 stall:
1414 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
1415 "halting endpoint...\n",
1416 ep->ep.name, crq->bRequestType, crq->bRequest,
1417 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1418 le16_to_cpu(crq->wLength));
1419 set_protocol_stall(udc, ep);
1420 return -1;
1421 }
1422
1423 static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
1424 {
1425 struct usba_request *req;
1426 u32 epstatus;
1427 u32 epctrl;
1428
1429 restart:
1430 epstatus = usba_ep_readl(ep, STA);
1431 epctrl = usba_ep_readl(ep, CTL);
1432
1433 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
1434 ep->ep.name, ep->state, epstatus, epctrl);
1435
1436 req = NULL;
1437 if (!list_empty(&ep->queue))
1438 req = list_entry(ep->queue.next,
1439 struct usba_request, queue);
1440
1441 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1442 if (req->submitted)
1443 next_fifo_transaction(ep, req);
1444 else
1445 submit_request(ep, req);
1446
1447 if (req->last_transaction) {
1448 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1449 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
1450 }
1451 goto restart;
1452 }
1453 if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
1454 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
1455
1456 switch (ep->state) {
1457 case DATA_STAGE_IN:
1458 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
1459 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1460 ep->state = STATUS_STAGE_OUT;
1461 break;
1462 case STATUS_STAGE_ADDR:
1463 /* Activate our new address */
1464 usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
1465 | USBA_FADDR_EN));
1466 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1467 ep->state = WAIT_FOR_SETUP;
1468 break;
1469 case STATUS_STAGE_IN:
1470 if (req) {
1471 list_del_init(&req->queue);
1472 request_complete(ep, req, 0);
1473 submit_next_request(ep);
1474 }
1475 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1476 ep->state = WAIT_FOR_SETUP;
1477 break;
1478 case STATUS_STAGE_TEST:
1479 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1480 ep->state = WAIT_FOR_SETUP;
1481 if (do_test_mode(udc))
1482 set_protocol_stall(udc, ep);
1483 break;
1484 default:
1485 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
1486 "halting endpoint...\n",
1487 ep->ep.name, ep->state);
1488 set_protocol_stall(udc, ep);
1489 break;
1490 }
1491
1492 goto restart;
1493 }
1494 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1495 switch (ep->state) {
1496 case STATUS_STAGE_OUT:
1497 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1498 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1499
1500 if (req) {
1501 list_del_init(&req->queue);
1502 request_complete(ep, req, 0);
1503 }
1504 ep->state = WAIT_FOR_SETUP;
1505 break;
1506
1507 case DATA_STAGE_OUT:
1508 receive_data(ep);
1509 break;
1510
1511 default:
1512 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1513 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1514 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
1515 "halting endpoint...\n",
1516 ep->ep.name, ep->state);
1517 set_protocol_stall(udc, ep);
1518 break;
1519 }
1520
1521 goto restart;
1522 }
1523 if (epstatus & USBA_RX_SETUP) {
1524 union {
1525 struct usb_ctrlrequest crq;
1526 unsigned long data[2];
1527 } crq;
1528 unsigned int pkt_len;
1529 int ret;
1530
1531 if (ep->state != WAIT_FOR_SETUP) {
1532 /*
1533 * Didn't expect a SETUP packet at this
1534 * point. Clean up any pending requests (which
1535 * may be successful).
1536 */
1537 int status = -EPROTO;
1538
1539 /*
1540 * RXRDY and TXCOMP are dropped when SETUP
1541 * packets arrive. Just pretend we received
1542 * the status packet.
1543 */
1544 if (ep->state == STATUS_STAGE_OUT
1545 || ep->state == STATUS_STAGE_IN) {
1546 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1547 status = 0;
1548 }
1549
1550 if (req) {
1551 list_del_init(&req->queue);
1552 request_complete(ep, req, status);
1553 }
1554 }
1555
1556 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1557 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1558 if (pkt_len != sizeof(crq)) {
1559 pr_warn("udc: Invalid packet length %u (expected %zu)\n",
1560 pkt_len, sizeof(crq));
1561 set_protocol_stall(udc, ep);
1562 return;
1563 }
1564
1565 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1566 memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
1567
1568 /* Free up one bank in the FIFO so that we can
1569 * generate or receive a reply right away. */
1570 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
1571
1572 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1573 ep->state, crq.crq.bRequestType,
1574 crq.crq.bRequest); */
1575
1576 if (crq.crq.bRequestType & USB_DIR_IN) {
1577 /*
1578 * The USB 2.0 spec states that "if wLength is
1579 * zero, there is no data transfer phase."
1580 * However, testusb #14 seems to actually
1581 * expect a data phase even if wLength = 0...
1582 */
1583 ep->state = DATA_STAGE_IN;
1584 } else {
1585 if (crq.crq.wLength != cpu_to_le16(0))
1586 ep->state = DATA_STAGE_OUT;
1587 else
1588 ep->state = STATUS_STAGE_IN;
1589 }
1590
1591 ret = -1;
1592 if (ep->index == 0)
1593 ret = handle_ep0_setup(udc, ep, &crq.crq);
1594 else {
1595 spin_unlock(&udc->lock);
1596 ret = udc->driver->setup(&udc->gadget, &crq.crq);
1597 spin_lock(&udc->lock);
1598 }
1599
1600 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1601 crq.crq.bRequestType, crq.crq.bRequest,
1602 le16_to_cpu(crq.crq.wLength), ep->state, ret);
1603
1604 if (ret < 0) {
1605 /* Let the host know that we failed */
1606 set_protocol_stall(udc, ep);
1607 }
1608 }
1609 }
1610
1611 static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
1612 {
1613 struct usba_request *req;
1614 u32 epstatus;
1615 u32 epctrl;
1616
1617 epstatus = usba_ep_readl(ep, STA);
1618 epctrl = usba_ep_readl(ep, CTL);
1619
1620 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
1621
1622 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1623 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
1624
1625 if (list_empty(&ep->queue)) {
1626 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1627 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1628 return;
1629 }
1630
1631 req = list_entry(ep->queue.next, struct usba_request, queue);
1632
1633 if (req->using_dma) {
1634 /* Send a zero-length packet */
1635 usba_ep_writel(ep, SET_STA,
1636 USBA_TX_PK_RDY);
1637 usba_ep_writel(ep, CTL_DIS,
1638 USBA_TX_PK_RDY);
1639 list_del_init(&req->queue);
1640 submit_next_request(ep);
1641 request_complete(ep, req, 0);
1642 } else {
1643 if (req->submitted)
1644 next_fifo_transaction(ep, req);
1645 else
1646 submit_request(ep, req);
1647
1648 if (req->last_transaction) {
1649 list_del_init(&req->queue);
1650 submit_next_request(ep);
1651 request_complete(ep, req, 0);
1652 }
1653 }
1654
1655 epstatus = usba_ep_readl(ep, STA);
1656 epctrl = usba_ep_readl(ep, CTL);
1657 }
1658 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1659 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
1660 receive_data(ep);
1661 }
1662 }
1663
1664 static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
1665 {
1666 struct usba_request *req;
1667 u32 status, control, pending;
1668
1669 status = usba_dma_readl(ep, STATUS);
1670 control = usba_dma_readl(ep, CONTROL);
1671 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1672 ep->last_dma_status = status;
1673 #endif
1674 pending = status & control;
1675 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
1676
1677 if (status & USBA_DMA_CH_EN) {
1678 dev_err(&udc->pdev->dev,
1679 "DMA_CH_EN is set after transfer is finished!\n");
1680 dev_err(&udc->pdev->dev,
1681 "status=%#08x, pending=%#08x, control=%#08x\n",
1682 status, pending, control);
1683
1684 /*
1685 * try to pretend nothing happened. We might have to
1686 * do something here...
1687 */
1688 }
1689
1690 if (list_empty(&ep->queue))
1691 /* Might happen if a reset comes along at the right moment */
1692 return;
1693
1694 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
1695 req = list_entry(ep->queue.next, struct usba_request, queue);
1696 usba_update_req(ep, req, status);
1697
1698 list_del_init(&req->queue);
1699 submit_next_request(ep);
1700 request_complete(ep, req, 0);
1701 }
1702 }
1703
1704 static int start_clock(struct usba_udc *udc);
1705 static void stop_clock(struct usba_udc *udc);
1706
1707 static irqreturn_t usba_udc_irq(int irq, void *devid)
1708 {
1709 struct usba_udc *udc = devid;
1710 u32 status, int_enb;
1711 u32 dma_status;
1712 u32 ep_status;
1713
1714 spin_lock(&udc->lock);
1715
1716 int_enb = usba_int_enb_get(udc);
1717 status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
1718 DBG(DBG_INT, "irq, status=%#08x\n", status);
1719
1720 if (status & USBA_DET_SUSPEND) {
1721 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND|USBA_WAKE_UP);
1722 usba_int_enb_set(udc, USBA_WAKE_UP);
1723 usba_int_enb_clear(udc, USBA_DET_SUSPEND);
1724 udc->suspended = true;
1725 toggle_bias(udc, 0);
1726 udc->bias_pulse_needed = true;
1727 stop_clock(udc);
1728 DBG(DBG_BUS, "Suspend detected\n");
1729 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1730 && udc->driver && udc->driver->suspend) {
1731 spin_unlock(&udc->lock);
1732 udc->driver->suspend(&udc->gadget);
1733 spin_lock(&udc->lock);
1734 }
1735 }
1736
1737 if (status & USBA_WAKE_UP) {
1738 start_clock(udc);
1739 toggle_bias(udc, 1);
1740 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
1741 DBG(DBG_BUS, "Wake Up CPU detected\n");
1742 }
1743
1744 if (status & USBA_END_OF_RESUME) {
1745 udc->suspended = false;
1746 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
1747 usba_int_enb_clear(udc, USBA_WAKE_UP);
1748 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1749 generate_bias_pulse(udc);
1750 DBG(DBG_BUS, "Resume detected\n");
1751 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1752 && udc->driver && udc->driver->resume) {
1753 spin_unlock(&udc->lock);
1754 udc->driver->resume(&udc->gadget);
1755 spin_lock(&udc->lock);
1756 }
1757 }
1758
1759 dma_status = USBA_BFEXT(DMA_INT, status);
1760 if (dma_status) {
1761 int i;
1762
1763 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1764
1765 for (i = 1; i <= USBA_NR_DMAS; i++)
1766 if (dma_status & (1 << i))
1767 usba_dma_irq(udc, &udc->usba_ep[i]);
1768 }
1769
1770 ep_status = USBA_BFEXT(EPT_INT, status);
1771 if (ep_status) {
1772 int i;
1773
1774 usba_int_enb_set(udc, USBA_DET_SUSPEND);
1775
1776 for (i = 0; i < udc->num_ep; i++)
1777 if (ep_status & (1 << i)) {
1778 if (ep_is_control(&udc->usba_ep[i]))
1779 usba_control_irq(udc, &udc->usba_ep[i]);
1780 else
1781 usba_ep_irq(udc, &udc->usba_ep[i]);
1782 }
1783 }
1784
1785 if (status & USBA_END_OF_RESET) {
1786 struct usba_ep *ep0, *ep;
1787 int i, n;
1788
1789 usba_writel(udc, INT_CLR,
1790 USBA_END_OF_RESET|USBA_END_OF_RESUME
1791 |USBA_DET_SUSPEND|USBA_WAKE_UP);
1792 generate_bias_pulse(udc);
1793 reset_all_endpoints(udc);
1794
1795 if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
1796 udc->gadget.speed = USB_SPEED_UNKNOWN;
1797 spin_unlock(&udc->lock);
1798 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1799 spin_lock(&udc->lock);
1800 }
1801
1802 if (status & USBA_HIGH_SPEED)
1803 udc->gadget.speed = USB_SPEED_HIGH;
1804 else
1805 udc->gadget.speed = USB_SPEED_FULL;
1806 DBG(DBG_BUS, "%s bus reset detected\n",
1807 usb_speed_string(udc->gadget.speed));
1808
1809 ep0 = &udc->usba_ep[0];
1810 ep0->ep.desc = &usba_ep0_desc;
1811 ep0->state = WAIT_FOR_SETUP;
1812 usba_ep_writel(ep0, CFG,
1813 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
1814 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
1815 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
1816 usba_ep_writel(ep0, CTL_ENB,
1817 USBA_EPT_ENABLE | USBA_RX_SETUP);
1818
1819 /* If we get reset while suspended... */
1820 udc->suspended = false;
1821 usba_int_enb_clear(udc, USBA_WAKE_UP);
1822
1823 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1) |
1824 USBA_DET_SUSPEND | USBA_END_OF_RESUME);
1825
1826 /*
1827 * Unclear why we hit this irregularly, e.g. in usbtest,
1828 * but it's clearly harmless...
1829 */
1830 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
1831 dev_err(&udc->pdev->dev,
1832 "ODD: EP0 configuration is invalid!\n");
1833
1834 /* Preallocate other endpoints */
1835 n = fifo_mode ? udc->num_ep : udc->configured_ep;
1836 for (i = 1; i < n; i++) {
1837 ep = &udc->usba_ep[i];
1838 usba_ep_writel(ep, CFG, ep->ept_cfg);
1839 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
1840 dev_err(&udc->pdev->dev,
1841 "ODD: EP%d configuration is invalid!\n", i);
1842 }
1843 }
1844
1845 spin_unlock(&udc->lock);
1846
1847 return IRQ_HANDLED;
1848 }
1849
1850 static int start_clock(struct usba_udc *udc)
1851 {
1852 int ret;
1853
1854 if (udc->clocked)
1855 return 0;
1856
1857 pm_stay_awake(&udc->pdev->dev);
1858
1859 ret = clk_prepare_enable(udc->pclk);
1860 if (ret)
1861 return ret;
1862 ret = clk_prepare_enable(udc->hclk);
1863 if (ret) {
1864 clk_disable_unprepare(udc->pclk);
1865 return ret;
1866 }
1867
1868 udc->clocked = true;
1869 return 0;
1870 }
1871
1872 static void stop_clock(struct usba_udc *udc)
1873 {
1874 if (!udc->clocked)
1875 return;
1876
1877 clk_disable_unprepare(udc->hclk);
1878 clk_disable_unprepare(udc->pclk);
1879
1880 udc->clocked = false;
1881
1882 pm_relax(&udc->pdev->dev);
1883 }
1884
1885 static int usba_start(struct usba_udc *udc)
1886 {
1887 unsigned long flags;
1888 int ret;
1889
1890 ret = start_clock(udc);
1891 if (ret)
1892 return ret;
1893
1894 if (udc->suspended)
1895 return 0;
1896
1897 spin_lock_irqsave(&udc->lock, flags);
1898 toggle_bias(udc, 1);
1899 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1900 /* Clear all requested and pending interrupts... */
1901 usba_writel(udc, INT_ENB, 0);
1902 udc->int_enb_cache = 0;
1903 usba_writel(udc, INT_CLR,
1904 USBA_END_OF_RESET|USBA_END_OF_RESUME
1905 |USBA_DET_SUSPEND|USBA_WAKE_UP);
1906 /* ...and enable just 'reset' IRQ to get us started */
1907 usba_int_enb_set(udc, USBA_END_OF_RESET);
1908 spin_unlock_irqrestore(&udc->lock, flags);
1909
1910 return 0;
1911 }
1912
1913 static void usba_stop(struct usba_udc *udc)
1914 {
1915 unsigned long flags;
1916
1917 if (udc->suspended)
1918 return;
1919
1920 spin_lock_irqsave(&udc->lock, flags);
1921 udc->gadget.speed = USB_SPEED_UNKNOWN;
1922 reset_all_endpoints(udc);
1923
1924 /* This will also disable the DP pullup */
1925 toggle_bias(udc, 0);
1926 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1927 spin_unlock_irqrestore(&udc->lock, flags);
1928
1929 stop_clock(udc);
1930 }
1931
1932 static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
1933 {
1934 struct usba_udc *udc = devid;
1935 int vbus;
1936
1937 /* debounce */
1938 udelay(10);
1939
1940 mutex_lock(&udc->vbus_mutex);
1941
1942 vbus = vbus_is_present(udc);
1943 if (vbus != udc->vbus_prev) {
1944 if (vbus) {
1945 usba_start(udc);
1946 } else {
1947 udc->suspended = false;
1948 if (udc->driver->disconnect)
1949 udc->driver->disconnect(&udc->gadget);
1950
1951 usba_stop(udc);
1952 }
1953 udc->vbus_prev = vbus;
1954 }
1955
1956 mutex_unlock(&udc->vbus_mutex);
1957 return IRQ_HANDLED;
1958 }
1959
1960 static int atmel_usba_start(struct usb_gadget *gadget,
1961 struct usb_gadget_driver *driver)
1962 {
1963 int ret;
1964 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
1965 unsigned long flags;
1966
1967 spin_lock_irqsave(&udc->lock, flags);
1968 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
1969 udc->driver = driver;
1970 spin_unlock_irqrestore(&udc->lock, flags);
1971
1972 mutex_lock(&udc->vbus_mutex);
1973
1974 if (udc->vbus_pin)
1975 enable_irq(gpiod_to_irq(udc->vbus_pin));
1976
1977 /* If Vbus is present, enable the controller and wait for reset */
1978 udc->vbus_prev = vbus_is_present(udc);
1979 if (udc->vbus_prev) {
1980 ret = usba_start(udc);
1981 if (ret)
1982 goto err;
1983 }
1984
1985 mutex_unlock(&udc->vbus_mutex);
1986 return 0;
1987
1988 err:
1989 if (udc->vbus_pin)
1990 disable_irq(gpiod_to_irq(udc->vbus_pin));
1991
1992 mutex_unlock(&udc->vbus_mutex);
1993
1994 spin_lock_irqsave(&udc->lock, flags);
1995 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1996 udc->driver = NULL;
1997 spin_unlock_irqrestore(&udc->lock, flags);
1998 return ret;
1999 }
2000
2001 static int atmel_usba_stop(struct usb_gadget *gadget)
2002 {
2003 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
2004
2005 if (udc->vbus_pin)
2006 disable_irq(gpiod_to_irq(udc->vbus_pin));
2007
2008 if (fifo_mode == 0)
2009 udc->configured_ep = 1;
2010
2011 udc->suspended = false;
2012 usba_stop(udc);
2013
2014 udc->driver = NULL;
2015
2016 return 0;
2017 }
2018
2019 static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
2020 {
2021 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2022 is_on ? AT91_PMC_BIASEN : 0);
2023 }
2024
2025 static void at91sam9g45_pulse_bias(struct usba_udc *udc)
2026 {
2027 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
2028 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2029 AT91_PMC_BIASEN);
2030 }
2031
2032 static const struct usba_udc_errata at91sam9rl_errata = {
2033 .toggle_bias = at91sam9rl_toggle_bias,
2034 };
2035
2036 static const struct usba_udc_errata at91sam9g45_errata = {
2037 .pulse_bias = at91sam9g45_pulse_bias,
2038 };
2039
2040 static const struct usba_ep_config ep_config_sam9[] __initconst = {
2041 { .nr_banks = 1 }, /* ep 0 */
2042 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */
2043 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */
2044 { .nr_banks = 3, .can_dma = 1 }, /* ep 3 */
2045 { .nr_banks = 3, .can_dma = 1 }, /* ep 4 */
2046 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */
2047 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */
2048 };
2049
2050 static const struct usba_ep_config ep_config_sama5[] __initconst = {
2051 { .nr_banks = 1 }, /* ep 0 */
2052 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */
2053 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */
2054 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 3 */
2055 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 4 */
2056 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */
2057 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */
2058 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 7 */
2059 { .nr_banks = 2, .can_isoc = 1 }, /* ep 8 */
2060 { .nr_banks = 2, .can_isoc = 1 }, /* ep 9 */
2061 { .nr_banks = 2, .can_isoc = 1 }, /* ep 10 */
2062 { .nr_banks = 2, .can_isoc = 1 }, /* ep 11 */
2063 { .nr_banks = 2, .can_isoc = 1 }, /* ep 12 */
2064 { .nr_banks = 2, .can_isoc = 1 }, /* ep 13 */
2065 { .nr_banks = 2, .can_isoc = 1 }, /* ep 14 */
2066 { .nr_banks = 2, .can_isoc = 1 }, /* ep 15 */
2067 };
2068
2069 static const struct usba_udc_config udc_at91sam9rl_cfg = {
2070 .errata = &at91sam9rl_errata,
2071 .config = ep_config_sam9,
2072 .num_ep = ARRAY_SIZE(ep_config_sam9),
2073 };
2074
2075 static const struct usba_udc_config udc_at91sam9g45_cfg = {
2076 .errata = &at91sam9g45_errata,
2077 .config = ep_config_sam9,
2078 .num_ep = ARRAY_SIZE(ep_config_sam9),
2079 };
2080
2081 static const struct usba_udc_config udc_sama5d3_cfg = {
2082 .config = ep_config_sama5,
2083 .num_ep = ARRAY_SIZE(ep_config_sama5),
2084 };
2085
2086 static const struct of_device_id atmel_udc_dt_ids[] = {
2087 { .compatible = "atmel,at91sam9rl-udc", .data = &udc_at91sam9rl_cfg },
2088 { .compatible = "atmel,at91sam9g45-udc", .data = &udc_at91sam9g45_cfg },
2089 { .compatible = "atmel,sama5d3-udc", .data = &udc_sama5d3_cfg },
2090 { /* sentinel */ }
2091 };
2092
2093 MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
2094
2095 static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
2096 struct usba_udc *udc)
2097 {
2098 struct device_node *np = pdev->dev.of_node;
2099 const struct of_device_id *match;
2100 int i, ret;
2101 struct usba_ep *eps, *ep;
2102 const struct usba_udc_config *udc_config;
2103
2104 match = of_match_node(atmel_udc_dt_ids, np);
2105 if (!match)
2106 return ERR_PTR(-EINVAL);
2107
2108 udc_config = match->data;
2109 udc->errata = udc_config->errata;
2110 udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
2111 if (IS_ERR(udc->pmc))
2112 udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9rl-pmc");
2113 if (IS_ERR(udc->pmc))
2114 udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
2115 if (udc->errata && IS_ERR(udc->pmc))
2116 return ERR_CAST(udc->pmc);
2117
2118 udc->num_ep = 0;
2119
2120 udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus",
2121 GPIOD_IN);
2122
2123 if (fifo_mode == 0) {
2124 udc->num_ep = udc_config->num_ep;
2125 udc->configured_ep = 1;
2126 } else {
2127 udc->num_ep = usba_config_fifo_table(udc);
2128 }
2129
2130 eps = devm_kcalloc(&pdev->dev, udc->num_ep, sizeof(struct usba_ep),
2131 GFP_KERNEL);
2132 if (!eps)
2133 return ERR_PTR(-ENOMEM);
2134
2135 udc->gadget.ep0 = &eps[0].ep;
2136
2137 INIT_LIST_HEAD(&eps[0].ep.ep_list);
2138
2139 i = 0;
2140 while (i < udc->num_ep) {
2141 const struct usba_ep_config *ep_cfg = &udc_config->config[i];
2142
2143 ep = &eps[i];
2144
2145 ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : i;
2146
2147 /* Only the first EP is 64 bytes */
2148 if (ep->index == 0)
2149 ep->fifo_size = 64;
2150 else
2151 ep->fifo_size = 1024;
2152
2153 if (fifo_mode) {
2154 if (ep->fifo_size < udc->fifo_cfg[i].fifo_size)
2155 dev_warn(&pdev->dev,
2156 "Using default max fifo-size value\n");
2157 else
2158 ep->fifo_size = udc->fifo_cfg[i].fifo_size;
2159 }
2160
2161 ep->nr_banks = ep_cfg->nr_banks;
2162 if (fifo_mode) {
2163 if (ep->nr_banks < udc->fifo_cfg[i].nr_banks)
2164 dev_warn(&pdev->dev,
2165 "Using default max nb-banks value\n");
2166 else
2167 ep->nr_banks = udc->fifo_cfg[i].nr_banks;
2168 }
2169
2170 ep->can_dma = ep_cfg->can_dma;
2171 ep->can_isoc = ep_cfg->can_isoc;
2172
2173 sprintf(ep->name, "ep%d", ep->index);
2174 ep->ep.name = ep->name;
2175
2176 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
2177 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
2178 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
2179 ep->ep.ops = &usba_ep_ops;
2180 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
2181 ep->udc = udc;
2182 INIT_LIST_HEAD(&ep->queue);
2183
2184 if (ep->index == 0) {
2185 ep->ep.caps.type_control = true;
2186 } else {
2187 ep->ep.caps.type_iso = ep->can_isoc;
2188 ep->ep.caps.type_bulk = true;
2189 ep->ep.caps.type_int = true;
2190 }
2191
2192 ep->ep.caps.dir_in = true;
2193 ep->ep.caps.dir_out = true;
2194
2195 if (fifo_mode != 0) {
2196 /*
2197 * Generate ept_cfg based on FIFO size and
2198 * banks number
2199 */
2200 if (ep->fifo_size <= 8)
2201 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
2202 else
2203 /* LSB is bit 1, not 0 */
2204 ep->ept_cfg =
2205 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
2206
2207 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
2208 }
2209
2210 if (i)
2211 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2212
2213 i++;
2214 }
2215
2216 if (i == 0) {
2217 dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
2218 ret = -EINVAL;
2219 goto err;
2220 }
2221
2222 return eps;
2223 err:
2224 return ERR_PTR(ret);
2225 }
2226
2227 static int usba_udc_probe(struct platform_device *pdev)
2228 {
2229 struct resource *res;
2230 struct clk *pclk, *hclk;
2231 struct usba_udc *udc;
2232 int irq, ret, i;
2233
2234 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2235 if (!udc)
2236 return -ENOMEM;
2237
2238 udc->gadget = usba_gadget_template;
2239 INIT_LIST_HEAD(&udc->gadget.ep_list);
2240
2241 res = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
2242 udc->regs = devm_ioremap_resource(&pdev->dev, res);
2243 if (IS_ERR(udc->regs))
2244 return PTR_ERR(udc->regs);
2245 dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n",
2246 res, udc->regs);
2247
2248 res = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
2249 udc->fifo = devm_ioremap_resource(&pdev->dev, res);
2250 if (IS_ERR(udc->fifo))
2251 return PTR_ERR(udc->fifo);
2252 dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo);
2253
2254 irq = platform_get_irq(pdev, 0);
2255 if (irq < 0)
2256 return irq;
2257
2258 pclk = devm_clk_get(&pdev->dev, "pclk");
2259 if (IS_ERR(pclk))
2260 return PTR_ERR(pclk);
2261 hclk = devm_clk_get(&pdev->dev, "hclk");
2262 if (IS_ERR(hclk))
2263 return PTR_ERR(hclk);
2264
2265 spin_lock_init(&udc->lock);
2266 mutex_init(&udc->vbus_mutex);
2267 udc->pdev = pdev;
2268 udc->pclk = pclk;
2269 udc->hclk = hclk;
2270
2271 platform_set_drvdata(pdev, udc);
2272
2273 /* Make sure we start from a clean slate */
2274 ret = clk_prepare_enable(pclk);
2275 if (ret) {
2276 dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
2277 return ret;
2278 }
2279
2280 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
2281 clk_disable_unprepare(pclk);
2282
2283 udc->usba_ep = atmel_udc_of_init(pdev, udc);
2284
2285 toggle_bias(udc, 0);
2286
2287 if (IS_ERR(udc->usba_ep))
2288 return PTR_ERR(udc->usba_ep);
2289
2290 ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
2291 "atmel_usba_udc", udc);
2292 if (ret) {
2293 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
2294 irq, ret);
2295 return ret;
2296 }
2297 udc->irq = irq;
2298
2299 if (udc->vbus_pin) {
2300 irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN);
2301 ret = devm_request_threaded_irq(&pdev->dev,
2302 gpiod_to_irq(udc->vbus_pin), NULL,
2303 usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
2304 "atmel_usba_udc", udc);
2305 if (ret) {
2306 udc->vbus_pin = NULL;
2307 dev_warn(&udc->pdev->dev,
2308 "failed to request vbus irq; "
2309 "assuming always on\n");
2310 }
2311 }
2312
2313 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2314 if (ret)
2315 return ret;
2316 device_init_wakeup(&pdev->dev, 1);
2317
2318 usba_init_debugfs(udc);
2319 for (i = 1; i < udc->num_ep; i++)
2320 usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
2321
2322 return 0;
2323 }
2324
2325 static int usba_udc_remove(struct platform_device *pdev)
2326 {
2327 struct usba_udc *udc;
2328 int i;
2329
2330 udc = platform_get_drvdata(pdev);
2331
2332 device_init_wakeup(&pdev->dev, 0);
2333 usb_del_gadget_udc(&udc->gadget);
2334
2335 for (i = 1; i < udc->num_ep; i++)
2336 usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
2337 usba_cleanup_debugfs(udc);
2338
2339 return 0;
2340 }
2341
2342 #ifdef CONFIG_PM_SLEEP
2343 static int usba_udc_suspend(struct device *dev)
2344 {
2345 struct usba_udc *udc = dev_get_drvdata(dev);
2346
2347 /* Not started */
2348 if (!udc->driver)
2349 return 0;
2350
2351 mutex_lock(&udc->vbus_mutex);
2352
2353 if (!device_may_wakeup(dev)) {
2354 udc->suspended = false;
2355 usba_stop(udc);
2356 goto out;
2357 }
2358
2359 /*
2360 * Device may wake up. We stay clocked if we failed
2361 * to request vbus irq, assuming always on.
2362 */
2363 if (udc->vbus_pin) {
2364 /* FIXME: right to stop here...??? */
2365 usba_stop(udc);
2366 enable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2367 }
2368
2369 enable_irq_wake(udc->irq);
2370
2371 out:
2372 mutex_unlock(&udc->vbus_mutex);
2373 return 0;
2374 }
2375
2376 static int usba_udc_resume(struct device *dev)
2377 {
2378 struct usba_udc *udc = dev_get_drvdata(dev);
2379
2380 /* Not started */
2381 if (!udc->driver)
2382 return 0;
2383
2384 if (device_may_wakeup(dev)) {
2385 if (udc->vbus_pin)
2386 disable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2387
2388 disable_irq_wake(udc->irq);
2389 }
2390
2391 /* If Vbus is present, enable the controller and wait for reset */
2392 mutex_lock(&udc->vbus_mutex);
2393 udc->vbus_prev = vbus_is_present(udc);
2394 if (udc->vbus_prev)
2395 usba_start(udc);
2396 mutex_unlock(&udc->vbus_mutex);
2397
2398 return 0;
2399 }
2400 #endif
2401
2402 static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
2403
2404 static struct platform_driver udc_driver = {
2405 .remove = usba_udc_remove,
2406 .driver = {
2407 .name = "atmel_usba_udc",
2408 .pm = &usba_udc_pm_ops,
2409 .of_match_table = atmel_udc_dt_ids,
2410 },
2411 };
2412
2413 module_platform_driver_probe(udc_driver, usba_udc_probe);
2414
2415 MODULE_DESCRIPTION("Atmel USBA UDC driver");
2416 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2417 MODULE_LICENSE("GPL");
2418 MODULE_ALIAS("platform:atmel_usba_udc");
Linux with added FPC-III support