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net: qmi_wwan: add Olivetti Olicard 500
[linux/fpc-iii.git] / drivers / ata / sata_fsl.c
blobfb0b40a191c217e47202d252aff5a36d21cf6f6b
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30
31 static unsigned int intr_coalescing_count;
32 module_param(intr_coalescing_count, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_count,
34 "INT coalescing count threshold (1..31)");
35
36 static unsigned int intr_coalescing_ticks;
37 module_param(intr_coalescing_ticks, int, S_IRUGO);
38 MODULE_PARM_DESC(intr_coalescing_ticks,
39 "INT coalescing timer threshold in AHB ticks");
40 /* Controller information */
41 enum {
42 SATA_FSL_QUEUE_DEPTH = 16,
43 SATA_FSL_MAX_PRD = 63,
44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
46
47 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
48 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
49
50 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
51 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
52 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
53
54 /*
55 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
56 * chained indirect PRDEs up to a max count of 63.
57 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
58 * be setup as an indirect descriptor, pointing to it's next
59 * (contiguous) PRDE. Though chained indirect PRDE arrays are
60 * supported,it will be more efficient to use a direct PRDT and
61 * a single chain/link to indirect PRDE array/PRDT.
62 */
63
64 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
65 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
66 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
67 SATA_FSL_CMD_DESC_RSRVD = 16,
68
69 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
70 SATA_FSL_CMD_DESC_SFIS_SZ +
71 SATA_FSL_CMD_DESC_ACMD_SZ +
72 SATA_FSL_CMD_DESC_RSRVD +
73 SATA_FSL_MAX_PRD * 16),
74
75 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
76 (SATA_FSL_CMD_DESC_CFIS_SZ +
77 SATA_FSL_CMD_DESC_SFIS_SZ +
78 SATA_FSL_CMD_DESC_ACMD_SZ +
79 SATA_FSL_CMD_DESC_RSRVD),
80
81 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
82 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
83 SATA_FSL_CMD_DESC_AR_SZ),
84
85 /*
86 * MPC8315 has two SATA controllers, SATA1 & SATA2
87 * (one port per controller)
88 * MPC837x has 2/4 controllers, one port per controller
89 */
90
91 SATA_FSL_MAX_PORTS = 1,
92
93 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
94 };
95
96 /*
97 * Interrupt Coalescing Control Register bitdefs */
98 enum {
99 ICC_MIN_INT_COUNT_THRESHOLD = 1,
100 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
101 ICC_MIN_INT_TICKS_THRESHOLD = 0,
102 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
103 ICC_SAFE_INT_TICKS = 1,
104 };
105
106 /*
107 * Host Controller command register set - per port
108 */
109 enum {
110 CQ = 0,
111 CA = 8,
112 CC = 0x10,
113 CE = 0x18,
114 DE = 0x20,
115 CHBA = 0x24,
116 HSTATUS = 0x28,
117 HCONTROL = 0x2C,
118 CQPMP = 0x30,
119 SIGNATURE = 0x34,
120 ICC = 0x38,
121
122 /*
123 * Host Status Register (HStatus) bitdefs
124 */
125 ONLINE = (1 << 31),
126 GOING_OFFLINE = (1 << 30),
127 BIST_ERR = (1 << 29),
128 CLEAR_ERROR = (1 << 27),
129
130 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
131 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
132 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
133 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
134 FATAL_ERR_DATA_OVERRUN = (1 << 12),
135 FATAL_ERR_CRC_ERR_TX = (1 << 11),
136 FATAL_ERR_CRC_ERR_RX = (1 << 10),
137 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
138 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
139
140 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
141 FATAL_ERR_PARITY_ERR_TX |
142 FATAL_ERR_PARITY_ERR_RX |
143 FATAL_ERR_DATA_UNDERRUN |
144 FATAL_ERR_DATA_OVERRUN |
145 FATAL_ERR_CRC_ERR_TX |
146 FATAL_ERR_CRC_ERR_RX |
147 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
148
149 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
150 INT_ON_FATAL_ERR = (1 << 5),
151 INT_ON_PHYRDY_CHG = (1 << 4),
152
153 INT_ON_SIGNATURE_UPDATE = (1 << 3),
154 INT_ON_SNOTIFY_UPDATE = (1 << 2),
155 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
156 INT_ON_CMD_COMPLETE = 1,
157
158 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
159 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
160
161 /*
162 * Host Control Register (HControl) bitdefs
163 */
164 HCONTROL_ONLINE_PHY_RST = (1 << 31),
165 HCONTROL_FORCE_OFFLINE = (1 << 30),
166 HCONTROL_LEGACY = (1 << 28),
167 HCONTROL_PARITY_PROT_MOD = (1 << 14),
168 HCONTROL_DPATH_PARITY = (1 << 12),
169 HCONTROL_SNOOP_ENABLE = (1 << 10),
170 HCONTROL_PMP_ATTACHED = (1 << 9),
171 HCONTROL_COPYOUT_STATFIS = (1 << 8),
172 IE_ON_FATAL_ERR = (1 << 5),
173 IE_ON_PHYRDY_CHG = (1 << 4),
174 IE_ON_SIGNATURE_UPDATE = (1 << 3),
175 IE_ON_SNOTIFY_UPDATE = (1 << 2),
176 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
177 IE_ON_CMD_COMPLETE = 1,
178
179 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
180 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
181 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
182
183 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
184 DATA_SNOOP_ENABLE_V1 = (1 << 22),
185 DATA_SNOOP_ENABLE_V2 = (1 << 28),
186 };
187
188 /*
189 * SATA Superset Registers
190 */
191 enum {
192 SSTATUS = 0,
193 SERROR = 4,
194 SCONTROL = 8,
195 SNOTIFY = 0xC,
196 };
197
198 /*
199 * Control Status Register Set
200 */
201 enum {
202 TRANSCFG = 0,
203 TRANSSTATUS = 4,
204 LINKCFG = 8,
205 LINKCFG1 = 0xC,
206 LINKCFG2 = 0x10,
207 LINKSTATUS = 0x14,
208 LINKSTATUS1 = 0x18,
209 PHYCTRLCFG = 0x1C,
210 COMMANDSTAT = 0x20,
211 };
212
213 /* TRANSCFG (transport-layer) configuration control */
214 enum {
215 TRANSCFG_RX_WATER_MARK = (1 << 4),
216 };
217
218 /* PHY (link-layer) configuration control */
219 enum {
220 PHY_BIST_ENABLE = 0x01,
221 };
222
223 /*
224 * Command Header Table entry, i.e, command slot
225 * 4 Dwords per command slot, command header size == 64 Dwords.
226 */
227 struct cmdhdr_tbl_entry {
228 u32 cda;
229 u32 prde_fis_len;
230 u32 ttl;
231 u32 desc_info;
232 };
233
234 /*
235 * Description information bitdefs
236 */
237 enum {
238 CMD_DESC_RES = (1 << 11),
239 VENDOR_SPECIFIC_BIST = (1 << 10),
240 CMD_DESC_SNOOP_ENABLE = (1 << 9),
241 FPDMA_QUEUED_CMD = (1 << 8),
242 SRST_CMD = (1 << 7),
243 BIST = (1 << 6),
244 ATAPI_CMD = (1 << 5),
245 };
246
247 /*
248 * Command Descriptor
249 */
250 struct command_desc {
251 u8 cfis[8 * 4];
252 u8 sfis[8 * 4];
253 u8 acmd[4 * 4];
254 u8 fill[4 * 4];
255 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
256 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
257 };
258
259 /*
260 * Physical region table descriptor(PRD)
261 */
262
263 struct prde {
264 u32 dba;
265 u8 fill[2 * 4];
266 u32 ddc_and_ext;
267 };
268
269 /*
270 * ata_port private data
271 * This is our per-port instance data.
272 */
273 struct sata_fsl_port_priv {
274 struct cmdhdr_tbl_entry *cmdslot;
275 dma_addr_t cmdslot_paddr;
276 struct command_desc *cmdentry;
277 dma_addr_t cmdentry_paddr;
278 };
279
280 /*
281 * ata_port->host_set private data
282 */
283 struct sata_fsl_host_priv {
284 void __iomem *hcr_base;
285 void __iomem *ssr_base;
286 void __iomem *csr_base;
287 int irq;
288 int data_snoop;
289 struct device_attribute intr_coalescing;
290 struct device_attribute rx_watermark;
291 };
292
293 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
294 unsigned int count, unsigned int ticks)
295 {
296 struct sata_fsl_host_priv *host_priv = host->private_data;
297 void __iomem *hcr_base = host_priv->hcr_base;
298 unsigned long flags;
299
300 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
301 count = ICC_MAX_INT_COUNT_THRESHOLD;
302 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
303 count = ICC_MIN_INT_COUNT_THRESHOLD;
304
305 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
306 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
307 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
308 (count > ICC_MIN_INT_COUNT_THRESHOLD))
309 ticks = ICC_SAFE_INT_TICKS;
310
311 spin_lock_irqsave(&host->lock, flags);
312 iowrite32((count << 24 | ticks), hcr_base + ICC);
313
314 intr_coalescing_count = count;
315 intr_coalescing_ticks = ticks;
316 spin_unlock_irqrestore(&host->lock, flags);
317
318 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
319 intr_coalescing_count, intr_coalescing_ticks);
320 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
321 hcr_base, ioread32(hcr_base + ICC));
322 }
323
324 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
325 struct device_attribute *attr, char *buf)
326 {
327 return sprintf(buf, "%d %d\n",
328 intr_coalescing_count, intr_coalescing_ticks);
329 }
330
331 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
332 struct device_attribute *attr,
333 const char *buf, size_t count)
334 {
335 unsigned int coalescing_count, coalescing_ticks;
336
337 if (sscanf(buf, "%d%d",
338 &coalescing_count,
339 &coalescing_ticks) != 2) {
340 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
341 return -EINVAL;
342 }
343
344 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
345 coalescing_count, coalescing_ticks);
346
347 return strlen(buf);
348 }
349
350 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
351 struct device_attribute *attr, char *buf)
352 {
353 unsigned int rx_watermark;
354 unsigned long flags;
355 struct ata_host *host = dev_get_drvdata(dev);
356 struct sata_fsl_host_priv *host_priv = host->private_data;
357 void __iomem *csr_base = host_priv->csr_base;
358
359 spin_lock_irqsave(&host->lock, flags);
360 rx_watermark = ioread32(csr_base + TRANSCFG);
361 rx_watermark &= 0x1f;
362
363 spin_unlock_irqrestore(&host->lock, flags);
364 return sprintf(buf, "%d\n", rx_watermark);
365 }
366
367 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
368 struct device_attribute *attr,
369 const char *buf, size_t count)
370 {
371 unsigned int rx_watermark;
372 unsigned long flags;
373 struct ata_host *host = dev_get_drvdata(dev);
374 struct sata_fsl_host_priv *host_priv = host->private_data;
375 void __iomem *csr_base = host_priv->csr_base;
376 u32 temp;
377
378 if (sscanf(buf, "%d", &rx_watermark) != 1) {
379 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&host->lock, flags);
384 temp = ioread32(csr_base + TRANSCFG);
385 temp &= 0xffffffe0;
386 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
387
388 spin_unlock_irqrestore(&host->lock, flags);
389 return strlen(buf);
390 }
391
392 static inline unsigned int sata_fsl_tag(unsigned int tag,
393 void __iomem *hcr_base)
394 {
395 /* We let libATA core do actual (queue) tag allocation */
396
397 /* all non NCQ/queued commands should have tag#0 */
398 if (ata_tag_internal(tag)) {
399 DPRINTK("mapping internal cmds to tag#0\n");
400 return 0;
401 }
402
403 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
404 DPRINTK("tag %d invalid : out of range\n", tag);
405 return 0;
406 }
407
408 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
409 DPRINTK("tag %d invalid : in use!!\n", tag);
410 return 0;
411 }
412
413 return tag;
414 }
415
416 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
417 unsigned int tag, u32 desc_info,
418 u32 data_xfer_len, u8 num_prde,
419 u8 fis_len)
420 {
421 dma_addr_t cmd_descriptor_address;
422
423 cmd_descriptor_address = pp->cmdentry_paddr +
424 tag * SATA_FSL_CMD_DESC_SIZE;
425
426 /* NOTE: both data_xfer_len & fis_len are Dword counts */
427
428 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
429 pp->cmdslot[tag].prde_fis_len =
430 cpu_to_le32((num_prde << 16) | (fis_len << 2));
431 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
432 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
433
434 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
435 pp->cmdslot[tag].cda,
436 pp->cmdslot[tag].prde_fis_len,
437 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
438
439 }
440
441 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
442 u32 *ttl, dma_addr_t cmd_desc_paddr,
443 int data_snoop)
444 {
445 struct scatterlist *sg;
446 unsigned int num_prde = 0;
447 u32 ttl_dwords = 0;
448
449 /*
450 * NOTE : direct & indirect prdt's are contiguously allocated
451 */
452 struct prde *prd = (struct prde *)&((struct command_desc *)
453 cmd_desc)->prdt;
454
455 struct prde *prd_ptr_to_indirect_ext = NULL;
456 unsigned indirect_ext_segment_sz = 0;
457 dma_addr_t indirect_ext_segment_paddr;
458 unsigned int si;
459
460 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
461
462 indirect_ext_segment_paddr = cmd_desc_paddr +
463 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
464
465 for_each_sg(qc->sg, sg, qc->n_elem, si) {
466 dma_addr_t sg_addr = sg_dma_address(sg);
467 u32 sg_len = sg_dma_len(sg);
468
469 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
470 (unsigned long long)sg_addr, sg_len);
471
472 /* warn if each s/g element is not dword aligned */
473 if (unlikely(sg_addr & 0x03))
474 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
475 (unsigned long long)sg_addr);
476 if (unlikely(sg_len & 0x03))
477 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
478 sg_len);
479
480 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
481 sg_next(sg) != NULL) {
482 VPRINTK("setting indirect prde\n");
483 prd_ptr_to_indirect_ext = prd;
484 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
485 indirect_ext_segment_sz = 0;
486 ++prd;
487 ++num_prde;
488 }
489
490 ttl_dwords += sg_len;
491 prd->dba = cpu_to_le32(sg_addr);
492 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
493
494 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
495 ttl_dwords, prd->dba, prd->ddc_and_ext);
496
497 ++num_prde;
498 ++prd;
499 if (prd_ptr_to_indirect_ext)
500 indirect_ext_segment_sz += sg_len;
501 }
502
503 if (prd_ptr_to_indirect_ext) {
504 /* set indirect extension flag along with indirect ext. size */
505 prd_ptr_to_indirect_ext->ddc_and_ext =
506 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
507 data_snoop |
508 (indirect_ext_segment_sz & ~0x03)));
509 }
510
511 *ttl = ttl_dwords;
512 return num_prde;
513 }
514
515 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
516 {
517 struct ata_port *ap = qc->ap;
518 struct sata_fsl_port_priv *pp = ap->private_data;
519 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
520 void __iomem *hcr_base = host_priv->hcr_base;
521 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
522 struct command_desc *cd;
523 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
524 u32 num_prde = 0;
525 u32 ttl_dwords = 0;
526 dma_addr_t cd_paddr;
527
528 cd = (struct command_desc *)pp->cmdentry + tag;
529 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
530
531 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
532
533 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
534 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
535
536 if (qc->tf.protocol == ATA_PROT_NCQ) {
537 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
538 cd->cfis[3], cd->cfis[11]);
539 }
540
541 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
542 if (ata_is_atapi(qc->tf.protocol)) {
543 desc_info |= ATAPI_CMD;
544 memset((void *)&cd->acmd, 0, 32);
545 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
546 }
547
548 if (qc->flags & ATA_QCFLAG_DMAMAP)
549 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
550 &ttl_dwords, cd_paddr,
551 host_priv->data_snoop);
552
553 if (qc->tf.protocol == ATA_PROT_NCQ)
554 desc_info |= FPDMA_QUEUED_CMD;
555
556 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
557 num_prde, 5);
558
559 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
560 desc_info, ttl_dwords, num_prde);
561 }
562
563 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
564 {
565 struct ata_port *ap = qc->ap;
566 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
567 void __iomem *hcr_base = host_priv->hcr_base;
568 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
569
570 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
571 ioread32(CQ + hcr_base),
572 ioread32(CA + hcr_base),
573 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
574
575 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
576
577 /* Simply queue command to the controller/device */
578 iowrite32(1 << tag, CQ + hcr_base);
579
580 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
581 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
582
583 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
584 ioread32(CE + hcr_base),
585 ioread32(DE + hcr_base),
586 ioread32(CC + hcr_base),
587 ioread32(COMMANDSTAT + host_priv->csr_base));
588
589 return 0;
590 }
591
592 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
593 {
594 struct sata_fsl_port_priv *pp = qc->ap->private_data;
595 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
596 void __iomem *hcr_base = host_priv->hcr_base;
597 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
598 struct command_desc *cd;
599
600 cd = pp->cmdentry + tag;
601
602 ata_tf_from_fis(cd->sfis, &qc->result_tf);
603 return true;
604 }
605
606 static int sata_fsl_scr_write(struct ata_link *link,
607 unsigned int sc_reg_in, u32 val)
608 {
609 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
610 void __iomem *ssr_base = host_priv->ssr_base;
611 unsigned int sc_reg;
612
613 switch (sc_reg_in) {
614 case SCR_STATUS:
615 case SCR_ERROR:
616 case SCR_CONTROL:
617 case SCR_ACTIVE:
618 sc_reg = sc_reg_in;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
625
626 iowrite32(val, ssr_base + (sc_reg * 4));
627 return 0;
628 }
629
630 static int sata_fsl_scr_read(struct ata_link *link,
631 unsigned int sc_reg_in, u32 *val)
632 {
633 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
634 void __iomem *ssr_base = host_priv->ssr_base;
635 unsigned int sc_reg;
636
637 switch (sc_reg_in) {
638 case SCR_STATUS:
639 case SCR_ERROR:
640 case SCR_CONTROL:
641 case SCR_ACTIVE:
642 sc_reg = sc_reg_in;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
649
650 *val = ioread32(ssr_base + (sc_reg * 4));
651 return 0;
652 }
653
654 static void sata_fsl_freeze(struct ata_port *ap)
655 {
656 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
657 void __iomem *hcr_base = host_priv->hcr_base;
658 u32 temp;
659
660 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
661 ioread32(CQ + hcr_base),
662 ioread32(CA + hcr_base),
663 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
664 VPRINTK("CmdStat = 0x%x\n",
665 ioread32(host_priv->csr_base + COMMANDSTAT));
666
667 /* disable interrupts on the controller/port */
668 temp = ioread32(hcr_base + HCONTROL);
669 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
670
671 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
672 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
673 }
674
675 static void sata_fsl_thaw(struct ata_port *ap)
676 {
677 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
678 void __iomem *hcr_base = host_priv->hcr_base;
679 u32 temp;
680
681 /* ack. any pending IRQs for this controller/port */
682 temp = ioread32(hcr_base + HSTATUS);
683
684 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
685
686 if (temp & 0x3F)
687 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
688
689 /* enable interrupts on the controller/port */
690 temp = ioread32(hcr_base + HCONTROL);
691 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
692
693 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
694 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
695 }
696
697 static void sata_fsl_pmp_attach(struct ata_port *ap)
698 {
699 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
700 void __iomem *hcr_base = host_priv->hcr_base;
701 u32 temp;
702
703 temp = ioread32(hcr_base + HCONTROL);
704 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
705 }
706
707 static void sata_fsl_pmp_detach(struct ata_port *ap)
708 {
709 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
710 void __iomem *hcr_base = host_priv->hcr_base;
711 u32 temp;
712
713 temp = ioread32(hcr_base + HCONTROL);
714 temp &= ~HCONTROL_PMP_ATTACHED;
715 iowrite32(temp, hcr_base + HCONTROL);
716
717 /* enable interrupts on the controller/port */
718 temp = ioread32(hcr_base + HCONTROL);
719 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
720
721 }
722
723 static int sata_fsl_port_start(struct ata_port *ap)
724 {
725 struct device *dev = ap->host->dev;
726 struct sata_fsl_port_priv *pp;
727 void *mem;
728 dma_addr_t mem_dma;
729 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
730 void __iomem *hcr_base = host_priv->hcr_base;
731 u32 temp;
732
733 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
734 if (!pp)
735 return -ENOMEM;
736
737 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
738 GFP_KERNEL);
739 if (!mem) {
740 kfree(pp);
741 return -ENOMEM;
742 }
743 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
744
745 pp->cmdslot = mem;
746 pp->cmdslot_paddr = mem_dma;
747
748 mem += SATA_FSL_CMD_SLOT_SIZE;
749 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
750
751 pp->cmdentry = mem;
752 pp->cmdentry_paddr = mem_dma;
753
754 ap->private_data = pp;
755
756 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
757 pp->cmdslot_paddr, pp->cmdentry_paddr);
758
759 /* Now, update the CHBA register in host controller cmd register set */
760 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
761
762 /*
763 * Now, we can bring the controller on-line & also initiate
764 * the COMINIT sequence, we simply return here and the boot-probing
765 * & device discovery process is re-initiated by libATA using a
766 * Softreset EH (dummy) session. Hence, boot probing and device
767 * discovey will be part of sata_fsl_softreset() callback.
768 */
769
770 temp = ioread32(hcr_base + HCONTROL);
771 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
772
773 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
774 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
775 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
776
777 #ifdef CONFIG_MPC8315_DS
778 /*
779 * Workaround for 8315DS board 3gbps link-up issue,
780 * currently limit SATA port to GEN1 speed
781 */
782 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
783 temp &= ~(0xF << 4);
784 temp |= (0x1 << 4);
785 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
786
787 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
788 dev_warn(dev, "scr_control, speed limited to %x\n", temp);
789 #endif
790
791 return 0;
792 }
793
794 static void sata_fsl_port_stop(struct ata_port *ap)
795 {
796 struct device *dev = ap->host->dev;
797 struct sata_fsl_port_priv *pp = ap->private_data;
798 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
799 void __iomem *hcr_base = host_priv->hcr_base;
800 u32 temp;
801
802 /*
803 * Force host controller to go off-line, aborting current operations
804 */
805 temp = ioread32(hcr_base + HCONTROL);
806 temp &= ~HCONTROL_ONLINE_PHY_RST;
807 temp |= HCONTROL_FORCE_OFFLINE;
808 iowrite32(temp, hcr_base + HCONTROL);
809
810 /* Poll for controller to go offline - should happen immediately */
811 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
812
813 ap->private_data = NULL;
814 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
815 pp->cmdslot, pp->cmdslot_paddr);
816
817 kfree(pp);
818 }
819
820 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
821 {
822 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
823 void __iomem *hcr_base = host_priv->hcr_base;
824 struct ata_taskfile tf;
825 u32 temp;
826
827 temp = ioread32(hcr_base + SIGNATURE);
828
829 VPRINTK("raw sig = 0x%x\n", temp);
830 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
831 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
832
833 tf.lbah = (temp >> 24) & 0xff;
834 tf.lbam = (temp >> 16) & 0xff;
835 tf.lbal = (temp >> 8) & 0xff;
836 tf.nsect = temp & 0xff;
837
838 return ata_dev_classify(&tf);
839 }
840
841 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
842 unsigned long deadline)
843 {
844 struct ata_port *ap = link->ap;
845 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
846 void __iomem *hcr_base = host_priv->hcr_base;
847 u32 temp;
848 int i = 0;
849 unsigned long start_jiffies;
850
851 DPRINTK("in xx_hardreset\n");
852
853 try_offline_again:
854 /*
855 * Force host controller to go off-line, aborting current operations
856 */
857 temp = ioread32(hcr_base + HCONTROL);
858 temp &= ~HCONTROL_ONLINE_PHY_RST;
859 iowrite32(temp, hcr_base + HCONTROL);
860
861 /* Poll for controller to go offline */
862 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
863 1, 500);
864
865 if (temp & ONLINE) {
866 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
867
868 /*
869 * Try to offline controller atleast twice
870 */
871 i++;
872 if (i == 2)
873 goto err;
874 else
875 goto try_offline_again;
876 }
877
878 DPRINTK("hardreset, controller off-lined\n");
879 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
880 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
881
882 /*
883 * PHY reset should remain asserted for atleast 1ms
884 */
885 ata_msleep(ap, 1);
886
887 /*
888 * Now, bring the host controller online again, this can take time
889 * as PHY reset and communication establishment, 1st D2H FIS and
890 * device signature update is done, on safe side assume 500ms
891 * NOTE : Host online status may be indicated immediately!!
892 */
893
894 temp = ioread32(hcr_base + HCONTROL);
895 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
896 temp |= HCONTROL_PMP_ATTACHED;
897 iowrite32(temp, hcr_base + HCONTROL);
898
899 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
900
901 if (!(temp & ONLINE)) {
902 ata_port_err(ap, "Hardreset failed, not on-lined\n");
903 goto err;
904 }
905
906 DPRINTK("hardreset, controller off-lined & on-lined\n");
907 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
908 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
909
910 /*
911 * First, wait for the PHYRDY change to occur before waiting for
912 * the signature, and also verify if SStatus indicates device
913 * presence
914 */
915
916 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
917 if ((!(temp & 0x10)) || ata_link_offline(link)) {
918 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
919 ioread32(hcr_base + HSTATUS));
920 *class = ATA_DEV_NONE;
921 return 0;
922 }
923
924 /*
925 * Wait for the first D2H from device,i.e,signature update notification
926 */
927 start_jiffies = jiffies;
928 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
929 500, jiffies_to_msecs(deadline - start_jiffies));
930
931 if ((temp & 0xFF) != 0x18) {
932 ata_port_warn(ap, "No Signature Update\n");
933 *class = ATA_DEV_NONE;
934 goto do_followup_srst;
935 } else {
936 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
937 jiffies_to_msecs(jiffies - start_jiffies));
938 *class = sata_fsl_dev_classify(ap);
939 return 0;
940 }
941
942 do_followup_srst:
943 /*
944 * request libATA to perform follow-up softreset
945 */
946 return -EAGAIN;
947
948 err:
949 return -EIO;
950 }
951
952 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
953 unsigned long deadline)
954 {
955 struct ata_port *ap = link->ap;
956 struct sata_fsl_port_priv *pp = ap->private_data;
957 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
958 void __iomem *hcr_base = host_priv->hcr_base;
959 int pmp = sata_srst_pmp(link);
960 u32 temp;
961 struct ata_taskfile tf;
962 u8 *cfis;
963 u32 Serror;
964
965 DPRINTK("in xx_softreset\n");
966
967 if (ata_link_offline(link)) {
968 DPRINTK("PHY reports no device\n");
969 *class = ATA_DEV_NONE;
970 return 0;
971 }
972
973 /*
974 * Send a device reset (SRST) explicitly on command slot #0
975 * Check : will the command queue (reg) be cleared during offlining ??
976 * Also we will be online only if Phy commn. has been established
977 * and device presence has been detected, therefore if we have
978 * reached here, we can send a command to the target device
979 */
980
981 DPRINTK("Sending SRST/device reset\n");
982
983 ata_tf_init(link->device, &tf);
984 cfis = (u8 *) &pp->cmdentry->cfis;
985
986 /* device reset/SRST is a control register update FIS, uses tag0 */
987 sata_fsl_setup_cmd_hdr_entry(pp, 0,
988 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
989
990 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
991 ata_tf_to_fis(&tf, pmp, 0, cfis);
992
993 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
994 cfis[0], cfis[1], cfis[2], cfis[3]);
995
996 /*
997 * Queue SRST command to the controller/device, ensure that no
998 * other commands are active on the controller/device
999 */
1000
1001 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
1002 ioread32(CQ + hcr_base),
1003 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1004
1005 iowrite32(0xFFFF, CC + hcr_base);
1006 if (pmp != SATA_PMP_CTRL_PORT)
1007 iowrite32(pmp, CQPMP + hcr_base);
1008 iowrite32(1, CQ + hcr_base);
1009
1010 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
1011 if (temp & 0x1) {
1012 ata_port_warn(ap, "ATA_SRST issue failed\n");
1013
1014 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1015 ioread32(CQ + hcr_base),
1016 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1017
1018 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1019
1020 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1021 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1022 DPRINTK("Serror = 0x%x\n", Serror);
1023 goto err;
1024 }
1025
1026 ata_msleep(ap, 1);
1027
1028 /*
1029 * SATA device enters reset state after receiving a Control register
1030 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1031 * FIS with SRST bit cleared, then the device does internal diags &
1032 * initialization, followed by indicating it's initialization status
1033 * using ATA signature D2H register FIS to the host controller.
1034 */
1035
1036 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1037 0, 0, 5);
1038
1039 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1040 ata_tf_to_fis(&tf, pmp, 0, cfis);
1041
1042 if (pmp != SATA_PMP_CTRL_PORT)
1043 iowrite32(pmp, CQPMP + hcr_base);
1044 iowrite32(1, CQ + hcr_base);
1045 ata_msleep(ap, 150); /* ?? */
1046
1047 /*
1048 * The above command would have signalled an interrupt on command
1049 * complete, which needs special handling, by clearing the Nth
1050 * command bit of the CCreg
1051 */
1052 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1053
1054 DPRINTK("SATA FSL : Now checking device signature\n");
1055
1056 *class = ATA_DEV_NONE;
1057
1058 /* Verify if SStatus indicates device presence */
1059 if (ata_link_online(link)) {
1060 /*
1061 * if we are here, device presence has been detected,
1062 * 1st D2H FIS would have been received, but sfis in
1063 * command desc. is not updated, but signature register
1064 * would have been updated
1065 */
1066
1067 *class = sata_fsl_dev_classify(ap);
1068
1069 DPRINTK("class = %d\n", *class);
1070 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1071 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1072 }
1073
1074 return 0;
1075
1076 err:
1077 return -EIO;
1078 }
1079
1080 static void sata_fsl_error_handler(struct ata_port *ap)
1081 {
1082
1083 DPRINTK("in xx_error_handler\n");
1084 sata_pmp_error_handler(ap);
1085
1086 }
1087
1088 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1089 {
1090 if (qc->flags & ATA_QCFLAG_FAILED)
1091 qc->err_mask |= AC_ERR_OTHER;
1092
1093 if (qc->err_mask) {
1094 /* make DMA engine forget about the failed command */
1095
1096 }
1097 }
1098
1099 static void sata_fsl_error_intr(struct ata_port *ap)
1100 {
1101 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1102 void __iomem *hcr_base = host_priv->hcr_base;
1103 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1104 unsigned int err_mask = 0, action = 0;
1105 int freeze = 0, abort=0;
1106 struct ata_link *link = NULL;
1107 struct ata_queued_cmd *qc = NULL;
1108 struct ata_eh_info *ehi;
1109
1110 hstatus = ioread32(hcr_base + HSTATUS);
1111 cereg = ioread32(hcr_base + CE);
1112
1113 /* first, analyze and record host port events */
1114 link = &ap->link;
1115 ehi = &link->eh_info;
1116 ata_ehi_clear_desc(ehi);
1117
1118 /*
1119 * Handle & Clear SError
1120 */
1121
1122 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1123 if (unlikely(SError & 0xFFFF0000))
1124 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1125
1126 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1127 hstatus, cereg, ioread32(hcr_base + DE), SError);
1128
1129 /* handle fatal errors */
1130 if (hstatus & FATAL_ERROR_DECODE) {
1131 ehi->err_mask |= AC_ERR_ATA_BUS;
1132 ehi->action |= ATA_EH_SOFTRESET;
1133
1134 freeze = 1;
1135 }
1136
1137 /* Handle SDB FIS receive & notify update */
1138 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1139 sata_async_notification(ap);
1140
1141 /* Handle PHYRDY change notification */
1142 if (hstatus & INT_ON_PHYRDY_CHG) {
1143 DPRINTK("SATA FSL: PHYRDY change indication\n");
1144
1145 /* Setup a soft-reset EH action */
1146 ata_ehi_hotplugged(ehi);
1147 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1148 freeze = 1;
1149 }
1150
1151 /* handle single device errors */
1152 if (cereg) {
1153 /*
1154 * clear the command error, also clears queue to the device
1155 * in error, and we can (re)issue commands to this device.
1156 * When a device is in error all commands queued into the
1157 * host controller and at the device are considered aborted
1158 * and the queue for that device is stopped. Now, after
1159 * clearing the device error, we can issue commands to the
1160 * device to interrogate it to find the source of the error.
1161 */
1162 abort = 1;
1163
1164 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1165 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1166
1167 /* find out the offending link and qc */
1168 if (ap->nr_pmp_links) {
1169 unsigned int dev_num;
1170
1171 dereg = ioread32(hcr_base + DE);
1172 iowrite32(dereg, hcr_base + DE);
1173 iowrite32(cereg, hcr_base + CE);
1174
1175 dev_num = ffs(dereg) - 1;
1176 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1177 link = &ap->pmp_link[dev_num];
1178 ehi = &link->eh_info;
1179 qc = ata_qc_from_tag(ap, link->active_tag);
1180 /*
1181 * We should consider this as non fatal error,
1182 * and TF must be updated as done below.
1183 */
1184
1185 err_mask |= AC_ERR_DEV;
1186
1187 } else {
1188 err_mask |= AC_ERR_HSM;
1189 action |= ATA_EH_HARDRESET;
1190 freeze = 1;
1191 }
1192 } else {
1193 dereg = ioread32(hcr_base + DE);
1194 iowrite32(dereg, hcr_base + DE);
1195 iowrite32(cereg, hcr_base + CE);
1196
1197 qc = ata_qc_from_tag(ap, link->active_tag);
1198 /*
1199 * We should consider this as non fatal error,
1200 * and TF must be updated as done below.
1201 */
1202 err_mask |= AC_ERR_DEV;
1203 }
1204 }
1205
1206 /* record error info */
1207 if (qc)
1208 qc->err_mask |= err_mask;
1209 else
1210 ehi->err_mask |= err_mask;
1211
1212 ehi->action |= action;
1213
1214 /* freeze or abort */
1215 if (freeze)
1216 ata_port_freeze(ap);
1217 else if (abort) {
1218 if (qc)
1219 ata_link_abort(qc->dev->link);
1220 else
1221 ata_port_abort(ap);
1222 }
1223 }
1224
1225 static void sata_fsl_host_intr(struct ata_port *ap)
1226 {
1227 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1228 void __iomem *hcr_base = host_priv->hcr_base;
1229 u32 hstatus, done_mask = 0;
1230 struct ata_queued_cmd *qc;
1231 u32 SError;
1232 u32 tag;
1233 u32 status_mask = INT_ON_ERROR;
1234
1235 hstatus = ioread32(hcr_base + HSTATUS);
1236
1237 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1238
1239 /* Read command completed register */
1240 done_mask = ioread32(hcr_base + CC);
1241
1242 /* Workaround for data length mismatch errata */
1243 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1244 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1245 qc = ata_qc_from_tag(ap, tag);
1246 if (qc && ata_is_atapi(qc->tf.protocol)) {
1247 u32 hcontrol;
1248 /* Set HControl[27] to clear error registers */
1249 hcontrol = ioread32(hcr_base + HCONTROL);
1250 iowrite32(hcontrol | CLEAR_ERROR,
1251 hcr_base + HCONTROL);
1252
1253 /* Clear HControl[27] */
1254 iowrite32(hcontrol & ~CLEAR_ERROR,
1255 hcr_base + HCONTROL);
1256
1257 /* Clear SError[E] bit */
1258 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1259 SError);
1260
1261 /* Ignore fatal error and device error */
1262 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1263 | INT_ON_FATAL_ERR);
1264 break;
1265 }
1266 }
1267 }
1268
1269 if (unlikely(SError & 0xFFFF0000)) {
1270 DPRINTK("serror @host_intr : 0x%x\n", SError);
1271 sata_fsl_error_intr(ap);
1272 }
1273
1274 if (unlikely(hstatus & status_mask)) {
1275 DPRINTK("error interrupt!!\n");
1276 sata_fsl_error_intr(ap);
1277 return;
1278 }
1279
1280 VPRINTK("Status of all queues :\n");
1281 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1282 done_mask,
1283 ioread32(hcr_base + CA),
1284 ioread32(hcr_base + CE),
1285 ioread32(hcr_base + CQ),
1286 ap->qc_active);
1287
1288 if (done_mask & ap->qc_active) {
1289 int i;
1290 /* clear CC bit, this will also complete the interrupt */
1291 iowrite32(done_mask, hcr_base + CC);
1292
1293 DPRINTK("Status of all queues :\n");
1294 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1295 done_mask, ioread32(hcr_base + CA),
1296 ioread32(hcr_base + CE));
1297
1298 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1299 if (done_mask & (1 << i))
1300 DPRINTK
1301 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1302 i, ioread32(hcr_base + CC),
1303 ioread32(hcr_base + CA));
1304 }
1305 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1306 return;
1307
1308 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1309 iowrite32(1, hcr_base + CC);
1310 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1311
1312 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1313 ioread32(hcr_base + CC));
1314
1315 if (qc) {
1316 ata_qc_complete(qc);
1317 }
1318 } else {
1319 /* Spurious Interrupt!! */
1320 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1321 ioread32(hcr_base + CC));
1322 iowrite32(done_mask, hcr_base + CC);
1323 return;
1324 }
1325 }
1326
1327 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1328 {
1329 struct ata_host *host = dev_instance;
1330 struct sata_fsl_host_priv *host_priv = host->private_data;
1331 void __iomem *hcr_base = host_priv->hcr_base;
1332 u32 interrupt_enables;
1333 unsigned handled = 0;
1334 struct ata_port *ap;
1335
1336 /* ack. any pending IRQs for this controller/port */
1337 interrupt_enables = ioread32(hcr_base + HSTATUS);
1338 interrupt_enables &= 0x3F;
1339
1340 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1341
1342 if (!interrupt_enables)
1343 return IRQ_NONE;
1344
1345 spin_lock(&host->lock);
1346
1347 /* Assuming one port per host controller */
1348
1349 ap = host->ports[0];
1350 if (ap) {
1351 sata_fsl_host_intr(ap);
1352 } else {
1353 dev_warn(host->dev, "interrupt on disabled port 0\n");
1354 }
1355
1356 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1357 handled = 1;
1358
1359 spin_unlock(&host->lock);
1360
1361 return IRQ_RETVAL(handled);
1362 }
1363
1364 /*
1365 * Multiple ports are represented by multiple SATA controllers with
1366 * one port per controller
1367 */
1368 static int sata_fsl_init_controller(struct ata_host *host)
1369 {
1370 struct sata_fsl_host_priv *host_priv = host->private_data;
1371 void __iomem *hcr_base = host_priv->hcr_base;
1372 u32 temp;
1373
1374 /*
1375 * NOTE : We cannot bring the controller online before setting
1376 * the CHBA, hence main controller initialization is done as
1377 * part of the port_start() callback
1378 */
1379
1380 /* sata controller to operate in enterprise mode */
1381 temp = ioread32(hcr_base + HCONTROL);
1382 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1383
1384 /* ack. any pending IRQs for this controller/port */
1385 temp = ioread32(hcr_base + HSTATUS);
1386 if (temp & 0x3F)
1387 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1388
1389 /* Keep interrupts disabled on the controller */
1390 temp = ioread32(hcr_base + HCONTROL);
1391 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1392
1393 /* Disable interrupt coalescing control(icc), for the moment */
1394 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1395 iowrite32(0x01000000, hcr_base + ICC);
1396
1397 /* clear error registers, SError is cleared by libATA */
1398 iowrite32(0x00000FFFF, hcr_base + CE);
1399 iowrite32(0x00000FFFF, hcr_base + DE);
1400
1401 /*
1402 * reset the number of command complete bits which will cause the
1403 * interrupt to be signaled
1404 */
1405 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1406 intr_coalescing_ticks);
1407
1408 /*
1409 * host controller will be brought on-line, during xx_port_start()
1410 * callback, that should also initiate the OOB, COMINIT sequence
1411 */
1412
1413 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1414 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1415
1416 return 0;
1417 }
1418
1419 /*
1420 * scsi mid-layer and libata interface structures
1421 */
1422 static struct scsi_host_template sata_fsl_sht = {
1423 ATA_NCQ_SHT("sata_fsl"),
1424 .can_queue = SATA_FSL_QUEUE_DEPTH,
1425 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1426 .dma_boundary = ATA_DMA_BOUNDARY,
1427 };
1428
1429 static struct ata_port_operations sata_fsl_ops = {
1430 .inherits = &sata_pmp_port_ops,
1431
1432 .qc_defer = ata_std_qc_defer,
1433 .qc_prep = sata_fsl_qc_prep,
1434 .qc_issue = sata_fsl_qc_issue,
1435 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1436
1437 .scr_read = sata_fsl_scr_read,
1438 .scr_write = sata_fsl_scr_write,
1439
1440 .freeze = sata_fsl_freeze,
1441 .thaw = sata_fsl_thaw,
1442 .softreset = sata_fsl_softreset,
1443 .hardreset = sata_fsl_hardreset,
1444 .pmp_softreset = sata_fsl_softreset,
1445 .error_handler = sata_fsl_error_handler,
1446 .post_internal_cmd = sata_fsl_post_internal_cmd,
1447
1448 .port_start = sata_fsl_port_start,
1449 .port_stop = sata_fsl_port_stop,
1450
1451 .pmp_attach = sata_fsl_pmp_attach,
1452 .pmp_detach = sata_fsl_pmp_detach,
1453 };
1454
1455 static const struct ata_port_info sata_fsl_port_info[] = {
1456 {
1457 .flags = SATA_FSL_HOST_FLAGS,
1458 .pio_mask = ATA_PIO4,
1459 .udma_mask = ATA_UDMA6,
1460 .port_ops = &sata_fsl_ops,
1461 },
1462 };
1463
1464 static int sata_fsl_probe(struct platform_device *ofdev)
1465 {
1466 int retval = -ENXIO;
1467 void __iomem *hcr_base = NULL;
1468 void __iomem *ssr_base = NULL;
1469 void __iomem *csr_base = NULL;
1470 struct sata_fsl_host_priv *host_priv = NULL;
1471 int irq;
1472 struct ata_host *host = NULL;
1473 u32 temp;
1474
1475 struct ata_port_info pi = sata_fsl_port_info[0];
1476 const struct ata_port_info *ppi[] = { &pi, NULL };
1477
1478 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1479
1480 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1481 if (!hcr_base)
1482 goto error_exit_with_cleanup;
1483
1484 ssr_base = hcr_base + 0x100;
1485 csr_base = hcr_base + 0x140;
1486
1487 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1488 temp = ioread32(csr_base + TRANSCFG);
1489 temp = temp & 0xffffffe0;
1490 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1491 }
1492
1493 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1494 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1495 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1496
1497 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1498 if (!host_priv)
1499 goto error_exit_with_cleanup;
1500
1501 host_priv->hcr_base = hcr_base;
1502 host_priv->ssr_base = ssr_base;
1503 host_priv->csr_base = csr_base;
1504
1505 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1506 if (irq < 0) {
1507 dev_err(&ofdev->dev, "invalid irq from platform\n");
1508 goto error_exit_with_cleanup;
1509 }
1510 host_priv->irq = irq;
1511
1512 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1513 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1514 else
1515 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1516
1517 /* allocate host structure */
1518 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1519 if (!host) {
1520 retval = -ENOMEM;
1521 goto error_exit_with_cleanup;
1522 }
1523
1524 /* host->iomap is not used currently */
1525 host->private_data = host_priv;
1526
1527 /* initialize host controller */
1528 sata_fsl_init_controller(host);
1529
1530 /*
1531 * Now, register with libATA core, this will also initiate the
1532 * device discovery process, invoking our port_start() handler &
1533 * error_handler() to execute a dummy Softreset EH session
1534 */
1535 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1536 &sata_fsl_sht);
1537
1538 platform_set_drvdata(ofdev, host);
1539
1540 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1541 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1542 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1543 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1544 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1545 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1546 if (retval)
1547 goto error_exit_with_cleanup;
1548
1549 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1550 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1551 sysfs_attr_init(&host_priv->rx_watermark.attr);
1552 host_priv->rx_watermark.attr.name = "rx_watermark";
1553 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1554 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1555 if (retval) {
1556 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1557 goto error_exit_with_cleanup;
1558 }
1559
1560 return 0;
1561
1562 error_exit_with_cleanup:
1563
1564 if (host)
1565 ata_host_detach(host);
1566
1567 if (hcr_base)
1568 iounmap(hcr_base);
1569 kfree(host_priv);
1570
1571 return retval;
1572 }
1573
1574 static int sata_fsl_remove(struct platform_device *ofdev)
1575 {
1576 struct ata_host *host = platform_get_drvdata(ofdev);
1577 struct sata_fsl_host_priv *host_priv = host->private_data;
1578
1579 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1580 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1581
1582 ata_host_detach(host);
1583
1584 irq_dispose_mapping(host_priv->irq);
1585 iounmap(host_priv->hcr_base);
1586 kfree(host_priv);
1587
1588 return 0;
1589 }
1590
1591 #ifdef CONFIG_PM
1592 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1593 {
1594 struct ata_host *host = platform_get_drvdata(op);
1595 return ata_host_suspend(host, state);
1596 }
1597
1598 static int sata_fsl_resume(struct platform_device *op)
1599 {
1600 struct ata_host *host = platform_get_drvdata(op);
1601 struct sata_fsl_host_priv *host_priv = host->private_data;
1602 int ret;
1603 void __iomem *hcr_base = host_priv->hcr_base;
1604 struct ata_port *ap = host->ports[0];
1605 struct sata_fsl_port_priv *pp = ap->private_data;
1606
1607 ret = sata_fsl_init_controller(host);
1608 if (ret) {
1609 dev_err(&op->dev, "Error initializing hardware\n");
1610 return ret;
1611 }
1612
1613 /* Recovery the CHBA register in host controller cmd register set */
1614 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1615
1616 iowrite32((ioread32(hcr_base + HCONTROL)
1617 | HCONTROL_ONLINE_PHY_RST
1618 | HCONTROL_SNOOP_ENABLE
1619 | HCONTROL_PMP_ATTACHED),
1620 hcr_base + HCONTROL);
1621
1622 ata_host_resume(host);
1623 return 0;
1624 }
1625 #endif
1626
1627 static struct of_device_id fsl_sata_match[] = {
1628 {
1629 .compatible = "fsl,pq-sata",
1630 },
1631 {
1632 .compatible = "fsl,pq-sata-v2",
1633 },
1634 {},
1635 };
1636
1637 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1638
1639 static struct platform_driver fsl_sata_driver = {
1640 .driver = {
1641 .name = "fsl-sata",
1642 .owner = THIS_MODULE,
1643 .of_match_table = fsl_sata_match,
1644 },
1645 .probe = sata_fsl_probe,
1646 .remove = sata_fsl_remove,
1647 #ifdef CONFIG_PM
1648 .suspend = sata_fsl_suspend,
1649 .resume = sata_fsl_resume,
1650 #endif
1651 };
1652
1653 module_platform_driver(fsl_sata_driver);
1654
1655 MODULE_LICENSE("GPL");
1656 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1657 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1658 MODULE_VERSION("1.10");
Linux with added FPC-III support