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net: qmi_wwan: add Olivetti Olicard 500
[linux/fpc-iii.git] / drivers / clocksource / exynos_mct.c
bloba6ee6d7cd63f19a4cdad01a1a82956f990a76194
1 /* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
27
28 #define EXYNOS4_MCTREG(x) (x)
29 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
30 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
31 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
32 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
33 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
34 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
35 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
36 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
37 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
38 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
39 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
40 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
41 #define EXYNOS4_MCT_L_MASK (0xffffff00)
42
43 #define MCT_L_TCNTB_OFFSET (0x00)
44 #define MCT_L_ICNTB_OFFSET (0x08)
45 #define MCT_L_TCON_OFFSET (0x20)
46 #define MCT_L_INT_CSTAT_OFFSET (0x30)
47 #define MCT_L_INT_ENB_OFFSET (0x34)
48 #define MCT_L_WSTAT_OFFSET (0x40)
49 #define MCT_G_TCON_START (1 << 8)
50 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
51 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
52 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
53 #define MCT_L_TCON_INT_START (1 << 1)
54 #define MCT_L_TCON_TIMER_START (1 << 0)
55
56 #define TICK_BASE_CNT 1
57
58 enum {
59 MCT_INT_SPI,
60 MCT_INT_PPI
61 };
62
63 enum {
64 MCT_G0_IRQ,
65 MCT_G1_IRQ,
66 MCT_G2_IRQ,
67 MCT_G3_IRQ,
68 MCT_L0_IRQ,
69 MCT_L1_IRQ,
70 MCT_L2_IRQ,
71 MCT_L3_IRQ,
72 MCT_L4_IRQ,
73 MCT_L5_IRQ,
74 MCT_L6_IRQ,
75 MCT_L7_IRQ,
76 MCT_NR_IRQS,
77 };
78
79 static void __iomem *reg_base;
80 static unsigned long clk_rate;
81 static unsigned int mct_int_type;
82 static int mct_irqs[MCT_NR_IRQS];
83
84 struct mct_clock_event_device {
85 struct clock_event_device evt;
86 unsigned long base;
87 char name[10];
88 };
89
90 static void exynos4_mct_write(unsigned int value, unsigned long offset)
91 {
92 unsigned long stat_addr;
93 u32 mask;
94 u32 i;
95
96 __raw_writel(value, reg_base + offset);
97
98 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
99 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
100 switch (offset & EXYNOS4_MCT_L_MASK) {
101 case MCT_L_TCON_OFFSET:
102 mask = 1 << 3; /* L_TCON write status */
103 break;
104 case MCT_L_ICNTB_OFFSET:
105 mask = 1 << 1; /* L_ICNTB write status */
106 break;
107 case MCT_L_TCNTB_OFFSET:
108 mask = 1 << 0; /* L_TCNTB write status */
109 break;
110 default:
111 return;
112 }
113 } else {
114 switch (offset) {
115 case EXYNOS4_MCT_G_TCON:
116 stat_addr = EXYNOS4_MCT_G_WSTAT;
117 mask = 1 << 16; /* G_TCON write status */
118 break;
119 case EXYNOS4_MCT_G_COMP0_L:
120 stat_addr = EXYNOS4_MCT_G_WSTAT;
121 mask = 1 << 0; /* G_COMP0_L write status */
122 break;
123 case EXYNOS4_MCT_G_COMP0_U:
124 stat_addr = EXYNOS4_MCT_G_WSTAT;
125 mask = 1 << 1; /* G_COMP0_U write status */
126 break;
127 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
128 stat_addr = EXYNOS4_MCT_G_WSTAT;
129 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
130 break;
131 case EXYNOS4_MCT_G_CNT_L:
132 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
133 mask = 1 << 0; /* G_CNT_L write status */
134 break;
135 case EXYNOS4_MCT_G_CNT_U:
136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
137 mask = 1 << 1; /* G_CNT_U write status */
138 break;
139 default:
140 return;
141 }
142 }
143
144 /* Wait maximum 1 ms until written values are applied */
145 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
146 if (__raw_readl(reg_base + stat_addr) & mask) {
147 __raw_writel(mask, reg_base + stat_addr);
148 return;
149 }
150
151 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
152 }
153
154 /* Clocksource handling */
155 static void exynos4_mct_frc_start(u32 hi, u32 lo)
156 {
157 u32 reg;
158
159 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
160 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
161
162 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
163 reg |= MCT_G_TCON_START;
164 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
165 }
166
167 static cycle_t exynos4_frc_read(struct clocksource *cs)
168 {
169 unsigned int lo, hi;
170 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
171
172 do {
173 hi = hi2;
174 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
175 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
176 } while (hi != hi2);
177
178 return ((cycle_t)hi << 32) | lo;
179 }
180
181 static void exynos4_frc_resume(struct clocksource *cs)
182 {
183 exynos4_mct_frc_start(0, 0);
184 }
185
186 struct clocksource mct_frc = {
187 .name = "mct-frc",
188 .rating = 400,
189 .read = exynos4_frc_read,
190 .mask = CLOCKSOURCE_MASK(64),
191 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
192 .resume = exynos4_frc_resume,
193 };
194
195 static void __init exynos4_clocksource_init(void)
196 {
197 exynos4_mct_frc_start(0, 0);
198
199 if (clocksource_register_hz(&mct_frc, clk_rate))
200 panic("%s: can't register clocksource\n", mct_frc.name);
201 }
202
203 static void exynos4_mct_comp0_stop(void)
204 {
205 unsigned int tcon;
206
207 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
208 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
209
210 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
211 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
212 }
213
214 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
215 unsigned long cycles)
216 {
217 unsigned int tcon;
218 cycle_t comp_cycle;
219
220 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
221
222 if (mode == CLOCK_EVT_MODE_PERIODIC) {
223 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
224 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
225 }
226
227 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
228 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
229 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
230
231 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
232
233 tcon |= MCT_G_TCON_COMP0_ENABLE;
234 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
235 }
236
237 static int exynos4_comp_set_next_event(unsigned long cycles,
238 struct clock_event_device *evt)
239 {
240 exynos4_mct_comp0_start(evt->mode, cycles);
241
242 return 0;
243 }
244
245 static void exynos4_comp_set_mode(enum clock_event_mode mode,
246 struct clock_event_device *evt)
247 {
248 unsigned long cycles_per_jiffy;
249 exynos4_mct_comp0_stop();
250
251 switch (mode) {
252 case CLOCK_EVT_MODE_PERIODIC:
253 cycles_per_jiffy =
254 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
255 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
256 break;
257
258 case CLOCK_EVT_MODE_ONESHOT:
259 case CLOCK_EVT_MODE_UNUSED:
260 case CLOCK_EVT_MODE_SHUTDOWN:
261 case CLOCK_EVT_MODE_RESUME:
262 break;
263 }
264 }
265
266 static struct clock_event_device mct_comp_device = {
267 .name = "mct-comp",
268 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
269 .rating = 250,
270 .set_next_event = exynos4_comp_set_next_event,
271 .set_mode = exynos4_comp_set_mode,
272 };
273
274 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
275 {
276 struct clock_event_device *evt = dev_id;
277
278 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
279
280 evt->event_handler(evt);
281
282 return IRQ_HANDLED;
283 }
284
285 static struct irqaction mct_comp_event_irq = {
286 .name = "mct_comp_irq",
287 .flags = IRQF_TIMER | IRQF_IRQPOLL,
288 .handler = exynos4_mct_comp_isr,
289 .dev_id = &mct_comp_device,
290 };
291
292 static void exynos4_clockevent_init(void)
293 {
294 mct_comp_device.cpumask = cpumask_of(0);
295 clockevents_config_and_register(&mct_comp_device, clk_rate,
296 0xf, 0xffffffff);
297 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
298 }
299
300 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
301
302 /* Clock event handling */
303 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
304 {
305 unsigned long tmp;
306 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
307 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
308
309 tmp = __raw_readl(reg_base + offset);
310 if (tmp & mask) {
311 tmp &= ~mask;
312 exynos4_mct_write(tmp, offset);
313 }
314 }
315
316 static void exynos4_mct_tick_start(unsigned long cycles,
317 struct mct_clock_event_device *mevt)
318 {
319 unsigned long tmp;
320
321 exynos4_mct_tick_stop(mevt);
322
323 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
324
325 /* update interrupt count buffer */
326 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
327
328 /* enable MCT tick interrupt */
329 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
330
331 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
332 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
333 MCT_L_TCON_INTERVAL_MODE;
334 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
335 }
336
337 static int exynos4_tick_set_next_event(unsigned long cycles,
338 struct clock_event_device *evt)
339 {
340 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
341
342 exynos4_mct_tick_start(cycles, mevt);
343
344 return 0;
345 }
346
347 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
348 struct clock_event_device *evt)
349 {
350 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
351 unsigned long cycles_per_jiffy;
352
353 exynos4_mct_tick_stop(mevt);
354
355 switch (mode) {
356 case CLOCK_EVT_MODE_PERIODIC:
357 cycles_per_jiffy =
358 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
359 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
360 break;
361
362 case CLOCK_EVT_MODE_ONESHOT:
363 case CLOCK_EVT_MODE_UNUSED:
364 case CLOCK_EVT_MODE_SHUTDOWN:
365 case CLOCK_EVT_MODE_RESUME:
366 break;
367 }
368 }
369
370 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
371 {
372 struct clock_event_device *evt = &mevt->evt;
373
374 /*
375 * This is for supporting oneshot mode.
376 * Mct would generate interrupt periodically
377 * without explicit stopping.
378 */
379 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
380 exynos4_mct_tick_stop(mevt);
381
382 /* Clear the MCT tick interrupt */
383 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
384 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
385 return 1;
386 } else {
387 return 0;
388 }
389 }
390
391 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
392 {
393 struct mct_clock_event_device *mevt = dev_id;
394 struct clock_event_device *evt = &mevt->evt;
395
396 exynos4_mct_tick_clear(mevt);
397
398 evt->event_handler(evt);
399
400 return IRQ_HANDLED;
401 }
402
403 static int exynos4_local_timer_setup(struct clock_event_device *evt)
404 {
405 struct mct_clock_event_device *mevt;
406 unsigned int cpu = smp_processor_id();
407
408 mevt = container_of(evt, struct mct_clock_event_device, evt);
409
410 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
411 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
412
413 evt->name = mevt->name;
414 evt->cpumask = cpumask_of(cpu);
415 evt->set_next_event = exynos4_tick_set_next_event;
416 evt->set_mode = exynos4_tick_set_mode;
417 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
418 evt->rating = 450;
419 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
420 0xf, 0x7fffffff);
421
422 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
423
424 if (mct_int_type == MCT_INT_SPI) {
425 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
426 if (request_irq(evt->irq, exynos4_mct_tick_isr,
427 IRQF_TIMER | IRQF_NOBALANCING,
428 evt->name, mevt)) {
429 pr_err("exynos-mct: cannot register IRQ %d\n",
430 evt->irq);
431 return -EIO;
432 }
433 } else {
434 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
435 }
436
437 return 0;
438 }
439
440 static void exynos4_local_timer_stop(struct clock_event_device *evt)
441 {
442 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
443 if (mct_int_type == MCT_INT_SPI)
444 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
445 else
446 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
447 }
448
449 static int exynos4_mct_cpu_notify(struct notifier_block *self,
450 unsigned long action, void *hcpu)
451 {
452 struct mct_clock_event_device *mevt;
453 unsigned int cpu;
454
455 /*
456 * Grab cpu pointer in each case to avoid spurious
457 * preemptible warnings
458 */
459 switch (action & ~CPU_TASKS_FROZEN) {
460 case CPU_STARTING:
461 mevt = this_cpu_ptr(&percpu_mct_tick);
462 exynos4_local_timer_setup(&mevt->evt);
463 break;
464 case CPU_ONLINE:
465 cpu = (unsigned long)hcpu;
466 if (mct_int_type == MCT_INT_SPI)
467 irq_set_affinity(mct_irqs[MCT_L0_IRQ + cpu],
468 cpumask_of(cpu));
469 break;
470 case CPU_DYING:
471 mevt = this_cpu_ptr(&percpu_mct_tick);
472 exynos4_local_timer_stop(&mevt->evt);
473 break;
474 }
475
476 return NOTIFY_OK;
477 }
478
479 static struct notifier_block exynos4_mct_cpu_nb = {
480 .notifier_call = exynos4_mct_cpu_notify,
481 };
482
483 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
484 {
485 int err;
486 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
487 struct clk *mct_clk, *tick_clk;
488
489 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
490 clk_get(NULL, "fin_pll");
491 if (IS_ERR(tick_clk))
492 panic("%s: unable to determine tick clock rate\n", __func__);
493 clk_rate = clk_get_rate(tick_clk);
494
495 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
496 if (IS_ERR(mct_clk))
497 panic("%s: unable to retrieve mct clock instance\n", __func__);
498 clk_prepare_enable(mct_clk);
499
500 reg_base = base;
501 if (!reg_base)
502 panic("%s: unable to ioremap mct address space\n", __func__);
503
504 if (mct_int_type == MCT_INT_PPI) {
505
506 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
507 exynos4_mct_tick_isr, "MCT",
508 &percpu_mct_tick);
509 WARN(err, "MCT: can't request IRQ %d (%d)\n",
510 mct_irqs[MCT_L0_IRQ], err);
511 } else {
512 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
513 }
514
515 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
516 if (err)
517 goto out_irq;
518
519 /* Immediately configure the timer on the boot CPU */
520 exynos4_local_timer_setup(&mevt->evt);
521 return;
522
523 out_irq:
524 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
525 }
526
527 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
528 {
529 mct_irqs[MCT_G0_IRQ] = irq_g0;
530 mct_irqs[MCT_L0_IRQ] = irq_l0;
531 mct_irqs[MCT_L1_IRQ] = irq_l1;
532 mct_int_type = MCT_INT_SPI;
533
534 exynos4_timer_resources(NULL, base);
535 exynos4_clocksource_init();
536 exynos4_clockevent_init();
537 }
538
539 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
540 {
541 u32 nr_irqs, i;
542
543 mct_int_type = int_type;
544
545 /* This driver uses only one global timer interrupt */
546 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
547
548 /*
549 * Find out the number of local irqs specified. The local
550 * timer irqs are specified after the four global timer
551 * irqs are specified.
552 */
553 #ifdef CONFIG_OF
554 nr_irqs = of_irq_count(np);
555 #else
556 nr_irqs = 0;
557 #endif
558 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
559 mct_irqs[i] = irq_of_parse_and_map(np, i);
560
561 exynos4_timer_resources(np, of_iomap(np, 0));
562 exynos4_clocksource_init();
563 exynos4_clockevent_init();
564 }
565
566
567 static void __init mct_init_spi(struct device_node *np)
568 {
569 return mct_init_dt(np, MCT_INT_SPI);
570 }
571
572 static void __init mct_init_ppi(struct device_node *np)
573 {
574 return mct_init_dt(np, MCT_INT_PPI);
575 }
576 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
577 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Linux with added FPC-III support